Solar cell and method of manufacturing the same

Abstract

A solar cell and its fabrication method are disclosed. The solar cell includes a substrate, a doped polycrystalline silicon layer, and grid lines. The substrate includes a first region, a second region, and a third region connected sequentially along a first direction, the first direction being parallel to the large surface of the substrate. The doped polycrystalline silicon layer is disposed on the substrate, the thickness of the doped polycrystalline silicon layer in the first region being greater than that in the second region, and the thickness of the doped polycrystalline silicon layer in the second region being greater than that in the third region. The grid lines are disposed in the first region and located on the side of the doped polycrystalline silicon layer facing away from the substrate. This solar cell has the advantage of low edge recombination rate.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, specifically to a solar cell and its fabrication method. Background Technology

[0002] In the fabrication and application of existing solar cells, edge recombination is a key bottleneck restricting the improvement of photoelectric conversion efficiency. Because charge carriers in the edge region of the cell are prone to recombination losses, charge collection efficiency decreases, thus affecting the overall performance of the cell. Therefore, solving the problem of high edge recombination in solar cells has become crucial. Summary of the Invention

[0003] The purpose of this application is to provide a solar cell and its fabrication method, which solves the problem of high edge recombination in existing solar cells.

[0004] To achieve the objectives of this application, the following technical solution is provided: In a first aspect, the present invention provides a solar cell, comprising a substrate, a doped polycrystalline silicon layer, and grid lines, wherein the substrate comprises a first region, a second region, and a third region connected sequentially along a first direction, the first direction being parallel to the large surface of the substrate; the doped polycrystalline silicon layer is disposed on the substrate, the thickness of the doped polycrystalline silicon layer in the first region being greater than that in the second region, and the thickness of the doped polycrystalline silicon layer in the second region being greater than that in the third region; the grid lines are disposed in the first region and located on the side of the doped polycrystalline silicon layer facing away from the substrate.

[0005] In some embodiments, the doped polysilicon layer includes a plurality of repeating units arranged sequentially along the first direction, and the third region is between two adjacent repeating units. Each repeating unit includes a first sub-layer and two second sub-layers. The first sub-layer is located in the first region, and the second sub-layer is located in the second region. In the first direction, the first sub-layer is located between the two second sub-layers.

[0006] In some embodiments, the thickness of the doped polysilicon layer in the first region is 100nm~150nm, the thickness of the doped polysilicon layer in the second region is 30nm~60nm, and the thickness of the doped polysilicon layer in the third region is 0nm~10nm.

[0007] In some embodiments, the thickness of the doped polysilicon layer in the first region is 120 nm, the thickness of the doped polysilicon layer in the second region is 45 nm, and the thickness of the doped polysilicon layer in the third region is 0 nm.

[0008] In some embodiments, the first region has a size of 20 μm to 60 μm along the first direction, the second region has a size of 300 μm to 350 μm along the first direction, and the third region has a size of 400 μm to 800 μm along the first direction.

[0009] In some embodiments, the first region has a size of 40 μm along the first direction, the second region has a size of 330 μm along the first direction, and the third region has a size of 600 μm along the first direction.

[0010] In a second aspect, the present invention provides a method for fabricating a solar cell, the method being used to fabricate a solar cell as described in the first aspect, the method comprising: depositing a doped polycrystalline silicon layer on a substrate, the substrate comprising a first region, a second region, and a third region; performing a first thinning treatment on the doped polycrystalline silicon layer in the first region, the second region, and the third region respectively using a laser; and performing a second thinning treatment on the doped polycrystalline silicon layer in the third region using wet etching.

[0011] In some embodiments, a laser is used to perform a first thinning process on the doped polysilicon layer in the first region, the second region, and the third region, respectively. This includes: using a first laser to process the doped polysilicon layer in the first region, using a second laser to process the doped polysilicon layer in the second region, and using a third laser to process the doped polysilicon layer in the third region; wherein the power of the first laser is less than the power of the second laser, and the power of the second laser is less than the power of the third laser; the scanning speed of the first laser is greater than the scanning speed of the second laser, and the scanning speed of the second laser is greater than the scanning speed of the third laser.

[0012] In some embodiments, the power of the first laser is 50W~100W, the power of the second laser is 100W~150W, the power of the third laser is 150W~200W, the scanning speed of the first laser is 400mm / s~800mm / s, the scanning speed of the second laser is 200mm / s~400mm / s, and the scanning speed of the third laser is 100mm / s~300mm / s.

[0013] In some embodiments, the power of the first laser is 70W, and / or the power of the second laser is 120W, and / or the power of the third laser is 150W, and / or the scanning speed of the first laser is 600mm / s, and / or the scanning speed of the second laser is 350mm / s, and / or the scanning speed of the third laser is 250mm / s, and / or the spot size of the first laser is 100μm, and / or the spot size of the second laser is 400μm, and / or the spot size of the third laser is 100μm.

[0014] This invention utilizes a first region as the core charge collection region for the gate line connection, requiring a relatively thick doped polysilicon layer to ensure charge carrying and extraction efficiency. The second region serves as a transition region, achieving smooth charge transfer from the third region to the first region with a moderate thickness, avoiding carrier recombination caused by abrupt thickness changes. The third region, located near the edge of the battery, uses a thinner doped polysilicon layer (or no layer deposited) to reduce carrier accumulation at the edge, suppressing edge recombination at its source and reducing recombination losses caused by redundant structures. Ultimately, this invention achieves the technical effect of reducing edge recombination and improving charge collection efficiency. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0016] Figure 1 This is a front view of a solar cell according to one embodiment; Figure 2 yes Figure 1 A schematic diagram of the cross-section of a solar cell in the AA direction; Figure 3 This is a cross-sectional schematic diagram of a repeating unit in one implementation method; Figure 4 This is a cross-sectional schematic diagram of a repeating unit in another implementation method; Figure 5 This is a cross-sectional schematic diagram of a repeating unit in another implementation method; Figure 6 This is a flowchart of a method for fabricating a solar cell according to one implementation.

[0017] Explanation of reference numerals in the attached figures: 100-Solar cell, 1-Substrate, 101-N-type silicon wafer substrate, 102-Tunneling oxide layer, 2-Doped polycrystalline silicon layer, 201-Repeating unit, 202-First sublayer, 203-Second sublayer, 204-First tilted surface, 205-Second tilted surface, 3-Passivation layer, 4-Gate line, A-First region, B-Second region, C-Third region, 001-First direction, 002-Thickness direction. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] It should be noted that when a component is said to be "fixed" to another component, it can be directly on the other component or it can be in a middle component. When a component is said to be "connected" to another component, it can be directly connected to the other component or it may be in a middle component.

[0020] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items.

[0021] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0022] The following is an explanation of the vocabulary in the text: (1) Tunnel Oxide Passivated Contact (TOPCon): The full name is Tunnel Oxide Passivated Contact Cell, which is a high-efficiency crystalline silicon solar cell technology based on N-type silicon substrate.

[0023] (2) Doped polycrystalline silicon layer (n+Poly-Si): a polycrystalline silicon layer doped with phosphorus.

[0024] (3) Polycrystalline silicon finger structure: n+Poly-Si core structure on the back of TOPCon cell in contact with metal grid lines.

[0025] (4) Tunneling oxide layer (SiO) x ): Silicon oxide between the silicon substrate and the doped polycrystalline silicon layer has a passivation effect.

[0026] (5) Phosphosilicate Glass (PSG): A surface-doped glass layer formed during the deposition of a doped polycrystalline silicon layer.

[0027] (6) Low Pressure Chemical Vapor Deposition (LPCVD): is a process for thin film deposition by activating gaseous substances with thermal energy in a low pressure environment of 27-270 Pa.

[0028] (7) Plasma-enhanced chemical vapor deposition (PECVD): is a method for preparing semiconductor thin film materials and other thin film materials by chemical reaction deposition on a substrate after ionization by glow discharge in a deposition chamber.

[0029] (8) Edge recombination current (J0_edge): Characterizes the degree of carrier recombination at the edge of the battery PolyFinger. The lower the value, the better the performance.

[0030] (9) Open-circuit voltage (Voc) is the terminal voltage of the battery when it is open-circuited, reflecting the barrier height of the PN junction.

[0031] (10) Short-circuit current density (Jsc; Short-Circuit Current Density) is the current density when the battery is short-circuited, reflecting the ability to collect photogenerated carriers.

[0032] (11) Fill Factor (FF) is the ratio of the battery’s maximum output power to the product of its open-circuit voltage and short-circuit current. It is a core efficiency indicator.

[0033] In the fabrication and application of existing solar cells, edge recombination is a key bottleneck restricting the improvement of photoelectric conversion efficiency. Because charge carriers in the edge region of the cell are prone to recombination losses, charge collection efficiency decreases, thus affecting the overall performance of the cell. To address this, this invention employs a gradient thickness design for the doped polycrystalline silicon layer to specifically solve the edge recombination problem, while simultaneously optimizing carrier transport efficiency, thus meeting the development needs of the current high-efficiency photovoltaic industry.

[0034] This invention provides a solar cell 100, please refer to... Figure 1 and Figure 2Specifically, it can be a high-efficiency solar cell 100 adapted to N-type TOPCon technology. The solar cell 100 includes a substrate 1, a doped polycrystalline silicon layer 2, and grid lines 4. The substrate 1 includes a first region A, a second region B, and a third region C connected sequentially along a first direction 001, and the first direction 001 is parallel to the large surface of the substrate 1. The doped polycrystalline silicon layer 2 is disposed on the substrate 1. The thickness of the doped polycrystalline silicon layer 2 in the first region A is greater than that in the second region B, and the thickness of the doped polycrystalline silicon layer 2 in the second region B is greater than that in the third region C. The grid lines 4 are disposed in the first region A and are located on the side of the doped polycrystalline silicon layer 2 that is away from the substrate 1.

[0035] In a specific embodiment, the substrate 1 may include an N-type silicon wafer substrate adapted for TOPCon cells and a tunneling oxide layer 102. The N-type silicon wafer substrate is phosphorus-doped, and the tunneling oxide layer 102 is deposited on the large surface of the N-type silicon wafer substrate. The doped polycrystalline silicon layer 2, as the core functional layer of the N-type TOPCon technology, is closely disposed on the surface of the substrate 1, specifically deposited on the side of the tunneling oxide layer 102 facing away from the N-type silicon wafer substrate. The tunneling oxide layer 102 can passivate the interface and reduce carrier recombination. The doped polycrystalline silicon layer 2, on the one hand, achieves field-effect passivation, further reducing the interface recombination rate.

[0036] In a specific embodiment, the substrate 1 is seamlessly connected with the first region A, the second region B and the third region C along the first direction 001. It should be noted that the first direction 001 mentioned here is parallel to the large surface of the substrate 1 (i.e. the surface with the largest area of ​​the substrate 1, which is also the main surface for light absorption and charge transport). The division of the three regions is not a physical separation, but is based on the thickness gradient design of the subsequent doped polycrystalline silicon layer 2 to achieve functional differentiation of different regions.

[0037] In a specific embodiment, doped polysilicon is deposited in the first region A and the second region B, and the third region C may or may not have doped polysilicon deposited there. It should be noted that regardless of whether doped polysilicon is deposited in the third region C, the doped polysilicon can form continuous or discontinuous polysilicon layers at the locations in the first region A, the second region B, and the third region C. When no doped polysilicon is deposited in the third region C, the doped polysilicon layers 2 in the first region A and the second region B can remain continuous, forming a discontinuous structure with the third region C.

[0038] In a specific embodiment, along the thickness direction 002 of the solar cell 100, the doped polycrystalline silicon layer 2 has the greatest thickness in the first region A, followed by the second region B, and the thinnest thickness in the third region C. Considering the flexible deposition design in the third region C mentioned earlier, the thickness of the doped polycrystalline silicon layer 2 in the third region C can also be 0, corresponding to the case where no doped polycrystalline silicon is deposited in the third region C, exposing the large surface area (tunneling oxide layer 102) of the substrate 1. It should be noted that the thickness direction 002 of the solar cell 100 is perpendicular to the first direction 001, meaning the thickness direction 002 is perpendicular to the large surface area of ​​the substrate 1.

[0039] The grid line 4, as a charge extraction component of the solar cell 100, is mainly used to extract the charge carriers collected in the doped polycrystalline silicon layer 2 to the external circuit, thereby realizing the output of electrical energy. Specifically, the grid line 4 is disposed in the first region A of the substrate 1, on the side of the doped polycrystalline silicon layer 2 facing away from the substrate 1, and in close contact with the doped polycrystalline silicon layer 2 to ensure the stability and efficiency of charge transfer. Since the doped polycrystalline silicon layer 2 in the first region A has the greatest thickness, it can better support the placement of the grid line 4, while providing a more sufficient transmission channel for charge extraction, further reducing contact resistance, reducing charge recombination in the core area, and working synergistically with the gradient thickness design to jointly solve the edge recombination problem and improve the overall efficiency of the cell.

[0040] This invention uses the first region A as the core charge collection region connected by the gate line 4, which requires a relatively thick doped polycrystalline silicon layer 2 to ensure charge carrying and extraction efficiency; the second region B serves as a transition region, and a moderate thickness is used to achieve a smooth transfer of charge from the third region C to the first region A, avoiding carrier recombination caused by abrupt changes in thickness; the third region C, as the region near the edge of the battery, uses a relatively thin doped polycrystalline silicon layer 2 (or no layer is deposited) to reduce the accumulation of carriers in the edge region, thereby suppressing edge recombination at its source and reducing recombination losses caused by redundant structures, ultimately achieving the technical effect of reducing edge recombination and improving charge collection efficiency.

[0041] For some implementation methods, please refer to Figure 2 The doped polycrystalline silicon layer 2 includes a plurality of repeating units 201 arranged sequentially along the first direction 001. The area between two adjacent repeating units 201 is a third region C. The repeating unit 201 includes a first sub-layer 202 and two second sub-layers 203. The first sub-layer 202 is located in the first region A, and the second sub-layer 203 is located in the second region B. In the first direction 001, the first sub-layer 202 is located between the two second sub-layers 203.

[0042] In a specific embodiment, the doped polysilicon layer 2 is composed of a plurality of spaced repeating units 201, with the space between the repeating units 201 forming a third region C. That is, the repeating units 201 may or may not have doped polysilicon (i.e., the thickness of the doped polysilicon layer 2 in the third region C is 0). The repeating units 201 can have a symmetrical structure in the thickness direction 002, including a first sub-layer 202 and two second sub-layers 203, and in the first direction 001, a symmetrical structure of "second sub-layer 203-first sub-layer 202-second sub-layer 203" is formed.

[0043] It should be noted that the substrate 1 can also be divided into multiple first regions A, second regions B, and third regions C. First region A is used to deposit the first sublayer 202, and second region B is used to deposit the second sublayer 203. The arrangement of the multiple regions on the substrate 1 can be "third region C-second region B-first region A-second region B-third region C".

[0044] By setting a symmetrical structure for the repeating unit 201, this aspect enables the charge to efficiently converge from the second sub-layers 203 on both sides to the first sub-layer 202 in the middle, reducing the loss and accumulation during the charge transport process. At the same time, in conjunction with the third region C between adjacent repeating units 201, it further suppresses edge recombination between adjacent core regions, making the charge transport of the entire doped polycrystalline silicon layer 2 more uniform and the recombination loss lower. In conjunction with the gradient thickness design mentioned above, it maximizes the achievement of the core technical goal of reducing edge recombination and improving photoelectric conversion efficiency.

[0045] Meanwhile, the doped polycrystalline silicon layer 2 forms a three-segment thickness gradient structure. The second sublayer 203 can protect the first sublayer 202 from lateral etching. The second sublayer 203 avoids excessive erosion during the preparation process, which would damage the first sublayer 202. At the same time, the second sublayer 203 can protect the tunneling oxide layer 102, achieving the effect of no damage to the tunneling oxide layer 102.

[0046] For some implementation methods, please refer to Figure 2 The thickness of the doped polycrystalline silicon layer 2 in the first region A is 100nm~150nm. This thickness range can meet the load-carrying requirements of the gate line 4, ensure efficient charge discharge in the core region, and avoid excessive contact resistance and carrier aggregation and recombination in the core region due to excessive thickness. At the same time, it can avoid increasing the fabrication cost due to excessive thickness, and provide a reasonable basis for gradient transition, indirectly helping to suppress edge recombination.

[0047] In a specific embodiment, the thickness H1 of the doped polysilicon layer 2 in the first region A can be 100 nm, 105 nm, 110 nm, 115 nm, 120 nm, 125 nm, 130 nm, 135 nm, 140 nm, 145 nm, or 150 nm. Preferably, the thickness of the doped polysilicon layer 2 in the first region A is 120 nm. This preferred thickness achieves an optimal balance between contact resistance and fabrication cost, while providing an optimal transition reference for the thickness gradients in the second region B and the third region C, ensuring the stability of the edge recombination suppression effect.

[0048] In some embodiments, the thickness of the doped polysilicon layer 2 in the second region B is 30 nm to 60 nm. As a charge transport transition region, the thickness of the second region B needs to balance transport efficiency and gradient connection. This range can effectively connect the thicknesses of the first region A and the third region C, avoiding carrier recombination caused by abrupt thickness changes, while guiding carriers to transport rapidly to the first region A, reducing the residence of carriers in the transition region, and indirectly reducing the risk of edge recombination.

[0049] In a specific embodiment, the thickness H2 of the doped polysilicon layer 2 in the second region B can be 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, or 60 nm. Preferably, the thickness of the doped polysilicon layer 2 in the second region B is 45 nm. This thickness enables smooth carrier transport from the first region A to the third region C, further reducing transport losses. Simultaneously, it provides a reasonable transition for the thinner design of the third region C, maximizing the effect of gradient thickness in suppressing edge recombination.

[0050] For some implementation methods, please refer to Figure 2 The thickness H3 (not shown in the figure) of the doped polysilicon layer 2 in the third region C is 0 nm to 10 nm. The third region C, as the area near the edge of the battery, is the main area where edge recombination occurs. This thickness range can reduce the accumulation of charge carriers in the edge region by reducing the thickness of the polysilicon layer (or by not setting it), thereby suppressing edge recombination at its source. At the same time, a thickness within 10 nm can meet the basic passivation requirements and avoid additional recombination caused by exposed edge interfaces.

[0051] In a specific embodiment, the thickness of the doped polysilicon layer 2 in the third region C can be 0 nm, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm. Preferably, the thickness of the doped polysilicon layer 2 in the third region C is 0 nm. This simplifies the fabrication process and reduces production costs to the greatest extent. Furthermore, the design without a polysilicon layer completely reduces carrier aggregation in the edge region, achieving optimal edge recombination suppression.

[0052] For some implementation methods, please refer to Figure 2The size L1 of the first region A along the first direction 001 is 20μm~60μm. This size range can fully accommodate the setting of the gate line 4, ensuring that the area of ​​the core charge collection region is sufficient, avoiding the crowding and recombination of charge carriers in the core region, and at the same time avoiding the excessively large region causing the charge carrier transport path to be too long, thus suppressing recombination in conjunction with the thickness design.

[0053] Optionally, the dimensions of the first region A along the first direction 001 can be 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, 50μm, 55μm, or 60μm. Preferably, the dimensions of the first region A along the first direction 001 are 40μm, which allows for optimal matching of the load-bearing capacity and transmission efficiency of the gate line 4 through precise process control, further aiding in reducing recombination losses.

[0054] For some implementation methods, please refer to Figure 2 The second region B has a size L2 of 300μm~350μm along the first direction 001. This size can ensure the smooth transport of charge carriers from the third region C to the first region A, provide sufficient transition space for charge collection, and avoid charge carriers staying in the transition region for too long, which would lead to recombination. At the same time, the medium thickness design enhances the gradient transition effect and indirectly suppresses edge recombination.

[0055] Optionally, the dimensions of the second region B along the first direction 001 can be 300μm, 305μm, 310μm, 315μm, 320μm, 325μm, 330μm, 335μm, 340μm, 345μm, or 350μm. Preferably, the dimension of the second region B along the first direction 001 is 330μm. This dimension can achieve a balance between transition transport and structural compactness, further optimize carrier transport efficiency, and improve edge recombination suppression effect in conjunction with thickness gradient design.

[0056] For some implementation methods, please refer to Figure 2 The third region C has a size L3 of 400μm~800μm along the first direction 001. As the main extension area of ​​the substrate 1 (near the edge of the cell), this size range can meet the requirements of light absorption and initial collection of charge carriers. At the same time, through reasonable size design, combined with a thin (or no) polycrystalline silicon layer, the accumulation range of charge carriers in the edge region is reduced, edge recombination is suppressed from the spatial dimension, and the overall cell size design is adapted.

[0057] Optionally, the dimensions of the third region C along the first direction 001 can be 400μm, 450μm, 500μm, 550μm, 600μm, 650μm, 700μm, 750μm, or 800μm. Preferably, the dimension of the third region C along the first direction 001 is 600μm, which achieves an optimal combination of light absorption efficiency and structural rationality.

[0058] For some implementation methods, please refer to Figures 3-5 The doped polysilicon layer 2 has a first inclined surface 204 in the first region A and a second inclined surface 205 in the second region B. The angle α between the first inclined surface 204 or the second inclined surface 205 and the large surface of the substrate 1 is 30° to 60°. Optionally, the angle between the first inclined surface 204 or the second inclined surface 205 and the large surface of the substrate 1 can be 30°, 35°, 40°, 45°, 50°, 55°, or 60°. The first inclined surface 204 and the second inclined surface 205 can enhance the recombination suppression effect at the gradient thickness transition. This angle range can achieve a smooth transition of charge carriers, avoid charge carrier recombination caused by interface abrupt changes, and adapt to the gradient thickness design of the polysilicon layer, thus helping to improve the edge recombination suppression effect.

[0059] In a specific embodiment, please refer to Figure 3 The first sublayer 202 has a first inclined surface 204, and the second sublayer 203 has a second inclined surface 205. The first inclined surface 204 can be located on the side of the first sublayer 202; along the thickness direction 002, one end of the first inclined surface 204 is connected to the top surface of the first sublayer 202 facing away from the substrate 1, and the other end of the first inclined surface 204 is connected to the top surface of the second sublayer 203 facing away from the substrate 1. The second inclined surface 205 can be located on the side of the second sublayer 203; along the thickness direction 002, one end of the second inclined surface 205 is connected to the top surface of the second sublayer 203 facing away from the substrate 1, and the other end of the second inclined surface 205 is connected to the large surface of the substrate 1. This design can achieve a smooth transition between the first sublayer 202 and the second sublayer 203, as well as between the second sublayer 203 and the substrate 1, avoiding the interface steps formed by abrupt thickness changes that cause carrier aggregation and recombination, while guiding the charge to flow smoothly from the second sublayer 203 to the first sublayer 202.

[0060] In a specific embodiment, the first sublayer 202 has two first inclined surfaces 204 at an included angle, the two first inclined surfaces 204 being arranged opposite to each other along a first direction 001. It can be understood that the side of the first sublayer 202 protruding from the second sublayer 203 is the first sublayer 202. The second sublayer 203 has two second inclined surfaces 205 at an included angle, the two second inclined surfaces 205 being arranged opposite to each other along the first direction 001. It can be understood that the side of the second sublayer 203 protruding from the substrate 1 is the second sublayer 203.

[0061] In other embodiments, please refer to Figure 4The first sublayer 202 may also have a first side surface, and the second sublayer 203 may also have a second side surface. Along the thickness direction 002, the first side surface connects to the top surface of the second sublayer 203 facing away from the substrate 1, and the other end connects to a first inclined surface 204, which in turn connects to the top surface of the first sublayer 202 facing away from the substrate 1. Thus, the first side surface can be a chamfer at the edge of the first sublayer 202. This chamfer design eliminates sharp edges, preventing carriers from accumulating and recombinizing at these sharp edges, and further optimizes the transition between the first sublayer 202 and the second sublayer 203. The second side surface is configured in the same way as the first side surface, both used to eliminate sharp edges and reduce recombination losses, and will not be elaborated upon here.

[0062] In other embodiments, please refer to Figure 5 The first inclined surface 204 can also be used to form the top surface of the first sub-layer 202, and the second inclined surface 205 can also be used to form the top surface of the second sub-layer 203; that is, the first inclined surface 204 is located on the side of the first sub-layer 202 facing away from the substrate 1, and the second inclined surface 205 is located on the side of the second sub-layer 203 facing away from the substrate 1. This design, through the inclined structure of the top surface, optimizes the light absorption effect while guiding the carriers to be transported efficiently in the direction of the gate line 4, reducing the residence time of the carriers on the top surface, indirectly reducing recombination loss. In conjunction with the gradient thickness design and the repeating unit 201 structure, it jointly achieves the effect of reducing edge recombination and improving photoelectric conversion efficiency.

[0063] For some implementation methods, please refer to Figure 2 The solar cell 100 also includes a passivation layer 3, which is disposed on the side of the doped polycrystalline silicon layer 2 facing away from the substrate 1, and the grid lines 4 are specifically disposed on the passivation layer 3. Specifically, when no doped polycrystalline silicon is disposed in the third region C, the passivation layer 3 is directly connected to the tunneling oxide layer 102 of the substrate 1, thereby achieving direct passivation protection of the edge region of the substrate 1. This avoids the interface exposure of the third region C due to the lack of doped polycrystalline silicon layer 2 coverage, reduces carrier recombination in the edge region from the source, ensures the overall recombination suppression effect of the cell, and further improves the photoelectric conversion efficiency.

[0064] This application also provides a method for preparing a solar cell, which is used to prepare the solar cell provided in the above embodiments. Please refer to... Figure 6 The preparation methods include: Step S100: Deposit a doped polysilicon layer on a substrate, the substrate including a first region, a second region and a third region; Step S200: Laser is used to perform the first thinning process on the doped polycrystalline silicon layers in the first region, the second region and the third region respectively; In step S300, a second thinning process is performed on the doped polysilicon layer in the third region using wet etching.

[0065] In a specific embodiment, the process before step S100 includes fabricating a substrate. Specifically, this includes cleaning the N-type silicon wafer substrate to remove surface oil and impurities, then texturing to easily create a uniform textured surface on the N-type silicon wafer substrate; and growing a tunneling oxide layer on the texturized N-type silicon wafer substrate to obtain the substrate.

[0066] In a specific embodiment, step S100 specifically includes depositing a doped polysilicon layer of a predetermined thickness on the substrate using an LPCVD process, wherein the thickness of the doped polysilicon layer is uniform; the doped polysilicon layer can cover a large area of ​​the substrate, so that doped polysilicon is deposited in the first region, the second region, and the third region. Optionally, the thickness of the doped polysilicon layer can be 120nm~150nm.

[0067] In a specific embodiment, before step S200, the process further includes image processing of the doped polysilicon layer. Specifically, this includes creating a preset pattern of repeating units on the doped polysilicon layer using photolithography to define the boundaries of the first sublayer and the second sublayer.

[0068] In a specific embodiment, step S200 specifically includes using a laser to process the doped polysilicon layers in the first region, the second region, and the third region respectively, thereby obtaining the first sub-layer and the second sub-layer, while minimizing the thickness of the doped polysilicon layer located in the third region to provide an environment for wet etching.

[0069] In a specific embodiment, step S300 specifically includes etching the doped polysilicon layer with an etching solution at a preset temperature, mainly removing the doped polysilicon in the third region, and forming a first inclined surface and a second inclined surface on the first sub-layer and the second sub-layer, respectively; then cleaning and repairing the etched material.

[0070] In a specific embodiment, after step S300, the method further includes fabricating a passivation layer and gate lines. Specifically, this includes depositing a passivation layer of a predetermined thickness on a polysilicon layer using a PVD process, and then printing conductive paste at the corresponding positions in the first region to form gate lines.

[0071] In some embodiments, a laser is used to perform a first thinning process on the doped polysilicon layers in the first, second, and third regions, respectively. This includes: using a first laser to process the doped polysilicon layer in the first region, using a second laser to process the doped polysilicon layer in the second region, and using a third laser to process the doped polysilicon layer in the third region; wherein the power of the first laser is less than the power of the second laser, and the power of the second laser is less than the power of the third laser; the scanning speed of the first laser is greater than the scanning speed of the second laser, and the scanning speed of the second laser is greater than the scanning speed of the third laser.

[0072] In some embodiments, the power of the first laser is 50W to 100W. Optionally, the power of the first laser can be 50W, 60W, 70W, 80W, 90W, or 100W. Preferably, the power of the first laser can be 70W.

[0073] In some embodiments, the power of the second laser is 100W to 150W. Optionally, the power of the second laser can be 100W, 110W, 120W, 130W, 140W, or 150W. Preferably, the power of the second laser can be 120W.

[0074] In some embodiments, the power of the third laser is 150W to 200W. Optionally, the power of the third laser can be 150W, 160W, 170W, 180W, 190W, or 200W. Preferably, the power of the third laser can be 150W.

[0075] In some embodiments, the scanning speed of the first laser is 400 mm / s to 800 mm / s. Optionally, the scanning speed of the first laser can be 400 mm / s, 500 mm / s, 600 mm / s, 700 mm / s, or 800 mm / s. Preferably, the scanning speed of the first laser can be 600 mm / s.

[0076] In some embodiments, the scanning speed of the second laser is 200 mm / s to 400 mm / s. Optionally, the scanning speed of the second laser can be 200 mm / s, 250 mm / s, 300 mm / s, 350 mm / s, or 400 mm / s. Preferably, the scanning speed of the second laser can be 350 mm / s.

[0077] In some embodiments, the scanning speed of the third laser is 100 mm / s to 300 mm / s. Optionally, the scanning speed of the third laser can be 100 mm / s, 150 mm / s, 200 mm / s, 250 mm / s, or 300 mm / s. Preferably, the scanning speed of the third laser can be 250 mm / s.

[0078] In some embodiments, the spot size of the first laser is 50 μm to 200 μm. Optionally, the spot size of the first laser can be 50 μm, 100 μm, 150 μm, or 200 μm. Preferably, the spot size of the first laser can be 100 μm.

[0079] In some embodiments, the spot size of the second laser is 200 μm to 600 μm. Optionally, the spot size of the second laser can be 200 μm, 300 μm, 400 μm, 500 μm, or 600 μm. Preferably, the spot size of the second laser can be 400 μm.

[0080] In some embodiments, the spot size of the third laser is 50 μm to 200 μm. Optionally, the spot size of the third laser can be 50 μm, 100 μm, 150 μm, or 200 μm. Preferably, the spot size of the third laser can be 100 μm.

[0081] The solar cell fabrication method provided by this invention employs a combination of laser and wet etching, completely eliminating the need for dry etching. This two-step etching process creates a gradient-varying doped polycrystalline silicon layer on the solar cell. This method offers the following advantages: 1) It is simple, requires no additional equipment, and simplifies the process steps. Laser and wet etching parameters are precisely matched, and production line modifications only require adjusting laser parameters, resulting in extremely low modification costs and fully meeting mass production needs; 2) It provides significant side etching protection, with no damage to the tunneling oxide layer; 3) It can significantly reduce edge recombination and significantly improve the battery's electrical performance; 4) It can reduce costs and improve yield.

[0082] The technical solution of the present invention will be described in detail below through specific embodiments.

[0083] Example 1 This embodiment provides a solar cell, which includes a substrate, a doped polycrystalline silicon layer, a passivation layer, and grid lines. The substrate has a first region, a second region, and a third region; the doped polycrystalline silicon layer in the first region has a thickness of 120 nm and a width of 40 μm; the doped polycrystalline silicon layer in the second region has a thickness of 45 nm and a width of 330 μm; and the doped polycrystalline silicon layer in the third region has a thickness of 0 nm and a width of 600 μm.

[0084] The fabrication steps of the solar cell in this embodiment include: 1) Substrate pretreatment: N-type single crystal silicon substrate is cleaned to remove surface oil and impurities, alkali texturing is performed to form a uniform textured surface, dried at 80℃ for 10 min, and then dried with nitrogen for later use. 2) Tunneling oxide layer growth: A tunneling oxide layer with a thickness of 1.5 nm was prepared by thermal oxidation (400℃~450℃, O2 flow rate of 5000sccm~20000sccm, 80s~120s) using LPCVD process. 3) Deposition of doped polycrystalline silicon layer: An amorphous silicon layer with a thickness of 135 nm was deposited using LPCVD process (600℃, silane 3000 sccm, phosphine 400 sccm, hydrogen 10000 sccm, 200s), followed by low-temperature rapid annealing at 650℃ for 30s to crystallize and form a doped polycrystalline silicon layer. A uniform PSG layer was generated on its surface, with a doping activation rate ≥92%. 4) Single-stage etching of the doped polysilicon layer: A pre-defined pattern of repeating units is fabricated on the doped polysilicon layer using photolithography. The width of each repeating unit is 700 μm. The PSG layer is removed using a laser, and the first, second, and third regions are processed with differentiating parameters. The first laser in the first region is set to a power of 70 W, a scanning speed of 600 mm / s, and a spot size of 100 μm, removing only the PSG and retaining a 120 nm thick doped polysilicon layer. The second laser in the second region is set to a power of 120 W, a scanning speed of 350 mm / s, and a spot size of 400 μm, retaining a 45 nm thick doped polysilicon layer. The third laser in the third region is set to a power of 150 W, a scanning speed of 250 mm / s, and a spot size of 100 μm, retaining a 15 nm thick doped polysilicon layer. 5) Secondary etching of the doped polysilicon layer: Wet etching is performed using an etching solution, which is a 0.1wt% hydrofluoric acid mixture. The etching is carried out at a constant temperature of 30℃ for 75s to completely remove the 15nm doped polysilicon in the third region. 6) Cleaning and damage repair: Use a 0.5wt% hydrofluoric acid mixture to clean the surface with a light wet method at 30℃ for 45s to remove etching residue; then use hydrogen plasma treatment (20s, hydrogen concentration 18%) to passivate edge defects and interface states. 7) Deposition of the passivation layer: Al2O3 / SiN was deposited using PVD process. x A composite passivation layer is formed, wherein the Al2O3 layer has a thickness of 20 nm and the SiN layer has a thickness of 10 nm. x The layer thickness is 80nm; 8) Fabrication of grid lines: Print aluminum-free back silver paste in the first region, with a grid line width of 35μm; after drying at 120℃ for 15min, and sintering at 420℃ for 20min, the solar cell is obtained.

[0085] Comparative Example 1 This comparative example provides a solar cell. The difference between this comparative example and Example 1 is that the thickness of the doped polycrystalline silicon layer in the second region is 120 nm; that is, the thickness of the doped polycrystalline silicon layer in the first and second regions is the same, and there is no doped polycrystalline silicon in the third region.

[0086] The difference between this comparative example and Example 1 is that the second laser is set to the same parameters as the first laser, and is only used to remove the PSG layer on the second region of the doped polysilicon layer; and dry etching is used in step 5).

[0087] Comparative Example 2 This comparative example provides a solar cell. The difference between this comparative example and Example 1 is that the thickness of the doped polycrystalline silicon layer is the same in the first region, the second region and the third region, and no repeating units with intervals are provided on the doped polycrystalline silicon layer.

[0088] The difference between this comparative example and Example 1 is that the settings of the first laser, the second laser, and the third laser are the same, and they are only used to remove the PSG layer on the doped polysilicon layer; and conventional wet etching is used in step 5).

[0089] The solar cells prepared in Examples 1 to 2 were tested, and the test results are shown in Table 1. The test contents included: 1) structural morphology, which was detected by microscopy and scanning electron microscopy (SEM); 2) lateral erosion and tunneling oxide layer damage rate, which were detected by microscopy and profilometer; 3) interface state density, which was detected by high-frequency capacitance-voltage method (CV); 4) edge recombination, which was tested by quasi-steady-state photoconductivity method (QSSPC) for J0_edge; 5) electrical performance, which was tested by solar cell IV tester for Voc, Jsc, FF and conversion efficiency.

[0090]

[0091] The test results from Examples 1 and 2 show that the solar cell provided in Example 1 uses a 330 μm wide second sublayer as a side etching buffer, allowing the second sublayer to be preferentially etched by the etching solution, effectively protecting the first sublayer and the tunneling oxide layer. Therefore, the side etching amount in Example 1 is reduced by 60% compared to Comparative Example 1 and by 42.9% compared to Comparative Example 2. The solar cell provided in Example 1 experiences no plasma damage throughout the entire etching process, and due to the precise matching of laser and wet etching parameters, there is no over-etching. The tunneling oxide layer damage rate in Example 1 is reduced by 82.5% compared to Comparative Example 1 and by 72% compared to Comparative Example 2, with a significant reduction in interface state density and significantly optimized interface characteristics.

[0092] Meanwhile, the test results of Example 1 and Comparative Example 2 show that the solar cell provided in Example 1 can reduce the concentration of the edge electric field, resulting in a significant reduction in carrier recombination. J0_edge is reduced by 62.5% compared to Comparative Example 1 and by 57.1% compared to Comparative Example 2, thereby eliminating the edge recombination problem of the solar cell. Furthermore, the solar cell provided in Example 1 has no damage to the tunneling oxide layer, low interface state density, and significantly reduced edge recombination, resulting in a significant improvement in Voc, Jsc, FF, and conversion efficiency compared to the comparative example.

[0093] Furthermore, the solar cell provided in Example 1 completely eliminates dry etching, requiring no additional equipment, and the equipment cost is reduced by 30% compared to Comparative Example 1; the laser and wet process are highly compatible, resulting in less material consumption, and the material cost is reduced by 20% compared to Comparative Example 1 and by 9.1% compared to Comparative Example 2. The yield of the solar cell provided in Example 1 can be increased to 97.8%, which is more than 1.8% higher than Comparative Example 1 and Comparative Example 2.

[0094] In the description of the embodiments of this application, it should be noted that the orientation or positional relationship of the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and other indicators are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0095] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Those skilled in the art will understand that all or part of the processes for implementing the above embodiments and equivalent variations made in accordance with the claims of this application are still within the scope of this application.

Claims

1. A solar cell (100), characterized in that, include: The substrate (1) includes a first region (A), a second region (B) and a third region (C) connected sequentially along a first direction (001), the first direction (001) being parallel to the large surface of the substrate (1); A doped polysilicon layer (2) is disposed on the substrate (1). The thickness of the doped polysilicon layer (2) in the first region (A) is greater than that in the second region (B). The thickness of the doped polysilicon layer (2) in the second region (B) is greater than that in the third region (C). A gate line (4) is disposed in the first region (A) and located on the side of the doped polysilicon layer (2) facing away from the substrate (1).

2. The solar cell (100) according to claim 1, characterized in that, The doped polycrystalline silicon layer (2) includes a plurality of repeating units (201) arranged sequentially along the first direction (001), and the third region (C) is between two adjacent repeating units (201). The repeating unit (201) includes a first sub-layer (202) and two second sub-layers (203). The first sub-layer (202) is located in the first region (A), and the second sub-layer (203) is located in the second region (B). In the first direction (001), the first sub-layer (202) is located between the two second sub-layers (203).

3. The solar cell (100) according to claim 1, characterized in that, The thickness of the doped polysilicon layer (2) in the first region (A) is 100nm~150nm, the thickness of the doped polysilicon layer (2) in the second region (B) is 30nm~60nm, and the thickness of the doped polysilicon layer (2) in the third region (C) is 0nm~10nm.

4. The solar cell (100) according to claim 3, characterized in that, The thickness of the doped polysilicon layer (2) in the first region (A) is 120 nm, the thickness of the doped polysilicon layer (2) in the second region (B) is 45 nm, and the thickness of the doped polysilicon layer (2) in the third region (C) is 0 nm.

5. The solar cell (100) according to claim 1, characterized in that, The first region (A) has a size of 20μm to 60μm along the first direction (001), the second region (B) has a size of 300μm to 350μm along the first direction (001), and the third region (C) has a size of 400μm to 800μm along the first direction (001).

6. The solar cell (100) according to claim 5, characterized in that, The first region (A) has a size of 40 μm along the first direction (001), the second region (B) has a size of 330 μm along the first direction (001), and the third region (C) has a size of 600 μm along the first direction (001).

7. A method for preparing a solar cell, characterized in that, The preparation method is used to prepare the solar cell according to any one of claims 1-6, the preparation method comprising: A doped polysilicon layer is deposited on a substrate, the substrate comprising a first region, a second region, and a third region; Laser is used to perform a first thinning process on the doped polycrystalline silicon layers in the first region, the second region, and the third region, respectively. The doped polysilicon layer in the third region is thinned a second time using wet etching.

8. The preparation method according to claim 7, characterized in that, The first thinning process is performed on the doped polycrystalline silicon layers in the first region, the second region, and the third region using lasers, including: A first laser is used to process the doped polycrystalline silicon layer in the first region, a second laser is used to process the doped polycrystalline silicon layer in the second region, and a third laser is used to process the doped polycrystalline silicon layer in the second region; wherein, the power of the first laser is less than the power of the second laser, and the power of the second laser is less than the power of the third laser; the scanning speed of the first laser is greater than the scanning speed of the second laser, and the scanning speed of the second laser is greater than the scanning speed of the third laser.

9. The preparation method according to claim 8, characterized in that, The power of the first laser is 50W~100W, the power of the second laser is 100W~150W, and the power of the third laser is 150W~200W. The scanning speed of the first laser is 400mm / s~800mm / s, the scanning speed of the second laser is 200mm / s~400mm / s, and the scanning speed of the third laser is 100mm / s~300mm / s. The spot size of the first laser is 50μm~200μm, the spot size of the second laser is 200μm~600μm, and the spot size of the third laser is 50μm~200μm.

10. The preparation method according to claim 9, characterized in that, The power of the first laser is 70W, and / or the power of the second laser is 120W, and / or the power of the third laser is 150W, and / or the scanning speed of the first laser is 600mm / s, and / or the scanning speed of the second laser is 350mm / s, and / or the scanning speed of the third laser is 250mm / s, and / or the spot size of the first laser is 100μm, and / or the spot size of the second laser is 400μm, and / or the spot size of the third laser is 100μm.

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