Display device

Abstract

The display device includes a power line and a driving transistor, a plurality of light-emitting elements including a first electrode and a second electrode, a first planarization layer partially surrounding the sides of the plurality of light-emitting elements, a first connection electrode disposed on the first planarization layer and configured to connect the first electrode and the driving transistor, a second connection electrode disposed on the first planarization layer, a passivation layer disposed on the first connection electrode and the second connection electrode, and a second planarization layer disposed on the passivation layer and configured to partially surround the sides of the plurality of light-emitting elements, wherein the passivation layer exposes an end of the first connection electrode that is configured to surround a portion of the sides of the light-emitting elements, and wherein the second planarization layer covers the end of the first connection electrode.

Description

[0001] Cross-reference to related applications This application claims priority to Korean Patent Application No. 10-2024-0188392, filed with the Korean Intellectual Property Office on December 17, 2024, the disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a display device, and more specifically, to a display device that minimizes short-circuit defects between connecting electrodes. Background Technology

[0003] Display devices used as displays for computers, televisions, mobile phones, etc. include organic light-emitting displays (OLEDs) that are configured to emit light themselves and liquid crystal displays (LCDs) that require a separate light source.

[0004] The applications of display devices are diverse, ranging from computer and television monitors to personal mobile devices, and research is underway on display devices with wide display areas and reduced size and weight.

[0005] Furthermore, display devices, including those using light-emitting diodes (LEDs), have recently garnered attention as next-generation display devices. Because LEDs are made from inorganic materials rather than organic materials, they are more reliable and have a longer lifespan than liquid crystal displays or organic light-emitting displays. Additionally, LEDs can be quickly switched on and off, exhibit excellent luminous efficiency, high shock resistance, and high stability, and can display high-brightness images. Summary of the Invention

[0006] One objective of this disclosure is to provide a display device that minimizes the separation of reflective electrodes caused by moisture penetration.

[0007] Another objective of this disclosure is to provide a display device that reduces crystallization of reflective electrodes.

[0008] Another objective of this disclosure is to provide a display device in which the first electrode of the first connecting electrode and the light-emitting element can be self-aligned.

[0009] Another objective of this disclosure is to provide a display device in which the second electrode of the third connecting electrode and the light-emitting element can be self-aligned.

[0010] Another objective of this disclosure is to provide a display device that minimizes short-circuit defects between connecting electrodes.

[0011] Another objective of this disclosure is to provide a display device that reduces line resistance.

[0012] Another objective of this disclosure is to provide a display device that can detect defects in light-emitting elements regardless of whether the driving transistor is defective.

[0013] Another objective of this disclosure is to provide a display device that improves electrical connections by minimizing connection defects caused by residual film during the manufacturing process.

[0014] The purpose of this disclosure is not limited to the foregoing objectives, and other objectives not mentioned above will be clearly understood by those skilled in the art from the following description.

[0015] A display device according to an embodiment of the present disclosure includes: a substrate defining a plurality of sub-pixels; a power line and a driving transistor disposed on the substrate; a first reflective electrode and a second reflective electrode disposed on the power line and the driving transistor and spaced apart from each other, the first reflective electrode being connected to the driving transistor and the second reflective electrode being connected to the power line; a bonding layer disposed on the first reflective electrode and the second reflective electrode; a plurality of light-emitting elements disposed on the bonding layer in the plurality of sub-pixels, and each including a first electrode and a second electrode; a first planarization layer disposed on the bonding layer and configured to partially surround the sides of the plurality of light-emitting elements; and a first connecting electrode. A first electrode and a driving transistor are disposed on a first planarization layer; a second connecting electrode is disposed on the first planarization layer, spaced apart from the first connecting electrode, and connected to a second reflecting electrode; a passivation layer is disposed on the first connecting electrode and the second connecting electrode; a second planarization layer is disposed on the passivation layer and configured to partially surround the sidewalls of a plurality of light-emitting elements; and a third connecting electrode is disposed on the second planarization layer and configured to connect the second electrode and a power line, wherein the passivation layer exposes the end of the first connecting electrode that is configured to surround a portion of the sidewalls of the light-emitting elements, and wherein the second planarization layer covers the end of the first connecting electrode.

[0016] A display device according to another embodiment of this disclosure includes: a substrate defining a plurality of pixels, each of the plurality of pixels including a plurality of sub-pixels; a power line and a driving transistor disposed on the substrate; a first reflective electrode and a second reflective electrode disposed on the power line and the driving transistor and spaced apart from each other, the first reflective electrode being connected to the driving transistor and the second reflective electrode being connected to the power line; a bonding layer disposed on the first reflective electrode and the second reflective electrode; a plurality of light-emitting elements disposed on the bonding layer in the plurality of sub-pixels, and each including a first electrode and a second electrode; a first planarization layer disposed on the bonding layer and configured to partially surround the sides of the plurality of light-emitting elements; a first connecting electrode disposed on the first planarization layer and configured to connect the first electrode and the driving transistor; a second connecting electrode disposed on the first planarization layer, spaced apart from the first connecting electrode and connected to the second reflective electrode; a passivation layer disposed on the first connecting electrode and the second connecting electrode; a second planarization layer disposed on the passivation layer and the height of the second planarization layer decreasing toward the plurality of light-emitting elements; and a third connecting electrode disposed on the second planarization layer and configured to connect the second electrode and the power line. Therefore, short-circuit defects between the connecting electrodes can be minimized.

[0017] Further details of the exemplary embodiments are included in the detailed description and the accompanying drawings.

[0018] According to embodiments of this disclosure, a passivation layer is disposed on a connection electrode connected to a reflective electrode, which can minimize moisture penetration into the reflective electrode.

[0019] According to embodiments of this disclosure, the separation of the reflective electrode caused by moisture penetration can be minimized.

[0020] According to embodiments of this disclosure, by minimizing potential defects caused by line corrosion and improving the lifespan of the display device, the display device can operate with low power consumption while reducing production energy.

[0021] According to embodiments of this disclosure, by utilizing the process of ashing the first planarization layer and the second planarization layer, the first connecting electrode and the third connecting electrode are self-aligned to the light-emitting element without a separate alignment process, thereby ensuring the transfer allowance of the light-emitting element.

[0022] According to embodiments of this disclosure, a passivation layer is disposed on the first connecting electrode to enable the first connecting electrode and the third connecting electrode to be separated, which can suppress short-circuit defects between the first connecting electrode and the third connecting electrode.

[0023] According to an embodiment of this disclosure, the second planarization layer flows back to the portion of the first connection electrode exposed by the passivation layer, thereby separating the first connection electrode and the third connection electrode, which can suppress short-circuit defects in the connection between the first connection electrode and the third connection electrode.

[0024] According to embodiments of this disclosure, an illumination inspection signal is applied to the light-emitting element without passing through the driving transistor, which can detect whether the light-emitting element is defective regardless of whether the driving transistor is defective.

[0025] The effects of this disclosure are not limited to those exemplified above, and include a variety of other effects. Attached Figure Description

[0026] The above and other aspects, features, and other advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic configuration diagram of a display device according to an embodiment of the present disclosure; Figure 2 This is an enlarged top plan view of the pixels of a display device according to an embodiment of the present disclosure; Figure 3 It is along Figure 2 A sectional view taken from line III-III' in the middle; Figures 4A to 4H This is a process diagram of a method for manufacturing a display device according to an embodiment of the present disclosure. Detailed Implementation

[0027] The advantages and features of this disclosure, as well as methods for implementing these advantages and features, will become clear from the exemplary embodiments described in detail below with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided by way of example only, so that those skilled in the art can fully understand the disclosure and scope of this disclosure.

[0028] The shapes, dimensions, ratios, angles, quantities, etc., shown in the accompanying drawings used to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout the specification, the same reference numerals generally denote the same elements. Furthermore, in the following description of this disclosure, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of other components, unless the term is used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0029] Even without explicit explanation, components are interpreted as including the normal tolerance range.

[0030] When using terms such as “above,” “over,” “below,” and “adjacent” to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless the term is used with the terms “immediately adjacent” or “directly.”

[0031] When one element or layer is placed "on" another element or layer, another layer or element can be directly inserted on or between the other element.

[0032] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from others. Therefore, the first component mentioned below can be the second component in the technical concept of this disclosure.

[0033] Throughout the specification, the same reference numerals generally denote the same elements.

[0034] For ease of description, the dimensions and thickness of each component shown in the accompanying drawings are illustrated, and this disclosure is not limited to the dimensions and thickness of the components shown.

[0035] The features of the various embodiments of this disclosure may be combined or integrated with each other in part or in whole, and may be associated and operated in a variety of technical ways, and the embodiments may be implemented independently or in relation to each other.

[0036] In the following, a display device according to exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0037] Figure 1 This is a schematic configuration diagram of a display device according to embodiments of the present disclosure. For ease of description, Figure 1 Only the display panel PN, gate driver GD, data driver DD, and timing controller TC among the various components of the display device 100 are shown.

[0038] Reference Figure 1 The display device 100 includes: a display panel PN, including a plurality of sub-pixels SP; a gate driver GD, configured to supply various types of signals to the display panel PN; and a timing controller TC, configured to control the data driver DD, the gate driver GD and the data driver DD.

[0039] The gate driver GD responds to multiple gate control signals provided by the timing controller TC to supply multiple scan signals to multiple scan lines SL. Figure 1 The illustration shows a single gate driver (GD) configured to be spaced apart from one side of the display panel (PN). However, the number and arrangement of gate drivers (GDs) are not limited to this.

[0040] The data driver DD converts image data input from the timing controller TC into a data voltage using a reference gamma voltage, in response to multiple data control signals provided from the timing controller TC. The data driver DD can then supply the converted data voltage to multiple data lines DL.

[0041] The timing controller TC aligns the externally input image data and supplies the image data to the data driver DD. The timing controller TC can generate gate control signals and data control signals using synchronization signals from external inputs (i.e., dot clock signals, data enable signals, and horizontal / vertical synchronization signals). Furthermore, the timing controller TC can control the gate driver GD and the data driver DD by supplying the generated gate control signals and data control signals to them.

[0042] The display panel PN is configured to display an image to the user and includes multiple subpixels SP. In the display panel PN, multiple scan lines SL and multiple data lines DL intersect each other, and each of the multiple subpixels SP is connected to both the scan lines SL and the data lines DL. Additionally, although not shown in the accompanying drawings, the multiple subpixels SP can be individually connected to high-potential power lines, low-potential power lines, reference lines, etc.

[0043] The display panel PN can have a display area AA and a non-display area NA configured to surround the display area AA.

[0044] The display area AA is the area of ​​the display device 100 that displays an image. The display area AA may include multiple sub-pixels SP constituting multiple pixels PX and circuitry configured to operate the multiple sub-pixels SP. The multiple sub-pixels SP are the smallest unit constituting the display area AA. n sub-pixels SP can constitute one pixel PX. Light-emitting elements, thin-film transistors for operating the light-emitting elements, etc., may be provided in each of the multiple sub-pixels SP. The multiple light-emitting elements may be defined differently depending on the type of the display panel PN. For example, in the case where the display panel PN is an inorganic light-emitting display panel, the light-emitting elements may be light-emitting diodes (LEDs) or micro LEDs.

[0045] Multiple signal lines for transmitting various types of signals to multiple sub-pixels SP are provided in the display area AA. For example, the multiple signal lines may include multiple data lines DL for supplying data voltage to the multiple sub-pixels SP and multiple scan lines SL for supplying gate voltage to the multiple sub-pixels SP. The multiple scan lines SL may extend in one direction within the display area AA and connect to the multiple sub-pixels SP. The multiple data lines DL may extend in the display area AA in a direction different from this one direction and connect to the multiple sub-pixels SP. Furthermore, low-potential power lines, high-potential power lines, etc., may be further provided in the display area AA. However, this disclosure is not limited thereto.

[0046] The non-display area NA can be defined as an area where no image is displayed, i.e., an area extending from the display area AA. The non-display area NA may include link lines and pad electrodes for transmitting signals to the sub-pixels SP in the display area AA. Alternatively, the non-display area NA may include driver ICs such as gate driver ICs and data driver ICs. The non-display area NA may be located on the rear surface of the display panel PN, i.e., on the surface where no sub-pixels SP exist. Alternatively, the non-display area NA may not be included. However, this disclosure is not limited to the configuration shown in the accompanying drawings.

[0047] Meanwhile, drivers such as gate driver GD, data driver DD, and timing controller TC can be connected to the display panel PN in various ways. For example, the gate driver GD can be mounted in the non-display area NA using the gate in-panel (GIP) method, or mounted between multiple sub-pixels SP in the display area AA using the gate in active area (GIA) method. For example, the data driver DD and timing controller TC can be formed on separate flexible films and printed circuit boards, and electrically connected to the display panel PN by bonding the flexible film and printed circuit board to pad electrodes formed in the non-display area NA of the display panel PN. When the gate driver GD is mounted using the GIP method and the data driver DD and timing controller TC transmit signals to the display panel PN through the pad electrodes in the non-display area NA, the area of ​​the non-display area NA needs to be ensured to accommodate the gate driver GD and the pad electrodes, which may increase the bezel.

[0048] Alternatively, if the gate driver GD is mounted in the display area AA using the GIA method, and the signal lines on the front side of the display panel PN are connected to the side lines of the pad electrodes on the back side of the display panel PN to bond the flexible film and printed circuit board to the rear surface of the display panel PN, the non-display area NA on the front surface of the display panel PN can be minimized. In other words, if the gate driver GD, data driver DD, and timing controller TC are connected to the display panel PN using the above method, a virtually bezel-less design can be achieved.

[0049] Figure 2 This is an enlarged top plan view of the pixels of a display device according to an embodiment of the present disclosure. Figure 3 It is along Figure 2 The sectional view taken from line III-III' in the middle. Figure 2 Only the first reflective electrode RE1, the second reflective electrode RE1, the first connecting electrode CE1, the second connecting electrode CE2, and the light-emitting element LED of the display device 100 are shown. Figure 3 This is a cross-sectional view showing a first sub-pixel including a first light-emitting element 120. The cross-section of the first sub-pixel including the first light-emitting element 120 is the same as the cross-section of the second sub-pixel including the second light-emitting element 130 and the cross-section of the third sub-pixel including the third light-emitting element 140.

[0050] First, refer to Figure 1 and Figure 3 The display panel PN includes multiple pixels PX, and each pixel PX has multiple subpixels SP. Each subpixel SP may include a light-emitting element LED and pixel circuitry, and emit light independently. A pixel PX may include a first subpixel, a second subpixel, and a third subpixel. For example, a pixel PX may include a first subpixel, a second subpixel, and a third subpixel. In this case, the first subpixel may be a red subpixel, the second subpixel may be a green subpixel, and the third subpixel may be a blue subpixel. However, this disclosure is not limited thereto.

[0051] Multiple light-emitting elements (LEDs) can be disposed in multiple sub-pixels (SPs). Specifically, the multiple light-emitting elements (LEDs) include a first light-emitting element 120, a second light-emitting element 130, and a third light-emitting element 140. The first light-emitting element 120 can be disposed in a first sub-pixel, the second light-emitting element 130 can be disposed in a second sub-pixel, and the third light-emitting element 140 can be disposed in a third sub-pixel. For example, the first light-emitting element 120 can be a red light-emitting element, the second light-emitting element 130 can be a green light-emitting element, and the third light-emitting element 140 can be a blue light-emitting element.

[0052] At the same time, refer to Figure 2The first light-emitting element 120, the second light-emitting element 130, and the third light-emitting element 140 can have different shapes. For example, the planar shape of the first light-emitting element 120 can be circular, and the planar shape of each of the second light-emitting element 130 and the third light-emitting element 140 can be elliptical. In this case, the dimensions of the second light-emitting element 130 and the third light-emitting element 140 can be different, thus having different elliptical shapes. Meanwhile, the second light-emitting element 130 and the third light-emitting element 140 can be identical in the direction of their major axes. However, this disclosure is not limited thereto.

[0053] Simultaneously refer to Figure 3 The first light-emitting element 120 may include a first semiconductor layer 121, a light-emitting layer 122, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and a passivation film 126. Although not shown in the figures, the planar shape of the first semiconductor layer 121 of the first light-emitting element 120 may be circular, and the planar shape of the second semiconductor layer 123 may be semi-circular. The planar shape of the first electrode 124 may be elliptical. The second electrode 125 may have a semi-circular shape, similar to the top surface of the second semiconductor layer 123.

[0054] The second light-emitting element 130 may include a first semiconductor layer, a light-emitting layer, a second semiconductor layer, a first electrode, a second electrode, and a passivation film. Although not shown in the figures, the planar shapes of the first semiconductor layer and the first electrode of the second light-emitting element 130 may be elliptical. In this case, the major axis direction of the first semiconductor layer may be configured to be different from the major axis direction of the first electrode. For example, when the first semiconductor layer is an elliptical shape with a major axis in the horizontal direction, the first electrode may be an elliptical shape with a major axis in the vertical direction. For example, the first electrode may be disposed on the top surface of the first semiconductor layer and disposed at one end of the first semiconductor layer based on the major axis direction. The planar shape of each of the second semiconductor layer and the second electrode may be a cut-out ellipse.

[0055] The third light-emitting element 140 may include a first semiconductor layer, a light-emitting layer, a second semiconductor layer, a first electrode, a second electrode, and a passivation film. Although not shown in the figures, the planar shapes of the first semiconductor layer and the first electrode of the third light-emitting element 140 may be elliptical. Unlike the second light-emitting element, the major axis direction of the first semiconductor layer in the third light-emitting element 140 may be the same as the major axis direction of the first electrode. For example, the first electrode may be disposed on the top surface of the first semiconductor layer and positioned at one end of the first semiconductor layer based on its major axis direction. The planar shape of each of the second semiconductor layer and the second electrode may be a cut-out ellipse.

[0056] In other words, in the display device 100 according to embodiments of the present disclosure, the first light-emitting element 120, the second light-emitting element 130, and the third light-emitting element 140 may have different shapes, making it possible to distinguish multiple light-emitting elements LED. For example, in the process of self-assembling the light-emitting elements LED, the multiple light-emitting elements LED may be formed in different shapes, so that the multiple light-emitting elements LED can self-assemble at positions respectively corresponding to multiple sub-pixels SP. However, the shapes of the multiple light-emitting elements LED are exemplary, and the present disclosure is not limited thereto.

[0057] At the same time, refer to Figure 2 A first contact area CA1, a second contact area CA2, and an illumination inspection area APA can be defined in each of the plurality of pixels PX of the display panel PN of the display device 100 according to an embodiment of the present disclosure.

[0058] The first contact area CA1 and the second contact area CA2 can be regions in which the power line VDD and the third connecting electrode CE3 are electrically connected. For example, in the first contact area CA1, the third connecting electrode CE3 can be electrically connected to the power line via the second reflecting electrode RE2 and the second connecting electrode CE2. In the second contact area CA2, the third connecting electrode CE3 extending from the first contact area CA1 can be additionally connected to the second connecting electrode CE2 extending from the first contact area CA1, so that the third connecting electrode CE3 can be electrically connected to the power line.

[0059] The illumination inspection area (APA) can be an area for transmitting illumination inspection signals to detect defects in the light-emitting element (LED). For example, in the illumination inspection area (APA), the illumination inspection pattern can transmit the illumination inspection signal to the first electrode of the LED via the first connection electrode CE1 without passing through the driving transistor DT. Therefore, whether the driving transistor DT is defective or not, the LED defect can be detected. The following will refer to... Figure 3 Describe the details related to the above configuration.

[0060] Next, refer to Figure 3The substrate 110, buffer layer 111, gate insulating layer 112, first interlayer insulating layer 113a, second interlayer insulating layer 113b, first passivation layer 114a, second passivation layer 114b, outer coating layer 115, bonding layer 116, first planarization layer 117a, second planarization layer 117b, dam 118, third planarization layer 119, driving transistor DT, light-emitting element LED, reflective electrode RE, light blocking layer LS, auxiliary electrode LE, first connecting electrode CE1, second connecting electrode CE2, third connecting electrode CE3, capacitor Cst, intermediate electrode TM, and illumination inspection pattern APP can be disposed in each of a plurality of sub-pixels SP on the display panel PN of the display device 100 according to an embodiment of the present disclosure.

[0061] First, the substrate 110 is a component used to support various constituent elements included in the display device 100, and can be made of an insulating material. For example, the substrate 110 can be made of glass, resin, etc. Furthermore, the substrate 110 can include plastics such as polymers, and can be made of a flexible material.

[0062] A light-blocking layer LS can be disposed on the substrate 110 in each of the plurality of sub-pixels SP. The light-blocking layer LS blocks light from entering the active layer ACT (described below) of the driving transistor DT from the underside of the substrate 110. The light-blocking layer LS can block light entering the active layer ACT of the driving transistor DT, thereby minimizing leakage current.

[0063] A buffer layer 111 can be disposed on the substrate 110 and the light-blocking layer LS. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. For example, the buffer layer 111 can be configured to be made of silicon oxide (SiO2). x ) or silicon nitride (SiN) x The substrate 110 may be made of a single layer or multiple layers. However, this disclosure is not limited thereto. However, depending on the type of substrate 110 or the type of transistor, the buffer layer 111 may not be included. However, this disclosure is not limited thereto.

[0064] The driving transistor DT can be disposed on the buffer layer 111. The driving transistor DT includes an active layer ACT, a gate GE, a source SE, and a drain DE.

[0065] The active layer ACT can be disposed on the buffer layer 111. The active layer ACT can be made of a semiconductor material such as oxide semiconductor, amorphous silicon, or polycrystalline silicon. However, this disclosure is not limited thereto.

[0066] A gate insulating layer 112 can be disposed on the active layer ACT. The gate insulating layer 112 is an insulating layer used to insulate the active layer ACT from the gate GE. The gate insulating layer 112 can be configured to be made of silicon oxide (SiO2).x ) or silicon nitride (SiN) x It can be made of a single layer or multiple layers. However, this disclosure is not limited thereto.

[0067] The gate GE may be disposed on the gate insulating layer 112. The gate GE may be made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof). However, this disclosure is not limited thereto.

[0068] The first interlayer insulating layer 113a and the second interlayer insulating layer 113b can be disposed on the gate GE. Contact holes are formed in the gate insulating layer 112, the first interlayer insulating layer 113a, and the second interlayer insulating layer 113b, through which the source SE and the drain DE are connected to the active layer ACT. The first interlayer insulating layer 113a and the second interlayer insulating layer 113b can be insulating layers for protecting components disposed beneath them, and each is configured to be made of silicon oxide (SiO2). x ) or silicon nitride (SiN) x It can be made of a single layer or multiple layers. However, this disclosure is not limited thereto.

[0069] The source SE and drain DE, electrically connected to the active layer ACT, can be disposed on the second interlayer insulating layer 113b. The source SE and drain DE can each be made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof). However, this disclosure is not limited thereto.

[0070] Furthermore, this disclosure has described a configuration in which a first interlayer insulating layer 113a and a second interlayer insulating layer 113b (i.e., multiple insulating layers) are disposed between the gate GE, the source SE, and the drain DE. However, only a single insulating layer may be disposed between the gate GE, the source SE, and the drain DE. However, this disclosure is not limited thereto.

[0071] Furthermore, although not shown in the accompanying drawings, the pixel circuit may include, in addition to the driving transistor DT, a switching transistor, a sensing transistor, a light-emitting control transistor, etc. However, this disclosure is not limited thereto.

[0072] Meanwhile, the intermediate electrode TM can be disposed on the first interlayer insulating layer 113a. The intermediate electrode TM can be configured to overlap with the gate GE of the driving transistor DT, with the first interlayer insulating layer 113a interposed therebetween, and the intermediate electrode TM and the gate GE of the driving transistor DT together form a capacitor. However, this disclosure is not limited thereto.

[0073] An auxiliary electrode LE can be disposed on the gate insulating layer 112. The auxiliary electrode LE is configured to electrically connect the photoblocking layer LS disposed below the buffer layer 111 to either the source SE or the drain DE of the driving transistor DT on the second interlayer insulating layer 113b. For example, the photoblocking layer LS can be electrically connected to either the source SE or the drain DE of the driving transistor DT via the auxiliary electrode LE to avoid operating as a floating gate, thereby minimizing the threshold voltage variation of the driving transistor DT caused by the floating photoblocking layer LS. The accompanying drawings show the photoblocking layer LS connected to the source SE of the driving transistor DT. However, the photoblocking layer LS can also be connected to the drain DE of the driving transistor DT. However, this disclosure is not limited thereto.

[0074] The capacitor Cst can be disposed on the gate insulating layer 112. The capacitor Cst may include a first capacitor electrode Cst1 and a second capacitor electrode Cst2.

[0075] First, the first capacitor electrode Cst1 can be disposed on the gate insulating layer 112. The first capacitor electrode Cst1 can be disposed on the same layer as the gate GE and made of the same material. However, this disclosure is not limited thereto.

[0076] The second capacitor electrode Cst2 can be disposed on the first interlayer insulating layer 113a. The second capacitor electrode Cst2 can be disposed on the same layer as the intermediate electrode TM and made of the same material. However, this disclosure is not limited thereto. The second capacitor electrode Cst2 can be disposed overlapping the first capacitor electrode Cst1, with the first interlayer insulating layer 113a interposed therebetween. The second capacitor electrode Cst2 can be connected to the source SE of the driving transistor DT.

[0077] The power line VDD can be disposed on the second interlayer insulating layer 113b. The power line VDD can be electrically connected to the light-emitting element LED together with the driving transistor DT, and can enable the light-emitting element LED to emit light. The power line VDD can be made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof). However, this disclosure is not limited thereto.

[0078] A first passivation layer 114a can be disposed on the driving transistor DT and the power line VDD. The first passivation layer 114a can protect the driving transistor DT and the power line VDD from the penetration of moisture or impurities. For example, the first passivation layer 114a can be configured to be made of silicon oxide (SiO2). x ) or silicon nitride (SiN) xIt may be a single layer or multiple layers made of [material name missing]. However, this specification is not limited thereto. However, depending on the type of substrate 110 or the type of transistor, the first passivation layer 114a may not be included. However, this disclosure is not limited thereto.

[0079] An outer coating 115 may be disposed on the first passivation layer 114a. The outer coating 115 may planarize the upper portion of the substrate 110 where the driving transistor DT is disposed. For example, the outer coating 115 may be configured as a single layer or multiple layers and made of photoresist or acrylic-based organic material. However, this disclosure is not limited thereto.

[0080] Multiple reflective electrodes RE, spaced apart from each other, can be disposed on the outer coating 115. The multiple reflective electrodes RE can be used to electrically connect the light-emitting element (LED) to the power line VDD and the driving transistor DT, and also serve as a reflector to reflect light emitted from the LED to the upper part of the LED. Each of the multiple reflective electrodes RE can be made of a conductive material with excellent reflective properties, and will reflect light emitted from the LED towards the upper part of the LED. Therefore, considering light reflection efficiency and resistance, the multiple reflective electrodes RE can include various conductive layers. For example, the reflector can be made using an opaque conductive layer made of silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), or alloys thereof, and a transparent conductive layer made of indium tin oxide (ITO). However, the structure and materials of the reflector RE are not limited to these.

[0081] The plurality of reflective electrodes RE may include a first reflective electrode RE1 and a second reflective electrode RE2. The first reflective electrode RE1 may be electrically connected to the driving transistor DT and the light-emitting element LED. The first reflective electrode RE1 may be connected to the source SE or drain DE of the driving transistor DT through contact holes formed in the first passivation layer 114a and the outer coating layer 115. In addition, the first reflective electrode RE1 may be electrically connected to the first electrode 124 of the light-emitting element LED through the first connection electrode CE1.

[0082] The second reflective electrode RE2 can be electrically connected to the power line VDD and the light-emitting element LED. The second reflective electrode RE2 can be connected to the power line VDD through contact holes formed in the first passivation layer 114a and the outer coating layer 115, and electrically connected to the second electrode 125 of the light-emitting element LED through the second connection electrode CE2 and the third connection electrode CE3, which will be described below.

[0083] On multiple reflective electrodes RE, a bonding layer 116 can be formed on the front surface of the substrate 110 to fix the light-emitting element LED disposed on the bonding layer 116. The bonding layer 116 can be made of a photocurable or thermosetting bonding material that can be cured by light or heat. For example, the bonding layer 116 can be made of an acrylic-based material including a photosensitizer. However, this disclosure is not limited thereto.

[0084] Multiple light-emitting elements (LEDs) can be disposed on the bonding layer 116 and in each of the multiple sub-pixels SP. The multiple LEDs can be elements configured to emit light by using current, and include LEDs configured to emit red, green, blue, etc. The multiple LEDs can achieve light of various colors, including white, by using combinations of red, green, blue, etc. For example, each of the multiple LEDs can be a light-emitting diode (LED) or a micro-LED. However, this disclosure is not limited thereto.

[0085] The first light-emitting element 120 may include a first semiconductor layer 121, a light-emitting layer 122, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and a passivation film 126.

[0086] A first semiconductor layer 121 may be disposed on a bonding layer 116, and a second semiconductor layer 123 may be disposed on the first semiconductor layer 121. The first semiconductor layer 121 and the second semiconductor layer 123 may each be formed by doping a specific material with n-type and p-type impurities. For example, the first semiconductor layer 121 and the second semiconductor layer 123 may each be formed by doping a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs) with n-type and p-type impurities. Furthermore, the p-type impurity may be magnesium, zinc (Zn), beryllium (Be), etc. The n-type impurity may be silicon (Si), germanium, tin (Sn), etc. However, this disclosure is not limited thereto.

[0087] A portion of the first semiconductor layer 121 may be configured to protrude beyond the second semiconductor layer 123. The top surface of the first semiconductor layer 121 may include a portion overlapping the bottom surface of the second semiconductor layer 123 and a portion disposed outside the bottom surface of the second semiconductor layer 123. The light-emitting element LED may be a lateral light-emitting element LED. However, the first semiconductor layer 121 and the second semiconductor layer 123 may be modified in various ways in size and shape. However, this disclosure is not limited thereto.

[0088] For example, the first semiconductor layer 121 may protrude outwards from the second semiconductor layer 123 in one direction. The first semiconductor layer 121 may protrude outwards from the edge of a portion of the second semiconductor layer 123. A portion of the first semiconductor layer 121 may protrude outwards from the second semiconductor layer 123 in a specific direction.

[0089] The light-emitting layer 122 can be disposed between the first semiconductor layer 121 and the second semiconductor layer 123. The light-emitting layer 122 can emit light by receiving positive holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123.

[0090] The light-emitting layer 122 can be configured as a single-layer or multiple quantum well (MQW) structure. For example, the light-emitting layer 122 can be made of indium gallium nitride (InGaN), gallium nitride (GaN), etc. However, this disclosure is not limited thereto.

[0091] The first electrode 124 may be disposed on the first semiconductor layer 121. The first electrode 124 is an electrode that electrically connects the driving transistor DT and the first semiconductor layer 121. In this case, the first semiconductor layer 121 may be a semiconductor layer doped with n-type impurities, and the first electrode 124 may be a cathode. The first electrode 124 may be disposed on the top surface of the first semiconductor layer 121 exposed from the light-emitting layer 122 and the second semiconductor layer 123. For example, the first electrode 124 may be disposed around the top surface of the first semiconductor layer 121, and the planar shape of the first electrode 124 may be annular. The first electrode 124 may be made of a conductive material (e.g., a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof). However, this disclosure is not limited thereto.

[0092] The second electrode 125 can be disposed on the second semiconductor layer 123. The second electrode 125 can be disposed on the top surface of the second semiconductor layer 123. In this case, since the second semiconductor layer 123 is disposed on the first semiconductor layer 121, the second electrode 125 disposed on the top surface of the second semiconductor layer 123 can be disposed at a higher position than the first electrode 124 disposed on the top surface of the first semiconductor layer 121. The second electrode 125 is an electrode used for electrically connecting the power supply line VDD and the second semiconductor layer 123. In this case, the second semiconductor layer 123 can be a semiconductor layer doped with p-type impurities, and the second electrode 125 can be an anode. The second electrode 125 can be made of a conductive material (e.g., a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof). However, this disclosure is not limited thereto.

[0093] Next, the passivation film 126 can be configured to surround the first semiconductor layer 121, the light-emitting layer 122, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. The passivation film 126 can be made of an insulating material and protect the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123. Furthermore, contact holes exposing the first electrode 124 and the second electrode 125 can be formed in the passivation film 126, allowing the subsequently formed first connecting electrode CE1, third connecting electrode CE3, first electrode 124, and second electrode 125 to be electrically connected.

[0094] At the same time, despite Figure 3 As not shown, the second light-emitting element 130 and the third light-emitting element 140 can be arranged in a manner substantially the same as that of the first light-emitting element 120.

[0095] The first planarization layer 117a may be disposed on the bonding layer 116. The first planarization layer 117a may be configured to partially surround the sides of the plurality of light-emitting elements LEDs and fix and protect the plurality of light-emitting elements LEDs.

[0096] For example, the first planarization layer 117a can be configured to surround the passivation film 126 disposed at the lower edge of the light-emitting element LED. Therefore, the disconnection of the first connection electrode CE1 caused by tearing of the passivation film 126 can be suppressed. For example, during the process of separating the light-emitting element LED from the wafer, a portion of the passivation film 126 may tear from the lower edge of the light-emitting element LED. Therefore, a portion of the first semiconductor layer 121 may be exposed at the lower edge of the light-emitting element LED due to the tearing of the passivation film 126. Therefore, a height difference may occur at the lower edge of the light-emitting element LED due to the tearing of the passivation film 126. In this case, if the first connection electrode CE1 is configured to surround the side of the passivation film 126, the first connection electrode CE1 may disconnect due to the height difference caused by the tearing of the passivation film 126.

[0097] Therefore, before the first connecting electrode CE1 is formed, the first planarization layer 117a is configured to surround the lower edge of the light-emitting element LED, such that the lower edge of the light-emitting element LED and the first connecting electrode CE1 can be spaced apart from each other. Thus, even if an undercut structure is formed at the lower edge of the light-emitting element LED due to tearing of the passivation film 126, the first planarization layer 117a fills the undercut structure while contacting at least a portion of the side surface of the light-emitting element LED, which minimizes the disconnection of the first connecting electrode CE1 caused by the undercut structure.

[0098] Simultaneously, the first planarization layer 117a can be configured to be lower than the height of the first electrode 124 and expose the first electrode 124. Therefore, the first connection electrode CE1 disposed on the first planarization layer 117a can be easily connected to the first electrode 124. (Referring to the following...) Figures 4A to 4H Describe in detail the details related to the above configuration.

[0099] Furthermore, the first planarization layer 117a may include a relatively low-height portion in the region adjacent to the light-emitting element LED. For example, during the process of forming the contact holes of the passivation film 126 to expose the first electrode 124 and the second electrode 125, a relatively low-height portion may be included by removing a portion of the first planarization layer 117a in the region adjacent to the light-emitting element LED. Referring below... Figures 4A to 4H Describe in detail the details related to the above configuration.

[0100] For example, the first planarization layer 117a may be configured as a single layer or multiple layers and made of a photoresist or an acrylic-based organic material. However, this disclosure is not limited thereto.

[0101] Simultaneously, the first planarization layer 117a can be lower than the height of the first electrode 124. For example, the thickness of the first planarization layer 117a can be adjusted by performing an ashing process. For example, after coating the material layer of the first planarization layer 117a to cover the light-emitting element LED, an ashing process is performed to reduce the total thickness of the material layer of the first planarization layer 117a, so that the height of the first planarization layer 117a can be lower than the height of the first electrode 124. Therefore, the first planarization layer 117a can expose the first electrode 124. Therefore, the first connection electrode CE1 disposed on the first planarization layer 117a can be easily connected to the first electrode 124 without the need for a separate contact hole. Therefore, the first connection electrode CE3 and the first electrode 124 can be self-aligned without having to ensure process margin.

[0102] The first connecting electrode CE1 can be disposed on the first planarization layer 117a. The first connecting electrode CE1 is an electrode disposed in each of the plurality of sub-pixels SP and configured to electrically connect the light-emitting element LED and the driving transistor DT. The first connecting electrode CE1 can be configured to surround the light-emitting element LED. The first connecting electrode CE1 can be connected to the first reflecting electrode RE1 through contact holes formed in the first planarization layer 117a and the bonding layer 116. Therefore, the first connecting electrode CE1 can be electrically connected to either the source SE or the drain DE of the driving transistor DT through the first reflecting electrode RE1. For example, the first connecting electrode CE1 can connect the first electrode 124 of the light-emitting element LED to the source SE of the driving transistor DT. However, this disclosure is not limited thereto. For example, the first connecting electrode CE1 can be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). However, this disclosure is not limited thereto.

[0103] In the first contact region CA1 and the second contact region CA2, the second connecting electrode CE2 can be disposed on the first planarization layer 117a. The second connecting electrode CE2 is an electrode that electrically connects the light-emitting element LED and the power line VDD. The second connecting electrode CE2 can be connected to the second reflective electrode RE2 through contact holes formed in the first planarization layer 117a and the bonding layer 116. For example, the second connecting electrode CE2 can be electrically connected to the second reflective electrode RE2 through the first contact hole CH1 disposed in the first contact region CA1 of the bonding layer 116 and the second contact hole CH2 of the first planarization layer 117a that overlaps with the first contact hole CH1. Therefore, the second connecting electrode CE2 can be electrically connected to the power line VDD through the second reflective electrode RE2. For example, the second connecting electrode CE2 can connect the second electrode 125 of the light-emitting element LED and the power line VDD. However, this disclosure is not limited thereto.

[0104] Simultaneously, the second connecting electrode CE2 can be disposed on the same layer as the first connecting electrode CE1 and made of the same material. However, this disclosure is not limited thereto. For example, the second connecting electrode CE2 can be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). However, this disclosure is not limited thereto.

[0105] The second passivation layer 114b can be disposed on the plurality of first connecting electrodes CE1 and the plurality of second connecting electrodes CE2. The second passivation layer 114b can be disposed on the plurality of first connecting electrodes CE1 and the plurality of second connecting electrodes CE2, and prevents moisture or impurities from penetrating into the plurality of reflective electrodes RE1 connected to the plurality of first connecting electrodes CE1 and the plurality of second connecting electrodes CE2. For example, the second passivation layer 114b can be configured to be made of silicon oxide (SiO2). x ) or silicon nitride (SiN)x It can be made of a single layer or multiple layers. However, this specification is not limited thereto.

[0106] Furthermore, the second passivation layer 114b can be configured to cover at least a portion of the first connection electrode CE1, allowing the first connection electrode CE1 and the third connection electrode CE3 to be separated from each other. Therefore, the second passivation layer 114b can suppress short circuits between the first connection electrode CE1 and the third connection electrode CE3.

[0107] The second passivation layer 114b may include a first opening OP1 through which the first planarization layer 117a is exposed. For example, the first opening OP1 may be disposed between the first connecting electrode CE1 and the second connecting electrode CE2.

[0108] The second planarization layer 117b can be disposed on the second passivation layer 114b. Together with the first planarization layer 117a, the second planarization layer 117b can planarize the upper part of the substrate 110 where the light-emitting element LED is disposed. Together with the bonding layer 116, the second planarization layer 117b can fix the light-emitting element LED to the substrate 110.

[0109] Furthermore, the second planarization layer 117b can be configured to cover the first connection electrode CE1, allowing the first connection electrode CE1 and the third connection electrode CE3 to be separated from each other. Therefore, short circuits between the first connection electrode CE1 and the third connection electrode CE3 can be suppressed.

[0110] Specifically, the second planarization layer 117b can be configured to cover the end of the first connecting electrode CE1 exposed by the second passivation layer 114b, such that the first connecting electrode CE1 and the third connecting electrode CE3 can be separated from each other. For example, during the process of forming the second planarization layer 117b, the curing process can allow the second planarization layer 117b to flow downwards, i.e., back to the end of the first connecting electrode CE1 exposed by the second passivation layer 114b. Therefore, the height of the portion of the second planarization layer 117b overlapping the end of the first connecting electrode CE1 exposed by the second passivation layer 114b can be relatively low. In other words, the portion of the second planarization layer 117b surrounding the end of the first connecting electrode CE1 can have an inclination.

[0111] For example, the end of the first connecting electrode CE1 that contacts the light-emitting element LED can be exposed by the second passivation layer 114b. Therefore, the height of the second planarization layer 117b can decrease towards the light-emitting element LED. However, since the second planarization layer 117b is configured to cover the end of the first connecting electrode CE1 exposed by the second passivation layer 114b, the height of the lowest end of the top surface of the second planarization layer 117b can be higher than the height of the highest end of the top surface of the end of the first connecting electrode CE1 exposed by the second passivation layer 114b.

[0112] Meanwhile, the second planarization layer 117b can be disposed in the first opening OP1 and cover the ends of the first connecting electrode CE1 and the second connecting electrode CE2, so that the first connecting electrode CE1 and the second connecting electrode CE2 can be separated from each other. Therefore, short circuits between the first connecting electrode CE1 and the second connecting electrode CE2 can be suppressed.

[0113] Specifically, an opening overlapping the first opening OP1 of the second passivation layer 114b can be formed in the second planarization layer 117b, and the curing process allows the second planarization layer 117b to reflow into the first opening OP1. Therefore, the width of the second opening OP2 formed due to the reflow of the second planarization layer 117b can be smaller than the width of the first opening OP1. (Refer to the following...) Figures 4A to 4H Describe the details related to the above configuration.

[0114] The second planarization layer 117b can be configured as a single layer or multiple layers. For example, similar to the first planarization layer 117a, the second planarization layer 117b can be made of a photoresist or an acrylic-based organic material. However, this disclosure is not limited thereto.

[0115] The third connecting electrode CE3 can be disposed on the second planarization layer 117b. The third connecting electrode CE3 is an electrode that electrically connects the light-emitting element LED and the power line VDD. The third connecting electrode CE3 can be connected to the second reflective electrode RE2 through contact holes formed in the second planarization layer 117b, the second passivation layer 114b, the first planarization layer 117a, and the bonding layer 116. Therefore, the third connecting electrode CE3 can be electrically connected to the power line VDD through the second reflective electrode RE2. For example, the third connecting electrode CE3 can connect the second electrode 125 of the light-emitting element LED and the power line VDD. However, this disclosure is not limited thereto. For example, the third connecting electrode CE3 can be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). However, this disclosure is not limited thereto.

[0116] For example, the third connecting electrode CE3 can be disposed in the bonding layer 116 in the first contact hole CH1 in the first contact region CA1, the second contact hole CH2 in the first planarization layer 117a, the third contact hole CH3 in the second passivation layer 114b that overlaps with the first contact hole CH1 and the second contact hole CH2, and the fourth contact hole CH4 in the second planarization layer 117b that overlaps with the first contact hole CH1, the second contact hole CH2, and the third contact hole CH3. The third connecting electrode CE3 can contact the second connecting electrode CE2. Therefore, the third connecting electrode CE3 can be electrically connected to the second reflecting electrode RE2 through the second connecting electrode CE2, and can be electrically connected to the power line VDD through the second reflecting electrode RE2.

[0117] In this configuration, the third connecting electrode CE3 can be additionally electrically connected to the second connecting electrode CE2 in the second contact region CA2. For example, the third connecting electrode CE3 can be continuously disposed in the first contact region CA1 and the second contact region CA2, and electrically connected to the second connecting electrode CE2 extending from the first contact region CA1 through the fifth contact hole CH5 of the second passivation layer 114b disposed in the second contact region CA2 and the sixth contact hole CH6 of the second planarization layer 117b. That is, the third connecting electrode CE3 can receive power supply voltage from the power line VDD through both the second contact region CA2 and the second connecting electrode CE2 in the first contact region CA1. Therefore, the resistance between the power line VDD and the third connecting electrode CE3 can be reduced.

[0118] Specifically, unlike the third contact hole CH3 and the fourth contact hole CH4 in the first contact region CA1, the fifth contact hole CH5 and the sixth contact hole CH6 in the second contact region CA2 may not overlap with the first contact hole CH1 in the bonding layer 116 and the second contact hole CH2 in the first planarization layer 117a. Therefore, the electrical connection between the third connecting electrode CE3 and the second connecting electrode CE2 can be improved by minimizing the defects in the bonding layer 116 and the first planarization layer 117a caused by residual film.

[0119] Furthermore, even if the second connecting electrode CE2 and the third connecting electrode CE3 are not electrically connected to each other in either the first contact region CA1 or the second contact region CA2, they can still be connected in the remaining region. Therefore, the electrical connection between the second connecting electrode CE2 and the third connecting electrode CE3 can be improved.

[0120] Meanwhile, the third connecting electrode CE3 is disposed on the second electrode 125 and is configured to be in direct contact with the second electrode 125, so that during illumination inspection, the illumination inspection signal can be directly transmitted to the second electrode 125 without passing through the driving transistor DT. Therefore, it is not necessary for the driving transistor DT to operate independently, so that defects in the light-emitting element LED can be detected regardless of whether the driving transistor DT is defective.

[0121] Additionally, the third connecting electrode CE3 can be formed before the process of forming the dam 118 described below. Therefore, defects in the light-emitting element LED can be detected before the process of forming the dam 118.

[0122] Meanwhile, the third connecting electrode CE3 can be disposed in the first opening OP1 and the second opening OP2 and configured to contact the second planarization layer 117b. In this case, since the width of the second opening OP2 is smaller than the width of the first opening OP1, the third connecting electrode CE3 may not contact the second passivation layer 114b. However, this disclosure is not limited thereto.

[0123] The illumination inspection pattern APP can be set on the second planarization layer 117b in the illumination inspection area APA. The illumination inspection pattern APP can contact the first connection electrode CE1 through the seventh contact hole CH7 formed in the second passivation layer 114b and the eighth contact hole CH8 formed in the second planarization layer 117b.

[0124] Therefore, the illumination inspection pattern APP can be electrically connected to the first electrode 124 of the light-emitting element LED via the first connection electrode CE1. Therefore, the illumination inspection signal can be directly transmitted to the first electrode 124 of the light-emitting element LED without passing through the driving transistor DT. Therefore, it is not necessary for the driving transistor DT to operate independently, allowing defects in the light-emitting element LED to be detected regardless of whether the driving transistor DT is defective. The illumination inspection pattern APP can be disposed on the same layer as the third connection electrode CE3 and made of the same material. However, this disclosure is not limited thereto. Therefore, similar to the third connection electrode CE3, the illumination inspection pattern APP is formed before the process of forming the dam 118 described below, allowing defects in the light-emitting element LED to be detected before the process of forming the dam 118. For example, the illumination inspection pattern APP can be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). Therefore, the illumination inspection pattern APP can be referred to as a conductive pattern. However, this disclosure is not limited thereto.

[0125] A protective pattern PP can be formed on the second planarization layer 117b. The protective pattern PP can be configured to cover the first reflective electrode RE1 exposed by the contact holes of the bonding layer 116. Therefore, the protective pattern PP can protect the first connecting electrode RE1. For example, the protective pattern PP can be used as a mask during the ashing process of the second planarization layer 117b, so that the ashing process can suppress the oxidation of the first reflective electrode RE1.

[0126] Additionally, the protective pattern PP can be connected to the first connection electrode RE1 and reduce the line resistance of the first connection electrode RE1.

[0127] A dam 118 can be disposed on the second planarization layer 117b, the third connection electrode CE3, and the second illumination inspection pattern APP. Therefore, the dam 118 can be in direct contact with the second planarization layer 117b, the third connection electrode CE3, and the second illumination inspection pattern APP. However, this disclosure is not limited thereto. The dam 118 can be configured not to overlap with the light-emitting element LED, and the dam 118 can define a light-emitting area. For example, the dam 118 can define the light-emitting area by covering the edge of the third connection electrode CE3 connected to the light-emitting element LED. That is, the dam 118 can separate multiple sub-pixels SP. The dam 118 can be made of an insulating material to insulate the second connection electrodes CE3 of adjacent sub-pixels SP. Additionally, the dam 118 can include a black component with high optical absorptivity to suppress color mixing between adjacent sub-pixels SP, and the dam 118 can be configured as a black dam. For example, the dam 118 can be made of polyimide resin, acrylic resin, or benzocyclobutene (BCB) resin. However, this disclosure is not limited thereto.

[0128] The third planarization layer 119 may be disposed on the second planarization layer 117b and the embankment 118. The third planarization layer 119 may be disposed to cover the top surface of the light-emitting element LED and fix and protect the light-emitting element LED, while planarizing the upper part of the substrate 110 where the light-emitting element LED is disposed. Therefore, the third planarization layer 119 may be referred to as a protective layer or a cover layer. However, this disclosure is not limited thereto. For example, the third planarization layer 119 may be configured as a single layer or multiple layers and made of photoresist or acrylic-based organic materials. However, this disclosure is not limited thereto.

[0129] In the following text, reference will be made to Figures 4A to 4H A method for manufacturing a display device according to embodiments of the present disclosure is described.

[0130] Figures 4A to 4H This is a process diagram of a method for manufacturing a display device according to an embodiment of the present disclosure.

[0131] First, refer to Figures 4A to 4HThe light-emitting element LED can be disposed on the bonding layer 116, and the first planarization layer 117a can be disposed on the bonding layer 116 and surround the light-emitting element LED.

[0132] The connecting electrode material layer CE' and the second first passivation material layer 114b' can be sequentially disposed on the front surface of the substrate 110 on the first planarization layer 117a and the light-emitting element LED.

[0133] The connecting electrode material layer CE' can be disposed on the front surface of the substrate 110 and cover the light-emitting element LED and the first planarization layer 117a. Therefore, the connecting electrode material layer CE' can also be disposed in the second contact hole CH2 formed in the first planarization layer 117a and the first contact hole CH1 of the bonding layer 116 that overlaps with the second contact hole CH2. In addition, the connecting electrode material layer CE' can be configured to cover the side and top surfaces of the light-emitting element LED.

[0134] The second-first passivation material layer 114b' can be disposed on the front surface of the substrate 110 on the connecting electrode material layer CE'. The second-first passivation material layer 114b' can be configured to be spaced apart from the light-emitting element LED, the first planarization layer 117a and the bonding layer 116 by the connecting electrode material layer CE'.

[0135] Simultaneously, the second-first passivation material layer 114b' can be formed by a deposition process. In this case, the temperature of the deposition process for the second-first passivation material layer 114b' can be determined by considering the connection electrode material layer CE' disposed below the second-first passivation material layer 114b'. For example, if the connection electrode material layer CE' is made of indium tin oxide (ITO) as a transparent conductive material, the connection electrode material layer CE' may crystallize at approximately 250°C. To suppress crystallization, the deposition process for the second-first passivation material layer 114b' can be performed at a relatively low temperature of approximately 200°C or lower (e.g., approximately 180°C).

[0136] Next, refer to Figure 4BA second-first planarization material layer 117b' can be disposed on and surrounding the second-first passivation material layer 114b'. The height of the second-first planarization material layer 117b' can be lower than the height of the second electrode 125 of the light-emitting element LED. For example, the thickness of the second-first planarization material layer 117b' can be adjusted by performing an ashing process. For example, after coating the second-first planarization material layer 117b' to cover the light-emitting element LED, an ashing process is performed to reduce the total thickness of the second-first planarization material layer 117b', such that the height of the second-first planarization material layer 117b' can be lower than the height of the second electrode 125. Therefore, during subsequent processes, the third connecting electrode CE3 disposed on the second-first planarization material layer 117b' can be easily connected to the second electrode 125.

[0137] Simultaneously, an initial second opening OP2' can be formed in the second-first planarization material layer 117b'. The initial second opening OP2' can expose the second-first passivation material layer 114b'.

[0138] Next, refer to Figure 4C The second-second passivation material layer 114b'' can be formed by etching the second-first passivation material layer 114b'. The second-second passivation material layer 114b'' can be formed by etching the second-first passivation material layer 114b' exposed from the second-first planarization material layer 117b'.

[0139] For example, since the thickness of the second-first planarization material layer 117b' is less than the thickness of the light-emitting element LED, the second-first passivation material layer 114b' covering the upper side of the light-emitting element LED can be exposed from the second-first planarization material layer 117b'.

[0140] Furthermore, because the second-first planarization material layer 117b' opens in the initial second opening OP2', the second-first passivation material layer 114b' overlapping with the initial second opening OP2' can be exposed from the second-first planarization material layer 117b'. Therefore, the second-second passivation material layer 114b'' can be formed by etching the portion of the second-first passivation material layer 114b' covering the upper side of the light-emitting element LED and the portion of the second-first passivation material layer 114b' overlapping with the initial second opening OP2'. Therefore, the first opening OP1 overlapping with the initial second opening OP2' can be formed in the second-second passivation material layer 114b''.

[0141] For example, the second-second passivation material layer 114b'' can be formed by a wet etching process. Therefore, not only can the portion of the second-first passivation material layer 114b' exposed by the second-first planarization material layer 117b' be partially removed, but the portion of the second-first passivation material layer 114b' overlapping with the second-first planarization material layer 117b' can also be partially removed. Therefore, the end of the second-second passivation material layer 114b'' can be located inside the end of the second-first planarization material layer 117b'. Therefore, the width of the first opening OP1 can be greater than the width of the initial second opening OP2'. However, this disclosure is not limited thereto.

[0142] Simultaneously, the second-second planarization material layer 117b'' ​​can be formed by etching a portion of the second-first planarization material layer 117b' during the etching process of the second-second passivation material layer 114b''. For example, a portion of the second-first planarization material layer 117b' adjacent to the light-emitting element LED can also be etched. However, this disclosure is not limited thereto.

[0143] Next, refer to Figure 4D The first connecting electrode CE1, the second connecting electrode CE2, and the protective pattern PP can be formed by etching the connecting electrode material layer CE'. The first connecting electrode CE1, the second connecting electrode CE2, and the protective pattern PP can be formed by etching the connecting electrode material layer CE' exposed from the second-first planarization material layer 117b' and the second-second passivation material layer 114b''.

[0144] Specifically, the second-second planarization material layer 117b'' ​​opens in the initial second opening OP2', and the second-second passivation material layer 114b'' opens in the first opening OP1, such that the connection electrode material layer CE' overlapping with the initial second opening OP2' and the first opening OP1 can be exposed from the second-second planarization material layer 117b'' ​​and the second-second passivation material layer 114b''. Therefore, the first connection electrode CE1, the second connection electrode CE2, and the protective pattern PP can be formed by etching the portion of the connection electrode material layer CE' that overlaps with the initial second opening OP2' and the first opening OP1.

[0145] For example, the first connecting electrode CE1, the second connecting electrode CE2, and the protective pattern PP can be formed by a wet etching process. Therefore, not only can the portion of the connecting electrode material layer CE' exposed to the second-second planarization material layer 117b'' ​​and the second-second passivation material layer 114b'' be partially removed, but also the portion of the connecting electrode material layer CE' overlapping with the second-second planarization material layer 117b'' ​​and the second-second passivation material layer 114b'' can be partially removed. Therefore, the ends of the first connecting electrode CE1, the second connecting electrode CE2, and the protective pattern PP can be located inside the ends of the second-second planarization material layer 117b'' ​​and the second-second passivation material layer 114b''. However, this disclosure is not limited to this.

[0146] Simultaneously, the second-third passivation layer 114b''' can also be formed by etching a portion of the second-second passivation material layer 114b''. For example, not only can the connection electrode material layer CE' disposed on the side of the light-emitting element LED be exposed by the second-second planarization material layer 117b'', but the second-second passivation material layer 114b'' can also be exposed by the second-second planarization material layer 117b''. Therefore, the second-third passivation layer 114b''' can be formed by removing a portion of the second-second passivation material layer 114b''' disposed on the side of the light-emitting element LED.

[0147] Simultaneously, the portion of the second-second passivation material layer 114b'' adjacent to the light-emitting element LED is removed, so that the end of the first connecting electrode CE1 that contacts the light-emitting element LED can be exposed by the second-third passivation layer 114b'''. However, this disclosure is not limited thereto.

[0148] Next, refer to Figure 4E The second-third planarization material layer 117b''' can be formed by partially graying (e.g., halftone graying) the second-second planarization material layer 117b''.

[0149] For example, the portion of the second-second planarization material layer 117b'' ​​that overlaps with the second connecting electrode CE2 can be partially ashed. For example, an initial fourth contact hole CH4' can be formed by ashing the portion of the second-second planarization material layer 117b'' ​​that overlaps with the first contact hole CH1 and the second contact hole CH2. Therefore, the initial fourth contact hole CH4' can overlap with the first contact hole CH1 and the second contact hole CH2. The initial fourth contact hole CH4' can be disposed on the second connecting electrode CE2, such that the third connecting electrode CE3 and the second connecting electrode CE2 are connected during subsequent processes.

[0150] Furthermore, an initial sixth contact hole CH6' can be formed by ashing the portion of the second-second planarization material layer 117b'' ​​that overlaps with the second connecting electrode CE2 but not with the first contact hole CH1 and the second contact hole CH2. The initial sixth contact hole CH6' can be provided on the second connecting electrode CE2, allowing the third connecting electrode CE3 and the second connecting electrode CE2 to be additionally connected during subsequent processes.

[0151] Furthermore, an initial eighth contact hole CH8' can be formed by partially ashing the portion of the second-second planarization material layer 117b'' ​​that overlaps with the first connecting electrode CE1. The initial eighth contact hole CH8' allows the illumination inspection pattern APP and the first connecting electrode CE1 to be connected during subsequent processes.

[0152] Next, refer to Figure 4F The second passivation layer 114b can be formed by etching the second-third passivation material layer 114b'''. The second passivation layer 114b can be formed by etching the second-third passivation material layer 114b''' exposed from the second-third planarization material layer 117b'''.

[0153] For example, because the second-third planarization material layer 117b''' opens in the initial fourth contact hole CH4', the initial sixth contact hole CH6', and the initial eighth contact hole CH8', the second-third passivation material layer 114b''' overlapping with the initial fourth contact hole CH4', the initial sixth contact hole CH6', and the initial eighth contact hole CH8' can be exposed from the second-third planarization material layer 117b'''. Therefore, the second passivation layer 114b can be formed by etching the second-third passivation material layer 114b''' exposed by the initial fourth contact hole CH4', the initial sixth contact hole CH6', and the initial eighth contact hole CH8'. Therefore, a third contact hole CH3 overlapping with the initial fourth contact hole CH4', a fifth contact hole CH5 overlapping with the initial sixth contact hole CH6', and a seventh contact hole CH7 overlapping with the initial eighth contact hole CH8' can be formed in the second passivation layer 114b.

[0154] For example, the second passivation layer 114b can be formed by a dry etching process. Therefore, unlike a wet etching process, the portion of the second-third passivation material layer 114b''' that overlaps with the second-third planarization material layer 117b''' can be left unremoved; instead, only the portion of the second-third passivation material layer 114b''' exposed by the second-third planarization material layer 117b''' can be removed. Therefore, the ends of the portions of the second passivation layer 114b open through the third contact hole CH3, the fifth contact hole CH5, and the seventh contact hole CH7 can coincide with the ends of the portions of the second-third planarization material layer 117b''' that open through the initial fourth contact hole CH4', the initial sixth contact hole CH6', and the initial eighth contact hole CH8'. However, this disclosure is not limited thereto.

[0155] Next, refer to Figure 4G The second planarization layer 117b can be formed by curing the second-third planarization material layer 117b'''. Specifically, the curing process allows the second-third planarization material layer 117b''' to be reflowed, so that the second-third planarization material layer 117b''' can cover the end of the second passivation layer 114b disposed below the second-third planarization material layer.

[0156] Specifically, the second-third planarization material layer 117b''', opened through the initial fourth contact hole CH4', can be reflowed and disposed in the third contact hole CH3. Therefore, the second planarization layer 117b can be configured to cover the end of the second passivation layer 114b opened through the third contact hole CH3. Therefore, the width of the fourth contact hole CH4 can be smaller than the width of the third contact hole CH3.

[0157] The second and third planarization material layers 117b''', opened through the initial sixth contact hole CH6', can be reflowed and disposed in the fifth contact hole CH5. Therefore, the second planarization layer 117b can be configured to cover the end of the second passivation layer 114b opened through the fifth contact hole CH5. Therefore, the width of the sixth contact hole CH6 can be smaller than the width of the fifth contact hole CH5.

[0158] The second-third planarization material layer 117b''', opened through the initial eighth contact hole CH8', can be reflowed and disposed in the seventh contact hole CH7. Therefore, the second planarization layer 117b can be configured to cover the end of the second passivation layer 114b open through the seventh contact hole CH7. Therefore, the width of the eighth contact hole CH8 of the second planarization layer 117b can be smaller than the width of the seventh contact hole CH7.

[0159] The second-third planarization material layer 117b''', opened through the initial second opening OP2', can be reflowed and disposed within the first opening OP1. Therefore, the second planarization layer 117b can be configured to cover the end of the second passivation layer 114b opened through the first opening OP1. Consequently, the width of the second opening OP2' of the second planarization layer 117b can be smaller than the width of the first opening OP1.

[0160] Simultaneously, the second planarization layer 117b can flow back to the first opening OP1 and be disposed on the first planarization layer 117a that overlaps with the first opening OP1. In this case, since the first opening OP1 is disposed between the first connecting electrode CE1 and the second connecting electrode CE2, the second planarization layer 117b can be configured to cover the ends of the first connecting electrode CE1 and the second connecting electrode CE2. Therefore, the second planarization layer 117b allows the first connecting electrode CE1 and the second connecting electrode CE2 to be separated.

[0161] Specifically, the second planarization layer 117b can be configured to cover not only the end of the second passivation layer 114b, but also the end of the first connection electrode CE1 exposed by the second passivation layer 114b. Therefore, the second planarization layer 117b allows the first connection electrode CE1 and the third connection electrode CE3 to be separated from each other during subsequent processes.

[0162] Specifically, as described above, the end of the first connecting electrode CE1 that contacts the light-emitting element LED can be exposed by the second passivation layer 114b. In this case, the curing process allows the second planarization layer 117b to be reflowed, so that the second planarization layer 117b can be disposed on the end of the first connecting electrode CE1 exposed by the second passivation layer 114b. Therefore, the second planarization layer 117b can be reflowed and cover the end of the first connecting electrode CE1 that contacts the light-emitting element LED. Therefore, the height of the second planarization layer 117b can be reduced toward the light-emitting element LED. The second planarization layer 117b can be configured to cover the end of the first connecting electrode CE1 and the end of the second passivation layer 114b, which are configured to surround a portion of the side surface of the light-emitting element LED. The tilt direction of the end of the first connecting electrode CE1 and the end of the second passivation layer 114b on the side surface of the light-emitting element LED can be the same as the tilt direction of the second planarization layer 117b covering the end of the first connecting electrode CE1 and the end of the second passivation layer 114b. The second planarization layer 117b and the light-emitting element LED can be defined in a "V" shape at the portion of the second planarization layer 117b that contacts the side of the light-emitting element LED. (See reference...) Figure 3 and Figure 4HThe side of the light-emitting element LED can be the left side, the right side, or both the left and right sides of the light-emitting element LED.

[0163] Next, refer to Figure 4H The third connecting electrode CE3 and the illumination inspection pattern APP can be disposed on the second planarization layer 117b and spaced apart from each other. The third connecting electrode CE3 can be disposed on the light-emitting element LED, and the illumination inspection pattern APP can be disposed to overlap with the eighth contact hole CH8.

[0164] As described above, the second planarization layer 117b is formed by performing only an ashing process until the second electrode 125 of the light-emitting element LED is exposed. The third connection electrode CE3 disposed on the second planarization layer 117b may only contact the top surface of the second electrode 125 exposed from the second planarization layer 117b, and the third connection electrode CE3 may be spaced apart from the first connection electrode CE1, the light-emitting layer 122, and the first semiconductor layer 121 disposed below the second planarization layer 117b. Therefore, the third connection electrode CE3 and the second electrode 125 can be self-aligned without ensuring process margin.

[0165] Meanwhile, the illumination inspection pattern APP can be disposed on the second planarization layer 117b in the seventh contact hole CH7 and the eighth contact hole CH8, and electrically connected to the first connection electrode CE1 exposed by the seventh contact hole CH7 and the eighth contact hole CH8.

[0166] In this configuration, an illumination check can be performed. For example, an illumination check signal can be applied to the illumination check pattern APP and the third connecting electrode CE3. Therefore, the illumination check signal applied through the illumination check pattern APP can be transmitted to the first electrode 124 of the light-emitting element LED via the first connecting electrode CE1. The illumination check signal applied through the third connecting electrode CE3 can be transmitted to the second electrode 125 of the light-emitting element LED. Thus, regardless of whether the driving transistor DT is defective, a defect in the light-emitting element LED can be detected.

[0167] Next, a dam 118 and a third planarization layer 119 are formed on the second planarization layer 117b, the third connecting electrode CE3, and the illumination inspection pattern APP, thereby completing the process of manufacturing the display device 100.

[0168] During the process of setting or transferring multiple light-emitting elements onto a substrate, some light-emitting elements may be misaligned or incorrectly positioned. In such cases, if subsequent processes are performed with some light-emitting elements misaligned or incorrectly positioned, short-circuit defects between electrodes may occur. For example, if light-emitting elements are misaligned and the same electrodes are connected to the first and second electrodes of the light-emitting element, or if the electrodes connected to the first and second electrodes of the light-emitting element are set to overlap instead of being separated, a short-circuit defect occurs, and the light-emitting element may not emit light properly.

[0169] Therefore, in the display device 100 according to an embodiment of the present disclosure, the first connecting electrode CE1 and the first electrode 124 of the light-emitting element LED can be self-aligned and connected. For example, after coating the material layer of the first planarization layer 117a to cover the light-emitting element LED, the material layer of the first planarization layer 117a is ashed so that the first electrode 124 can be exposed. Therefore, the first connecting electrode CE1 disposed on the first planarization layer 117a can be easily connected to the first electrode 124 without a separate contact hole. Therefore, the first connecting electrode CE1 and the first electrode 124 can be self-aligned without ensuring process margin. Therefore, short-circuit defects of the first connecting electrode CE1 and the third connecting electrode CE3 caused by process errors can be minimized.

[0170] Similarly, in the display device 100 according to an embodiment of the present disclosure, the third connecting electrode CE3 and the second electrode 125 of the light-emitting element LED can be self-aligned and connected. For example, after coating a material layer of the second planarization layer 117b to cover the second semiconductor layer 123 and the second electrode 125 of the light-emitting element LED, the material layer of the second planarization layer 117b is ashed so that only the second electrode 125 can be exposed. Therefore, even if the second connecting electrode CE2 is formed by forming and patterning a material layer of the second connecting electrode CE2 on the front surface of the substrate 110 including the second planarization layer 117b, the second connecting electrode CE2 can only contact the top surface of the second electrode 125 exposed from the second planarization layer 117b. That is, the third connecting electrode CE3 and the second electrode 125 can be self-aligned without ensuring process margin. Therefore, short-circuit defects of the first connecting electrode CE1 and the third connecting electrode CE3 caused by process errors can be minimized.

[0171] Furthermore, in the display device 100 according to an embodiment of the present disclosure, a second passivation layer 114b may be disposed on the first connecting electrode CE1 and the second connecting electrode CE2. Because the second passivation layer 114b is configured to cover at least a portion of the first connecting electrode CE1, the second passivation layer 114b, together with the second planarization layer 117b, allows the first connecting electrode CE1 and the third connecting electrode CE3 to be separated from each other. Therefore, the second passivation layer 114b can suppress short circuits between the first connecting electrode CE1 and the third connecting electrode CE3.

[0172] Furthermore, the second passivation layer 114b is made of an inorganic insulating material, which can inhibit moisture or impurities from penetrating into the multiple reflective electrodes RE connected to the multiple first connecting electrodes CE1 and the multiple second connecting electrodes CE2. Therefore, separation and corrosion of the multiple reflective electrodes RE caused by moisture penetration can be suppressed.

[0173] Specifically, in the display device 100 according to an embodiment of the present disclosure, when the first connection electrode CE1 is exposed by the second passivation layer 114b, the second planarization layer 117b flows back onto the exposed first connection electrode CE1, allowing the first connection electrode CE1 and the third connection electrode CE3 to be separated. For example, the curing process allows the second planarization layer 117b to flow back, so that the second planarization layer 117b can be configured to cover the first connection electrode CE1 exposed by the second passivation layer 114b. Therefore, in the display device 100 according to an embodiment of the present disclosure, even if the first connection electrode CE1 is exposed by the second passivation layer 114b during the process, the second planarization layer 117b can flow back, allowing the first connection electrode CE1 and the third connection electrode CE3 to be separated, which can suppress short-circuit defects in the connection between the first connection electrode CE1 and the third connection electrode CE3.

[0174] Exemplary embodiments of this disclosure can also be described as follows: According to one aspect of this disclosure, a display device is provided. The display device includes: a substrate defining a plurality of sub-pixels; a power line and a driving transistor disposed on the substrate; a first reflective electrode and a second reflective electrode disposed on the power line and the driving transistor and spaced apart from each other, the first reflective electrode being connected to the driving transistor and the second reflective electrode being connected to the power line; a bonding layer disposed on the first reflective electrode and the second reflective electrode; a plurality of light-emitting elements disposed on the bonding layer in the plurality of sub-pixels, and each including a first electrode and a second electrode; a first planarization layer disposed on the bonding layer and configured to partially surround the sides of the plurality of light-emitting elements; a first connecting electrode disposed on the first planarization layer and configured to connect the first electrode and the driving transistor; a second connecting electrode disposed on the first planarization layer, spaced apart from the first connecting electrode, and connected to the second reflective electrode; a passivation layer disposed on the first connecting electrode and the second connecting electrode; a second planarization layer disposed on the passivation layer and configured to partially surround the sides of the plurality of light-emitting elements; and a third connecting electrode disposed on the second planarization layer and configured to connect the second electrode and the power line. The passivation layer exposes the end of the first connection electrode, which is positioned to surround a portion of the side of the light-emitting element. A second planarization layer covers the end of the first connection electrode.

[0175] The second planarization layer can be configured to cover the end of the first connecting electrode and the end of the passivation layer corresponding to the end of the first connecting electrode.

[0176] The tilt direction of the end of the first connecting electrode and the end of the passivation layer disposed on the side of the light-emitting element can be the same as the tilt direction of the second planarization layer covering the end of the first connecting electrode and the end of the passivation layer. The second planarization layer can define a "V" shape in the area contacting the light-emitting element.

[0177] The height of the portion of the second planarization layer that overlaps with the end of the first connecting electrode can be lower than the height of the portion of the second planarization layer that does not overlap with the end of the first connecting electrode.

[0178] The passivation layer may include a first opening that exposes the first planarization layer. The second planarization layer may include a second opening that overlaps with the first opening. The width of the first opening may be greater than the width of the second opening. The second planarization layer may be disposed in the first opening and may cover the other end of the first connecting electrode and the end of the second connecting electrode.

[0179] The third connecting electrode can be disposed in the first opening and the second opening, and is configured to contact the first planarization layer.

[0180] The bonding layer may include a first contact hole exposing the second reflective electrode. The first planarization layer may include a second contact hole overlapping the first contact hole and exposing the second reflective electrode. A second connecting electrode may be disposed in the first and second contact holes and may contact the second reflective electrode. The passivation layer may include a third contact hole overlapping the first and second contact holes and exposing the second connecting electrode. The second planarization layer may include a fourth contact hole overlapping the first, second, and third contact holes and exposing the second connecting electrode. A third connecting electrode may be disposed in the first, second, third, and fourth contact holes and may contact the second connecting electrode.

[0181] The width of the third contact hole can be greater than the width of the fourth contact hole. The second planarization layer can be disposed in the third contact hole and can cover the end of the passivation layer.

[0182] The bonding layer may include a first contact hole exposing the second reflective electrode. The first planarization layer may include a second contact hole overlapping the first contact hole and exposing the second reflective electrode. A second connecting electrode may be disposed in the first and second contact holes and may contact the second reflective electrode. The passivation layer may include a fifth contact hole exposing the second connecting electrode without overlapping the first and second contact holes. The second planarization layer may include a sixth contact hole overlapping the fifth contact hole. A third connecting electrode may be disposed in the fifth and sixth contact holes and may contact the second connecting electrode.

[0183] The width of the fifth contact hole can be greater than the width of the sixth contact hole. The second planarization layer can be disposed in the fifth contact hole and can cover the end of the passivation layer.

[0184] The display device may further include a conductive pattern disposed on a second planarization layer. The passivation layer may include a seventh contact hole exposing a first connection electrode. The second planarization layer may include an eighth contact hole overlapping the seventh contact hole. The conductive pattern can be connected to the first connection electrode through the seventh and eighth contact holes.

[0185] The width of the seventh contact hole can be greater than the width of the eighth contact hole. The second planarization layer can be disposed in the seventh contact hole and can cover the end of the passivation layer.

[0186] The height of the first planarization layer can be lower than the height of the first electrode, and the height of the second planarization layer can be lower than the height of the second electrode.

[0187] The sides of multiple light-emitting elements can be any one or both of the two sides of the multiple light-emitting elements.

[0188] According to another aspect of this disclosure, a display device is provided. The display device includes: a substrate defining a plurality of pixels, each of the plurality of pixels including a plurality of sub-pixels; a power line and a driving transistor disposed on the substrate; a first reflective electrode and a second reflective electrode disposed on the power line and the driving transistor and spaced apart from each other, the first reflective electrode connected to the driving transistor and the second reflective electrode connected to the power line; a bonding layer disposed on the first reflective electrode and the second reflective electrode; a plurality of light-emitting elements disposed on the bonding layer in the plurality of sub-pixels, each including a first electrode and a second electrode; a first planarization layer disposed on the bonding layer and configured to partially surround the sides of the plurality of light-emitting elements; a first connecting electrode disposed on the first planarization layer and configured to connect the first electrode and the driving transistor; a second connecting electrode disposed on the first planarization layer, spaced apart from the first connecting electrode and connected to the second reflective electrode; a passivation layer disposed on the first connecting electrode and the second connecting electrode; a second planarization layer disposed on the passivation layer and the height of the second planarization layer decreasing toward the plurality of light-emitting elements; and a third connecting electrode disposed on the second planarization layer and configured to connect the second electrode and the power line.

[0189] The passivation layer may surround multiple light-emitting elements and may expose a portion of the first connection electrode. The height of the lowest point of the top surface of the second planarization layer may be higher than the height of the highest point of the top surface of the exposed portion of the first connection electrode.

[0190] The passivation layer may include an opening that exposes the first planarization layer. The second planarization layer may include an opening that overlaps with the opening of the passivation layer, and the width of the opening of the second planarization layer may be smaller than the width of the opening of the passivation layer. The second planarization layer may be disposed in the opening of the passivation layer and may separate the first connection electrode and the second connection electrode.

[0191] Each of the multiple pixels may include a first region in which a third connection electrode and a power line can be electrically connected, and a second region spaced apart from the first region. The third connection electrode in the first region can be connected to the power line via a second reflective electrode and a second connection electrode. The third connection electrode in the second region can be connected to the power line via a second connection electrode extending from the first region.

[0192] The bonding layer may include contact holes disposed in the first region and exposing the second reflective electrode. The first planarization layer may include contact holes disposed in the first region and overlapping with the contact holes of the bonding layer. The second connecting electrode can be connected to the second reflective electrode through the contact holes of the first planarization layer and the contact holes of the bonding layer.

[0193] The passivation layer may include a first region that overlaps with the contact holes of the first planarization layer and the bonding layer, and exposes the contact holes of the second connection electrode. The second planarization layer may include a first region that overlaps with the contact holes of the first planarization layer, the bonding layer, and the passivation layer, and exposes the contact holes of the second connection electrode. The third connection electrode can be connected to the second connection electrode through the contact holes of the second planarization layer, the passivation layer, the first planarization layer, and the bonding layer.

[0194] The passivation layer may further include contact holes disposed in the second region and exposing a second connection electrode extending from the first region. The second planarization layer may further include contact holes disposed in the second region and exposing a second connection electrode extending from the first region. The third connection electrode can be connected to the second connection electrode through the contact holes of the passivation layer in the second region and the contact holes of the second planarization layer.

[0195] The display device may further include an illumination inspection area disposed in each of a plurality of pixels, wherein an illumination inspection pattern is disposed on a second planarization layer in the illumination inspection area. A passivation layer may include contact holes disposed in the illumination inspection area and exposing a first connection electrode. The second planarization layer may include contact holes overlapping with the contact holes of the passivation layer and exposing contact holes of the first connection electrode. The first illumination inspection pattern may be connected to the first connection electrode through the contact holes of the second planarization layer and the contact holes of the passivation layer.

[0196] The height of the passivation layer and the first connecting electrode can also be reduced towards multiple light-emitting elements.

[0197] The sides of multiple light-emitting elements can be any one or both of the two sides of the multiple light-emitting elements.

[0198] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be construed as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: A substrate, on which a plurality of sub-pixels are defined; Power lines and drive transistors are disposed on the substrate; A first reflective electrode and a second reflective electrode are disposed on the power line and the driving transistor and spaced apart from each other. The first reflective electrode is connected to the driving transistor and the second reflective electrode is connected to the power line. A bonding layer is disposed on the first reflective electrode and the second reflective electrode; Multiple light-emitting elements are respectively disposed in the multiple sub-pixels on the bonding layer, and each includes a first electrode and a second electrode; A first planarization layer is disposed on the bonding layer and configured to partially surround the sides of the plurality of light-emitting elements; A first connection electrode is disposed on the first planarization layer and configured to connect the first electrode and the driving transistor; The second connecting electrode is disposed on the first planarization layer, spaced apart from the first connecting electrode, and connected to the second reflective electrode; A passivation layer is disposed on the first connection electrode and the second connection electrode; A second planarization layer is disposed on the passivation layer and configured to partially surround the sides of the plurality of light-emitting elements; as well as A third connection electrode is disposed on the second planarization layer and configured to connect the second electrode and the power line. The passivation layer exposes the end of the first connection electrode that is configured to surround a portion of the side surface of the light-emitting element, and The second planarization layer covers the end of the first connecting electrode.

2. The display device according to claim 1, wherein, The second planarization layer is configured to cover the end of the first connection electrode and the end of the passivation layer corresponding to the end of the first connection electrode.

3. The display device according to claim 2, wherein, The inclination direction of the end of the first connecting electrode and the end of the passivation layer disposed on the side of the light-emitting element is the same as the inclination direction of the second planarization layer covering the end of the first connecting electrode and the end of the passivation layer, and The second planarization layer defines a "V" shape in the region that contacts the light-emitting element.

4. The display device according to claim 1, wherein, The height of the portion of the second planarization layer that overlaps with the end of the first connecting electrode is lower than the height of the portion of the second planarization layer that does not overlap with the end of the first connecting electrode.

5. The display device according to claim 1, wherein, The passivation layer includes a first opening that exposes the first planarization layer. The second planarization layer includes a second opening that overlaps with the first opening. Wherein, the width of the first opening is greater than the width of the second opening, and The second planarization layer is disposed in the first opening and covers the other end of the first connecting electrode and the end of the second connecting electrode.

6. The display device according to claim 1, wherein, The third connecting electrode is disposed in the first opening and the second opening, and is configured to contact the first planarization layer.

7. The display device according to claim 1, wherein, The bonding layer includes a first contact hole that exposes the second reflective electrode. The first planarization layer includes a second contact hole that overlaps with the first contact hole and exposes the second reflective electrode. The second connecting electrode is disposed in both the first contact hole and the second contact hole, and contacts the second reflective electrode. The passivation layer includes a third contact hole that overlaps with the first and second contact holes and exposes the second connection electrode. The second planarization layer includes a fourth contact hole that overlaps with the first contact hole, the second contact hole, and the third contact hole and exposes the second connection electrode. The third connecting electrode is disposed in the first contact hole, the second contact hole, the third contact hole and the fourth contact hole, and contacts the second connecting electrode.

8. The display device according to claim 7, wherein, The width of the third contact hole is greater than the width of the fourth contact hole, and The second planarization layer is disposed in the third contact hole and covers the end of the passivation layer.

9. The display device according to claim 1, wherein, The bonding layer includes a first contact hole that exposes the second reflective electrode. The first planarization layer includes a second contact hole that overlaps with the first contact hole and exposes the second reflective electrode. The second connecting electrode is disposed in both the first contact hole and the second contact hole, and contacts the second reflective electrode. The passivation layer includes a fifth contact hole that exposes the second connection electrode without overlapping with the first and second contact holes. The second planarization layer includes a sixth contact hole that overlaps with the fifth contact hole, and The third connecting electrode is disposed in the fifth contact hole and the sixth contact hole and contacts the second connecting electrode.

10. The display device according to claim 9, wherein, The width of the fifth contact hole is greater than the width of the sixth contact hole, and The second planarization layer is disposed in the fifth contact hole and covers the end of the passivation layer.

11. The display device according to claim 1, further comprising: A conductive pattern is disposed on the second planarization layer. The passivation layer includes a seventh contact hole that exposes the first connection electrode. The second planarization layer includes an eighth contact hole that overlaps with the seventh contact hole, and The conductive pattern is connected to the first connecting electrode through the seventh contact hole and the eighth contact hole.

12. The display device according to claim 11, wherein, The width of the seventh contact hole is greater than the width of the eighth contact hole, and The second planarization layer is disposed in the seventh contact hole and covers the end of the passivation layer.

13. The display device according to claim 1, wherein, The height of the first planarization layer is lower than the height of the first electrode, and the height of the second planarization layer is lower than the height of the second electrode.

14. The display device according to claim 1, wherein, The side surface of the plurality of light-emitting elements is any one or both of the two sides of the plurality of light-emitting elements.

15. A display device, comprising: A substrate having a plurality of pixels defined thereon, each of the plurality of pixels including a plurality of sub-pixels; Power lines and drive transistors are disposed on the substrate; A first reflective electrode and a second reflective electrode are disposed on the power line and the driving transistor and spaced apart from each other. The first reflective electrode is connected to the driving transistor and the second reflective electrode is connected to the power line. A bonding layer is disposed on the first reflective electrode and the second reflective electrode; Multiple light-emitting elements are respectively disposed in the multiple sub-pixels on the bonding layer, and each includes a first electrode and a second electrode; A first planarization layer is disposed on the bonding layer and configured to partially surround the sides of the plurality of light-emitting elements; A first connection electrode is disposed on the first planarization layer and configured to connect the first electrode and the driving transistor; The second connecting electrode is disposed on the first planarization layer, spaced apart from the first connecting electrode, and connected to the second reflective electrode; A passivation layer is disposed on the first connection electrode and the second connection electrode; A second planarization layer is disposed on the passivation layer, and the height of the second planarization layer decreases toward the plurality of light-emitting elements; as well as A third connection electrode is disposed on the second planarization layer and configured to connect the second electrode and the power line.

16. The display device according to claim 15, wherein, The passivation layer surrounds the plurality of light-emitting elements and exposes a portion of the first connection electrode, and The height of the lowest end of the top surface of the second planarization layer is higher than the height of the highest end of the top surface of the exposed portion of the first connecting electrode.

17. The display device according to claim 15, wherein, The passivation layer includes an opening that exposes the first planarization layer. The second planarization layer includes an opening that overlaps with the opening of the passivation layer, and the width of the opening in the second planarization layer is smaller than the width of the opening in the passivation layer. The second planarization layer is disposed in the opening of the passivation layer and separates the first connection electrode and the second connection electrode.

18. The display device according to claim 15, wherein, Each of the plurality of pixels includes a first region electrically connected to the third connection electrode and the power line, and a second region spaced apart from the first region. In the first region, the third connection electrode is connected to the power line via the second reflective electrode and the second connection electrode, and In the second region, the third connection electrode is connected to the power line via the second connection electrode extending from the first region.

19. The display device according to claim 18, wherein, The bonding layer includes a contact hole disposed in the first region and exposing the second reflective electrode. The first planarization layer includes contact holes disposed in the first region and overlapping with the contact holes of the bonding layer. The second connecting electrode is connected to the second reflective electrode through the contact holes of the first planarization layer and the contact holes of the bonding layer.

20. The display device according to claim 19, wherein, The passivation layer includes a contact hole disposed in the first region that overlaps with the contact hole of the first planarization layer and the contact hole of the bonding layer, and exposes the contact hole of the second connection electrode. The second planarization layer includes a layer disposed in the first region that overlaps with the contact holes of the first planarization layer, the contact holes of the bonding layer, and the contact holes of the passivation layer, and exposes the contact holes of the second connection electrode. The third connection electrode is connected to the second connection electrode through the contact holes of the second planarization layer, the contact holes of the passivation layer, the contact holes of the first planarization layer, and the contact holes of the bonding layer.

21. The display device according to claim 19, wherein, The passivation layer also includes a contact hole disposed in the second region and exposing the second connection electrode extending from the first region. The second planarization layer further includes a contact hole disposed in the second region and exposing the second connection electrode extending from the first region. The third connection electrode is connected to the second connection electrode through the contact holes of the passivation layer and the second planarization layer disposed in the second region.

22. The display device according to claim 15, further comprising: An illumination inspection area is provided in each of the plurality of pixels, and an illumination inspection pattern is provided on the second planarization layer in the illumination inspection area. The passivation layer includes a contact hole disposed in the illumination inspection area and exposing the first connection electrode. The second planarization layer includes contact holes that overlap with the contact holes of the passivation layer and expose the first connection electrode. The first illumination inspection pattern is connected to the first connection electrode through the contact holes of the second planarization layer and the contact holes of the passivation layer.

23. The display device according to claim 15, wherein, The height of the passivation layer and the first connecting electrode also decreases toward the plurality of light-emitting elements.

24. The display device according to claim 15, wherein, The side surface of the plurality of light-emitting elements is any one or both of the two sides of the plurality of light-emitting elements.

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