Display device

Abstract

This disclosure provides a display device, comprising: a substrate; an insulating layer disposed on the substrate and including a recess and a peripheral portion surrounding the recess; a first electrode disposed on the recess and the peripheral portion; an auxiliary line spaced apart from the first electrode and disposed on the peripheral portion; a dam covering at least a portion of the auxiliary line and the first electrode and disposed on the peripheral portion; a protective layer disposed on the first electrode and the dam; an intermediate layer disposed on the first electrode and the protective layer; and a second electrode electrically connected to the auxiliary line and disposed on the intermediate layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0187959, filed with the Korean Intellectual Property Office on December 17, 2024, which is incorporated herein by reference for all purposes, as if fully set forth herein. Technical Field

[0003] This disclosure relates to electronic devices, and more specifically, to display devices. Background Technology

[0004] In today's information society, display devices used to present images or visual information to users are becoming increasingly important. This need has led to the rapid development of display technology, and various types and applications of display devices have been developed. Furthermore, as display devices become thinner and lighter, their applications are expanding, and displays are widely used in various fields of equipment, devices, and systems.

[0005] Even as the area occupied by the display area used to display images increases, display devices tend to add various functions, including functions that interoperate or are associated with other devices, apparatuses, and systems, as well as independent functions.

[0006] As so-called bezel-less or bezel-free designs that make the display area appear fuller become more popular, recent work has made progress in reducing the area of ​​non-display areas outside the display area. Summary of the Invention

[0007] To address these issues, one or more aspects of this disclosure may provide a display device with improved reliability.

[0008] One or more aspects of this disclosure may provide a display device including a structure in which a cathode contact area electrically connected to a common electrode and a common voltage line is provided in a display area, and is capable of improving the brightness uniformity of each area in the display area.

[0009] One or more aspects of this disclosure may provide a display device including a structure in which a cathode contact area electrically connecting a common electrode and a common voltage line is provided in a display area, and a narrow bezel can be achieved by reducing the bezel width.

[0010] One or more aspects of this disclosure may provide a display device that includes a black embankment and is capable of improving reflective visibility and reflectivity due to external light.

[0011] One or more aspects of this disclosure may provide a display device including a protective layer located between a black embankment and a light-emitting element, and capable of preventing smoke gases generated by the black embankment from penetrating into the light-emitting element.

[0012] According to one or more aspects of this disclosure, a display device may be provided, which includes a structure capable of improving brightness non-uniformity and reflectivity, and is capable of being driven with low power consumption.

[0013] The aspects, examples, and embodiments provided in this disclosure are not limited to the foregoing description, and the additional aspects, examples, and embodiments provided in this disclosure will become apparent to those skilled in the art from the following description.

[0014] According to one or more example embodiments of this disclosure, a display device may be provided, the display device comprising: a substrate; an insulating layer disposed on the substrate and including a recess and a peripheral portion surrounding the recess; a first electrode disposed on the recess and the peripheral portion; an auxiliary line spaced apart from the first electrode and disposed on the peripheral portion; a dam covering at least a portion of the auxiliary line and the first electrode and disposed on the peripheral portion; a protective layer disposed on the first electrode and the dam; an intermediate layer disposed on the first electrode and the protective layer; and a second electrode electrically connected to the auxiliary line and disposed on the intermediate layer.

[0015] According to one or more example embodiments of this disclosure, a display device may be provided, the display device comprising: a substrate including a display area and a non-display area surrounding the display area; an insulating layer located in the display area and including a recess and a peripheral portion; a first electrode disposed on the insulating layer; an auxiliary line spaced apart from the first electrode and disposed on the peripheral portion; a dam including a first opening area corresponding to the recess and a second opening area exposing a portion of the auxiliary line; a protective layer disposed on the first electrode positioned corresponding to the inclined portion of the dam and the recess; an undercut region overlapping at least a portion of the second opening region and disposed below the protective layer; an intermediate layer disposed on the first electrode and the protective layer; and a second electrode electrically connected to the auxiliary line in the undercut region and disposed on the intermediate layer.

[0016] According to one or more aspects of this disclosure, a display device with improved reliability can be provided.

[0017] According to one or more aspects of this disclosure, a display device may be provided, the display device including a structure in which a cathode contact area electrically connected to a common electrode and a common voltage line is provided in a display area, and is capable of improving the brightness uniformity of each area in the display area.

[0018] According to one or more aspects of this disclosure, a display device may be provided, the display device including a structure in which a cathode contact area electrically connecting a common electrode and a common voltage line is provided in a display area, and a narrow bezel can be achieved by reducing the bezel width.

[0019] According to one or more aspects of this disclosure, a display device may be provided, the display device including a black embankment and capable of improving reflective visibility and reflectivity due to external light.

[0020] According to one or more aspects of this disclosure, a display device may be provided, the display device including a protective layer located between a black embankment and a light-emitting element, and capable of preventing smoke gases generated by the black embankment from penetrating into the light-emitting element.

[0021] According to one or more aspects of this disclosure, a display device may be provided, the display device including a structure capable of improving brightness non-uniformity and reflectivity, and capable of being driven with low power consumption.

[0022] The effects or advantages derived from the aspects, examples, and embodiments described herein are not limited thereto, and additional effects or advantages will be apparent to those skilled in the art from the following description. Attached Figure Description

[0023] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated into and constitute a part of this disclosure. The drawings illustrate various aspects of this disclosure and, together with the description, serve to explain the principles of this disclosure. Therefore, it should be understood that the aspects, examples, and embodiments described herein are not limited to the illustrations in the drawings. In the drawings:

[0024] Figure 1 An example system configuration of a display device according to aspects of this disclosure is shown;

[0025] Figure 2 This is an example floor plan of a display panel according to aspects of this disclosure;

[0026] Figure 3 It is in the display panel according to aspects of this disclosure Figure 2 An enlarged view of example region A;

[0027] Figures 4 to 7It is in accordance with the aspects of this disclosure that the display panel is along Figure 3 Example cross-sectional view taken from line I-I';

[0028] Figure 8 It is in accordance with the aspects of this disclosure that the display panel is along Figure 3 Example cross-sectional view taken from line II-II';

[0029] Figures 9 to 13 An example process for manufacturing a display panel according to aspects of this disclosure is shown;

[0030] Figure 14 This is a floor plan of the example display panel;

[0031] Figure 15 and Figure 16 This is an example cross-sectional view of the display panel; and

[0032] Figure 17 It shows Figure 8 The example cross-sectional view of the display panel shown and along Figure 14 Example cross-sectional view taken from line III-III' in the display panel. Detailed Implementation

[0033] In the following description of examples or embodiments of this disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that may be implemented are illustrated by way of illustration, and wherein the same reference numerals and symbols may be used to designate them even when the same or similar components are shown in different drawings. Furthermore, in the following description of examples or embodiments of this disclosure, detailed descriptions of well-known functions and components incorporated herein will be omitted where it is determined that the description might make the subject matter of some embodiments of this disclosure unclear. Terms such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed from” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Singular forms used herein are intended to include plural forms unless the context clearly indicates otherwise.

[0034] This document may use terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” to describe elements of this disclosure. Each of these terms is not intended to define the nature, order, sequence, or number of elements, but is only used to distinguish the corresponding element from other elements.

[0035] When referring to a first element as being "connected or coupled to," "in contact with," or "overlapping" with a second element, it should be understood that the first element can not only be "directly connected or coupled to" or "directly contact with or overlap" the second element, but a third element can also be "inserted" between the first and second elements, or the first and second elements can be "connected or coupled to," "in contact with," or "overlapping" with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or coupled to," "in contact with," or "overlap" with each other.

[0036] When time-relative terms (e.g., “after,” “following,” “next,” “before,” etc.) are used to describe a process or operation of an element or configuration, or a flow or step in an operation, processing, or manufacturing method, these terms may be used to describe a discontinuous or non-sequential process or operation, unless the terms “direct” or “immediate” are used simultaneously.

[0037] Furthermore, when referring to any dimension, relative size, etc., the numerical value or corresponding information of the component or feature (e.g., level, range, etc.) should be considered, including tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the term "may" fully encompasses all the meanings of the term "able to".

[0038] In the following description, various exemplary aspects of this disclosure will be described in detail with reference to the accompanying drawings. Regarding the reference numerals for each element in the drawings, unless otherwise stated, the same element may be shown in other drawings, and the same reference numerals may refer to the same element. The same or similar elements may be denoted by the same reference numerals even if they are shown in different drawings. Furthermore, for ease of description, the scale, dimensions, size, and thickness of each element shown in the drawings may differ from the actual scale, dimensions, size, and thickness, and therefore, aspects of this disclosure are not limited to the scale, dimensions, size, and thickness shown in the drawings.

[0039] Figure 1 An example system configuration of a display device 100 according to aspects of this disclosure is shown.

[0040] refer to Figure 1 In one or more example embodiments, the display device 100 may include a display panel 110 and at least one display driving circuit as an element for displaying images. The at least one display driving circuit may be a circuit for driving the display panel 110 and includes a data driving circuit 120, a gate driving circuit 130, a controller 140, and other circuit components.

[0041] The display panel 110 may include a substrate 111 and a plurality of sub-pixels SP disposed on the substrate 111.

[0042] Substrate 111 may include a display area DA that allows an image to be displayed and a non-display area NDA located outside the display area DA. Substrate 111 may include glass or a flexible plastic substrate. In examples where a flexible plastic substrate is used as substrate 111, the flexible plastic substrate may be polyimide or include polyamide.

[0043] The display area DA can also be called the active area, and multiple sub-pixels SP can be set in the display area DA for displaying images. The non-display area NDA can also be called the non-active area and includes the pad area PA.

[0044] In one or more aspects, the display panel 110 may be configured to have a very small non-display area NDA. The non-display area NDA may also be referred to as a "bezel" or "bezel area". For example, the non-display area NDA may include: a first non-display area located outside the display area DA in a first direction; a second non-display area located outside the display area DA in a second direction; a third non-display area located outside the display area DA in a direction opposite to the first direction; and a fourth non-display area located outside the display area DA in a direction opposite to the second direction.

[0045] The first non-display area among the first to fourth non-display areas may include pad areas connected or bonded to one or more drive circuits. Among the first to fourth non-display areas, the second to fourth non-display areas may have a very small size compared to the first non-display area.

[0046] In another example, a boundary region can be defined between the display area DA and the non-display area NDA. In this example, the boundary region may be curved at a specific angle to the display area DA, thereby placing the non-display area NDA below the display area DA. In this implementation, all or most of the non-display area NDA may be invisible to the user when viewing the display device 100 located in front of them. For example, the first non-display area may include a curved region. Due to the curvature of the curved region, the first non-display area may be invisible in front of the display device 100.

[0047] Several types of signal lines for driving multiple sub-pixels SP can be disposed on the substrate 111 of the display panel 110.

[0048] In one or more aspects, the display device 100 herein may be a liquid crystal display device or the like, or a self-emissive display device in which light is emitted from the display panel 110 itself. In an example where the display device 100 is a self-emissive display device, each of the plurality of sub-pixels SP may include a light-emitting element.

[0049] For example, the display device 100 according to aspects of this disclosure may be an organic light-emitting display device, wherein the light-emitting element is implemented using an organic light-emitting diode (OLED). In another example, the display device 100 according to aspects of this disclosure may be an inorganic light-emitting display device, wherein the light-emitting element is implemented using a light-emitting diode based on inorganic materials. In yet another example, the display device 100 according to aspects of this disclosure may be a quantum dot display device, wherein the light-emitting element is implemented using quantum dots, which are self-emissive semiconductor crystals.

[0050] The structure of each or at least one subpixel of the plurality of subpixels SP included in the display device 100 may depend on the type of the display device 100. For example, when the display device 100 is a self-emissive display device including self-emissive subpixels SP, each subpixel SP may include a self-emissive light-emitting element, one or more transistors, and one or more capacitors.

[0051] refer to Figure 1 Each subpixel or at least one subpixel in a plurality of subpixels SP in the display area DA may include a light-emitting element ED and a subpixel circuit SPC configured to drive the light-emitting element ED.

[0052] refer to Figure 1 The subpixel circuit (SPC) may include multiple transistors and at least one capacitor for driving the light-emitting element (ED). The SPC can drive the ED by providing a drive current to the ED in a predetermined timing sequence. The ED emits light by being driven by the drive current.

[0053] The multiple transistors may include a driving transistor DT for driving the light-emitting element ED and a scanning transistor ST configured to be turned on or off according to the scanning signal SC.

[0054] The driving transistor DT can provide driving current to the light-emitting element ED.

[0055] The scanning transistor ST can be configured to control the electrical state of the corresponding node in the sub-pixel circuit SPC or to control the state or operation of the driving transistor DT.

[0056] At least one capacitor may include a storage capacitor Cst, which is configured to maintain a constant voltage level during a display frame or a period of a display frame.

[0057] To drive one or more sub-pixels SP, at least one data signal VDATA (which is an image signal) and at least one scan signal SC (which is a gate signal) can be applied to one or more sub-pixels SP. Furthermore, to drive one or more sub-pixels SP, at least one common driving voltage (which includes a first common driving voltage VDD and a second common driving voltage VSS) can be applied to one or more sub-pixels SP.

[0058] The light-emitting element (ED) may include a pixel electrode (PE), an intermediate layer (EL), and a common electrode (CE). The intermediate layer (EL) may be disposed between the pixel electrode (PE) and the common electrode (CE).

[0059] For example, a pixel electrode PE can be an electrode disposed in each sub-pixel SP, and a common electrode CE can be an electrode commonly disposed in all or some of the multiple sub-pixels SP. For example, the pixel electrode PE can be an anode electrode, and the common electrode CE can be a cathode electrode. In another example, the pixel electrode PE can be a cathode electrode, and the common electrode CE can be an anode electrode. In the following discussion, for ease of explanation, we can base our discussion on an example in which the pixel electrode PE is an anode electrode and the common electrode CE is a cathode electrode.

[0060] In an example where the light-emitting element ED is an organic light-emitting diode, the intermediate layer EL may include an emitter layer EML, a first common intermediate layer COM1 located between the pixel electrode PE and the emitter layer EML, and a second common intermediate layer COM2 located between the emitter layer EML and the common electrode CE. The layer including the first common intermediate layer COM1 and the second common intermediate layer COM2 may be referred to as the common intermediate layer EL_COM.

[0061] In one or more aspects, the emitter layer EML can be set for each subpixel SP, and the common intermediate layer EL_COM can be set publicly across all or some of the multiple subpixel SPs.

[0062] For example, an emission layer EML can be set for each emitting region, and a common intermediate layer EL_COM can be set across multiple emitting and non-emitting regions.

[0063] In one or more aspects, the emitter layer EML and the common intermediate layer EL_COM can span all or some of multiple sub-pixels SP.

[0064] For example, the emitter layer EML and the common intermediate layer EL_COM can be set together across multiple emitting and non-emitting regions.

[0065] In one or more aspects, the first common intermediate layer COM1 may include a hole injection layer (HIL), a hole transport layer (HTL), etc. The second common intermediate layer COM2 may include an electron transport layer (ETL), an electron injection layer (EIL), etc.

[0066] The hole injection layer injects holes from the pixel electrode (PE) into the hole transport layer, which then transports the holes to the emitter layer (EML). The electron injection layer injects electrons from the common electrode (CE) into the electron transport layer, which then transports the electrons to the emitter layer (EML).

[0067] In one or more aspects, the common electrode CE may be electrically connected to a second common driving voltage line VSSL. A second common driving voltage VSS may be applied to the common electrode CE via the second common driving voltage line VSSL. The pixel electrode PE may be electrically connected, directly or indirectly (via another transistor), to the first node N1 of the corresponding driving transistor DT of each sub-pixel SP. In this document, the second common driving voltage VSS may also be referred to as a “reference voltage,” and the second common driving voltage line VSSL may also be referred to as a “low power supply voltage line,” a “low voltage line,” or a “reference voltage line.”

[0068] Each light-emitting element (ED) can be configured by overlapping a pixel electrode (PE), an emissive layer (EML) in the intermediate EL layer, and a common electrode (CE). Each ED can form a corresponding light-emitting region. For example, the corresponding light-emitting region of each ED can include the area where the pixel electrode (PE), the emissive layer (EML) in the intermediate EL layer, and the common electrode (CE) overlap.

[0069] In one or more aspects, each or at least one of the plurality of light-emitting elements ED included in the display panel 110 of the display device 100 may be an organic light-emitting diode (OLED), an inorganic light-emitting diode (LED), a quantum dot (QD) light-emitting element, a micro light-emitting diode, a mini light-emitting diode, etc., but the aspects of this disclosure are not limited thereto. In an example in which each or at least one of the plurality of light-emitting elements ED included in the display panel 110 of the display device 100 is an organic light-emitting diode (OLED), the intermediate layer EL included in the organic light-emitting diode (OLED) may include an organic material.

[0070] refer to Figure 1 The driving transistor DT can be a transistor configured to provide drive current to the light-emitting element ED. The driving transistor DT can be connected between the first common drive voltage line VDDL and the light-emitting element ED.

[0071] The driving transistor DT may include a first node N1, a second node N2, and a third node N3. The first node N1 may be electrically connected to the light-emitting element ED. The data signal VDATA may be applied to the second node N2. The first common driving voltage VDD delivered through the first common driving voltage line VDDL may be applied to the third node N3.

[0072] In the driving transistor DT, the second node N2 can be the gate node, the first node N1 can be the source node or the drain node, and the third node N3 can be the drain node or the source node. In the following discussion, for ease of explanation only, examples are provided where the first, second, and third nodes (N1, N2, and N3) of the driving transistor DT are the source node, the gate node, and the drain node, respectively. However, aspects of this disclosure are not limited thereto.

[0073] Figure 1 The scanning transistor ST included in the sub-pixel circuit SPC shown can be a switching transistor used to allow the data signal VDATA (which is an image signal) to be provided to the second node N2 (which is the gate node of the driving transistor DT).

[0074] The scan transistor ST can be turned on or off by a scan signal SC (a gate signal) applied via the scan line SCL (which is a gate line GL), and controls the electrical connection between the second node N2 of the drive transistor DT and the data line DL. The drain or source electrode of the scan transistor ST can be electrically connected to the data line DL. The source or drain electrode of the scan transistor ST can be electrically connected to the second node N2 of the drive transistor DT. The gate electrode of the scan transistor ST can be electrically connected to the scan line SCL.

[0075] The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2 of the driving transistor DT. The storage capacitor Cst can include: a first capacitor electrode electrically connected to or corresponding to the first node N1 of the driving transistor DT; and a second capacitor electrode electrically connected to or corresponding to the second node N2 of the driving transistor DT.

[0076] The storage capacitor Cst can be an external capacitor that is intentionally designed to be located outside the driving transistor DT, and therefore, it is different from the internal capacitor that may be formed between the first node N1 and the second node N2 of the driving transistor DT, such as parasitic capacitors (e.g., Cgs, Cgd).

[0077] Each of the driving transistor DT and the scanning transistor ST can be an n-type transistor or a p-type transistor.

[0078] The display panel 110 may have a top-emitting structure or a bottom-emitting structure.

[0079] In an example where the display panel 110 has a top-emitting structure, at least a portion of the sub-pixel circuit SPC can overlap with at least a portion of the light-emitting element ED in the vertical direction. In this configuration, the area or size of the corresponding light-emitting region can be increased, and the corresponding aperture ratio can be increased.

[0080] In an example where the display panel 110 has a bottom emission structure, the sub-pixel circuit SPC can be designed not to overlap with the light-emitting element ED in the vertical direction.

[0081] like Figure 1 As shown, the sub-pixel circuit SPC may include two transistors (2T: DT and ST) and a capacitor (1C: Cst) (which may be referred to as a "2T1C structure"), and in some embodiments, it may also include one or more transistors, or one or more capacitors.

[0082] For example, a subpixel circuit SPC can have an 8T1C structure comprising 8 transistors and 1 capacitor. In yet another example, a subpixel circuit SPC can have a 6T2C structure comprising 6 transistors and 2 capacitors. In yet another example, a subpixel circuit SPC can have a 7T1C structure comprising 7 transistors and 1 capacitor. However, aspects of this disclosure are not limited to these specific structures.

[0083] The type and quantity of signals supplied to the sub-pixel SP and / or the type and quantity of lines connected to the sub-pixel SP can vary depending on the structure of the corresponding sub-pixel circuit SPC. Furthermore, the type and quantity of the common driving voltage supplied to the sub-pixel SP can vary depending on the structure of the corresponding sub-pixel circuit SPC.

[0084] For example, several types of signal lines may include multiple data lines DL for carrying data signals (which may be referred to as data voltages or image signals), multiple gate lines GL for carrying gate signals (which may be referred to as scan signals), etc.

[0085] In one or more aspects, multiple data lines DL and multiple gate lines GL may intersect each other. Each of the multiple data lines DL may be configured to extend in a first direction, and each of the multiple gate lines GL may be configured to extend in a second direction. For example, the first direction may be a column direction, and the second direction may be a row direction. In another example, the first direction may be a row direction, and the second direction may be a column direction. Hereinafter, for ease of explanation only, the discussion will be based on an example in which the first direction is a column direction and the second direction is a row direction. Hereinafter, for ease of explanation, the discussion will be based on an example in which each of the multiple data lines DL is arranged in a column direction and each of the multiple gate lines GL is arranged in a row direction, but aspects of this disclosure are not limited thereto.

[0086] The data driving circuit 120 can be a circuit used to drive multiple data lines DL, and can output data signals to multiple data lines DL.

[0087] The data drive circuit 120 can receive digital image data DATA from the controller 140, convert the received image data DATA into analog data signals, and output the obtained data signals to multiple data lines DL.

[0088] In one or more aspects, the data driving circuit 120 may be connected to the display panel 110 via tape-on-carrier bonding (TAB) technology, or to conductive pads (e.g., bonding pads of the display panel 110) via chip-on-glass (COG) technology or chip-on-panel (COP) technology, or to the display panel 110 via chip-on-film (COF) technology. However, the aspects of this disclosure are not limited thereto.

[0089] In one or more aspects, the data driving circuit 120 may be disposed and / or electrically connected to (but not limited to) only one side or one side (e.g., the upper or lower part) of the display panel 110. In one or more aspects, depending on the driving scheme, panel design, etc., the data driving circuit 120 may be disposed and / or electrically connected to (but not limited to) both sides or two portions (e.g., the upper edge and the lower edge) of the display panel 110, or at least two of the four sides or four portions (e.g., the upper edge, the lower edge, the left edge, and the right edge) of the display panel 110.

[0090] The data driving circuit 120 can be connected to an area outside the display area DA of the display panel 110, or it can be located in the display area DA of the display panel 110.

[0091] The gate drive circuit 130 can be a circuit for driving multiple gate lines GL and can output gate signals to multiple gate lines GL.

[0092] The gate drive circuit 130 can receive various types of gate drive control signals GCS, and in addition, it can also receive a first gate voltage corresponding to the on-level voltage and a second gate voltage corresponding to the off-level voltage. Thus, the gate drive circuit 130 can generate a gate signal and provide the generated gate signal to multiple gate lines GL.

[0093] In one or more aspects, the gate driving circuitry 130 included in the display device 100 may be embedded in the display panel 110 using gate in-panel (GIP) technology. In an example where the gate driving circuitry 130 is implemented using GIP technology, the gate driving circuitry 130 may be disposed on the substrate 111 of the display panel 110 during the manufacturing process of the display panel 110 or the display device 100.

[0094] In one or more aspects, the gate drive circuit 130 may be disposed in the non-display area NDA of the display panel 110.

[0095] In one or more aspects, the gate driving circuit 130 may be disposed in the display area DA of the display panel 110. In this embodiment, for example, the gate driving circuit 130 may be disposed in and / or electrically connected to (but not limited to) a first area (e.g., a left or right side area) of the display area DA of the display panel 110. In another example, the gate driving circuit 130 may be disposed in and / or electrically connected to (but not limited to) a first area (e.g., a left or right side area) and a second area (e.g., a right or left side area) of the display area DA of the display panel 110.

[0096] In this document, the gate drive circuit 130 embedded in the display panel 110 using gate in-panel (GIP) technology can also be referred to as an "in-panel gate circuit".

[0097] The controller 140 may be a device configured to control the data drive circuit 120 and the gate drive circuit 130, and may control the drive timing for multiple data lines DL and the drive timing for multiple gate lines GL.

[0098] The controller 140 can provide a data control signal DCS to the data drive circuit 120 to control the data drive circuit 120, and provide a gate control signal GCS to the gate drive circuit 130 to control the gate drive circuit 130.

[0099] The controller 140 can receive image data input from the host system 150 and provide image data DATA, which can be read by the data driving circuit 120, to the data driving circuit 120 based on the input image data.

[0100] The controller 140 can be implemented in a separate component from the data drive circuit 120, or integrated with the data drive circuit 120, such that the controller 140 and the data drive circuit 120 can be implemented in a single integrated circuit.

[0101] Controller 140 may be a timing controller used in typical display technologies, or it may be a control device / app that additionally performs other control functions beyond the typical functions of a timing controller. In one or more embodiments, controller 140 may be one or more other control circuits different from a timing controller, or it may be a circuit or component in a control device / app. Controller 140 may be implemented using various circuits or electronic components, such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), processors, etc.

[0102] The controller 140 can be mounted on a printed circuit board, flexible printed circuit, etc., and can be electrically connected to the data drive circuit 120 and the gate drive circuit 130 through the printed circuit board, flexible printed circuit, etc.

[0103] The controller 140 can transmit signals to and receive signals from the data drive circuit 120 via one or more predetermined interfaces. Such interfaces may include, for example, a low-voltage differential signaling (LVDS) interface, an embedded point-to-point clock interface (EPI), a serial peripheral interface (SPI), etc. However, this disclosure is not limited thereto.

[0104] In one or more aspects, in order to provide touch sensing and image display functions, the display device 100 may include a touch sensor and a touch sensing circuit configured to sense the touch sensor and detect whether a touch is applied by an object such as a finger or a pen, or the location (or coordinates) of the touch.

[0105] The touch sensing circuit may include: a touch driving circuit configured to drive and sense the touch sensor and generate and output touch sensing data; and a touch controller configured to detect whether a touch has been applied or the location (or coordinates) of the touch based on the touch sensing data.

[0106] A touch sensor may include multiple touch electrodes. A touch sensor may also include multiple touch lines for electrically connecting the multiple touch electrodes to touch driving circuitry.

[0107] The touch sensor can be disposed on the exterior of the display panel 110 in the form of a touch panel, or it can be disposed inside the display panel 110. A touch sensor disposed on the exterior of the display panel 110 can be referred to as an additional touch sensor. In an example where the additional touch sensor is disposed within the display device 100, the touch panel and the display panel 110 can be manufactured separately and combined during assembly. The additional touch panel may include a touch panel substrate and a plurality of touch electrodes disposed on the touch panel substrate.

[0108] In an example where the touch sensor is located inside the display panel 110, the touch sensor can be formed on the substrate together with the display driving-related signal lines and electrodes during the manufacturing process of the display panel 110.

[0109] The touch driving circuit can provide a touch driving signal to at least one of a plurality of touch electrodes and generate touch sensing data by sensing at least one of the plurality of touch electrodes.

[0110] Touch sensing circuits can perform touch sensing using self-capacitance sensing technology or mutual capacitance sensing technology.

[0111] In an example where the touch sensing circuit performs touch sensing using self-capacitance sensing technology, the touch sensing circuit can perform touch sensing based on the capacitance between each touch electrode and the touch object (e.g., a finger, a pen, etc.). According to self-capacitance sensing technology, each of the multiple touch electrodes can be used as both a driving touch electrode and a sensing touch electrode. The touch driving circuit can drive all or one or more of the multiple touch electrodes and sense all or one or more of the multiple touch electrodes.

[0112] In an example where the touch sensing circuit performs touch sensing using mutual capacitance sensing technology, the touch sensing circuit can perform touch sensing based on the capacitance between the touch electrodes. According to mutual capacitance sensing technology, the multiple touch electrodes can be divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit can drive the driving touch electrodes and sense the sensing touch electrodes.

[0113] In one or more aspects, the touch driving circuit and touch controller included in the touch sensing circuit can be implemented in a separate device, or can be implemented in a single device. In one or more aspects, the touch driving circuit and data driving circuit can be implemented in a separate device, or can be implemented in a single device.

[0114] The display device 100 may also include a power supply circuit for providing several types of power to the display driving circuit and / or touch sensing circuit.

[0115] In one or more aspects, the display device 100 may be a mobile terminal, such as a smartphone, tablet computer, etc., or it may be a monitor, television (TV), etc. Such devices can be configured in various types, sizes, and shapes. The display device 100 according to an aspect of this disclosure is not limited thereto, and may include various types, sizes, and shapes configured to display information or images. The display device according to an aspect of this disclosure can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, stretchable devices, curved devices, sliding devices, variable devices, electronic notebooks, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbooks, workstations, navigation devices, car navigation devices, in-vehicle display devices, vehicle devices, cinema devices, cinema display devices, televisions, wallpaper devices, signage devices, gaming devices, laptop computers, monitors, cameras, camcorders, and home appliances, etc.

[0116] In one or more aspects, the display device 100 may also include electronic devices, such as a camera (e.g., an image sensor), a sensor capable of detecting objects and ambient light, etc. For example, the sensor may be a sensor capable of detecting objects or the human body by receiving light such as infrared light, ultrasonic light, ultraviolet light, etc.

[0117] Figure 2 This is an example floor plan view of the display panel 110 according to aspects of this disclosure. In the following... Figure 2 In the discussion of the configuration, for the sake of simplicity, descriptions and references will be omitted or briefly explained. Figure 1 Discussion of features and configurations that are identical, substantially identical, or similar to those described.

[0118] refer to Figure 2 In one or more example embodiments, the display panel 110 may include a substrate 111, a printed circuit board 20 located outside the substrate 111 and providing electrical signals, power supply voltages, etc., and a flexible circuit board or connector 10 connecting the printed circuit board 20 to the substrate 111.

[0119] The common electrode CE can be configured to extend from the display area DA to a portion of the non-display area NDA located outside the display area DA, and partially overlap with the power supply voltage line. For example, the common electrode CE can be integrally formed in the display area DA and the portion of the non-display area NDA located outside the display area DA.

[0120] In one or more aspects, the display panel 110 may include a structure in which a common electrode CE is electrically contacted with one or more auxiliary lines 220 in the display area DA. This structure provides the advantages of preventing voltage drop of the common voltage VSS applied to the common electrode CE and improving brightness uniformity in each region of the display area DA. For example, a structure in the non-display area NDA in which the common electrode CE is electrically contacted with power supply voltage lines via connecting electrodes or the like may be formed. However, this implementation may hinder the reduction of the bezel width (i.e., the non-display area NDA) of the display panel 110 or display device 100, and therefore, it may be difficult to form a display panel 110 or display device 100 with a narrow bezel.

[0121] The display area DA may include multiple light-emitting areas, which are independently formed, spaced apart from each other, and located in multiple sub-pixels SP disposed in the display area DA. In one or more aspects, auxiliary lines 220 may be disposed spaced apart from each other in the display area DA. Figure 2 An example is shown in which the auxiliary line 220 is configured to extend along a second direction (e.g., a horizontal direction), but aspects of this disclosure are not limited thereto. For example, the auxiliary line 220 may be configured to extend in a first direction (e.g., in a column direction). In another example, the auxiliary line 220 may be configured to extend in both the first and second directions. The auxiliary line 220 may extend to a portion of the non-display area NDA outside the display area DA and be electrically connected to the common voltage line 210. In this embodiment, a common voltage VSS delivered through the common voltage line 210 may be applied to the auxiliary line 220.

[0122] The display device 100 may include a structure in which an auxiliary line 220 is connected to a common electrode CE that overlaps with the auxiliary line 220. According to this structure, a common voltage provided by the auxiliary line 220 in the display area DA can be supplied to the common electrode CE at multiple locations in the display area DA. With this configuration, the common electrode CE can provide a common voltage VSS through both its connection to a common voltage line 210 in the non-display area NDA and its connection to the auxiliary line 220 in the display area DA. Thus, a common voltage VSS with a uniform level can be provided to the common electrode CE throughout the entire area of ​​the display area DA, and voltage drop in the integrally formed common electrode CE can be prevented.

[0123] For example, refer to Figure 2In the display area DA, a common voltage VSS of substantially equal level can be applied to the common electrode CE in the region formed along the auxiliary line 220 connected from position P1 to the common electrode CE, and in the region formed along another auxiliary line 220 connected from position P2 to the common electrode CE. Therefore, by providing a common voltage VSS of substantially equal level without voltage drop at the common electrode CE, equal (or substantially equal) current amounts can be provided to the light-emitting elements ED located in the sub-pixels SP respectively in the regions formed along the auxiliary line 220 connected to the common electrode CE at position P1 and along the auxiliary line 220 connected to the common electrode CE at position P2, without changing the current amount. This means that the corresponding light-emitting elements ED can be provided with substantially equal current amounts in either the region formed along the auxiliary line 220 connected to the common electrode CE at position P1 or along the auxiliary line 220 connected to the common electrode CE at position P2, thus avoiding different brightness caused by differences in the driving current when the light-emitting elements ED are driven.

[0124] Figure 3 The display panel 110 is based on aspects of this disclosure. Figure 2 A magnified view of example region A. In the following... Figure 3 In the discussion of the configuration, for the sake of simplicity, descriptions and references will be omitted or briefly explained. Figure 1 and Figure 2 Discussion of features and configurations that are identical, substantially identical, or similar to those described.

[0125] refer to Figure 3 In one or more example embodiments, a plurality of subpixels SP may be provided in the display area DA. The area in the display area DA with subpixels SP may be referred to as a subpixel area. The area in the display area DA without subpixels SP may be referred to as a non-subpixel area. A subpixel can be the smallest unit for generating an image and refers to a light-emitting area.

[0126] The first sub-pixel SP1 can be a green sub-pixel emitting green light, the second sub-pixel SP2 can be a red sub-pixel emitting red light, and the third sub-pixel SP3 can be a blue sub-pixel emitting blue light. However, this disclosure is not limited to these aspects.

[0127] For example, each sub-pixel SP may include a first light-emitting region EA1, a second light-emitting region EA2, a first non-light-emitting region NEA1, and a second non-light-emitting region NEA2. The second light-emitting region EA2 may be formed in a shape surrounding the first light-emitting region EA1. The first non-light-emitting region NEA1 may be located between the first light-emitting region EA1 and the second light-emitting region EA2, and formed in a shape surrounding the first light-emitting region EA1. The second non-light-emitting region NEA2 may be formed in a shape surrounding the second light-emitting region EA2.

[0128] refer to Figure 3 The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be configured to be spaced apart from each other by a predetermined interval. For example, the second sub-pixel SP2 and the third sub-pixel SP3 can be configured to be spaced apart from each other by a predetermined interval in the same row; and adjacent first sub-pixels SP1 can be configured to be spaced apart from each other by a predetermined interval in adjacent rows. The arrangement of these sub-pixels SP can be repeated in adjacent rows. In this arrangement, the size or area of ​​at least one of the second sub-pixel SP2 and the third sub-pixel SP3 can be larger than that of the first sub-pixel SP1.

[0129] The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be arranged in an alternating pattern. For example, adjacent first sub-pixels SP1 can be arranged to be spaced apart from each other by a predetermined interval in the same column, and the second sub-pixels SP2 and the third sub-pixels SP3 can be arranged to be spaced apart from each other by a predetermined interval in adjacent columns. The arrangement of these sub-pixels SP can be repeated in adjacent columns.

[0130] refer to Figure 3 One or more auxiliary lines 220 may be provided in the display area DA. The auxiliary lines 220 may be located in the non-sub-pixel area of ​​the display area DA. The auxiliary lines 220 may be lines used to apply a common voltage VSS, that is, lines used to electrically connect the common electrode CE and the common voltage line 210. The auxiliary lines 220 may be disposed in substantially the same layer as the pixel electrode PE and are part of a metal layer comprising the same material as the pixel electrode PE.

[0131] Each auxiliary line 220 may extend between sub-pixels SP in a second direction and be spaced apart from each other in a first direction intersecting the second direction. The auxiliary lines 220 may be spaced apart from each other, and sub-pixels SP may be positioned between two adjacent auxiliary lines 220. For example, a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 may be positioned between two adjacent auxiliary lines 220.

[0132] The auxiliary line 220 can be configured to extend in a second direction. For example, the auxiliary line 220 can extend through the non-sub-pixel region between the first sub-pixel SP1 and the third sub-pixel SP3, the non-sub-pixel region between the third sub-pixel SP3 and the first sub-pixel SP2, and the non-sub-pixel region between the first sub-pixel SP1 and the second sub-pixel SP2. In this configuration, since the first sub-pixel SP1 is arranged in a staggered pattern in a different row than the second sub-pixel SP2 and the third sub-pixel SP3, each auxiliary line 220 can be arranged in a zigzag pattern on the plane between the sub-pixels. The auxiliary lines 220 with the zigzag pattern can be configured to be spaced apart from each other. Figure 3 The structure shown represents a portion of the display area DA, and the display area DA can have repetition. Figure 3 The configuration structure. Although Figure 3 The illustration shows an auxiliary line 220 configured to extend in a second direction and have a zigzag pattern; however, aspects of this disclosure are not limited thereto. For example, the auxiliary line 220 may have a structure in which the auxiliary line 220 is configured to extend in a first direction and have a zigzag pattern. In another example, one or more auxiliary lines 220 may have a zigzag pattern in the first direction, and one or more other auxiliary lines 220 may have a zigzag pattern in the second direction.

[0133] Each auxiliary line 220 may be electrically connected to the common electrode CE in a non-sub-pixel region between sub-pixels SP. To enable the auxiliary line 220 to be electrically connected to the common electrode CE, a corresponding upper surface or portion of the auxiliary line 220 may include a first contact portion CP1 exposing a corresponding portion of the auxiliary line 220. For example, the first contact portion CP1 may expose a portion of the auxiliary line 220 and electrically connect the auxiliary line 220 to the common electrode CE. In this example, the first contact portion CP1 may overlap with the pattern on which the auxiliary line 220 is disposed. For example, at least one first contact portion CP1 for electrically connecting the auxiliary line 220 to the common electrode CE may be formed on the pattern on which the auxiliary line 220 is disposed.

[0134] In one or more aspects, reference Figure 3One or more first contact portions CP1 may be disposed in one or more holes, said holes being formed in one or more portions of the pattern on which each auxiliary line 220 is disposed. For example, a plurality of first contact portions CP1 may be disposed on each auxiliary line 220 having a serrated shape in a planar view. The holes formed by the first contact portions CP1 may be circular, but this is not a limitation of the present disclosure. For example, these holes may have a polygonal shape, such as a square. For example, at least one first contact portion CP1 may be disposed in the central portion of a non-sub-pixel region between at least one first sub-pixel SP1 and at least one third sub-pixel SP3, or in the central portion of a non-sub-pixel region between at least one first sub-pixel SP1 and at least one second sub-pixel SP2, such as... Figure 3 As shown in the figure. However, the aspects of this disclosure are not limited thereto. For example, a first contact portion CP1 in the form of a hole may be formed in any portion of the area overlapping with each auxiliary line 220 having a serrated pattern.

[0135] In one or more aspects, one or more first contact portions CP1 may be formed in a straight line shape on a plane along the pattern of each auxiliary line 220 therein. For example, one or more first contact portions CP1 may be formed along the pattern of each auxiliary line 220 therein in a zigzag pattern identical to the auxiliary line 220. In a configuration similar to the auxiliary line 220, the first contact portion CP1 may extend in a second direction along the non-subpixel region in the display area DA where the first to third subpixels (SP1, SP2, and SP3) are not disposed.

[0136] refer to Figure 3 The auxiliary line 220 can be electrically connected to the common voltage line 210 in the non-display area NDA. To enable the auxiliary line 220 to be electrically connected to the common voltage line 210, a second contact portion CP2 can be provided below the auxiliary line 220.

[0137] Figures 4 to 7 For the display panel 110 along the aspect of this disclosure Figure 3 Example cross-sectional view taken from line I-I' in the following section. Figures 4 to 7 In the discussion of the configuration, for the sake of simplicity, descriptions and references will be omitted or briefly explained. Figures 1 to 3 Discussion of features and configurations that are the same, substantially the same, or similar.

[0138] refer to Figure 4 In one or more example embodiments, in terms of a stacked configuration, the display panel 110 may include a transistor portion, a light-emitting element portion, and a package portion.

[0139] The substrate 111 can be a single layer or multiple layers. In an example where the substrate 111 is a multiple layer, the substrate 111 may include a first substrate 301, an intermediate substrate layer 302, and a second substrate 303. The intermediate substrate layer 302 may be located between the first substrate 301 and the second substrate 303. For example, each of the first substrate 301 and the second substrate 303 may be a polyimide (PI) layer. The intermediate substrate layer 302 may be an inorganic insulating layer. When charge is stored in the first substrate 301 (which is a polyimide layer), the intermediate substrate layer 302 may prevent the charge from affecting one or more transistors disposed on the second substrate 303 through the second substrate 303 (which is a polyimide layer).

[0140] Additionally, the intermediate substrate layer 302 can prevent moisture from penetrating upward through the first substrate 301. For example, the intermediate substrate layer 302 can be a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), or a bilayer of silicon dioxide (SiO2) and silicon nitride (SiNx). However, the aspects of this disclosure are not limited thereto.

[0141] The transistor portion may include a substrate 111, several types of insulating layers (311, 312, 313, 314, 315 and 316) on the substrate 111, several types of transistors (TFT1 and TFT2), a storage capacitor Cst, and various electrodes or signal lines.

[0142] The transistors (TFT1 and TFT2) included in the transistor section may include a first transistor TFT1 and a second transistor TFT2.

[0143] The first transistor TFT1 may include a first active layer ACT1, a first electrode E1a, a second electrode E1b, and a third electrode E1c. The first active layer ACT1 may be a first semiconductor layer, but this disclosure is not limited thereto. For example, the first active layer ACT1 may be configured with oxide semiconductor, amorphous silicon, polycrystalline silicon, low-temperature polycrystalline silicon (LTPS), etc., but this disclosure is not limited thereto. The first transistor TFT1 may be a p-channel transistor or an n-channel transistor, but this disclosure is not limited thereto.

[0144] The first electrode E1a can be a gate electrode, the second electrode E1b can be a source electrode or a drain electrode, and the third electrode E1c can be a drain electrode or a source electrode. In the following discussion, for ease of explanation, examples will be used where the first electrode, second electrode, and third electrode (E1a, E1b, and E1c) are respectively the first gate electrode E1a, the first source electrode E1b, and the first drain electrode E1c. However, the aspects of this disclosure are not limited thereto.

[0145] The second transistor TFT2 may include a second active layer ACT2, a fourth electrode E2a, a fifth electrode E2b, and a sixth electrode E2c. The second active layer ACT2 may be a second semiconductor layer, but this disclosure is not limited thereto. For example, the second active layer ACT2 may be configured with oxide semiconductor, amorphous silicon, polycrystalline silicon, low-temperature polycrystalline silicon (LTPS), etc., but this disclosure is not limited thereto. The second transistor TFT2 may be a p-channel transistor or an n-channel transistor, but this disclosure is not limited thereto.

[0146] For example, one of the first transistors TFT1 and TFT2 may include an active layer formed of oxide semiconductor. In another example, one of the first transistors TFT1 and TFT2 may include an active layer formed of cryogenic polysilicon. In another example, the first transistor TFT1 and TFT2 may include an active layer formed of oxide semiconductor. In another example, the first transistor TFT1 and TFT2 may include an active layer formed of cryogenic polysilicon. In another example, in the first transistor TFT1 and TFT2, the driving transistor DT may include an active layer formed of oxide semiconductor, and the scanning transistor ST may include an active layer formed of cryogenic polysilicon. In another example, in the first transistor TFT1 and TFT2, the driving transistor DT may include an active layer formed of cryogenic polysilicon, and the scanning transistor ST may include an active layer formed of oxide semiconductor. In another example, one or more transistors in the gate drive circuit 130 that are configured with gate-in-panel (GIP) may include an active layer comprising oxide semiconductor or cryogenic polysilicon. In another example, all transistors disposed on substrate 111 and transistors in gate drive circuit 130 that employ an in-panel gate (GIP) configuration may include an active layer comprising oxide semiconductor.

[0147] The fourth electrode E2a can be the gate electrode, the fifth electrode E2b can be the source electrode or the drain electrode, and the sixth electrode E2c can be the drain electrode or the source electrode. In the following discussion, for ease of explanation, an example is provided in which the fourth, fifth, and sixth electrodes (E2a, E2b, and E2c) are respectively the second gate electrode E2a, the second source electrode E2b, and the second drain electrode E2c. However, aspects of this disclosure are not limited thereto.

[0148] although Figure 4The diagram shows that the second active layer ACT2 of the second transistor TFT2 is located at a higher position from the substrate 111 than the first active layer ACT1 of the first transistor TFT1; however, the scope of this disclosure is not limited thereto. For example, the first active layer ACT1 of the first transistor TFT1 may be located at a higher position from the substrate 111 than the second active layer ACT2 of the second transistor TFT2.

[0149] Furthermore, despite Figure 4 The second transistor TFT2 is shown to be located at a higher position from the substrate 111 than the first transistor TFT1; however, aspects of this disclosure are not limited thereto. For example, the first transistor TFT1 may be located at a higher position from the substrate 111 than the second transistor TFT2.

[0150] A first buffer layer (311 and / or 312) may be disposed below the first active layer ACT1 of the first transistor TFT1, and a second buffer layer 315 may be disposed below the second active layer ACT2 of the second transistor TFT2. For example, the first active layer ACT1 of the first transistor TFT1 may be located on the first buffer layer (311 and / or 312), and the second active layer ACT2 of the second transistor TFT2 may be located on the second buffer layer 315. The second buffer layer 315 may be located at a higher position than the first buffer layer (311 and / or 312) above the substrate 111.

[0151] The storage capacitor Cst can be disposed in several metal layers in the display panel 110. For example, the storage capacitor Cst may include a first capacitor electrode CAPE1 and a second capacitor electrode CAPE2.

[0152] The light-emitting element portion may include a plurality of light-emitting elements ED disposed on the insulating layer 320. Each of the plurality of light-emitting elements ED may include a first electrode 331, an intermediate layer 333, and a second electrode 335.

[0153] The following text will refer to Figure 4 The stacking configuration of display panel 110 is described in more detail.

[0154] refer to Figure 4 A first buffer layer (311 and / or 312) may be disposed on the substrate 111. The first buffer layer (311 and / or 312) may be a single layer or a multilayer. In an example where the first buffer layer (311 and / or 312) is a multilayer, the first buffer layer (311 and / or 312) may include a multi-buffer layer 311 and an active buffer layer 312.

[0155] Various types of transistors, at least one storage capacitor, and various electrodes or signal lines may be disposed on the first buffer layer (311 and / or 312). For example, the transistors disposed on the first buffer layer (311 and / or 312) may comprise the same material and be located in one or more identical layers. Alternatively, the transistors disposed on the first buffer layer (311 and / or 312) may comprise different materials and be located in one or more different layers.

[0156] The first active layer ACT1 of the first transistor TFT1 may be disposed on the first buffer layer (311 and / or 312). The first active layer ACT1 may include a channel region in which a channel is formed, a source connection region located on a first side of the channel region, and a drain connection region located on a second opposite side of the channel region. The first active layer ACT1 may refer to the active layer of the transistor, or it may refer to a semiconductor layer comprising the same material as the active layer. Therefore, the first active layer ACT1 may be included in the transistor, or it may be a circuit element and / or signal line different from the transistor.

[0157] A first gate insulating layer 313 may be disposed on the first active layer ACT1 of the first transistor TFT1. The first gate insulating layer 313 may be, for example, a single layer comprising silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer comprising silicon nitride (SiNx) and / or silicon oxide (SiOx). However, the aspects of this disclosure are not limited thereto.

[0158] The first gate electrode E1a of the first transistor TFT1 may be disposed on the first gate insulating layer 313. The first gate electrode E1a may refer to the gate electrode of the transistor, or it may refer to a metal layer comprising the same material as the gate electrode. Therefore, the first gate electrode E1a may be included in the transistor, or it may be a circuit element and / or signal line different from the transistor. The first gate electrode E1a may comprise a conductive material. For example, the first gate electrode E1a may be in the form of a single layer or multiple layers comprising one or more of the following materials, or an alloy comprising two or more of the following materials: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). However, aspects of this disclosure are not limited thereto. For example, the first gate electrode E1a may comprise a stack of two layers of Mo and Ti.

[0159] The first interlayer insulating layer 314 may be disposed on the first gate electrode E1a of the first transistor TFT1. The first interlayer insulating layer 314 may be, for example, a single layer comprising silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer comprising silicon nitride (SiNx) and / or silicon oxide (SiOx). However, the aspects of this disclosure are not limited thereto.

[0160] The second buffer layer 315 may be disposed on the first interlayer insulating layer 314. For example, the second buffer layer 315 may be a single layer comprising silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer comprising silicon nitride (SiNx) and / or silicon oxide (SiOx). However, the aspects of this disclosure are not limited thereto.

[0161] The second active layer ACT2 of the second transistor TFT2 may be disposed on the second buffer layer 315. The second active layer ACT2 may include a channel region forming a channel, a source connection region located on a first side of the channel region, and a drain connection region located on a second opposite side of the channel region. The second active layer ACT2 may refer to the active layer of the transistor, or it may refer to a semiconductor layer comprising the same material as the active layer. Therefore, the second active layer ACT2 may be included in the transistor, or it may be a circuit element and / or signal line different from the transistor.

[0162] The second gate insulating layer 316 may be disposed on the second active layer ACT2 of the second transistor TFT2. For example, the second gate insulating layer 316 may be a single layer comprising silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer comprising silicon nitride (SiNx) and / or silicon oxide (SiOx). However, the aspects of this disclosure are not limited thereto.

[0163] The second gate electrode E2a of the second transistor TFT2 may be disposed on the second gate insulating layer 316. The second gate electrode E2a may refer to the gate electrode of the transistor, or it may refer to a metal layer comprising the same material as the gate electrode. Therefore, the second gate electrode E2a may be included in the transistor, or it may be a circuit element and / or signal line different from the transistor. The second gate electrode E2a may comprise a conductive material. For example, the second gate electrode E2a may be in the form of a single layer or multiple layers comprising one or more of the following materials, or an alloy comprising two or more of the following materials: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). However, aspects of this disclosure are not limited thereto. For example, the second gate electrode E2a may comprise a stack of two layers of Mo and Ti.

[0164] The second interlayer insulating layer 317 may be disposed on the second gate electrode E2a of the second transistor TFT2. The second interlayer insulating layer 317 may be, for example, a single layer comprising silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer comprising silicon nitride (SiNx) and / or silicon oxide (SiOx). However, the aspects of this disclosure are not limited thereto.

[0165] The first source electrode E1b and the first drain electrode E1c of the first transistor TFT1, and the second source electrode E2b and the second drain electrode E2c of the second transistor TFT2 can be disposed on the second interlayer insulating layer 317.

[0166] The first source electrode E1b and the first drain electrode E1c of the first transistor TFT1 can be electrically connected to the source connection region and the drain connection region of the first active layer ACT1 through holes in the second interlayer insulating layer 317, the second gate insulating layer 316, the second buffer layer 315, the first interlayer insulating layer 314, and the first gate insulating layer 313, respectively.

[0167] The second source electrode E2b and the second drain electrode E2c of the second transistor TFT2 can be electrically connected to the source connection region and the drain connection region of the second active layer ACT2 through holes in the second interlayer insulating layer 317 and the second gate insulating layer 316, respectively.

[0168] The first source electrode E1b and the first drain electrode E1c of the first transistor TFT1, and the second source electrode E2b and the second drain electrode E2c of the second transistor TFT2, may comprise a first metal and may be disposed in a first metal layer. For example, the first metal and the first metal layer may be referred to as a first source-drain metal and a first source-drain metal layer, respectively, and the first metal layer may refer to a metal layer comprising the same material as the first source-drain metal. Therefore, the first source-drain electrodes (E1b and E1c) may be included in the transistor, or may be circuit elements and / or signal lines different from the transistor. The first source-drain electrodes (E1b and E1c) may comprise a conductive material. For example, the first source-drain electrodes (E1b and E1c) may be in the form of a single layer or multiple layers, which may comprise one or more of the following materials, or one or more alloys comprising two or more of the following materials: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). However, this disclosure is not limited thereto. For example, the first source-drain electrodes (E1b and E1c) may comprise a stack of three layers of Ti, Al, and Ti.

[0169] refer to Figure 4 In one or more aspects, the storage capacitor Cst may be configured with a first capacitor electrode CAPE1 and a second capacitor electrode CAPE2. In one or more aspects, the storage capacitor Cst may include three or more capacitor electrodes, or may include two or more capacitors connected in parallel.

[0170] Each of the first capacitor electrode CAPE1 and the second capacitor electrode CAPE2 can be disposed in several metal layers in the display panel 110.

[0171] In one or more aspects, the first capacitor electrode CAPE1 may include the same first gate metal as the first gate electrode E1a of the first transistor TFT1 on the first gate insulating layer 313, and is disposed in the first gate metal layer.

[0172] In one or more aspects, the second capacitor electrode CAPE2 may be disposed on the first interlayer insulating layer 314.

[0173] The second source electrode E2b of the second transistor TFT2 can be electrically connected to the second capacitor electrode CAPE2 through holes in the second interlayer insulating layer 317, the second gate insulating layer 316, and the second buffer layer 315.

[0174] For example, the first transistor TFT1 can be Figure 1 The scanning transistor ST, and the second transistor TFT2 can be Figure 1 The driving transistor DT.

[0175] refer to Figure 4 The transistor portion may further include a first shielding metal BSM1 disposed on the substrate 111, the first shielding metal BSM1 overlapping with the first active layer ACT1 of the first transistor TFT1 and disposed below the first active layer ACT1 of the first transistor TFT1. For example, the first shielding metal BSM1 may be disposed between the substrate 111 and the first buffer layer (311 and / or 312), or it may be disposed between the multiple buffer layer 311 and the active buffer layer 312.

[0176] The transistor portion may further include a second shielding metal BSM2 disposed on the substrate 111, the second shielding metal BSM2 overlapping with the second active layer ACT2 of the second transistor TFT2 and disposed below the second active layer ACT2 of the second transistor TFT2.

[0177] For example, the second shielding metal BSM2 can be disposed in the metal layer between the first interlayer insulating layer 314 and the second buffer layer 315. The second shielding metal BSM2 can be disposed in the same metal layer as the second capacitor electrode CAPE2.

[0178] In another example, the second shielding metal BSM2 may be disposed in the same first gate metal layer as the first gate electrode E1a of the first transistor TFT1.

[0179] An insulating layer 320 may be disposed on the first transistor TFT1 and the second transistor TFT2. The insulating layer 320 may be a planarization layer for planarizing one or more functional layers on which the first transistor TFT1 and the second transistor TFT2 are disposed. The insulating layer 320 may comprise one or more materials selected from acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polystyrene resin, benzocyclobutene, and polyphenylene sulfide resin, but this disclosure is not limited thereto.

[0180] The insulating layer 320 may include at least one recess 324 in at least one sub-pixel. The insulating layer 320 may include at least one peripheral portion 320c that surrounds and is located around the at least one recess 324.

[0181] The recess 324 may include a flat portion 320a and a sloped portion 320b surrounding the flat portion 320a. The surface of the flat portion 320a may be substantially parallel to the surface of the substrate 111. The sloped portion 320b may surround the flat portion 320a, and the surface of the sloped portion 320b may have a predetermined angle relative to the surface of the substrate 111. The surface of the sloped portion 320b may not be parallel to the surface of the substrate 111. For example, the surface of the sloped portion 320b may be a sloped surface with a predetermined angle relative to the surface of the substrate 111. A peripheral portion 320c may surround the sloped portion 320b and be located around the sloped portion 320b. The surface of the peripheral portion 320c may be substantially parallel to the surface of the substrate 111. To expose the relay electrode RE, an aperture may be located in the peripheral portion 320c, such that the aperture is spaced apart from the sloped portion 320b.

[0182] The insulating layer 320 can be a single layer or multiple layers. For example, Figure 4 The insulating layer 320 shown may include a structure in which three insulating layers (321, 322, and 323) are stacked on the first transistor TFT1 and the second transistor TFT2. For example, the insulating layer 320 may include a first insulating layer 321, a second insulating layer 322, and a third insulating layer 323, but the aspects of this disclosure are not limited thereto. When the insulating layer 320 is a multilayer comprising a first insulating layer 321, a second insulating layer 322, and a third insulating layer 323, the first to third insulating layers (321, 322, and 323) may comprise the same insulating material or may comprise different insulating materials.

[0183] For example, the first insulating layer 321 may be disposed on the first source electrode E1b and the first drain electrode E1c of the first transistor TFT1 and the second source electrode E2b and the second drain electrode E2c of the second transistor TFT2. For example, the first insulating layer 321 may be disposed to cover both the first transistor TFT1 and the second transistor TFT2. The first insulating layer 321 may include a hole for exposing the first source electrode E1b of the first transistor TFT1.

[0184] A relay electrode RE may be disposed on the first insulating layer 321. The relay electrode RE may be electrically connected to the first source electrode E1b of the first transistor TFT1 through a hole formed in the first insulating layer 321. In one or more aspects, the first source electrode E1b of the first transistor TFT1 may be electrically connected to the first shielding metal BSM1.

[0185] The relay electrode RE may be disposed in a second metal layer on the first insulating layer 321, and may include a second metal. The second metal and the second metal layer may be referred to as a second source-drain metal and a second source-drain metal layer, respectively. The second source-drain metal layer may refer to an electrode used for electrically connecting the first source-drain electrodes (E1b and E1c) and the light-emitting element ED, and may refer to a metal layer comprising the same material as the electrode. Therefore, the second source-drain metal layer may be included in an electrode used for electrically connecting the first transistor TFT1 and the light-emitting element ED, or may be included in a circuit element and / or signal line different from the electrode. The second source-drain metal layer may include a conductive material. For example, the second source-drain metal layer may be in the form of a single layer or multiple layers, which may include one or more of the following materials, or one or more alloys of two or more of the following materials: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). However, the aspects of this disclosure are not limited thereto. For example, the second source-drain metal layer may include a stack of Ti, Al, and Ti three layers.

[0186] A second insulating layer 322 may be disposed on the relay electrode RE. The second insulating layer 322 may include a hole for exposing the relay electrode RE. The second insulating layer 322 may include a flat portion 320a.

[0187] A third insulating layer 323 may be disposed on the second insulating layer 322. The third insulating layer 323 may include a hole for exposing the relay electrode RE. The third insulating layer 323 may include an inclined portion 320b and a peripheral portion 320c.

[0188] refer to Figure 4The second insulating layer 322 may include a flat portion 320a, and the third insulating layer 323 may include a sloped portion 320b and a peripheral portion 320c. For example, the flat portion 320a may represent a portion of the upper surface of the second insulating layer 322. The sloped portion 320b may extend from a portion of the upper surface of the second insulating layer 322 to the upper surface of the third insulating layer 323, and may represent a surface having a predetermined angle relative to the surface of the substrate 111. The peripheral portion 320c may represent the upper surface of the third insulating layer 323. However, the aspects of this disclosure are not limited thereto. For example, the third insulating layer 323 may include all of the flat portion 320a, the sloped portion 320b, and the peripheral portion 320c.

[0189] refer to Figure 4 The light-emitting element portion may be disposed on the insulating layer 320. The light-emitting element ED, which is electrically connected to the relay electrode RE through a hole, may be disposed on the insulating layer 320. For example, the light-emitting element ED may be disposed on the second insulating layer 322 and the third insulating layer 323.

[0190] The light-emitting element (ED) may include: a first electrode 331 electrically connected to the first source electrode E1b of the first transistor TFT1; an intermediate layer 333 disposed on the first electrode 331; and a second electrode 335 disposed on the intermediate layer 333. The first electrode 331, the intermediate layer 333, and the second electrode 335 may be respectively connected to... Figure 1 The pixel electrode PE, intermediate layer EL, and common electrode CE correspond to each other. Figure 4 The first electrode 331 is shown to be electrically connected to the first source electrode E1b of the first transistor TFT1, but this disclosure is not limited thereto. For example, the first electrode 331 may be electrically connected to the first drain electrode E1c of the first transistor TFT1.

[0191] The first electrode 331 may include a first portion 331a, the surface of which is substantially parallel to the surface of the substrate 111 in the region overlapping with the recess 324; and a second portion 331b, extending from the first portion 331a and having a surface inclined at a predetermined angle relative to the substrate 111. The surface of the second portion 331b may not be parallel to the surface of the substrate 111. The first portion 331a may be a region overlapping with the flat portion 320a. The second portion 331b may be a region overlapping with the inclined portion 320b. The first electrode 331 may include a third portion 331c, extending from the second portion 331b and having a surface substantially parallel to the surface of the substrate 111. The third portion 331c may be a region overlapping with the peripheral portion 320c. For example, the first portion 331a may correspond to the flat portion 320a included in the second insulating layer 322. The second portion 331b may correspond to the inclined portion 320b of the third insulating layer 323. The third part 331c can correspond to the outer part 320c of the third insulating layer 323.

[0192] The auxiliary line 220 may be disposed on the insulating layer 320. The auxiliary line 220 may be disposed on the peripheral portion 320c of the insulating layer 320 and spaced apart from the first electrode 331. The auxiliary line 220 may include the material included in the first electrode 331. The auxiliary line 220 may be disposed in a layer substantially the same as the first electrode 331. For example, the auxiliary line 220 may be disposed on the peripheral portion 320c of the third insulating layer 323 and spaced apart from the first electrode 331.

[0193] A dam 325 may be disposed on the insulating layer 320, a portion of the first electrode 331, and a portion of the auxiliary line 220. The dam 325 may be disposed on the corresponding portions of the first electrode 331, the insulating layer 320, and the auxiliary line 220 in the region corresponding to the peripheral portion 320c of the insulating layer 320. The dam 325 may be disposed on the corresponding portions of the first electrode 331, the insulating layer 320, and the auxiliary line 220 in the region corresponding to the peripheral portion 320c of the third insulating layer 323. The dam 325 may expose the first portion 331a and the second portion 331b of the first electrode 331 in the region overlapping with the recess 324. The dam 325 may be configured to cover the third portion 331c of the first electrode 331 in the region overlapping with the peripheral portion 320c of the insulating layer 320, and may also be configured to expose a portion of the third portion 331c of the first electrode 331. For example, the embankment 325 may be configured to expose the portion of the third portion 331c of the first electrode 331 adjacent to the second portion 331b of the first electrode 331. The embankment 325 may be configured to expose a portion of the upper surface of the auxiliary line 220 in the region overlapping with the peripheral portion 320c of the insulating layer 320.

[0194] The embankment 325 may include a first opening region OA1 overlapping the recess 324 and a second opening region OA2 exposing at least a portion of the auxiliary line 220. In the first opening region OA1, the embankment 325 may be configured not to overlap with the first portion 331a and the second portion 331b of the first electrode 331. For example, in the first opening region OA1, the second portion 331b of the first electrode 331 and at least one first side surface of the embankment 325 may include inclined surfaces located in the same plane. In a plan view, the first opening region OA1 may overlap with the first portion 331a of the first electrode 331, and the second opening region OA2 may overlap with a portion of the auxiliary line 220.

[0195] The dam 325 may include a transparent insulating resin, such as polyimide resin, acrylic resin, benzocyclobutene resin, etc., but this disclosure is not limited thereto.

[0196] For example, the dam 325 can be a black dam with high light absorption. In this example, the black dam can absorb light propagating toward adjacent sub-pixels and prevent color mixing between sub-pixels SP. Furthermore, the black dam can absorb light incident on the display panel 110 from the outside, reducing reflectivity and improving reflective visibility.

[0197] For example, a black embankment can be formed by dispersing a colorant in a transparent insulating resin. The colorant can be selected from carbon-based pigments, metal oxide-based pigments, or organic pigments. For example, carbon-based pigments can be selected from carbon black, carbon nanotubes, vanta black, etc., but this disclosure is not limited thereto. For example, metal oxide pigments can be titanium black (TiNxOy) or Cu-Mn-Fe-based black pigments, but this disclosure is not limited thereto. For example, organic pigments can be selected from lactam black, perylene black, or aniline black, but this disclosure is not limited thereto. In another example, the colorant can be a mixture of two or more pigments or dyes with different colors.

[0198] The protective layer 340 may be disposed on the embankment 325 and the first electrode 331. The protective layer 340 may include a first portion 340a, a second portion 340b, and a third portion 340c.

[0199] The first portion 340a of the protective layer 340 may be configured to correspond to the inclined portion 320b of the recess 324. For example, in the first opening region OA1, the first portion 340a of the protective layer 340 may be disposed on the entire second portion 331b of the first electrode 331 and the entire first side surface of the embankment 325.

[0200] The second portion 340b of the protective layer 340 may be disposed on the upper surface of the embankment 325 disposed in the peripheral portion 320c. For example, the second portion 340b of the protective layer 340 may extend from the first portion 340a of the protective layer 340 and be disposed on the entire upper surface of the embankment 325 between the first opening region OA1 and the second opening region OA2.

[0201] The third portion 340c of the protective layer 340 may be disposed on the entire second side surface of the embankment 325 disposed in the peripheral portion 320c. For example, the third portion 340c of the protective layer 340 may extend from the second portion 340b of the protective layer 340 and be disposed on the entire second side surface of the embankment 325 in the second opening region OA2. In this example, the third portion 340c of the protective layer 340 may contact the upper surface of the auxiliary line 220 disposed in the second opening region OA2, but aspects of this disclosure are not limited thereto.

[0202] The protective layer 340 may further include a fourth portion 340d disposed on a second side embankment 325, which is spaced apart from the first side embankment 325, wherein a third portion 340c of the protective layer 340 is disposed in the second opening region OA2. In this document, the first side embankment 325 and the second side embankment 325 may be referred to as adjacent portions of the embankment 325 located on one side of the embankment 325 in a cross-sectional view. For example, the fourth portion 340d of the protective layer 340 may be configured such that the fourth portion 340d extends from the upper surface of the second side embankment 325 and protrudes into the second opening region OA2.

[0203] refer to Figure 4 An undercut region UCA may be formed below the protective layer 340. The undercut region UCA may be the area where no embankment 325 is provided below the protective layer 340. In the undercut region UCA, the protective layer 340 may protrude beyond the embankment 325. For example, in the undercut region UCA, the fourth portion 340d of the protective layer 340 may protrude beyond the second side embankment 325. In the second opening region OA2, the fourth portion 340d of the protective layer 340 and the auxiliary line 220 may be spaced apart from each other, but in a plan view, the fourth portion 340d of the protective layer 340 and the auxiliary line 220 may overlap each other.

[0204] The protective layer 340 may include a transparent inorganic insulating material. The protective layer 340 may be a single layer or multiple layers of silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy), but this disclosure is not limited thereto.

[0205] An intermediate layer 333, including at least one emitter layer, may be disposed on the protective layer 340 and the first electrode 331. The intermediate layer 333 may be formed by a deposition or coating method having flatness. For example, the intermediate layer 333 may be formed by a physical vapor deposition (PVD) method (e.g., evaporation process). The intermediate layer 333 may include a first portion 333a, a second portion 333b, and a third portion 333c.

[0206] The first portion 333a of the intermediate layer 333 may be configured to correspond to the flat portion 320a and the inclined portion 320b of the recess 333. For example, in the first opening region OA1, the first portion 333a of the intermediate layer 333 may be disposed on the first portion 331a of the first electrode 331 and the first portion 340a of the protective layer 340.

[0207] The second portion 333b of the intermediate layer 333 may be disposed on the upper surface of the embankment 325 disposed in the peripheral portion 320c. For example, the second portion 333b of the intermediate layer 333 may extend from the first portion 333a of the intermediate layer 333 and be disposed on the second portion 340b of the protective layer 340 between the first opening region OA1 and the second opening region OA2.

[0208] The third portion 333c of the intermediate layer 333 may be disposed on the entire second side surface of the embankment 325 disposed in the peripheral portion 320c. For example, the third portion 333c of the intermediate layer 333 may extend from the second portion 333b of the intermediate layer 333 and be disposed on the third portion 340c of the protective layer 340 in the second opening region OA2. In this example, the third portion 333c of the intermediate layer 333 may extend to a portion of the upper surface of the auxiliary line 220 disposed in the second opening region OA2 and may not overlap with the fourth portion 340d of the protective layer 340. However, aspects of this disclosure are not limited thereto. For example, the intermediate layer 333 may not be disposed in the undercut region UCA, but aspects of this disclosure are not limited thereto.

[0209] The intermediate layer 333 may also include a fourth portion 333d spaced apart from the third portion 333c of the intermediate layer 333. For example, the fourth portion 333d of the intermediate layer 333 may be disposed on the fourth portion 340d of the protective layer 340. In the undercut region UCA, the intermediate layer 333 may protrude beyond the embankment 325. For example, in the undercut region UCA, the fourth portion 333d of the protective layer 333 may protrude beyond the second side embankment 325. In the second opening region OA2, the fourth portion 333d of the intermediate layer 333 and the auxiliary line 220 may be spaced apart from each other, but the fourth portion 333d of the intermediate layer 333 and the auxiliary line 220 may overlap each other in the plan view. In the second opening region OA2, the third portion 333c and the fourth portion 333d of the intermediate layer 333 may be configured not to overlap each other in the plan view.

[0210] The second electrode 335 may be disposed on the intermediate layer 333. The second electrode 335 may be disposed along the shape of the intermediate layer 333. The second electrode 335 may be formed by a deposition method with an irregular orientation. For example, the second electrode 335 may be formed by a deposition process with an irregular orientation, such as sputtering. The second electrode 335 may include a first portion 335a, a second portion 335b, and a third portion 335c.

[0211] The first portion 335a of the second electrode 335 may be configured such that the first portion 335a corresponds to the first portion 333a of the intermediate layer 333 and the flat portion 320a and inclined portion 320b of the recess 324. For example, in the first opening region OA1, the first portion 335a of the second electrode 335 may be disposed on the first portion 333a of the intermediate layer 333.

[0212] The second portion 335b of the second electrode 335 may be disposed on the upper surface of the embankment 325 disposed in the peripheral portion 320c. For example, the second portion 335b of the second electrode 335 may extend from the first portion 335a of the second electrode 335 and be disposed on the second portion 333b of the intermediate layer 333 between the first opening region OA1 and the second opening region OA2.

[0213] The third portion 335c of the second electrode 335 may be disposed on the entire second side surface of the embankment 325 disposed in the peripheral portion 320c. For example, the third portion 335c of the second electrode 335 may extend from the second portion 335b of the second electrode 335 and be disposed to cover the third portion 333c of the intermediate layer 333 in the second opening region OA2. In this example, the third portion 335c of the second electrode 335 may cover a portion of the third portion 333c of the intermediate layer 333 (which is formed by extending to a portion of the upper surface of the auxiliary line 220 in the second opening region OA2) and be disposed on a portion of the upper surface of the auxiliary line 220. For example, the third portion 335c of the second electrode 335 may be disposed such that the third portion 335c extends to the undercut region UCA.

[0214] The second electrode 335 may further include a fourth portion 335d spaced apart from the third portion 335c of the second electrode 335. For example, the fourth portion 335d of the second electrode 335 may be disposed on the fourth portion 333d of the intermediate layer 333. In the undercut region UCA, the second electrode 335 may protrude beyond the embankment 325. For example, in the undercut region UCA, the fourth portion 335d of the second electrode 335 may protrude beyond the second side embankment 325. In the second opening region OA2, the fourth portion 335d of the second electrode 335 may be spaced apart from the auxiliary line 220, but the fourth portion 340d of the second electrode 335 and the auxiliary line 220 may overlap each other in the plan view. The third portion 335c and the fourth portion 335d of the second electrode 335 may be spaced apart from each other in the second opening region OA2, but the third portion 335c and the fourth portion 335d of the second electrode 335 may overlap each other in the plan view.

[0215] refer to Figure 4 Because the fourth portion 340d of the protective layer 340 is positioned to protrude beyond the embankment 325, each of the intermediate layer 333 and the second electrode 335 located on the protective layer 340 may have a discontinuous structure. For example, due to the shading effect, the intermediate layer 333 and the second electrode 335 may be difficult to deposit in the undercut region UCA below the protective layer 340. Therefore, the intermediate layer 333 may be formed discontinuously, and for example, in the region corresponding to the second opening region OA2 in the cross-sectional view, it is divided into a first portion on the first side and a second portion on the second opposite side. Similarly, the second electrode 335 may also be formed discontinuously, and for example, in the region corresponding to the second opening region OA2 in the cross-sectional view, it is divided into a first portion on the first side and a second portion on the second opposite side.

[0216] The intermediate layer 333 can be formed by a deposition process with flatness (e.g., vapor deposition), and the second electrode 335 can be formed by a deposition process with irregular orientation (e.g., sputtering). According to these embodiments, the intermediate layer 333 may not be formed below the fourth portion 340d of the protective layer 340, while the second electrode 335 can be formed by extending a portion below the fourth portion 340d of the protective layer 340. Therefore, the second electrode 335 can be easily electrically connected to the auxiliary line 220 in the second opening region OA2. Thus, the display panel 110 can provide the advantage of reduced resistance of the second electrode 335 and improved brightness uniformity.

[0217] In the following discussion of the configuration shown in the figures, for ease of description, the representations of transistors (TFT1 and TFT2) and storage capacitor Cst are omitted, and the first buffer layer (311, 312), first gate insulating layer 313, first interlayer insulating layer 314, second buffer layer 315, second gate insulating layer 316, and second interlayer insulating layer 317, which have been discussed above with reference to the preceding figures, are collectively referred to as TFT array substrate 310. However, it should be noted that although the omitted configuration can be applied equivalently or similarly, the structure with the omitted configuration is not limited to... Figure 4 The configuration shown.

[0218] Figure 5 The display panel 110 is along the edge of the aspect of this disclosure. Figure 3 Another example cross-sectional view taken from the I-I' line. In the following... Figure 5 In the discussion of the configuration, for the sake of simplicity, descriptions and references will be omitted or briefly explained. Figures 1 to 4 Discussion of features and configurations that are identical, substantially identical, or similar to those described.

[0219] refer to Figure 5 In one or more example embodiments, the display panel 110 may include a substrate 111, and a TFT array substrate 310, an insulating layer 320, a dam 325, a first electrode 331, an intermediate layer 333, a second electrode 335, and a protective layer 340 disposed on the substrate 111.

[0220] refer to Figure 5 The encapsulation portion may be disposed on the light-emitting element portion and located on the second electrode 335. The encapsulation portion may include an encapsulation layer 350 disposed on the second electrode 335.

[0221] The encapsulation layer 350 prevents moisture or oxygen from penetrating into the light-emitting element (ED). For example, the encapsulation layer 350 prevents moisture or oxygen from penetrating into the organic material included in the intermediate layer 333 of the light-emitting element (ED). For example, the encapsulation layer 350 may be in the form of a single layer or multiple layers, but this disclosure is not limited thereto.

[0222] refer to Figure 5 For example, the encapsulation layer 350 may include a first encapsulation layer 351, a second encapsulation layer 352, and a third encapsulation layer 353. The first encapsulation layer 351 and the third encapsulation layer 353 may include, for example, inorganic layers, and the second encapsulation layer 352 may include, for example, an organic layer.

[0223] The color filter layer 360 can be disposed on the encapsulation layer 350.

[0224] The third buffer layer 361 can be disposed on the third encapsulation layer 353.

[0225] A black matrix 362 and at least one color filter 363 may be disposed on the third buffer layer 361. The black matrix 362 and the color filter 363 may have anti-reflective functions to minimize the decrease in visibility and contrast of the display device 100 due to external light by absorbing external light while maintaining the brightness of the light emitted from the light-emitting element ED at a high level.

[0226] A black matrix 362 may be disposed on a third buffer layer 361 such that the black matrix 362 overlaps with at least a portion of the embankment 325. The black matrix 362 may define at least one color filter 363. Therefore, the black matrix 362 can minimize color mixing between adjacent sub-pixels SP. The black matrix 362 can absorb external light. Therefore, the degradation of visibility and contrast of the display device 100 due to external light can be minimized.

[0227] The width of the black matrix 362 can be smaller than the width of its corresponding embankment 325. For example, at least one side of the embankment 325 can protrude more towards the light-emitting area of ​​the light-emitting element ED than at least one corresponding side of the black matrix 362. According to this example, viewing angle brightness and color viewing angle can be improved.

[0228] Black matrix 362 may include organic materials. Black matrix 362 may include a base resin and a colorant. The base resin may be at least one selected from cardo-based resins, epoxy-based resins, acrylate-based resins, siloxane-based resins, or polyimides, but this disclosure is not limited thereto. For example, the colorant may be selected from carbon-based pigments, metal oxide-based pigments, or organic pigments. For example, carbon-based pigments may be selected from carbon black, carbon nanotubes, vander black, etc., but this disclosure is not limited thereto. For example, metal oxide pigments may be titanium black (TiNxOy) or Cu-Mn-Fe-based black pigments, but this disclosure is not limited thereto. For example, organic pigments may be selected from lactam black, perylene black, or aniline black, but this disclosure is not limited thereto. In another example, the colorant may be a mixture of two or more pigments or dyes with different colors.

[0229] Color filter 363 may be disposed on the third buffer layer 361 to overlap with the light-emitting element ED on the insulating layer 320. Color filter 363 may be configured to cover a portion of the black matrix 362.

[0230] although Figure 5 The diagram shows a structure in which the black matrix 362 and the color filter 363 are disposed on the third buffer layer 361; however, the scope of this disclosure is not limited thereto. For example, the third buffer layer 361 may be omitted, and the black matrix 362 and the color filter 363 may be disposed on the third encapsulation layer 353.

[0231] A color filter protection layer 364 can be set to cover the black matrix 362 and the color filter 363.

[0232] refer to Figure 5 The sub-pixel SP may include a first light-emitting region EA1, a second light-emitting region EA2, a first non-light-emitting region NEA1, and a second non-light-emitting region NEA2. The second light-emitting region EA2 may be configured in a shape surrounding the first light-emitting region EA1. The first non-light-emitting region NEA1 may be located between the first light-emitting region EA1 and the second light-emitting region EA2, and configured in a shape surrounding the first light-emitting region EA1. The second non-light-emitting region NEA2 may be configured in a shape surrounding the second light-emitting region EA2.

[0233] The first light-emitting region EA1 may correspond to the region in which the first electrode 331, the intermediate layer 333, and the second electrode 335 overlap. For example, the first light-emitting region EA1 may correspond to the region in which light emitted from the light-emitting element ED is emitted. The second light-emitting region EA2 may correspond to the region in which light emitted from the light-emitting element ED is reflected and guided from the second portion 331b of the first electrode 331.

[0234] The first non-light-emitting region NEA1 may correspond to a region in which a portion of the first portion 331a of the first electrode 331 disposed on the flat portion 320a of the recess 324 of the insulating layer 320 overlaps with the protective layer 340. The second non-light-emitting region NEA2 may correspond to a region between adjacent sub-pixels SP, for example, the region between the corresponding second light-emitting regions EA2 of adjacent sub-pixels SP.

[0235] The luminescent and non-luminescent regions of subpixel SP will be discussed in more detail below.

[0236] The first electrode 331 may include a reflective metal.

[0237] For ease of explanation, Figure 5The first electrode 331 is shown as a single layer, but this disclosure is not limited thereto. For example, the first electrode 331 may have a multilayer structure. In an example where the first electrode 331 has a multilayer structure, at least one layer may include a reflective metal.

[0238] For example, the first electrode 331 may have a multilayer structure, including: a transparent layer comprising a transparent conductive film; and a reflective layer comprising an opaque conductive film having high reflectivity. For example, the transparent conductive film may comprise a material with a relatively large work function value, such as indium tin oxide (ITO) or indium zinc oxide (IZO); and the opaque conductive film may have a single-layer or multilayer structure, including aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), or titanium (Ti), or alloys thereof. For example, the first electrode 331 may have a structure in which the transparent conductive film, the opaque conductive film, and the transparent conductive film are sequentially stacked, or a structure in which the transparent conductive film and the opaque conductive film are sequentially stacked.

[0239] In one or more aspects, a second portion 331b of the first electrode 331 may be disposed on a corresponding side surface of at least one inclined portion 320b of the insulating layer 320, following the shape of the inclined portion 320b. The second portion 331b of the first electrode 331 disposed on a side surface of at least one inclined portion 320b of the insulating layer 320 may have an inverted conical shape, which slopes from the first portion 331a of the first electrode 331 toward the third portion 331c. However, aspects of this disclosure are not limited thereto. The second portion 331b of the first electrode 331, including a reflective layer, may serve as a side reflective layer.

[0240] In this structure, the second portion 331b of the first electrode 331 can serve as a reflective layer to reflect light emitted from the light-emitting element ED upwards. Light emitted from the intermediate layer 333 of the light-emitting element ED can propagate not only upwards but also laterally. For example, the second portion 331b of the first electrode 331, including the reflective layer, can be configured as a side surface covering at least one inclined portion 320b of the insulating layer 320, thereby guiding laterally propagated light upwards. That is, a second light-emitting region EA2 can be formed. According to this configuration, the light extraction efficiency of the display device 100 can be improved.

[0241] The second electrode 335 can be configured to face the first electrode 331, with the intermediate layer 333 inserted between the second electrode 335 and the first electrode 331. Therefore, the second electrode 335 can be disposed on the intermediate layer 333.

[0242] The second electrode 335 may include a conductive material that is transparent or semi-transparent. For example, the second electrode 335 may include at least one transparent conductive oxide, such as ITO, IZO, indium tin zinc oxide (ITZO), zinc oxide, tin oxide, etc., or include a semi-transparent metal, such as magnesium (Mg), silver (Ag), or an alloy of magnesium and silver.

[0243] For example, when the second electrode 335 comprises a translucent metal, the thickness of the second electrode 335 can be less than the thickness of the first electrode 331.

[0244] Figure 6 For the display panel 110 along the aspect of this disclosure Figure 3 Another example cross-sectional view taken from the I-I' line. In the following... Figure 6 In the discussion of the configuration, for the sake of simplicity, descriptions and references will be omitted or briefly explained. Figures 1 to 5 Discussion of features and configurations that are the same, substantially the same, or similar.

[0245] refer to Figure 6 In one or more example embodiments, the display panel 110 may include a substrate 111, and a TFT array substrate 310, an insulating layer 320, a dam 325, a first electrode 331, an intermediate layer 333, a second electrode 335 and a protective layer 340 disposed on the substrate 111.

[0246] refer to Figure 6 The display panel 110 may include a stepped portion STP located at the outer portion 320c of the insulating layer 320.

[0247] The stepped portion STP can be formed such that the embankment 325 exposes a portion of the third portion 331c of the first electrode 331 in the region where the embankment 325 overlaps with the peripheral portion 320c of the insulating layer 320. For example, the stepped portion STP can be formed in such a configuration that the embankment 325 is positioned at a specific distance from at least one inclined portion 320b of the insulating layer 320 at the peripheral portion 320c of the insulating layer 320.

[0248] Since the stepped portion STP is located at the outer portion 320c of the insulating layer 320, the distance between the embankment 325 and the first portion 331a of the first electrode 331 is increased, and thus the travel distance of the exhaust can be increased even when exhaust is released from the embankment 325.

[0249] Figure 7 The display panel 110 is along the edge of the aspect of this disclosure. Figure 3 Another example cross-sectional view taken from the I-I' line. In the following... Figure 7In the discussion of the configuration, for the sake of simplicity, descriptions and references will be omitted or briefly explained. Figures 1 to 6 Discussion of features and configurations that are the same, substantially the same, or similar.

[0250] refer to Figure 7 In one or more example embodiments, the display panel 110 may include a substrate 111, and a TFT array substrate 310, an insulating layer 320, a dam 325, a first electrode 331, an intermediate layer 333, a second electrode 335 and a protective layer 340 disposed on the substrate 111.

[0251] The TFT array substrate 310 may include transistors (TFT1 and TFT2). The transistors (TFT1 and TFT2) may include active layers (ACT1 and ACT2) comprising oxide semiconductors. When the active layers (ACT1 and ACT2) comprise oxide semiconductors, hydrogen in the active layers (ACT1 and ACT2) may induce conductivity.

[0252] The protective layer 340 may comprise a transparent inorganic insulating material. The protective layer 340 may be a single layer or multiple layers of silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy). For example, when the protective layer 340 comprises a nitride (e.g., silicon nitride (SiNx) or silicon oxynitride (SiOxNy)), hydrogen may remain during the deposition of the protective layer 340. In this case, the active layers (ACT1 and ACT2) may achieve conductivity through the hydrogen remaining in the protective layer 340.

[0253] Therefore, a hydrogen trapping layer 710 for preventing or reducing hydrogen movement can be provided between the protective layer 340 and the active layers (ACT1 and ACT2).

[0254] The hydrogen trapping layer 710 may be disposed on the first planarization layer 321. The hydrogen trapping layer 710 may be disposed in a region that overlaps with at least one active layer (ACT1 and / or ACT2). For example, the hydrogen trapping layer 710 may be disposed in a region in which no metal layer is disposed between the protective layer 340 and at least one active layer (ACT1 and / or ACT2).

[0255] Since the hydrogen capture layer 710 is disposed in the region overlapping with at least one active layer (ACT1 and / or ACT2), residual hydrogen in the protective layer 340 can be captured efficiently, thereby preventing hydrogen from diffusing into at least one active layer (ACT1 and / or ACT2).

[0256] The hydrogen trapping layer 340 may include a hydrogen trapping metal. For example, the hydrogen trapping metal may be at least one of titanium (Ti), tantalum (Ta), zirconium (Zr), scandium (Sc), yttrium (Y), lutetium (Lu), hafnium (Hf), vanadium (V), niobium (Nb), cerium (Ce), calcium (Ca), magnesium (Mg), barium (Ba), lithium (Li), and strontium (Sr), but aspects of this disclosure are not limited thereto.

[0257] In one or more aspects, the source and drain electrodes of the transistors (TFT1 and TFT2) may be configured to overlap with the hydrogen trapping layer 710. For example, the second source and second drain electrodes (E2b and E2c) of the second transistor TFT2 may be configured to overlap with the hydrogen trapping layer 710. For example, the second source and second drain electrodes (E2b and E2c) of the second transistor TFT2 may be configured to cover the second active layer ACT2. Since the second source and second drain electrodes (E2b and E2c) are configured to overlap with the hydrogen trapping layer 710 and cover the active layer, hydrogen migration can be prevented or reduced. Figure 7 The diagram shows a structure in which the second source electrode and the second drain electrode (E2b and E2c) of the second transistor TFT2 are configured to cover the second active layer ACT2, but this disclosure is not limited thereto. For example, the first source electrode and the first drain electrode (E1b and E1c) of the first transistor TFT1 may also be configured to cover the first active layer ACT1.

[0258] Figure 8 For the display panel 110 along the aspect of this disclosure Figure 3 Example cross-sectional view taken from line II-II' in the following section. Figure 8 In the discussion of the configuration, for the sake of simplicity, descriptions and references will be omitted or briefly explained. Figures 1 to 7 Discussion of features and configurations that are the same, substantially the same, or similar.

[0259] In one or more example embodiments, Figure 8 An example electrical connection structure of auxiliary line 220 and common voltage line 210 in the outer edge of display panel 110 is shown.

[0260] refer to Figure 8 One or more first contacts CP1 can be formed in the display area DA. The second electrode 335 and the auxiliary line 220 can be electrically connected in the first contacts CP1. The auxiliary line 220 can be electrically connected to the common voltage line 210 in the non-display area NDA. To enable the auxiliary line 220 to be electrically connected to the common voltage line 210, a second contact CP2 can be provided below the auxiliary line 220. The second contact CP2 can be provided in the non-display area NDA. The auxiliary line 220 can be electrically connected to the common voltage line 210 through the second contact CP2.

[0261] Since the first contact CP1, which electrically interconnects the second electrode 335 with the auxiliary line 220, is located in the display area DA instead of the non-display area NDA, the bezel size of the display panel 110 can be reduced.

[0262] Figures 9 to 13 An example process for manufacturing a display panel 110 according to aspects of this disclosure is shown. In the following... Figures 9 to 13 In the discussion of the configuration, for the sake of simplicity, descriptions and references will be omitted or briefly explained. Figures 1 to 8 Discussion of features and configurations that are identical, substantially identical, or similar to those described.

[0263] First, refer to Figure 9 The substrate 111 and the TFT array substrate 310 can be formed sequentially. Next, an insulating layer 320 can be formed on the array substrate 310. The insulating layer 320 may include a recess 324 and at least one contact hole.

[0264] For example, as insulating layer 320, a first insulating layer 321, a second insulating layer 322, and a third insulating layer 323 can be sequentially formed on the TFT array substrate 310. Contact holes for electrical connection to the source or drain electrode of a transistor can be formed in the first insulating layer 321. Contact holes for electrical connection to the relay electrode RE can be formed in the second insulating layer 322. Contact holes for electrical connection to the relay electrode RE and a recess for disposing a light-emitting element can be formed in the third insulating layer 323.

[0265] Next, a first electrode 331 and an auxiliary line 220 can be formed by patterning on the insulating layer 320. The auxiliary line 220 may include the same material as that included in the first electrode 331. The auxiliary line 220 may be formed in a layer substantially the same as the first electrode 331. The first electrode 331 can be electrically connected to the relay electrode RE through contact holes in the second insulating layer 322 and the third insulating layer 323. Therefore, the first electrode 331 can be electrically connected to the transistor. The auxiliary line 220 may be formed to be spaced apart from the recess 324 and the first electrode 331.

[0266] Next, the embankment 325a may be formed to cover the first electrode 331 and the auxiliary line 220. The embankment 325a may be formed such that a first opening region OA1 overlapping the recess 324 and a second opening region OA2 exposing a portion of the auxiliary line 220 are formed through a patterning process. At least a portion of the first electrode 331 disposed on at least one inclined portion of the recess 324 and at least one inclined portion of the first opening region OA1 of the embankment 325a may be formed to have the same inclined surface. In this embodiment, the embankment 325a may comprise a black embankment material.

[0267] Next, refer to Figure 10 A protective layer 340 is formed on the embankment 325a, the first electrode 331, and the auxiliary line 220. The protective layer 340 may comprise an inorganic insulating material. The protective layer 340 may be formed such that the upper surface of the first electrode 331 disposed in the flat portion of the recess 324 and the upper surface of the auxiliary line 220 disposed in the second opening region OA2 are exposed by a patterning process. For example, the protective layer 340 may have a discontinuous structure in the regions corresponding to the first opening region OA1 and the second opening region OA2. In this example, the protective layer 340 may be formed in the second opening region OA2 such that the protective layer 340 extends along the inclined portion of the first side embankment 325a, and the protective layer 340 is disposed on the second side embankment 325a but does not extend along the inclined portion of the second side embankment 325a. For example, the inclined portion of the second side embankment 325a may be exposed to the outside.

[0268] Next, refer to Figure 11 The exposed inclined portion of the second side embankment 325a can be further etched to complete the embankment 325. In this embodiment, a protective layer 340 comprising an inorganic insulating material can be used as a mask, and the embankment 325 can be formed by additional etching through an ashing or developing process. According to this process, an undercut region UCA can be formed below the protective layer 340. The undercut region UCA can refer to the area where the embankment 325 is removed below the protective layer 340. In the undercut region UCA, the protective layer 340 may protrude beyond the embankment 325. With the formation of the undercut region UCA, the size of the second opening region OA2 of the exposed auxiliary line 220 can be increased.

[0269] Next, refer to Figure 12 An intermediate layer 333 can be formed on the protective layer 340, the first electrode 331, and the auxiliary line 220. The intermediate layer 333 may have a discontinuous structure in the region corresponding to the second opening region OA2. The intermediate layer 333 can be formed by a deposition process with flatness (e.g., vapor deposition). For example, the intermediate layer 333 can be formed by a deposition process of vapor deposition of organic materials. The intermediate layer 333 may be formed only on the protective layer 340, the first electrode 331, and the auxiliary line 220, and may not be formed in the undercut region UCA covered by the protective layer 340. For example, the intermediate layer 333 may not be formed on the inclined portion of the embankment 325 located below the protruding protective layer 340 in the second opening region OA2 and on the auxiliary line 220. Since the intermediate layer 333 is formed to be discontinuous in the second opening region OA2, the auxiliary line 220 can be exposed by the intermediate layer 333.

[0270] refer to Figure 13A second electrode 335 can be formed on the intermediate layer 333. The second electrode 335 may have a discontinuous structure in the region corresponding to the second opening region OA2. The second electrode 335 can be formed by a deposition process (e.g., sputtering) with an irregular orientation. According to this process, the second electrode 335 may cover one end of the intermediate layer 333 in the second opening region OA2 and may be deposited onto a portion of the auxiliary line 220. For example, the second electrode 335 may be formed to the portion of the auxiliary line 220 that overlaps with the undercut region UCA. For example, the second electrode 335 may be formed to extend to the portion of the auxiliary line 220 located below the protective layer 340 with protrusions in the second opening region OA2. Therefore, the second electrode 335 can be easily electrically connected to the auxiliary line 220 in the second opening region OA2, and the auxiliary line 220 can be electrically connected to the common voltage line 210 in the outer edge of the display region DA. Thus, the display panel 110 can provide the advantages of reduced resistance of the second electrode 335 and improved brightness uniformity.

[0271] Figure 14 This is a floor plan of example display panel 1100. In the following... Figure 14 In the discussion of the configuration, for the sake of simplicity, descriptions and references will be omitted or briefly explained. Figures 1 to 13 Discussion of features and configurations that are the same, substantially the same, or similar.

[0272] refer to Figure 14 The display panel 1100 can have the following structure: a common electrode CE extends to the non-display area NDA and is connected to a common voltage line 510 via a connection electrode in the non-display area NDA. In this structure, the common electrode CE can be a single layer corresponding to a plurality of sub-pixels SP of the display panel 110. The common electrode CE can include a thin transparent conductive material to improve transmittance, and in this embodiment, the common electrode CE can have a high surface resistance value. Therefore, the common electrode CE may not have a constant voltage value throughout its surface. For example, a voltage difference may occur between regions P1 and P2. Due to this voltage drop (IR drop) phenomenon, brightness differences may occur between regions in the display area DA. For example, as the area of ​​the display device 100 increases, the voltage drop phenomenon may become more severe.

[0273] Figure 15 and Figure 16 This is an example cross-sectional view of display panel 1100. In the following... Figure 15 and Figure 16 In the discussion of the configuration, for the sake of simplicity, descriptions and references will be omitted or briefly explained. Figures 1 to 14 Discussion of features and configurations that are the same, substantially the same, or similar.

[0274] like Figure 15 As shown, the display panel 1100 may have an intermediate layer 333 disposed on the first electrode 331.

[0275] The intermediate layer 333 can be formed by physically depositing an organic material on the first electrode 331 using a vapor deposition process. In this case, the thickness of the intermediate layer 333 in the region at a predetermined angle to the horizontal plane may be thinner than its thickness in the region parallel to the horizontal plane. For example, the thickness of the intermediate layer 333 disposed in the region corresponding to the inclined portion of the recess 324 may be less than the thickness of the intermediate layer 333 disposed in the region corresponding to the flat portion of the recess 324. Therefore, when driving the light-emitting element ED, the current density is highest in the region where the intermediate layer 333 is formed with a relatively thin thickness (e.g., the region corresponding to the inclined portion of the recess 324), and a strong electric field may be applied in the region corresponding to the inclined portion of the recess 324. Therefore, the light-emitting characteristics of the light-emitting element ED in the region corresponding to the inclined portion of the recess 324 may differ from those in the region corresponding to the flat portion of the recess 324, and device degradation may occur as a result.

[0276] like Figure 16 As shown, in order to prevent component degradation and different light emission characteristics between regions, the embankment 325 can be configured to cover the first electrode 331 disposed in the inclined portion of the recess 324.

[0277] refer to Figure 16 A dam 325 may be disposed between the first electrode 331 and the intermediate layer 333 at the inclined portion of the insulating layer 320. When the dam 325 comprises a transparent material, light emitted from the intermediate layer 331 and propagating laterally can be reflected by the first electrode 331 located at the inclined portion and guided out of the display panel 1100. However, in this case, reflection due to external light may occur, and the problem of reduced visibility due to reflection may occur. To solve this problem, the dam 325 may comprise a black material, thereby allowing the dam 325 to absorb external light.

[0278] However, as Figure 16 As shown, when the dam 325, which includes black material, is disposed between the first electrode 331 and the intermediate layer 333 and directly contacts the first electrode 331 and the intermediate layer 333, light propagating from the intermediate layer 331 to the side may be absorbed by the dam 325 and cannot reach the first electrode 331, which has reflective properties, and therefore may not be able to be emitted from the display panel 1100.

[0279] For example, when the embankment 325, which includes a black material, is configured to directly contact the first electrode 331 and the intermediate layer 333, the embankment 325 may deteriorate during subsequent high-temperature processes, and exhaust gases such as smoke gases may be generated from the embankment 325. In this case, the exhaust gases may contaminate the light-emitting element ED and cause pixel shrinkage, resulting in a reduction in the size of the corresponding pixel.

[0280] As described above, the display panel 110 according to one or more aspects of this disclosure may include a protective layer 340 disposed between a first electrode 331 disposed on an inclined portion of the insulating layer 320 and an intermediate layer 333, and between a dam 325 and the intermediate layer 333. When the protective layer 340 is disposed between the first electrode 331 disposed on the inclined portion of the insulating layer 320 and the intermediate layer 333, light propagating laterally from the intermediate layer 331 can be reflected by the first electrode 331 located on the inclined portion and guided out of the display panel 110, and can prevent component degradation and differences in light emission characteristics between areas.

[0281] Furthermore, when the protective layer 340 is disposed between the embankment 325, which includes a black material, and the intermediate layer 333, the protective layer 340 can block the movement of the exhaust even when exhaust is generated from the embankment 325, thereby preventing pixel shrinkage.

[0282] Figure 17 It shows Figure 8 An example cross-sectional view of the display panel 110 shown, and along... Figure 14 An example cross-sectional view taken from line III-III' in the display panel 1100. In the following... Figure 17 In the discussion of the configuration, for the sake of simplicity, descriptions and references will be omitted or briefly explained. Figures 1 to 16 Discussion of features and configurations that are the same, substantially the same, or similar.

[0283] Figure 17 The dimensions of the display panel 1100 and the corresponding bezel areas of the display panel 1100 according to one or more aspects of this disclosure are shown.

[0284] refer to Figure 17 The display panel 110 may include a second electrode 335 and an auxiliary line 220 electrically connected in the display area DA, and the auxiliary line 220 and the common voltage line 210 may be electrically connected via a relay electrode RE in the non-display area NDA. In this configuration, the size of the area where the auxiliary line 220, the relay electrode RE, and the common voltage line 210 are electrically connected can be defined as BW2, and the size of the area between the display area DA and BW2 can be defined as BW1. In this case, the size of the bezel can be defined as BW1+BW2.

[0285] The display panel 1100 may include a second electrode 335 and a connection electrode 520 electrically connected in the non-display area NDA, and the connection electrode 520 and the common voltage line 210 may be electrically connected via a relay electrode RE. In this configuration, the size of the area where the connection electrode 520, the relay electrode RE, and the common voltage line 510 are electrically connected can be defined as BW2', and the size of the area between the display area DA and BW2' can be defined as BW1'. In this case, the size of the bezel can be defined as BW1'+BW2'.

[0286] refer to Figure 17 It can be seen that BW2 and BW2' are basically the same size, but BW1 is smaller than BW1'. This means that, compared with the size of the bezel of the display panel 1100, the size of the bezel of the display panel 1100 according to one or more aspects of this disclosure is reduced by (BW1'-BW1).

[0287] Examples, aspects, and embodiments of the display device 100 and display panel 110 described herein can be described as follows.

[0288] According to one or more example embodiments described herein, a display device may be provided, the display device comprising: a substrate; an insulating layer disposed on the substrate and including a recess and a peripheral portion surrounding the recess; a first electrode disposed on the recess and the peripheral portion; an auxiliary line spaced apart from the first electrode and disposed on the peripheral portion; a dam covering at least a portion of the auxiliary line and the first electrode and disposed on the peripheral portion; a protective layer disposed on the first electrode and the dam; an intermediate layer disposed on the first electrode and the protective layer; and a second electrode electrically connected to the auxiliary line and disposed on the intermediate layer.

[0289] In one or more aspects, the recess may include a flat portion and a sloped portion. In one or more aspects, the first electrode may include a first portion corresponding to the flat portion and a second portion corresponding to the sloped portion. In one or more aspects, the protective layer may include a first portion disposed on at least one first side surface of the second portion of the first electrode and the embankment.

[0290] In one or more aspects, the second portion of the first electrode may have the same inclined surface as at least one first side surface of the embankment located in the same plane.

[0291] In one or more aspects, the protective layer may include a second portion disposed on the upper surface of the dike and a third portion disposed on a second side surface of the dike and in contact with the auxiliary line.

[0292] In one or more aspects, the intermediate layer may include a first portion disposed on a first portion of the first electrode and a first portion of the protective layer, a second portion disposed on a second portion of the protective layer, and a third portion disposed on a third portion of the protective layer and in contact with the auxiliary line.

[0293] In one or more aspects, the second electrode may include a first portion disposed on a first portion of the intermediate layer, a second portion disposed on a second portion of the intermediate layer, and a third portion configured to cover a third portion of the intermediate layer and contact the auxiliary line.

[0294] In one or more aspects, the embankment may include an opening region that at least partially overlaps with the auxiliary line. In one or more aspects, the second electrode may cover the intermediate layer in the opening region and be electrically connected to the auxiliary line.

[0295] In one or more aspects, the display device may include an undercut region that overlaps with at least a portion of the opening region. In one or more aspects, the second electrode may be configured to overlap with the undercut region in a plan view.

[0296] In one or more aspects, intermediate layers can be set to not overlap with undercut regions in a planar diagram.

[0297] In one or more aspects, the side embankment may be configured to be spaced apart from the embankment in a plan view. In one or more aspects, the opening area may be located between the embankment and the side embankment. In one or more aspects, the protective layer may be provided on the side embankment and include a fourth portion protruding toward the opening area.

[0298] In one or more aspects, the intermediate layer may include a fourth portion disposed on the fourth portion of the protective layer. In one or more aspects, the fourth portion of the intermediate layer may not overlap with intermediate layers disposed on auxiliary lines in a plan view.

[0299] In one or more aspects, the second electrode may include a fourth portion disposed on a fourth portion of the intermediate layer. In one or more aspects, the fourth portion of the second electrode may overlap with a second electrode disposed on an auxiliary line in a plan view.

[0300] In one or more aspects, the display device may include a stepped portion disposed on a peripheral portion, the stepped portion allowing the embankment to expose a portion of the first electrode adjacent to the inclined portion.

[0301] In one or more aspects, the dike may be a black dike. In one or more aspects, the protective layer may be a transparent inorganic insulating layer.

[0302] In one or more aspects, the auxiliary line and the first electrode may comprise the same material and be disposed on the same layer.

[0303] In one or more aspects, the display device may include a common voltage line electrically connected to the auxiliary line.

[0304] In one or more aspects, the display device may include: a transistor including an active layer; and a hydrogen trapping layer located between the protective layer and the transistor and overlapping the active layer. In one or more aspects, the active layer may be an oxide semiconductor.

[0305] In one or more aspects, a transistor may include a gate electrode, a source electrode, and a drain electrode. In one or more aspects, the source electrode and the drain electrode may overlap with a hydrogen trapping layer.

[0306] In one or more aspects, the substrate may include at least one sub-pixel, and the first electrode is configured to correspond to the sub-pixel.

[0307] According to one or more example embodiments described herein, a display device may be provided, the display device comprising: a substrate including: a display area and a non-display area surrounding the display area; an insulating layer located in the display area and including a recess and a peripheral portion; a first electrode disposed on the insulating layer; an auxiliary line spaced apart from the first electrode and disposed on the peripheral portion; a dam including a first opening area corresponding to the recess and a second opening area exposing a portion of the auxiliary line; a protective layer disposed on the first electrode positioned corresponding to an inclined portion of the recess and the dam; an undercut region overlapping at least a portion of the second opening region and disposed below the protective layer; an intermediate layer disposed on the first electrode and the protective layer; and a second electrode electrically connected to the auxiliary line in the undercut region and disposed on the intermediate layer.

[0308] In one or more aspects, the undercut region can be configured such that a hole is formed in a portion of the pattern in which auxiliary lines are provided.

[0309] In one or more aspects, the undercut region can be set as a straight line on a plane along a pattern in which auxiliary lines are provided.

[0310] In one or more aspects, the display device may include a common voltage line disposed in a non-display area. In one or more aspects, auxiliary lines and the common voltage line may be electrically connected in the non-display area.

[0311] In one or more aspects, the display device may include an encapsulation layer on a second electrode, a buffer layer on the encapsulation layer, and a black matrix on the buffer layer, wherein the black matrix overlaps with at least a portion of the embankment.

[0312] In one or more aspects, the display area may include at least one luminescent area.

[0313] The display device 100 according to embodiments of this disclosure can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, sliding devices, variable devices, electronic notebooks, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbooks, workstations, navigation devices, car navigation devices, vehicle display devices, vehicle devices, cinema devices, cinema display devices, televisions, wallpaper devices, signage devices, gaming devices, laptop computers, monitors, cameras, camcorders, and home appliances, etc.

[0314] The above description is intended to enable those skilled in the art to implement and use the technical concepts of this disclosure, and is provided in the context of a specific application and its requirements. Those skilled in the art will readily understand that various modifications, additions, and substitutions can be made to the described embodiments, and that the principles described herein can be applied to other embodiments and applications without departing from the scope of this disclosure. The above description and accompanying drawings are provided for illustrative purposes only, illustrating examples of the technical features of this disclosure. That is, the disclosed embodiments are intended to illustrate the scope of the technical features of this disclosure.

Claims

1. A display device, comprising: Substrate; An insulating layer disposed on the substrate, and comprising a recess and a peripheral portion surrounding the recess; A first electrode is disposed on the recess and the peripheral portion; An auxiliary line, which is spaced apart from the first electrode and disposed on the peripheral portion; A dike portion, which covers the corresponding portions of the auxiliary line and the first electrode, and is disposed on the peripheral portion; A protective layer is disposed on the first electrode and the embankment; An intermediate layer is disposed on the first electrode and the protective layer; as well as The second electrode is electrically connected to the auxiliary line and is disposed on the intermediate layer.

2. The display device according to claim 1, wherein, The depression includes a flat portion and a sloping portion. The first electrode includes a first portion corresponding to the flat portion and a second portion corresponding to the inclined portion, and The protective layer includes a first portion, which is disposed on at least one first side surface of the second portion of the first electrode and the embankment.

3. The display device according to claim 2, wherein, The second portion of the first electrode has the same inclined surface that is located on the same plane as the at least one first side surface of the embankment.

4. The display device according to claim 2, wherein, The protective layer includes: The second part, the second part being disposed on the upper surface of the embankment; and The third part is disposed on the second side surface of the embankment and contacts the auxiliary line.

5. The display device according to claim 4, wherein, The intermediate layer includes: The first part is disposed on the first part of the first electrode and the first part of the protective layer; The second part, the second part being disposed on the second part of the protective layer; and The third part is disposed on the third part of the protective layer and contacts the auxiliary line.

6. The display device according to claim 5, wherein, The second electrode includes: The first part is disposed on the first part of the intermediate layer; The second part, the second part being disposed on the second part of the intermediate layer; and The third part is configured to cover the third part of the intermediate layer and contact the auxiliary line.

7. The display device according to claim 1, wherein, The embankment includes an opening region that at least partially overlaps with the auxiliary line, and the second electrode covers the intermediate layer in the opening region and is electrically connected to the auxiliary line.

8. The display device of claim 7, further comprising an undercut region overlapping at least a portion of the opening region. in, The second electrode is configured to overlap with the undercut region in the plan view.

9. The display device according to claim 8, wherein, The intermediate layer is configured not to overlap with the undercut region in the plan view.

10. The display device according to claim 7, wherein, The side embankment is positioned spaced apart from the main embankment in the plan view, and the opening area is located between the main embankment and the side embankment. The protective layer is disposed on the side embankment and includes a fourth portion protruding toward the opening area.

11. The display device according to claim 10, wherein, The intermediate layer includes a fourth portion disposed on the fourth portion of the protective layer, and the fourth portion of the intermediate layer does not overlap with the intermediate layer disposed on the auxiliary line in the plan view.

12. The display device according to claim 11, wherein, The second electrode includes a fourth portion disposed on the fourth portion of the intermediate layer, and the fourth portion of the second electrode overlaps with the second electrode disposed on the auxiliary line in the plan view.

13. The display device of claim 2, further comprising a stepped portion disposed on the peripheral portion, the stepped portion allowing the embankment to expose a portion of the first electrode adjacent to the inclined portion.

14. The display device according to claim 1, wherein, The embankment is black, and the protective layer is a transparent inorganic insulating layer.

15. The display device according to claim 1, wherein, The auxiliary line is made of the same material as the first electrode and is disposed on the same layer.

16. The display device according to claim 1, further comprising a common voltage line electrically connected to the auxiliary line.

17. The display device according to claim 1, further comprising: A transistor, the transistor including an active layer; and A hydrogen trapping layer is located between the protective layer and the transistor and overlaps with the active layer. The active layer includes an oxide semiconductor.

18. The display device according to claim 17, wherein, The transistor includes a gate electrode, a source electrode, and a drain electrode, and The source electrode and the drain electrode overlap with the hydrogen capture layer.

19. The display device according to claim 17, wherein, The substrate includes at least one sub-pixel, and the first electrode is configured to correspond to the sub-pixel.

20. A display device, comprising: A substrate, the substrate including a display area and a non-display area surrounding the display area; An insulating layer located in the display area, and including a recess and a peripheral portion; A first electrode is disposed on the insulating layer; An auxiliary line, which is spaced apart from the first electrode and disposed on the peripheral portion; The embankment includes a first opening region corresponding to the recess and a second opening region exposing a portion of the auxiliary line; A protective layer is disposed on the first electrode, which is positioned corresponding to the inclined portion of the recess; A bottom-cut region, which overlaps at least a portion of the second opening region and is disposed below the protective layer; An intermediate layer is disposed on the first electrode and the protective layer; as well as The second electrode is electrically connected to the auxiliary line in the undercut region and is disposed on the intermediate layer.

21. The display device according to claim 20, wherein, The undercut region is configured such that a hole is formed in the portion of the pattern in which the auxiliary lines are provided.

22. The display device according to claim 20, wherein, The undercut region is arranged as a straight line on the plane along the pattern in which the auxiliary lines are provided.

23. The display device according to claim 20, further comprising a common voltage line disposed in the non-display area. in, The auxiliary line and the common voltage line are electrically connected in the non-display area.

24. The display device of claim 20, further comprising an encapsulation layer on the second electrode, a buffer layer on the encapsulation layer, and a black matrix on the buffer layer. in, The black matrix overlaps with at least a portion of the embankment.

25. The display device according to claim 20, wherein, The display area includes at least one light-emitting area.

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