Packaging structure of power semiconductor module

Abstract

This application provides a packaging structure for a power semiconductor module, including a substrate and multiple semiconductor chips. The substrate includes a first conductive layer, an insulating layer, and a second conductive layer stacked sequentially. Multiple semiconductor chips are disposed on the second conductive layer. The second conductive layer is divided into multiple conductive regions, which, together with the multiple semiconductor chips, form a first switching topology, a second switching topology, and a third switching topology. Specifically, the packaging structure of the power semiconductor module provided in this application integrates the first, second, and third switching topologies. Compared to existing electronic switches composed of discrete devices, it features smaller size, lower parasitic inductance, and better consistency, thereby improving switching performance.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a packaging structure for a power semiconductor module. Background Technology

[0002] Mechanical switching circuits use physical mechanisms to open and close the circuit, but they are slow, susceptible to wear and corrosion, and have low accuracy and reliability. Electronic switches, on the other hand, use electrical current to open and close the circuit, resulting in fast response, low loss, and high accuracy.

[0003] In related technologies, electronic switches are often composed of discrete components, that is, several single-transistor devices packaged on separate chips form a switching circuit, which can cause a large parasitic inductance, thereby affecting the switching performance. Summary of the Invention

[0004] To address the aforementioned issues, this application provides a packaging structure for a power semiconductor module that can improve the switching performance of existing electronic switches.

[0005] To address the aforementioned problems, the first technical solution provided in this application is: a packaging structure for a power semiconductor module, comprising:

[0006] The substrate includes a first conductive layer, an insulating layer, and a second conductive layer that are sequentially stacked.

[0007] Multiple semiconductor chips are disposed on the second conductive layer; wherein the second conductive layer is divided into multiple conductive regions, and the multiple conductive regions and the multiple semiconductor chips form a first switch topology, a second switch topology and a third switch topology.

[0008] In some embodiments, the first switch topology is composed of a first DC+ conductive region, a first driving gate conductive region, a first auxiliary source conductive region, a first AC conductive region, and a DC- conductive region among the plurality of conductive regions; and a first semiconductor chip, a second semiconductor chip, a third semiconductor chip, a fourth semiconductor chip, a fifth semiconductor chip, a sixth semiconductor chip, a seventh semiconductor chip, and an eighth semiconductor chip among the plurality of semiconductor chips;

[0009] The drains of the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip are all electrically connected to the first DC+ conductive region.

[0010] The gates of the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip are all electrically connected to the conductive region of the first driving gate.

[0011] The auxiliary sources of the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip are all electrically connected to the conductive region of the first auxiliary source.

[0012] The power sources of the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip are all electrically connected to the first AC conductive region.

[0013] The cathodes of the fifth semiconductor chip, the sixth semiconductor chip, the seventh semiconductor chip, and the eighth semiconductor chip are all electrically connected to the first AC conductive region.

[0014] The anodes of the fifth, sixth, seventh, and eighth semiconductor chips are all electrically connected to the DC-conductive region.

[0015] In some embodiments, the second switch topology comprises a second DC+ conductive region, a second driving gate conductive region, a second auxiliary source conductive region, a first AC conductive region, and a DC- conductive region among the plurality of conductive regions; and a fifth semiconductor chip, a sixth semiconductor chip, a seventh semiconductor chip, an eighth semiconductor chip, a ninth semiconductor chip, and a tenth semiconductor chip among the plurality of semiconductor chips;

[0016] The drains of both the ninth and tenth semiconductor chips are electrically connected to the second DC+ conductive region.

[0017] The gates of both the ninth semiconductor chip and the tenth semiconductor chip are electrically connected to the conductive region of the second driving gate.

[0018] The auxiliary sources of the ninth semiconductor chip and the tenth semiconductor chip are both electrically connected to the conductive region of the second auxiliary source.

[0019] The power sources of both the ninth and tenth semiconductor chips are electrically connected to the first AC conductive region.

[0020] In some embodiments, the third switch topology is composed of a first DC+ conductive region, a third driving gate conductive region, a third auxiliary source conductive region, a second AC conductive region, and the DC- conductive region among the plurality of conductive regions; and an eleventh semiconductor chip and a twelfth semiconductor chip among the plurality of semiconductor chips;

[0021] The drain of the eleventh semiconductor chip is electrically connected to the first DC+ conductive region.

[0022] The gate of the eleventh semiconductor chip is electrically connected to the conductive region of the third driving gate.

[0023] The auxiliary source of the eleventh semiconductor chip is electrically connected to the conductive region of the third auxiliary source.

[0024] The power source of the eleventh semiconductor chip is electrically connected to the second AC conductive region.

[0025] The cathode of the twelfth semiconductor chip is electrically connected to the second AC conductive region.

[0026] The anode of the twelfth semiconductor chip is electrically connected to the DC-conductive region.

[0027] In some embodiments, the packaging structure of the power semiconductor module further includes:

[0028] The gate driving terminal includes a first gate driving terminal, a second gate driving terminal, and a third gate driving terminal; wherein the first gate driving terminal is disposed in the first driving gate conductive region, the second gate driving terminal is disposed in the second driving gate conductive region, and the third gate driving terminal is disposed in the third driving gate conductive region.

[0029] An auxiliary source driving terminal includes a first auxiliary source driving terminal, a second auxiliary source driving terminal, and a third auxiliary source driving terminal; wherein the first auxiliary source driving terminal is disposed in the first auxiliary source conductive region, the second auxiliary source driving terminal is disposed in the second auxiliary source conductive region, and the third auxiliary source driving terminal is disposed in the third auxiliary source conductive region.

[0030] The DC+ power terminal includes a first DC+ power terminal, a second DC+ power terminal, a third DC+ power terminal, a fourth DC+ power terminal, a fifth DC+ power terminal, and a sixth DC+ power terminal; wherein the first DC+ power terminal, the second DC+ power terminal, the third DC+ power terminal, the fourth DC+ power terminal, and the fifth DC+ power terminal are disposed in the first DC+ conductive region, and the sixth DC+ power terminal is disposed in the second DC+ conductive region;

[0031] The DC-power terminal includes a first DC-power terminal, a second DC-power terminal, a third DC-power terminal, a fourth DC-power terminal, and a fifth DC-power terminal; wherein the first DC-power terminal, the second DC-power terminal, the third DC-power terminal, the fourth DC-power terminal, and the fifth DC-power terminal are all disposed in the DC-conductive region;

[0032] The AC power terminal includes a first AC power terminal, a second AC power terminal, a third AC power terminal, a fourth AC power terminal, and a fifth AC power terminal; wherein the first AC power terminal, the second AC power terminal, the third AC power terminal, and the fourth AC power terminal are all disposed in the first AC conductive area; and the fifth AC power terminal is disposed in the second AC conductive area.

[0033] In some embodiments, the number of the first DC+ power terminal, the second DC+ power terminal, the third DC+ power terminal, the fourth DC+ power terminal, the fifth DC+ power terminal, and the sixth DC+ power terminal are all multiple;

[0034] The number of the first DC-power terminal, the second DC-power terminal, the third DC-power terminal, the fourth DC-power terminal, and the fifth DC-power terminal are all multiple;

[0035] The number of the first AC power terminal, the second AC power terminal, the third AC power terminal, the fourth AC power terminal, and the fifth AC power terminal are all multiple.

[0036] In some embodiments, the corners of the plurality of conductive regions are arc-shaped.

[0037] In some embodiments, the first conductive layer and the second conductive layer have a plurality of through holes.

[0038] In some embodiments, the gate driving terminal, the auxiliary source driving terminal, the DC+ power terminal, the DC- power terminal, and the AC power terminal each include a first connecting segment, a second connecting segment, and a third connecting segment located between the first connecting segment and the second connecting segment; the first connecting segment is connected to the second conductive layer, the second connecting segment extends in a direction away from the second conductive layer, and the third connecting segment has a bent design.

[0039] In some embodiments, the packaging structure of the power semiconductor module further includes:

[0040] The housing, the substrate, and the semiconductor chip are disposed within the housing, and at least a portion of the first conductive layer, the gate driving terminal, the auxiliary source driving terminal, the DC+ power terminal, the DC- power terminal, and the AC power terminal are exposed outside the housing;

[0041] An insulating medium is filled inside the housing.

[0042] The beneficial effect of this application is that, unlike the prior art, the power semiconductor module packaging structure provided in this application includes a substrate and multiple semiconductor chips; wherein, the substrate includes a first conductive layer, an insulating layer, and a second conductive layer stacked sequentially; multiple semiconductor chips are disposed on the second conductive layer; wherein, the second conductive layer is divided into multiple conductive regions, and the multiple conductive regions and the multiple semiconductor chips form a first switching topology, a second switching topology, and a third switching topology. Specifically, the power semiconductor module packaging structure provided in this application integrates the first switching topology, the second switching topology, and the third switching topology, and compared with existing electronic switches composed of discrete devices, it has the characteristics of smaller size, lower parasitic inductance, and better consistency, thereby improving switching performance. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0044] Figure 1 A schematic diagram of one embodiment of the packaging structure of the power semiconductor module provided in this application;

[0045] Figure 2 A schematic diagram of the structure of an embodiment of the substrate provided in this application;

[0046] Figure 3 A top view of an embodiment of the substrate provided in this application;

[0047] Figure 4 A bottom view of an embodiment of the substrate provided in this application;

[0048] Figure 5 A schematic diagram of the internal layout of the package structure of the power semiconductor module provided in the first embodiment of this application from a first perspective;

[0049] Figure 6 A schematic diagram of the internal layout of the package structure of the power semiconductor module provided in the first embodiment of this application from a second perspective;

[0050] Figure 7 A schematic diagram of the internal layout of the package structure of the power semiconductor module provided in the second embodiment of this application from a second perspective;

[0051] Figure 8 A schematic diagram of a structure of an embodiment of the wiring terminal provided in this application;

[0052] Figure 9A circuit topology diagram of the packaging structure of the power semiconductor module provided in this application;

[0053] Figure 10 A circuit topology diagram compatible with the packaging structure of the power semiconductor module provided in this application;

[0054] Figure 11 Another circuit topology diagram compatible with the packaging structure of the power semiconductor module provided in this application.

[0055] Label Explanation:

[0056] Substrate 1 includes: a first conductive layer 2; an insulating layer 3; a second conductive layer 4; a solder resist 4-1; and a through-hole H;

[0057] The driving gate conductive region includes a first driving gate conductive region 5-1; a second driving gate conductive region 5-2; and a third driving gate conductive region 5-3.

[0058] The auxiliary source conductive region includes a first auxiliary source conductive region 6-1; a second auxiliary source conductive region 6-2; and a third auxiliary source conductive region 6-3.

[0059] The DC+ conductive region includes a first DC+ conductive region 7-1 and a second DC+ conductive region 7-2;

[0060] The AC conductive region includes a first AC conductive region 8-1 and a second AC conductive region 8-2.

[0061] DC-conductive region 9;

[0062] The NTC conductive region includes a first NTC conductive region 10-1 and a second NTC conductive region 10-2;

[0063] First semiconductor chip 12, second semiconductor chip 13, third semiconductor chip 14, fourth semiconductor chip 15, fifth semiconductor chip 19, sixth semiconductor chip 20, seventh semiconductor chip 21, eighth semiconductor chip 22, ninth semiconductor chip 17, tenth semiconductor chip 18, eleventh semiconductor chip 16 and twelfth semiconductor chip 23;

[0064] The micron-sized bonding wires include: multiple gate micron-sized bonding wires 12a to 18a; multiple auxiliary source micron-sized bonding wires 12b to 18b; and multiple power electrode micron-sized bonding wires 12c to 23c.

[0065] The gate driving terminals include a first gate driving terminal 24-1; a second gate driving terminal 24-2; and a third gate driving terminal 24-3.

[0066] The auxiliary source drive terminals include a first auxiliary source drive terminal 25-1; a second auxiliary source drive terminal 25-2; and a third auxiliary source drive terminal 25-3.

[0067] The DC+ power terminals include a first DC+ power terminal 26-1; a second DC+ power terminal 26-2; a third DC+ power terminal 26-3; a fourth DC+ power terminal 26-4; a fifth DC+ power terminal 26-5; and a sixth DC+ power terminal 26-6.

[0068] The DC power terminals include a first DC power terminal 27-1; a second DC power terminal 27-2; a third DC power terminal 27-3; a fourth DC power terminal 27-4; and a fifth DC power terminal 27-5.

[0069] The AC power terminals include a first AC power terminal 28-1, a second AC power terminal 28-2, a third AC power terminal 28-3, a fourth AC power terminal 28-4, and a fifth AC power terminal 28-5;

[0070] First connecting segment L1; Second connecting segment L2; Third connecting segment L3;

[0071] The NTC terminals include a first NTC terminal 29-1 and a second NTC terminal 29-2;

[0072] Thermistor 30; Load resistor 31; Insulating medium 32; Housing 33; Glue inlet 33-1; Protrusion 33-2. Detailed Implementation

[0073] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0074] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0075] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0076] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0077] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0078] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0079] The power semiconductor module packaging structure provided in this application mainly consists of a substrate, multiple semiconductor chips, micron-sized bonding wires, a thermistor (NTC resistor), a load resistor, an insulating dielectric, a housing, and connection terminals (i.e., pins). The substrate can be fixedly mounted inside the housing using methods such as dispensing or snap-fitting. The load resistor, NTC resistor, connection terminals, and multiple semiconductor chips are soldered onto the substrate; and the surface electrodes of the multiple semiconductor chips are electrically connected to the substrate via micron-sized bonding wires.

[0080] See Figures 1-4 , Figure 1 A schematic diagram of one embodiment of the packaging structure of the power semiconductor module provided in this application; Figure 2 A schematic diagram of the structure of an embodiment of the substrate provided in this application; Figure 3 A top view of an embodiment of the substrate provided in this application; Figure 4 A bottom view of an embodiment of the substrate provided in this application.

[0081] The substrate 1 includes a first conductive layer 2, an insulating layer 3, and a second conductive layer 4 stacked sequentially. The insulating layer 3 provides mechanical support and insulation for the upper and lower conductive layers. The second conductive layer 4 is divided into multiple conductive regions. Multiple semiconductor chips are soldered onto at least a portion of the conductive regions to be electrically connected to the multiple conductive regions. The multiple semiconductor chips are also electrically connected to other conductive regions through micron-sized bonding wires to form a corresponding circuit topology. The first conductive layer 2 can be used as a heat-conducting layer. At least a portion of the first conductive layer 2 is exposed outside the outer shell 33 and connected to a heat sink. The heat from the multiple semiconductor chips and the second conductive layer 4 can be transferred to the first conductive layer 2 through the insulating layer 3 and then dissipated.

[0082] In one embodiment, the substrate 1 can be a copper-clad ceramic substrate (or DBC), which comprises three layers: an upper copper layer, a middle ceramic layer, and a lower copper layer. The upper copper layer serves as the second conductive layer 4 and is divided into multiple sub-regions to act as multiple conductive regions. These conductive regions are designed with minimal electrical clearance to reduce parasitic inductance in the circuit topology and achieve current consistency. Furthermore, the corners of the conductive regions are arc-shaped to reduce stress concentration during soldering. Additionally, multiple vias H (e.g., dimple holes) are formed on some conductive regions forming the second conductive layer 4 and on the lower copper layer serving as the first conductive layer 2, further reducing stress concentration. In some embodiments, solder resist 4-1 is provided on the multiple conductive regions to prevent solder overflow during soldering of semiconductor chips, load resistors, thermistors, etc., and to prevent electrical short circuits during use.

[0083] In some embodiments, depending on actual machinability and insulation withstand voltage requirements, multiple conductive areas and the lower copper layer are all at a certain distance from the edge of the central ceramic; and a certain gap is also maintained between the multiple conductive areas.

[0084] In some embodiments, the material of the central ceramic includes, but is not limited to, alumina, aluminum nitride, zirconium-doped alumina, and silicon nitride. Among these, aluminum nitride is preferred as the material of the central ceramic because it has the highest thermal conductivity, thereby improving the heat dissipation performance of the packaging structure.

[0085] In some embodiments, the housing 33 is fixed to the substrate 1 with high-temperature silicone. The housing 33 has a potting port 33-1, and the space between the housing 33 and the upper copper layer is filled with an insulating medium 32 (e.g., epoxy resin) that is not subject to external contamination through the potting port 33-1. The insulating medium 32 can cover the semiconductor chip, the second conductive layer 4, and the arcing height of the micron-sized bonding wires, ensuring that the three are not contaminated by the external environment. Furthermore, a protective protrusion 33-2 is provided on the top of the housing 33 to facilitate connection and positioning of external devices such as circuit boards. The housing 33 is made of a material with resistance to plastic deformation, heat deformation, and electrical insulation, such as PBT material.

[0086] See Figure 3 , Figures 5-7 , Figure 5 A schematic diagram of the internal layout of the package structure of the power semiconductor module provided in the first embodiment of this application from a first perspective; Figure 6 A schematic diagram of the internal layout of the package structure of the power semiconductor module provided in the first embodiment of this application from a second perspective; Figure 7 This is a schematic diagram of the internal layout of the power semiconductor module package structure provided in the second embodiment of this application from a second perspective.

[0087] See Figure 5 In some embodiments, the plurality of semiconductor chips include a first semiconductor chip 12, a second semiconductor chip 13, a third semiconductor chip 14, a fourth semiconductor chip 15, a fifth semiconductor chip 19, a sixth semiconductor chip 20, a seventh semiconductor chip 21, an eighth semiconductor chip 22, a ninth semiconductor chip 17, a tenth semiconductor chip 18, an eleventh semiconductor chip 16, and a twelfth semiconductor chip 23.

[0088] See Figure 3Multiple conductive regions include a first DC+ conductive region 7-1, a second DC+ conductive region 7-2, a first driving gate conductive region 5-1, a second driving gate conductive region 5-2, a third driving gate conductive region 5-3, a first auxiliary source conductive region 6-1, a second auxiliary source conductive region 6-2, a third auxiliary source conductive region 6-3, a first AC conductive region 8-1, a second AC conductive region 8-2, a DC- conductive region 9, a first NTC conductive region 10-1, and a second NTC conductive region 10-2.

[0089] Specifically, in the power semiconductor module packaging structure provided in this application embodiment, multiple conductive regions and multiple semiconductor chips form a first switch topology, a second switch topology, and a third switch topology, and the first switch topology, the second switch topology, and the third switch topology are electrically connected to an external circuit through wiring terminals.

[0090] Understandably, compared to existing electronic switches composed of discrete components, the power semiconductor module packaging structure provided in this application has the characteristics of smaller size, lower parasitic inductance, and better consistency, thereby improving switching performance. Furthermore, the highly integrated packaging structure offers better overcurrent carrying capacity, easier installation, and higher reliability.

[0091] See Figure 6 and Figure 7 Among them, multiple connection terminals include gate drive terminal, auxiliary source drive terminal, DC+ power terminal, DC- power terminal, AC power terminal and NTC terminal.

[0092] The number of gate drive terminals, auxiliary source drive terminals, DC+ power terminals, DC- power terminals, and AC power terminals can be designed according to actual needs. For example, the number of the same type of connection terminals in a conductive area can be one or more. It is understandable that having multiple connection terminals of the same type in a conductive area can improve current flow capacity and thus improve switching performance.

[0093] In some embodiments of this application, the gate driving terminal includes a first gate driving terminal 24-1, a second gate driving terminal 24-2, and a third gate driving terminal 24-3; wherein, the first gate driving terminal 24-1 is disposed in the first driving gate conductive region 5-1, the second gate driving terminal 24-2 is disposed in the second driving gate conductive region 5-2, and the third gate driving terminal 24-3 is disposed in the third driving gate conductive region 5-3.

[0094] The auxiliary source drive terminal includes a first auxiliary source drive terminal 25-1, a second auxiliary source drive terminal 25-2, and a third auxiliary source drive terminal 25-3; wherein, the first auxiliary source drive terminal 25-1 is disposed in the first auxiliary source conductive region 6-1, the second auxiliary source drive terminal 25-2 is disposed in the second auxiliary source conductive region 6-2, and the third auxiliary source drive terminal 25-3 is disposed in the third auxiliary source conductive region 6-3.

[0095] The DC+ power terminals include a first DC+ power terminal 26-1, a second DC+ power terminal 26-2, a third DC+ power terminal 26-3, a fourth DC+ power terminal 26-4, a fifth DC+ power terminal 26-5, and a sixth DC+ power terminal 26-6. The first DC+ power terminal 26-1, the second DC+ power terminal 26-2, the third DC+ power terminal 26-3, the fourth DC+ power terminal 26-4, and the fifth DC+ power terminal 26-5 are disposed in the first DC+ conductive region 7-1, and the sixth DC+ power terminal 26-6 is disposed in the second DC+ conductive region 7-2. See also... Figure 6 and Figure 7 The number of the first DC+ power terminal 26-1, the second DC+ power terminal 26-2, the third DC+ power terminal 26-3, the fourth DC+ power terminal 26-4, the fifth DC+ power terminal 26-5, and the sixth DC+ power terminal 26-6 can be one or more, and there is no limitation here.

[0096] The DC power terminals include a first DC power terminal 27-1, a second DC power terminal 27-2, a third DC power terminal 27-3, a fourth DC power terminal 27-4, and a fifth DC power terminal 27-5; wherein the first DC power terminal 27-1, the second DC power terminal 27-2, the third DC power terminal 27-3, the fourth DC power terminal 27-4, and the fifth DC power terminal 27-5 are all disposed in the DC conductive region 9. See also... Figure 6 and Figure 7 The number of the first DC-power terminal 27-1, the second DC-power terminal 27-2, the third DC-power terminal 27-3, the fourth DC-power terminal 27-4, and the fifth DC-power terminal 27-5 can be one or more, and there is no limitation here.

[0097] The AC power terminals include a first AC power terminal 28-1, a second AC power terminal 28-2, a third AC power terminal 28-3, a fourth AC power terminal 28-4, and a fifth AC power terminal 28-5; wherein the first AC power terminal 28-1, the second AC power terminal 28-2, the third AC power terminal 28-3, and the fourth AC power terminal 28-4 are all disposed in the first AC conductive region 8-1; the fifth AC power terminal 28-5 is disposed in the second AC conductive region 8-2. See also... Figure 6 and Figure 7 The number of the first AC power terminal 28-1, the second AC power terminal 28-2, the third AC power terminal 28-3, the fourth AC power terminal 28-4, and the fifth AC power terminal 28-5 can be one or more, and there is no limitation here.

[0098] The NTC terminal includes a first NTC terminal 29-1 and a second NTC terminal 29-2. The first NTC terminal 29-1 and the second NTC terminal 29-2 are respectively disposed in the first NTC conductive region 10-1 and the second NTC conductive region 10-2. The number of the first NTC terminal 29-1 and the second NTC terminal 29-2 can be one or more, which is not limited here.

[0099] Specifically, the number and diameter of the wiring terminals are determined based on the current-carrying capacity of the module design. Furthermore, in some embodiments, the surface of the wiring terminals has a plating layer, which can be a nickel layer and / or a gold layer. This plating layer can resist moisture, mold, and salt spray, thus enhancing service life.

[0100] In some embodiments, combined with Figure 8 , Figure 8 This is a schematic diagram of an embodiment of the wiring terminal provided in this application; each wiring terminal includes a first connecting segment L1, a second connecting segment L2, and a third connecting segment L3 located between the first connecting segment L1 and the second connecting segment L2; the first connecting segment L1 is connected to a corresponding conductive area on the second conductive layer 4, for example, by welding; the second connecting segment L2 extends in a direction away from the second conductive layer 4 and extends out of the outer shell 33 to connect with an external circuit; the third connecting segment L3 has a bent design, so as to have a certain buffering effect under external stress and improve the toughness of the wiring terminal.

[0101] The following provides a detailed description of three switching topologies used in the packaging structure of power semiconductor modules. Please refer to [the documentation / reference] for details. Figure 6 and Figure 9 , Figure 9 The circuit topology diagram of the package structure of the power semiconductor module provided in this application.

[0102] The first switch topology can serve as the main switch and is composed of a first DC+ conductive region 7-1, a first driving gate conductive region 5-1, a first auxiliary source conductive region 6-1, a first AC conductive region 8-1, and a DC- conductive region 9 in multiple conductive regions; and a first semiconductor chip 12, a second semiconductor chip 13, a third semiconductor chip 14, a fourth semiconductor chip 15, a fifth semiconductor chip 19, a sixth semiconductor chip 20, a seventh semiconductor chip 21, and an eighth semiconductor chip 22 in multiple semiconductor chips.

[0103] Specifically, the first semiconductor chip 12, the second semiconductor chip 13, the third semiconductor chip 14, and the fourth semiconductor chip 15 can be MOSFET chips; the fifth semiconductor chip 19, the sixth semiconductor chip 20, the seventh semiconductor chip 21, and the eighth semiconductor chip 22 can be SBD chips.

[0104] The drains of the first semiconductor chip 12, the second semiconductor chip 13, the third semiconductor chip 14, and the fourth semiconductor chip 15 are all electrically connected to the first DC+ conductive region 7-1. The electrical connection can be achieved by soldering, and then by connecting to an external circuit through the DC+ power terminal on the first DC+ conductive region 7-1.

[0105] The gates of the first semiconductor chip 12, the second semiconductor chip 13, the third semiconductor chip 14, and the fourth semiconductor chip 15 are all electrically connected to the first driving gate conductive region 5-1. The electrical connection can be made by connecting through micron bonding wires 12a to 15a, and then electrically connecting to an external circuit through the gate driving terminal on the first driving gate conductive region 5-1.

[0106] The auxiliary sources of the first semiconductor chip 12, the second semiconductor chip 13, the third semiconductor chip 14, and the fourth semiconductor chip 15 are all electrically connected to the first auxiliary source conductive region 6-1. The electrical connection can be made by connecting through micron bonding wires 12b to 15b, and then electrically connecting to an external circuit through the auxiliary source drive terminal on the first auxiliary source conductive region 6-1.

[0107] The power sources of the first semiconductor chip 12, the second semiconductor chip 13, the third semiconductor chip 14, and the fourth semiconductor chip 15 are all electrically connected to the first AC conductive region 8-1. The electrical connection can be made by connecting through micron bonding wires 12c to 15c, and then electrically connecting to an external circuit through the AC power terminal on the first AC conductive region 8-1.

[0108] The cathodes of the fifth semiconductor chip 19, the sixth semiconductor chip 20, the seventh semiconductor chip 21, and the eighth semiconductor chip 22 are all electrically connected to the first AC conductive region 8-1; wherein, the electrical connection can be achieved by soldering, and then by connecting to an external circuit through the AC power terminal on the first AC conductive region 8-1.

[0109] The anodes of the fifth semiconductor chip 19, the sixth semiconductor chip 20, the seventh semiconductor chip 21, and the eighth semiconductor chip 22 are all electrically connected to the DC-conductive region 9. The electrical connection can be made by connecting through micron bonding wires 19c to 22c, and then electrically connecting to an external circuit through the DC-power terminal on the DC-conductive region 9.

[0110] The second switch topology can serve as an auxiliary switch and is composed of a second DC+ conductive region 7-2, a second driving gate conductive region 5-2, a second auxiliary source conductive region 6-2, a first AC conductive region 8-1, and a DC- conductive region 9 in multiple conductive regions; and a fifth semiconductor chip 19, a sixth semiconductor chip 20, a seventh semiconductor chip 21, an eighth semiconductor chip 22, a ninth semiconductor chip 17, and a tenth semiconductor chip 18 in multiple semiconductor chips.

[0111] Specifically, the ninth semiconductor chip 17 and the tenth semiconductor chip 18 can be MOSFET chips.

[0112] The drains of the ninth semiconductor chip 17 and the tenth semiconductor chip 18 are both electrically connected to the second DC+ conductive region 7-2; wherein, the electrical connection can be made by soldering, and then electrically connected to an external circuit through the DC+ power terminal on the second DC+ conductive region 7-2.

[0113] The gates of the ninth semiconductor chip 17 and the tenth semiconductor chip 18 are both electrically connected to the second driving gate conductive region 5-2. The electrical connection can be made by connecting through micron bonding wires 17a to 18a, and then electrically connecting to an external circuit through the gate driving terminal on the second driving gate conductive region 5-2.

[0114] The auxiliary sources of the ninth semiconductor chip 17 and the tenth semiconductor chip 18 are both electrically connected to the second auxiliary source conductive region 6-2. The electrical connection can be made by connecting through micron bonding wires 17b to 18b, and then electrically connecting to an external circuit through the auxiliary source drive terminal on the second auxiliary source conductive region 6-2.

[0115] The power sources of the ninth semiconductor chip 17 and the tenth semiconductor chip 18 are both electrically connected to the first AC conductive region 8-1; wherein, the electrical connection can be made by connecting through micron bonding wires 17c to 18c, and then electrically connecting to an external circuit through the AC power terminal on the first AC conductive region 8-1.

[0116] The third switch topology can be used as a resistive load switch and is composed of a first DC+ conductive region 7-1, a third driving gate conductive region 5-3, a third auxiliary source conductive region 6-3, a second AC conductive region 8-2, a DC- conductive region 9 in multiple conductive regions; and an eleventh semiconductor chip 16 and a twelfth semiconductor chip 23 in multiple semiconductor chips.

[0117] Specifically, the eleventh semiconductor chip 16 can be a MOSFET chip; the fifth semiconductor chip 19, the sixth semiconductor chip 20, and the twelfth semiconductor chip 23 can be SBD chips.

[0118] The drain of the eleventh semiconductor chip 16 is electrically connected to the first DC+ conductive region 7-1; wherein, the electrical connection can be made by soldering, and then electrically connected to an external circuit through the DC+ power terminal on the first DC+ conductive region 7-1.

[0119] The gate of the eleventh semiconductor chip 16 is electrically connected to the third driving gate conductive region 5-3; wherein, the electrical connection can be made by connecting through a micron bonding wire 16a, and then electrically connecting to an external circuit through the gate driving terminal on the third driving gate conductive region 5-3.

[0120] The auxiliary source of the eleventh semiconductor chip 16 is electrically connected to the third auxiliary source conductive region 6-3; wherein, the electrical connection can be made by connecting through a micron bonding wire 16b, and then electrically connecting to an external circuit through the auxiliary source drive terminal on the third auxiliary source conductive region 6-3.

[0121] The power source of the eleventh semiconductor chip 16 is electrically connected to the second AC conductive region 8-2; wherein, the electrical connection can be made by connecting through a micron bonding wire 16c, and then electrically connecting to an external circuit through the AC power terminal on the second AC conductive region 8-2.

[0122] The cathode of the twelfth semiconductor chip 23 is electrically connected to the second AC conductive region 8-2; wherein, the electrical connection can be made by soldering, and then electrically connected to an external circuit through the AC power terminal on the second AC conductive region 8-2.

[0123] The anode of the twelfth semiconductor chip 23 is electrically connected to the DC-conductive region 9; wherein, the electrical connection can be made by connecting via micron bonding wire 23c, and then electrically connecting to an external circuit via the DC-power terminal on the DC-conductive region 9.

[0124] In the three circuit topologies mentioned above, the semiconductor chips and interconnecting terminals are evenly arranged, resulting in better current sharing.

[0125] The number of micron-sized bonding wires connecting the electrodes and conductive regions of each semiconductor chip is determined by the size of the bondable area of ​​the semiconductor chip electrodes. The thickness of the micron-sized bonding wires is determined by the characteristics of the semiconductor chip electrodes and the application. Specifically, the micron-sized bonding wires connecting the power source of the semiconductor chip to the conductive region use thicker wires (e.g., diameter greater than 10 μm), while the micron-sized bonding wires connecting the gate and auxiliary source of the semiconductor chip to the conductive region use thinner wires (e.g., diameter less than or equal to 10 μm). The micron-sized bonding wire materials can include aluminum micron-sized bonding wires, copper micron-sized bonding wires, etc.

[0126] In addition, in the three circuit topologies mentioned above, the auxiliary source and power source of the semiconductor chip are electrically connected to the corresponding conductive regions through micron-sized bonding wires to form a Kelvin connection structure, which can reduce the coupling between the drive circuit and the power circuit and provide stability of the drive signal.

[0127] Furthermore, combined Figure 3 and Figure 5 The load resistor 31 is connected across the first DC+ conductive region 7-1 and the second DC+ conductive region 7-2 by soldering. The NTC resistor 30 is connected across the first NTC conductive region 10-1 and the second NTC conductive region 10-2 by soldering, and the NTC resistor 30 is electrically connected to the external circuit through the NTC terminals provided on the first NTC conductive region 10-1 and the second NTC conductive region 10-2.

[0128] Further, see Figure 10 and Figure 11 , Figure 10 A circuit topology diagram compatible with the packaging structure of the power semiconductor module provided in this application; Figure 11 This is another circuit topology diagram compatible with the packaging structure of the power semiconductor module provided in this application. The packaging structure of the power semiconductor module provided in this application embodiment is also compatible with both half-bridge chopper circuit topologies and full-bridge chopper circuit topologies.

[0129] For details, see Figure 10 The circuit topology of the half-bridge chopper circuit was realized when the second and third switch topologies were not working.

[0130] See Figure 11 The circuit topology of the full-bridge chopper circuit was realized when the second switch topology was not working.

[0131] Specifically, the packaging structure of the power semiconductor module provided in this application has the following advantages compared to solid-state switching circuits composed of discrete devices:

[0132] 1. It integrates three switching circuit topologies, has high integration, and good overcurrent carrying capacity.

[0133] 2. It has good scalability and compatibility.

[0134] 3. In all embodiments, the MOSFET chips are connected using Kelvin, which reduces the coupling between the drive circuit and the power circuit and improves the stability of the drive signal.

[0135] 4. Small size, easy installation, and high reliability.

[0136] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A packaging structure of a power semiconductor module, characterized by, include: The substrate includes a first conductive layer, an insulating layer, and a second conductive layer that are sequentially stacked. Multiple semiconductor chips are disposed on the second conductive layer; wherein the second conductive layer is divided into multiple conductive regions, and the multiple conductive regions and the multiple semiconductor chips form a first switch topology, a second switch topology and a third switch topology.

2. The packaging structure of a power semiconductor module according to claim 1, characterized by, The first switch topology consists of a first DC+ conductive region, a first driving gate conductive region, a first auxiliary source conductive region, a first AC conductive region, and a DC- conductive region among the multiple conductive regions. It comprises a first semiconductor chip, a second semiconductor chip, a third semiconductor chip, a fourth semiconductor chip, a fifth semiconductor chip, a sixth semiconductor chip, a seventh semiconductor chip, and an eighth semiconductor chip among the plurality of semiconductor chips; The drains of the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip are all electrically connected to the first DC+ conductive region. The gates of the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip are all electrically connected to the conductive region of the first driving gate. The auxiliary sources of the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip are all electrically connected to the conductive region of the first auxiliary source. The power sources of the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip are all electrically connected to the first AC conductive region. The cathodes of the fifth semiconductor chip, the sixth semiconductor chip, the seventh semiconductor chip, and the eighth semiconductor chip are all electrically connected to the first AC conductive region. The anodes of the fifth, sixth, seventh, and eighth semiconductor chips are all electrically connected to the DC-conductive region.

3. The packaging structure of a power semiconductor module according to claim 2, characterized by The second switch topology consists of a second DC+ conductive region, a second driving gate conductive region, a second auxiliary source conductive region, a first AC conductive region, and a DC- conductive region among the multiple conductive regions. It comprises the fifth semiconductor chip, the sixth semiconductor chip, the seventh semiconductor chip, the eighth semiconductor chip, the ninth semiconductor chip, and the tenth semiconductor chip among the plurality of semiconductor chips; The drains of both the ninth and tenth semiconductor chips are electrically connected to the second DC+ conductive region. The gates of both the ninth semiconductor chip and the tenth semiconductor chip are electrically connected to the conductive region of the second driving gate. The auxiliary sources of the ninth semiconductor chip and the tenth semiconductor chip are both electrically connected to the conductive region of the second auxiliary source. The power sources of both the ninth and tenth semiconductor chips are electrically connected to the first AC conductive region.

4. The packaging structure of a power semiconductor module according to claim 3, characterized by The third switch topology consists of the first DC+ conductive region, the third driving gate conductive region, the third auxiliary source conductive region, the second AC conductive region, and the DC- conductive region among the multiple conductive regions. It comprises an eleventh semiconductor chip and a twelfth semiconductor chip among the plurality of said semiconductor chips; The drain of the eleventh semiconductor chip is electrically connected to the first DC+ conductive region. The gate of the eleventh semiconductor chip is electrically connected to the conductive region of the third driving gate. The auxiliary source of the eleventh semiconductor chip is electrically connected to the conductive region of the third auxiliary source. The power source of the eleventh semiconductor chip is electrically connected to the second AC conductive region. The cathode of the twelfth semiconductor chip is electrically connected to the second AC conductive region. The anode of the twelfth semiconductor chip is electrically connected to the DC-conductive region.

5. The packaging structure of a power semiconductor module according to claim 4, characterized by, The packaging structure of the power semiconductor module also includes: The gate driving terminal includes a first gate driving terminal, a second gate driving terminal, and a third gate driving terminal; wherein the first gate driving terminal is disposed in the first driving gate conductive region, the second gate driving terminal is disposed in the second driving gate conductive region, and the third gate driving terminal is disposed in the third driving gate conductive region. An auxiliary source driving terminal includes a first auxiliary source driving terminal, a second auxiliary source driving terminal, and a third auxiliary source driving terminal; wherein the first auxiliary source driving terminal is disposed in the first auxiliary source conductive region, the second auxiliary source driving terminal is disposed in the second auxiliary source conductive region, and the third auxiliary source driving terminal is disposed in the third auxiliary source conductive region. The DC+ power terminal includes a first DC+ power terminal, a second DC+ power terminal, a third DC+ power terminal, a fourth DC+ power terminal, a fifth DC+ power terminal, and a sixth DC+ power terminal; wherein the first DC+ power terminal, the second DC+ power terminal, the third DC+ power terminal, the fourth DC+ power terminal, and the fifth DC+ power terminal are disposed in the first DC+ conductive region, and the sixth DC+ power terminal is disposed in the second DC+ conductive region; The DC-power terminal includes a first DC-power terminal, a second DC-power terminal, a third DC-power terminal, a fourth DC-power terminal, and a fifth DC-power terminal; wherein the first DC-power terminal, the second DC-power terminal, the third DC-power terminal, the fourth DC-power terminal, and the fifth DC-power terminal are all disposed in the DC-conductive region; The AC power terminal includes a first AC power terminal, a second AC power terminal, a third AC power terminal, a fourth AC power terminal, and a fifth AC power terminal; wherein the first AC power terminal, the second AC power terminal, the third AC power terminal, and the fourth AC power terminal are all disposed in the first AC conductive area; and the fifth AC power terminal is disposed in the second AC conductive area.

6. The packaging structure of the power semiconductor module according to claim 5, characterized in that, The number of the first DC+ power terminal, the second DC+ power terminal, the third DC+ power terminal, the fourth DC+ power terminal, the fifth DC+ power terminal, and the sixth DC+ power terminal are all multiple; The number of the first DC-power terminal, the second DC-power terminal, the third DC-power terminal, the fourth DC-power terminal, and the fifth DC-power terminal are all multiple; The number of the first AC power terminal, the second AC power terminal, the third AC power terminal, the fourth AC power terminal, and the fifth AC power terminal are all multiple.

7. The packaging structure of a power semiconductor module according to Claim 1, characterized by, The corners of the multiple conductive regions are arc-shaped.

8. The packaging structure of the power semiconductor module according to claim 1, characterized in that, The first conductive layer and the second conductive layer have multiple through holes.

9. The packaging structure of the power semiconductor module according to claim 5, characterized in that, The gate driving terminal, the auxiliary source driving terminal, the DC+ power terminal, the DC- power terminal, and the AC power terminal each include a first connecting segment, a second connecting segment, and a third connecting segment located between the first connecting segment and the second connecting segment; the first connecting segment is connected to the second conductive layer, the second connecting segment extends in a direction away from the second conductive layer, and the third connecting segment has a bent design.

10. The packaging structure of the power semiconductor module according to claim 5, characterized in that, The packaging structure of the power semiconductor module also includes: The housing, the substrate, and the semiconductor chip are disposed within the housing, and at least a portion of the first conductive layer, the gate driving terminal, the auxiliary source driving terminal, the DC+ power terminal, the DC- power terminal, and the AC power terminal are exposed outside the housing; An insulating medium is filled inside the housing.

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