Pulse width determination in single-wire bus devices

Abstract

This disclosure describes pulse width determination in a single-wire bus device. Here, a pulse width determination circuit is configured to determine the pulse width based on a sampling clock. More specifically, the sampling clock may be a half-rate clock with reduced sampling power. Alternatively, the sampling clock may be a full-rate clock with improved sampling accuracy. Given that the pulse and the sampling clock may be asynchronous, the pulse width determination circuit is further configured to mitigate possible sampling errors associated with the rising and / or falling edges of the pulse, thereby improving sampling accuracy. In embodiments, the pulse width determination circuit may be located in one or more slave circuits in the single-wire bus device to determine a synchronization pulse transmitted by the master circuit via the single-wire bus, thereby establishing a timing basis for subsequent communication with the master circuit.

Description

[0001] Related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 601,796, filed November 22, 2023, and U.S. Provisional Patent Application No. 63 / 627,262, filed January 31, 2024, the disclosures of which are hereby incorporated herein by reference in their entirety. Technical Field

[0003] The technology disclosed herein generally relates to determining the pulse width by digitally sampling the pulse based on a sampling clock. Background Technology

[0004] Mobile communication devices have become increasingly prevalent in today's society. This widespread use is partly driven by the many features now available on such devices. The increased processing power in these devices means that they have evolved from mere communication tools into sophisticated mobile multimedia hubs capable of enhancing the user experience.

[0005] To provide a redefined user experience, existing wireless communication devices (e.g., smartphones) are equipped with various circuits to support diverse applications and achieve various user experiences. Furthermore, wireless communication devices employ various communication buses to achieve inter-circuit and intra-circuit communication. For example, a two-wire radio frequency front-end (RFFE) bus enables transceiver circuitry to communicate with power amplifier circuitry, power management circuitry, and / or antenna circuitry. Multi-wire high-bandwidth memory buses enable time-critical direct access to memory circuitry, and multi-wire general-purpose input / output (GPIO) buses can bridge communication to external peripheral devices.

[0006] However, not all communication requires a multi-wire bus like the RFFE bus, memory bus, and GPIO bus. In some cases, a single-wire serial bus may be sufficient or even desirable for low-speed and / or low-bandwidth communication between certain types of circuits (e.g., antenna tuners, sensors, and switches). Summary of the Invention

[0007] The aspects disclosed in the detailed description relate to pulse width determination in a single-wire bus device. Herein, a pulse width determination circuit is configured to determine the pulse width based on a sampling clock. More specifically, the sampling clock may be a half-rate clock with reduced sampling power. Alternatively, the sampling clock may be a full-rate clock with improved sampling accuracy. Given that the pulse and the sampling clock may be asynchronous, the pulse width determination circuit is further configured to mitigate potential sampling errors associated with the rising and / or falling edges of the pulse, thereby improving sampling accuracy. In embodiments, the pulse width determination circuit may be located in one or more slave circuits in the single-wire bus device to determine a synchronization pulse transmitted by the master circuit via the single-wire bus, thereby establishing a timing basis for subsequent communication with the master circuit.

[0008] In one aspect, a pulse width determination circuit is provided. The pulse width determination circuit is configured to receive a pulse defined by a rising edge and a falling edge. The pulse width determination circuit is further configured to enable a sampling clock having a plurality of clock cycles in response to detecting the rising edge of the pulse, each clock cycle including a high clock interval defined by the rising edge and the falling edge of the clock, and a subsequent low clock interval. The pulse width determination circuit is further configured to increment a sampling counter for each of the plurality of clock cycles of the sampling clock. The pulse width determination circuit is further configured to disable the sampling clock in response to detecting the rising edge and the falling edge of the clock that define the high clock interval immediately following the falling edge of the pulse. The pulse width determination circuit is further configured to determine a phase error indicator based on the relative position between the falling edge of the pulse and one of the plurality of clock cycles of the sampling clock. The pulse width determination circuit is further configured to determine a digital sample count based on the sampling counter and the phase error indicator.

[0009] In another aspect, a method for determining the pulse width of a pulse is provided. The method includes receiving the pulse as defined by a rising edge and a falling edge. The method further includes enabling a sampling clock having a plurality of clock cycles in response to detecting the rising edge of the pulse, each clock cycle including a high clock interval defined by the rising edge and the falling edge, followed by a low clock interval. The method further includes incrementing a sampling counter for each of the plurality of clock cycles of the sampling clock. The method further includes disabling the sampling clock in response to detecting the rising edge and the falling edge of the clock that define the high clock interval immediately following the falling edge of the pulse. The method further includes determining a phase error indicator based on the relative position between the falling edge of the pulse and one of the plurality of clock cycles of the sampling clock. The method further includes determining a digital sample count based on the sampling counter and the phase error indicator.

[0010] In another aspect, a wireless device is provided. The wireless device includes a single-wire bus device. The single-wire bus device includes a master circuit. The master circuit is coupled to a single-wire bus consisting of a single wire. The master circuit is configured to transmit multiple bus telegrams, each bus telegram preceded by a sequence start (SOS) sequence. The SOS sequence includes a synchronization pulse defined by a rising edge and a falling edge. The single-wire bus device also includes multiple slave circuits. Each of the multiple slave circuits is coupled to the single-wire bus. Each of the multiple slave circuits includes pulse width determination circuitry. The pulse width determination circuitry is configured to receive the synchronization pulse via the single-wire bus. The pulse width determination circuitry is further configured to enable a sampling clock having multiple clock cycles in response to detecting the rising edge of the pulse, each clock cycle including a high clock interval defined by a rising edge and a falling edge, followed by a low clock interval. The pulse width determination circuitry is further configured to increment a sampling counter for each of the multiple clock cycles of the sampling clock. The pulse width determination circuit is further configured to disable the sampling clock in response to detecting a rising edge and a falling edge of the clock that define a high clock interval immediately following the falling edge of the pulse. The pulse width determination circuit is also configured to determine a phase error indicator based on the relative position between the falling edge of the pulse and one of the plurality of clock cycles in the sampling clock. The pulse width determination circuit is further configured to determine a digital sample count based on the sampling counter and the phase error indicator.

[0011] After reading the following detailed description in conjunction with the accompanying drawings, those skilled in the art will understand the scope of this disclosure and recognize its additional aspects. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0013] Figure 1A This is a schematic diagram of an exemplary conventional single-wire bus device in which the master circuit is configured to communicate with the slave circuit via a single-wire bus;

[0014] Figure 1B It provides access through Figure 1A A schematic diagram illustrating an exemplary single-wire bus transmitting one or more bus telegrams from the master circuit to the slave circuit.

[0015] Figure 1C It provides access through Figure 1A A schematic diagram illustrating an exemplary single-wire bus transmitting one or more bus telegrams from a slave circuit to a master circuit;

[0016] Figure 1D This is a schematic diagram illustrating an exemplary illustration of a bus symbol modulated to represent a voltage PWM value of one (“1”) based on voltage pulse width modulation (PWM);

[0017] Figure 1E This is a schematic diagram illustrating an exemplary illustration of a bus symbol that is modulated based on voltage PWM to represent a voltage PWM value of zero (“0”);

[0018] Figure 1F This is a schematic diagram providing an exemplary illustration of a Sequence Start (SOS) sequence, which includes a synchronization pulse and... Figure 1B and 1C Before each of the bus telegraphs;

[0019] Figure 2 This is a schematic diagram of an exemplary single-wire bus device, wherein the slave circuitry can be configured to determine the pulse width of a pulse with reasonable precision and to achieve a computational trade-off between sampling accuracy and power consumption, the pulse being, for example... Figure 1F Synchronization pulses in the middle;

[0020] Figure 3 This is a flowchart of an exemplary program, thereby Figure 2 The pulse width determination circuit in the circuit can determine the pulse width;

[0021] Figures 4A to 4D This is a schematic diagram, which provides... Figure 2 Exemplary illustrations of various operating scenarios for the pulse width determination circuit in the diagram;

[0022] Figure 5 This is a schematic diagram, which provides... Figure 2 An exemplary illustration of a pulse width determination circuit, which is configured to process... Figures 4A to 4D Various operational scenarios within;

[0023] Figure 6 It is a schematic diagram that provides information about Figure 5 How can the pulse width determination circuit in the middle be handled? Figures 4A to 4D Exemplary illustrations of metastable conditions in some operational scenarios are shown; and

[0024] Figure 7 This is a schematic diagram of an exemplary user element (e.g., a wireless device) in which such an element may be provided. Figure 2 A single-wire bus device. Detailed Implementation

[0025] The embodiments described below illustrate the information necessary to enable those skilled in the art to practice the embodiments and demonstrate the best mode of practice. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and will appreciate the application of these concepts, even those not specifically set forth herein. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

[0026] It will be understood that while the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0027] It should be understood that when an element, such as a layer, region, or substrate, is referred to as "on another element" or "extending to another element," it may be directly located on or directly extended to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly located on another element" or "directly extended to another element," no intermediate elements are present. Similarly, it should be understood that when an element, such as a layer, region, or substrate, is referred to as "on top of another element" or "extending over another element," it may be directly located on top of or directly extended over the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly located on top of another element" or "extending directly over another element," no intermediate elements are present. It will also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected to or coupled to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediate elements are present.

[0028] For example, relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe the relationship of one element, layer, or area to another element, layer, or area as shown in the figures. It should be understood that these terms, and those discussed above, are intended to cover different orientations of the device other than those depicted in the figures.

[0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” are intended to include the plural forms as well. It should also be understood that, when used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0030] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should be further understood that the terms used herein shall be interpreted as having the same meaning as in the context of this specification and related art, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0031] The aspects disclosed in the detailed description relate to pulse width determination in a single-wire bus device. Herein, a pulse width determination circuit is configured to determine the pulse width based on a sampling clock. More specifically, the sampling clock may be a half-rate clock with reduced sampling power. Alternatively, the sampling clock may be a full-rate clock with improved sampling accuracy. Given that the pulse and the sampling clock may be asynchronous, the pulse width determination circuit is further configured to mitigate potential sampling errors associated with the rising and / or falling edges of the pulse, thereby improving sampling accuracy. In embodiments, the pulse width determination circuit may be located in one or more slave circuits in the single-wire bus device to determine a synchronization pulse transmitted by the master circuit via the single-wire bus, thereby establishing a timing basis for subsequent communication with the master circuit.

[0032] From Figure 2 Before discussing the single-wire bus devices of this disclosure, first refer to Figures 1A to 1F A brief overview of typical single-wire bus devices is provided to help understand the basic operation of the single-wire bus and the technical issues addressed in this article.

[0033] In this regard, Figure 1A This is a schematic diagram of an exemplary conventional single-wire bus device 10 in which the master circuit 12 is configured to communicate with a plurality of slave circuits 14(1)-14(M) via a single-wire bus 16 coupled to the master control port 18. Thus, the master circuit 12 and the slave circuits 14(1)-14(M) can communicate with each other only in an alternating manner (e.g., time-division manner).

[0034] The master circuit 12 is configured to always initiate bus telegraph communication on the single-wire bus 16 by transmitting bus telegraphs to one or more slave circuits among the slave circuits 14(1)-14(M). Thus, the conventional single-wire bus device 10 is also referred to as a “master-slave bus architecture”. The slave circuits 14(1)-14(M) can provide a data payload to the master circuit 12 via the single-wire bus 16 in response to receiving a bus telegraph from the master circuit 12. In the following text, the bus telegraph transmitted from the master circuit 12 to the slave circuits 14(1)-14(M) is referred to as a “forward bus telegraph”, and the data payload transmitted from the slave circuits 14(1)-14(M) to the master circuit 12 is referred to as a “reverse bus telegraph”.

[0035] Figure 1B It provides access through Figure 1A This is a schematic illustration of an exemplary single-wire bus 16 transmitting one or more bus messages 20, 22 from master circuit 12 to any one of slave circuits 14(1)-14(M). Each bus message 20, 22 begins with an SOS sequence 24 followed by a bus command sequence 26. The bus command sequence 26 includes a write command frame 28 and a write data frame 30. The write command frame 28 includes a command field 32 (labeled "CMD"), which is encoded with the binary value "100" to indicate a register write operation. The write data frame 30 includes a write data period 34. The write data period 34 may contain one or more write data symbols T. S It is modulated to carry data to slave circuits 14(1)-14(M) during register write operations. In this respect, bus telegrams 20, 22 can be examples of forward bus telegrams.

[0036] SOS sequence 24 always precedes bus command sequence 26 and is always transmitted from master circuit 12 to slave circuits 14(1)-14(M). Bus message 22, following bus message 20, can be separated from bus message 20 by a fast charging period 36 and an idle period 38, the fast charging period starting at time T1 and ending at time T2 (T2>T1), and the idle period starting at time T2 and ending at time T3 (T3>T2). In general, the duration between time T1 and T3 is also referred to as the pause period (T3 - T1).

[0037] Fast charging period 36 is configured to allow each slave circuit in circuits 14(1)-14(M) to draw a higher charging current via a single-wire bus 16 and to harvest power from said higher charging current. In this respect, the single-wire bus 16 is referred to as being in a fast charging state during fast charging period 36. Idle period 38 may be an inactive period during which the master circuit 12 and slave circuits 14(1)-14(M) may be inactive to help save power. Therefore, the single-wire bus 16 is referred to as being in an idle state during idle period 38.

[0038] The bus command sequence includes a slave address field 40, followed by a bus dwell period 42 and four acknowledgment (ACK) symbols 44. The slave address field 40 can be used to address slave circuits 14(1)-14(M). The bus dwell period 42 can be used to switch between forward communication mode and reverse communication mode. The ACK symbols 44 can be used by up to four slave circuits in slave circuits 14(1)-14(M) to acknowledge the corresponding reception of data carried in the write data period 34. When the ACK symbols 44 are transmitted immediately before the fast charge period 36, each slave circuit in slave circuits 14(1)-14(M) can determine the start time T1 of the fast charge period 36 by counting the four ACKs transmitted in the four ACK symbols 44 starting from the end of the bus dwell period 42.

[0039] Each slave circuit in 14(1)-14(M) is uniquely identified by a corresponding unique slave identifier (USID). Thus, when the slave address field 40 contains the USID of any slave circuit 14(1)-14(M), the bus command sequence 26 in bus telegrams 20 and 22 can be a unicast command sequence destined for said slave circuit 14(1)-14(M). When the slave address field 40 contains a group slave identifier (GSID) corresponding to a subset of slave circuits 14(1)-14(M), the bus command sequence 26 in bus telegrams 20 and 22 can also be a multicast command sequence destined for said subset of slave circuits 14(1)-14(M). Furthermore, when the slave address field 40 contains a broadcast slave identifier (BSID), the bus command sequence 26 in bus telegrams 20 and 22 can be a broadcast command sequence destined for all slave circuits 14(1)-14(M).

[0040] Figure 1C It provides access through Figure 1A A schematic diagram illustrating an exemplary single-wire bus 16 transmitting one or more bus telegrams 46, 48 from slave circuits 14(1)-14(M) to master circuit 12. Figure 1B and 1C The common elements between them are shown in the accompanying drawings with common reference numerals, and will not be described again herein.

[0041] Each bus telegram in bus telegrams 46 and 48 contains a bus command sequence 26. The bus command sequence 26 contains a read command frame 50 and a read data frame 52 separated by a bus dwell period 42. The read command frame 50 contains a command field 32 (labeled "CMD"), encoded with the binary value "010" to indicate a register read operation. The read data frame 52 contains a read data period 54, which contains one or more read data symbols T. S It is modulated to carry a data payload to master circuit 12 during a register read operation. Master circuit 12 first sends a read command frame 50 to slave circuits 14(1)-14(M) identified by slave address field 40 to initiate a register read operation. Then, master circuit 12 tri-states during bus dwell period 42 to transfer control of single-wire bus 16 to slave circuits 14(1)-14(M). Subsequently, slave circuits 14(1)-14(M) can begin sending a data payload during data read period 54. In this respect, bus telegrams 46 and 48 can be examples of both forward and reverse bus telegrams.

[0042] Return to reference Figure 1A The master circuit 12 is configured to suspend bus telegraph communication on the single-wire bus 16 during the pause period (T3 - T1). Therefore, the master circuit 12 and slave circuits 14(1)-14(M) are configured to stop transmitting bus telegraphs and data payloads from time T1 to T3. In this respect, it can be said that the single-wire bus 16 is in a pause mode between time T1 and T3. During the pause period (T3-T1), the master circuit 12 will reduce the bus voltage V of the single-wire bus 16. BUS Maintain at a high voltage level V HIGH (V HIGH >0 V). Thus, each of the circuits 14(1)-14(M) can draw charging current through the single-wire bus 16, thereby collecting power from the main circuit 12.

[0043] Outside of the pause period (T3 - T1), it can be achieved by maintaining a high voltage level V. HIGH With low voltage level V LOW (V LOW <V HIGH Switching bus voltage V between ) BUS To modulate the write data symbol T in the write data period 34 S and the data reading symbol T in data reading period 54 S ,like Figure 1D and 1E As shown. Figure 1D It provides a bus symbol T that is modulated based on voltage PWM to represent a voltage PWM value of -1 ("1"). S An exemplary illustration is provided.

[0044] It can be the data symbol T that is written. S and read data symbol T S any of the bus symbols T S Modulation is based on a predefined low voltage interval 56 and a predefined high voltage interval 58 configured according to a predefined ratio. To represent a voltage PWM value "1", the predefined low voltage interval 56 is shorter than the predefined high voltage interval 58. For example, bus symbol T S It may contain sixteen (16) digitally controlled oscillators (DCOs), and a predefined configuration ratio of 25% to 75% (or 1 to 3) between a predefined low-voltage interval 56 and a predefined high-voltage interval 58. In a non-limiting example, the DCOs are derived from a clock running at main circuit 12. Thus, the predefined low-voltage interval 56 lasts for four (4) DCOs, while the predefined high-voltage interval 58 lasts for twelve (12) DCOs.

[0045] In this regard, in order to modulate the bus symbol T S To indicate the voltage PWM value "1", the bus voltage V BUS First, within a predefined low-voltage interval of 56, at a low voltage level V LOW Assertion (V) BUS = V LOW Then, within a predefined high-voltage interval of 58, at a high voltage level V HIGH Assertion (V) HIGH > V LOW ).

[0046] Figure 1E It provides a voltage PWM symbol T that is modulated to represent a voltage PWM value of zero (“0”). S An exemplary illustration is provided. Figure 1D and 1E The common elements between them are shown in the accompanying drawings with common reference numerals, and will not be described again herein.

[0047] To represent a voltage PWM value of "0", the predefined low voltage interval 56 is longer than the predefined high voltage interval 58. Based on Figure 1D In the same example, a predefined low-voltage interval 56 lasts for 12 DCOs, while a predefined high-voltage interval 58 lasts for 4 DCOs. Therefore, in order to modulate the bus symbol T... S To indicate a voltage PWM value of "0", the bus voltage V BUS First, within a predefined low voltage interval of 56, at a lower voltage level V LOW Assertion (V) BUS = V LOW Then, within a predefined high-voltage interval of 58, at a high voltage level V HIGH Assertion (V) BUS = VHIGH ).

[0048] Figure 1F It provides Figure 1B and 1C A schematic diagram illustrating an exemplary SOS sequence 24. Figure 1B , 1C The common elements between 1F and 1F are shown in the accompanying drawings with common reference numerals, and will not be described again herein.

[0049] SOS sequence 24 is a unique sequence that will never appear with any bit combination in bus command sequence 26. Each of circuits 14(1)-14(M) is configured to always monitor SOS sequence 24, which indicates the start of bus telegrams 20, 22, 46, 48. SOS sequence 24 includes a synchronization pulse 60 during which the bus voltage V... BUS Maintain at a high voltage level V HIGH Synchronization pulse 60 is defined by a rising edge 62 and a falling edge 64, and includes several DCO pulses 66, from which a corresponding timing basis (e.g., for reading, acknowledgment, and other functions) can be established from each of circuits 14(1)-14(M). Following synchronization pulse 60, there is a pair of PWM symbols 68, 70. In a non-limiting example, PWM symbol 68 is based on... Figure 1E Modulation is used to represent binary "0", and the PWM symbol 70 is based on Figure 1D Modulation is used to represent binary "1".

[0050] To accurately determine the corresponding timing basis for subsequent communication with the main circuit 12, each of the circuits 14(1)-14(M) must determine the pulse width 72 of the synchronization pulse 60. Therefore, each of the circuits 14(1)-14(M) can digitally sample the synchronization pulse 60 based on a sampling clock 74 comprising a plurality of repetitive clock cycles 76. In a non-limiting example, the sampling clock 74 can be a square wave clock, wherein each of the repetitive clock cycles 76 comprises a high clock interval 78 and a low clock interval 80 configured according to a 50-50 (50-50) ratio. Specifically, the high clock interval 78 is defined by a clock rising edge 82 and a clock falling edge 84.

[0051] Understandably, the faster the sampling clock 74, the more accurate the sampling that can be performed. However, increasing the speed of the sampling clock 74 not only requires a more expensive and / or considerably larger oscillator, but also increases the power consumption from circuits 14(1)-14(M). Furthermore, since the sampling clock 74 operates from circuits 14(1)-14(M), the sampling clock 74 may be asynchronous with the rising edge 62 and / or falling edge 64 of the synchronization pulse 60. Therefore, the pulse width 72 of the synchronization pulse 60 may not be accurately determined from circuits 14(1)-14(M).

[0052] Therefore, the technical problem this paper aims to solve is to determine the pulse width 72 of the synchronization pulse 60 or any square wave pulse as a whole with reasonable accuracy, such as within an error tolerance of ±0.5 least significant bits (LSB). Furthermore, a computational trade-off needs to be struck between improving sampling accuracy and reducing sampling power consumption.

[0053] Figure 2 This is a schematic diagram of an exemplary single-wire bus device 86, wherein at least one slave circuit 88 can be configured to determine the pulse width P of pulse 90 with reasonable accuracy (e.g., ±0.5 LSB). WIDTH Furthermore, it achieves a computational trade-off between sampling accuracy and power consumption, wherein the pulse is, for example, in... Figure 1B Bus telegraphs 20, 22 and / or Figure 1C The synchronization pulse 60 is transmitted in bus telegrams 46 and 48. In this paper, the pulse width P of pulse 90 is... WIDTH The pulse 90 is defined by its rising edge 92 and falling edge 94. The single-wire bus device 86 also includes a master circuit 96 that generates the pulse 90 and transmits it to the slave circuit 88 via the single-wire bus 98.

[0054] The circuit 88 can be configured to include a control circuit 100, a switch 102, and a power harvesting circuit 104. The power harvesting circuit 104 can be implemented as a resistor-capacitor (RC) circuit, which includes a resistor R (e.g., 200 Ω) and a holding capacitor C. HOLD (e.g., 1 nF). Control circuit 100 is configured to close switch 102 during pause periods (T3 - T1) to couple power harvesting circuit 104 to single-wire bus 98. Therefore, bus current I can be drawn from circuit 88. BUS To hold capacitor C HOLD Charged to local voltage V CAP Outside of the pause period (T3 - T1), switch 102 is disconnected from control circuit 100 to decouple power harvesting circuit 104 from single-wire bus 98. Therefore, capacitor C is held... HOLD The discharge will reduce the local voltage V CAPSupply to control circuit 100.

[0055] The control circuit 100 may include a pulse width determination circuit 106 and a transceiver circuit 108. The pulse width determination circuit 106 is configured according to various embodiments described below to determine the pulse width P of the pulse 90. WIDTH And the determined pulse width P WIDTH Provided to transceiver circuit 108. Transceiver circuit 108 can then be based on the determined pulse width P. WIDTH The timing basis (e.g., timing synchronization) is determined so that subsequent communication with the main circuit 96 can be performed via a single-wire bus 98.

[0056] In an embodiment, the pulse width determination circuit 106 is configured to determine the pulse width P of the pulse 90 by digitally sampling the pulse 90 based on the sampling clock 110. WIDTH Similar to Figure 1F The sampling clock 74 in the sample clock 110 comprises multiple clock cycles 112. In a non-limiting example, the sampling clock 110 may be a square wave clock, wherein each of the repetitive clock cycles 112 comprises a high clock interval 114 and a low clock interval 116 configured according to a 50-50 ratio. Specifically, the high clock interval 114 is defined by a clock rising edge 118 and a clock falling edge 120.

[0057] Figure 3 This is a flowchart of the exemplary procedure 122, thereby Figure 2 The pulse width determination circuit 106 in the middle can determine the pulse width P of pulse 90. WIDTH . Figure 2 and 3 The common elements between them are shown in the accompanying drawings with common reference numerals, and will not be described again herein.

[0058] The pulse width determination circuit 106 is first configured to detect the rising edge of the pulse 92 (step 124). In response to the detection of the rising edge of the pulse 92, the pulse width determination circuit 106 enables (also referred to as activating) the sampling clock 110. Notably, since the sampling clock 110 is enabled by the rising edge of the pulse 92, the measurement error associated with the rising edge of the pulse 92 can be eliminated.

[0059] In an embodiment, the pulse width determination circuit 106 may enable a full-rate clock or a half-rate clock as the sampling clock 110 depending on configuration requirements. In this regard, the pulse width determination circuit 106 first determines whether the configuration requirement is to improve sampling accuracy or reduce sampling power consumption (step 126). If the configuration requirement is to reduce sampling power consumption, the pulse width determination circuit 106 enables a half-rate clock as the sampling clock 110 (step 128). However, if the configuration requirement is to improve sampling accuracy, the pulse width determination circuit 106 enables a full-rate clock as the sampling clock 110 (step 130). In a non-limiting example, the clock frequency of the full-rate clock is twice that of the half-rate clock.

[0060] The pulse width determination circuit 106 can be configured to include a sampling counter S MSB When sampling clock 110 is active, sampling counter S... MSB The sampling clock 110 increments for each clock cycle 112 (step 132). In this embodiment, for each clock cycle 112 of the sampling clock 110, the pulse width determination circuit 106 causes the sampling counter S to... MSB Add two (2).

[0061] The pulse width determination circuit 106 is configured to determine whether the sampling clock 110 should be disabled (also known as deactivated) to stop the sampling counter S. MSB The increment (step 134). In an embodiment, the pulse width determination circuit 106 is configured to disable the sampling clock 110 in response to detecting a high clock interval 114 immediately following the falling edge of the pulse 94. In other words, the pulse width determination circuit 106 will disable the sampling clock 110 after detecting the first high clock interval 114 following the falling edge of the pulse 94. To do this, the pulse width determination circuit 106 must detect both the rising edge 118 and the falling edge 120 that define the high clock interval 114 immediately following the falling edge of the pulse 94. If the pulse width determination circuit 106 determines that the condition for disabling the sampling clock 110 is not met, then procedure 122 returns to step 132. Otherwise, the pulse width determination circuit 106 will disable the sampling clock 110, thereby preventing the sampling counter S from being incremented. MSB Perform the counting (step 136).

[0062] Given that sampling clock 110 is asynchronous with pulse 90, when sampling clock 110 stops, the falling edge of pulse 94 may fall within either a high clock interval 114 or a low clock interval 116. Furthermore, the falling edge of pulse 94 may even coincide with either a rising edge 118 or a falling edge 120. If not properly handled, such alignment uncertainties could lead to a pulse width P of pulse 90. WIDTHThe final determination has errors. In this regard, the pulse width determination circuit 106 is further configured to determine the phase error indicator S based on the relative position between the pulse falling edge 94 and the clock period 112 in the sampling clock 110. LSB (Step 138). According to an embodiment of this disclosure, when the falling edge of the pulse 94 is within the high clock interval 114, the phase error indicator S is... LSB Set to false (logic "0"), or set to true (logic "1") when the falling edge of the pulse 94 is within the low clock interval 116.

[0063] Therefore, the pulse width determination circuit 106 can be based on the phase error indicator S LSB and sampling counter S MSB And determine the digital sampling count S COUNT (Step 140). Specifically, when the phase error indicator S... LSB When true, the digital sample count S COUNT Equal to the sampling counter P MSB The value minus "1" (S) COUNT = S MSB - 1). In contrast, when the phase error indicator S LSB When it is false, the digital sampling count S COUNT Equal to the sampling counter S MSB The value minus "2" (S) COUNT = S MSB - 2). Finally, the pulse width determination circuit 106 can be based on the digital sampling count S. COUNT The pulse width P of pulse 90 is determined by the clock rate of sampling clock 110. WIDTH (Step 142).

[0064] In this embodiment, the digital sample count S can be optimized. COUNT The arithmetic determination is used to help further reduce power consumption. As an example, the sampling counter S... MSB It can be configured to increment by one (1) instead of two (2) for each clock cycle 112 of the sampling clock 110. When the sampling clock 110 stops, the sampling counter S MSB Shift left by one (1), thereby shifting the sampling counter S... MSB Multiply by two (2). Then, the sampling counter S is shifted left. MSB Can be used with phase error indicator S LSB Cascaded to generate digital sample count S COUNT .

[0065] Figures 4A to 4D This is a schematic diagram, which provides... Figure 2 Exemplary illustrations of various operating scenarios of the pulse width determination circuit 106 in the circuit. Figure 2 , 3 The common elements between 4A and 4D are shown with common reference numerals and will not be described again herein. It is worth noting that... Figures 4A to 4D The operating scenario described herein is based on a half-rate sampling clock (110). It should be understood that the operating scenario discussed herein also applies to full-rate clocks.

[0066] Figure 4A The scenario is illustrated where the falling edge 94 of the pulse is within the low clock interval 116 of the sampling clock 110. In this example, at time T1, the pulse width determination circuit 106 detects the rising edge 92 of pulse 90. In response, the pulse width determination circuit 106 enables the sampling clock 110 at time T2 (T2 ≥ T1). At time T3 (T3 > T2), the pulse width determination circuit 106 detects the falling edge 120 of the clock. Therefore, the sampling counter S... MSB Increase 2 (S) MSB = 2). At time T4 (T4> T3), the pulse width determination circuit 106 detects the falling edge of the clock 120 again. Therefore, the sampling counter S MSB Add 2 (S) again MSB =4).

[0067] At time T5 (T5 > T4), the pulse width determination circuit 106 detects the falling edge 94 of pulse 90, which falls within the low clock interval 116 of sampling clock 110. However, the falling edge 94 falls within the low clock interval 116 of sampling clock 110. In this respect, at time T5, the pulse width determination circuit 106 has not yet detected another rising edge 118. Shortly after time T5, the pulse width determination circuit 106 detects the rising edge 118. Subsequently, at time T6 (T6 > T5), the pulse width determination circuit 106 detects both the rising edge 118 and the falling edge 120 immediately following the falling edge 94. Therefore, the sampling counter S... MSB Add 2 (S) again MSB = 6).

[0068] Since pulse 90 has gone low at time T5 and the pulse width determination circuit 106 detected both the rising edge 118 and the falling edge 120 of the clock at time T6, the condition for disabling the sampling clock 110 has been met. Therefore, the pulse width determination circuit 106 disables the sampling clock 110 at time T7 (T7 ≥ T6). Therefore, the sampling counter S MSB The increment stops. Since the falling edge of the pulse at 94 is already within the low clock interval 116, the phase error indicator S... LSB It will be true (logic "1"). Therefore, the digital sample count SCOUNT Equals five (5) (S) MSB - 1). In the embodiment, the phase error indicator S LSB Reversible means "the clock phase at which a negative edge of the pulse occurs". Therefore, the phase error indicator S LSB It will become fake again.

[0069] Figure 4B The scenario is illustrated where the falling edge 94 of the pulse is within the high clock interval 114 of the sampling clock 110. In this example, at time T1, the pulse width determination circuit 106 detects the rising edge 92 of pulse 90. In response, the pulse width determination circuit 106 enables the sampling clock 110 at time T2 (T2 ≥ T1). At time T3 (T3 > T2), the pulse width determination circuit 106 detects the falling edge 120 of the clock. Therefore, the sampling counter S... MSB Increase 2 (S) MSB = 2).

[0070] At time T4 (T4 > T3), the pulse width determination circuit 106 detects the falling edge 94 of pulse 90, which falls within the high clock interval 114 of sampling clock 110. At time T5 (T5 > T4), the pulse width determination circuit 106 detects the falling edge 120 again. Therefore, the sampling counter S... MSB Add 2 (S) again MSB = 4). At time T6 (T6>T5), the pulse width determination circuit 106 detects both the rising clock edge 118 and the falling clock edge 120 immediately following the falling pulse edge 94. Therefore, the sampling counter S MSB Add 2 (S) again MSB = 6).

[0071] Since pulse 90 went low at time T4 and the pulse width determination circuit 106 detected both the rising edge 118 and the falling edge 120 of the clock at time T6, the condition for disabling the sampling clock 110 has been met. Therefore, the pulse width determination circuit 106 disables the sampling clock 110 at time T7 (T7 ≥ T6). Therefore, the sampling counter S... MSB The increment stops. Since the falling edge of the pulse at 94 is already within the high clock interval 114, the phase error indicator S... LSB The result will be false (logic "0"). Therefore, the digital sample count S COUNT Equals four (4) (S) MSB - 2).

[0072] Figure 4C and 4D Two metastable scenarios are illustrated. Specifically, Figure 4CThe example shown illustrates a scenario where the falling edge 94 of the pulse coincides with the rising edge 92 of the sampling clock 110 pulse.

[0073] In this paper, at time T1, the pulse width determination circuit 106 detects the rising edge 92 of pulse 90. In response, the pulse width determination circuit 106 enables the sampling clock 110 at time T2 (T2 ≥ T1). At time T3 (T3 > T2), the pulse width determination circuit 106 detects the falling edge 120 of the clock. Therefore, the sampling counter S... MSB Increase 2 (S) MSB = 2).

[0074] At time T4 (T4 > T3), the pulse width determination circuit 106 detects the falling edge 94 of pulse 90, which coincides with the rising edge 118 of sampling clock 110. At time T5 (T5 > T4), the pulse width determination circuit 106 detects the falling edge 120 of sampling clock 110. Therefore, the sampling counter S... MSB Add 2 (S) again MSB = 4). At this point, the pulse width determination circuit 106 can generate a digital sampling count S with two different values. COUNT This depends on whether the pulse width determination circuit 106 has sufficient setup and / or hold time to detect the rising edge of the clock 118 at time T4.

[0075] If the pulse width determination circuit 106 has sufficient set / hold time to actually detect the rising edge 118 of the clock at time T4, the condition for disabling the sampling clock 110 will be met at time T5, and the pulse width determination circuit 106 can disable the sampling clock 110 at time T6 (T6 ≥ T5). Therefore, the falling edge 94 of the pulse will be considered to be within the low clock interval 116, and the sampling error indicator S LSB This will be set to true (as shown by the solid line). Therefore, the digital sample count S COUNT Equals three (3)(S) MSB - 1).

[0076] However, if the pulse width determination circuit 106 does not have sufficient set / hold time to actually detect the rising clock edge 118 at time T4, then the pulse width determination circuit 106 will detect both the rising clock edge 118 and the falling clock edge 120 at time T7 (T7>T6). In this respect, the pulse width determination circuit 106 will process an additional clock cycle 112 (as shown by the dashed line). Therefore, the sampling counter S MSB Add 2 (S) again MSB= 6). Subsequently, the pulse width determination circuit 106 disables the sampling clock 110 at time T8 (T8 ≥ T7). Therefore, the falling edge of the pulse 94 will be considered to be within the high clock interval 114, and the sampling error indicator S... LSB This will be set to false (indicated by the dashed line). Therefore, the digital sample count S COUNT Equals four (4) (S) MSB - 2).

[0077] Figure 4D The scenario is illustrated where the falling edge 94 of the pulse coincides with the falling edge 120 of the sampling clock 110. In this example, at time T1, the pulse width determination circuit 106 detects the rising edge 92 of pulse 90. In response, the pulse width determination circuit 106 enables the sampling clock 110 at time T2 (T2 ≥ T1). At time T3 (T3 > T2), the pulse width determination circuit 106 detects the falling edge 120. Therefore, the sampling counter S... MSB Increase 2 (S) MSB = 2).

[0078] At time T4 (T4>T3), the pulse width determination circuit 106 detects the falling edge 94 of pulse 90, which coincides with the falling edge 120 of sampling clock 110. Therefore, the sampling counter S... MSB Add 2 (S) again MSB = 4). At time T5 (T5> T4), the pulse width determination circuit 106 detects both the rising clock edge 118 and the falling clock edge 120 immediately following the falling pulse edge 94. Therefore, the sampling counter S MSB Add 2 (S) again MSB = 6).

[0079] Since pulse 90 went low at time T4 and the pulse width determination circuit 106 detected both the rising edge 118 and the falling edge 120 of the clock at time T5, the condition for disabling the sampling clock 110 has been met. Therefore, the pulse width determination circuit 106 disables the sampling clock 110 at time T6 (T6 ≥ T5). Therefore, the sampling counter S... MSB Stop increasing.

[0080] At this point, the pulse width determination circuit 106 may encounter the sampling error indicator S. LSB The dilemma of whether it should be true or false. If the pulse width determination circuit 106 will set the sampling error indicator S... LSB If true, then the digital sampling count S COUNT Equals five (5) (S) MSB - 1). Otherwise, the digital sample count S COUNTThis will equal four (4) (S) MSB - 2).

[0081] Figure 5 This is a schematic diagram, which provides... Figure 2 An exemplary illustration of a pulse width determination circuit 106 configured to process... Figures 4A to 4D Various operational scenarios within it. Figure 2 and Figure 5 The common elements between them are shown in the accompanying drawings with common reference numerals, and will not be described again herein.

[0082] In this embodiment, the pulse width determination circuit 106 includes a first flip-flop circuit 144, a second flip-flop circuit 146, a sampling counter circuit 148, and an oscillator 150. When enabled, the oscillator 150 is configured to generate a sampling clock 110 as a half-rate clock or a full-rate clock.

[0083] The first flip-flop circuit 144 is configured to control the oscillator 150, thereby enabling and disabling the sampling clock 110. Specifically, the first flip-flop circuit 144 is configured to perform... Figure 3 Steps 124, 126, 128, 130, 134 and 136 in procedure 122.

[0084] The second trigger circuit 146 is configured to determine the phase error indicator S. LSB More specifically, the second trigger circuit 146 is configured to execute step 138 in program 122.

[0085] The sampling counter circuit 148 is configured to make the sampling count S MSB Increment to determine the digital sampling count S COUNT And the pulse width P of pulse 90 WIDTH In other words, the sampling counter circuit 148 is configured to perform steps 132, 140, and 142 in program 122.

[0086] According to an embodiment of this disclosure, the first flip-flop circuit 144 includes a pair of first flip-flops 152 and 154. The first flip-flops 152 and 154 are locked to a rising clock edge 118 and a falling clock edge 120, respectively. Therefore, when pulse 90 transitions from high to low, the first flip-flops 152 and 154 will be able to detect the rising clock edge 118 first after the falling clock edge 94, and subsequently detect the falling clock edge 120. Thus, the first flip-flop circuit 144 can control the oscillator 150 to disable the sampling clock 110 on or after the detection of the falling clock edge 120.

[0087] The second flip-flop circuit 146 includes a pair of second flip-flops 156 and 158. In this document, the second flip-flops 156 and 158 are configured to track the relative position between the falling edge of the pulse 94 and the same one of the rising edge of the clock 118 and the falling edge of the clock 120, thereby determining the phase error indicator S. LSB Since the second flip-flops 156 and 158 in the second flip-flop circuit 146 are locked to the same edge of the sampling clock 110, the second flip-flop circuit 146 will target the sampling counter S. MSB Different values ​​produce different phase error indicators SLSB .

[0088] The first flip-flop circuit 144 and the second flip-flop circuit 146 configured in this article can effectively handle... Figure 4C and 4D The metastable scenario is illustrated. Specifically, since the clocks of the first flip-flop circuit 144 and the second flip-flop circuit 146 are timed on opposite clock edges, the first flip-flop circuit 144 and the second flip-flop circuit 146 will correspond to opposite polarities. In this respect, if one of the first flip-flop circuit 144 and the second flip-flop circuit 146 experiences metastability, the other of the first flip-flop circuit 144 and the second flip-flop circuit 146 will not experience metastability. As an example, Figure 6 It is a schematic diagram that provides information about Figure 5 How can the pulse width determination circuit 105 in the middle be handled? Figure 4C An exemplary illustration of the metastable state in the figure. Figure 2 and 6 The common elements between them are shown in the accompanying drawings with common reference numerals, and will not be described again herein.

[0089] In this paper, the falling edge of the pulse 94 coincides with the rising edge of the clock 118. In one possibility, the first flip-flop circuit 144 can treat the falling edge of the pulse 94 as being within a low clock interval 116, thereby causing the sampling counter S... MSB Count three (3) times (S) MSB = 6). Simultaneously, the second trigger circuit 146 will display the phase error indicator S. LSB Set to true. Therefore, the digital sample count S COUNT This will equal five (5) (S) MSB - 1).

[0090] In another possibility, the first flip-flop circuit 144 can treat the falling edge of the pulse 94 as being in the high clock interval 114, thereby causing the sampling counter S to... MSB Count four (4) times (S) MSB = 8). Simultaneously, the second trigger circuit 146 will trigger the phase error indicator S. LSBSet to false. Therefore, the digital sample count S COUNT This will equal six (6) (S) MSB - 2). Although the digital sample count S in the two different cases COUNT It may result in a difference of one (1) LSB, but the overall error tolerance remains within a reasonable error tolerance of ±0.5 LSB.

[0091] It can be provided in user components (e.g., wireless devices). Figure 2 A single-wire bus device 86 is provided to support the embodiments described above. In this regard, Figure 7 This is a schematic diagram of an exemplary user element 200, in which the following can be provided Figure 2 86 is a single-wire bus device.

[0092] In this document, user element 200 can be any type of user element, such as a mobile terminal, smartwatch, tablet computer, computer, navigation device, access point, and similar wireless communication devices supporting wireless communication, such as cellular, wireless local area network (WLAN), Bluetooth, and near-field communication. User element 200 typically includes a control system 202, a baseband processor 204, a transmitting circuit system 206, a receiving circuit system 208, an antenna switching circuit system 210, multiple antennas 212, and a user interface circuit system 214. In a non-limiting example, the control system 202 may be a field-programmable gate array (FPGA). In this respect, the control system 202 may include at least a microprocessor, embedded memory circuitry, and a communication bus interface. The receiving circuit system 208 receives radio frequency signals from one or more base stations via antenna 212 and through antenna switching circuit system 210. Low-noise amplifiers and filters cooperate to amplify and eliminate broadband interference from the received signal for processing. Then, a down-conversion and digitization circuit system (not shown) down-converts the filtered received signal to an intermediate or baseband frequency signal, and then uses an analog-to-digital converter (ADC) to digitize the signal into one or more digital streams.

[0093] The baseband processor 204 processes the digitized received signal to extract the information or data bits transmitted in the received signal. This processing typically includes demodulation, decoding, and error correction operations, which will be discussed in more detail below. The baseband processor 204 is typically implemented in one or more digital signal processors (DSPs) and application-specific integrated circuits (ASICs).

[0094] For transmission, baseband processor 204 receives digitized data, which may represent voice, data, or control information, from control system 202. The baseband processor encodes the digitized data for transmission. The encoded data is output to transmission circuitry 206, where a digital-to-analog converter (DAC) converts the digitized data into an analog signal, and a modulator modulates the analog signal onto a carrier signal at one or more desired transmission frequencies. A power amplifier amplifies the modulated carrier signal to a level suitable for transmission and delivers the modulated carrier signal to antenna 212 via antenna switching circuitry 210. Multiple antennas 212, along with replicated transmission circuitry 206 and receiving circuitry 208, can provide spatial diversity. Those skilled in the art will understand the modulation and processing details.

[0095] In one embodiment, a single-wire bus device 86 may be disposed in the antenna switching circuit system 210 to enable communication between the antenna switching circuit system 210 and the antenna 212. In other embodiments, the single-wire bus device 86 may also be used to enable communication between the antenna switching circuit system 210, the transmission circuit system 206, and / or the receiving circuit system 208.

[0096] Those skilled in the art will recognize improvements and modifications to the embodiments of this disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the following claims.

Claims

1. A pulse width determination circuit, configured to: Receives pulses defined by the rising and falling edges of the pulse; A sampling clock with multiple clock cycles is enabled in response to the detection of the rising edge of the pulse, each clock cycle including a high clock interval defined by the rising edge and the falling edge of the clock and a subsequent low clock interval. The sampling counter is incremented for each of the plurality of clock cycles of the sampling clock; In response to the detection of a rising edge and a falling edge of a clock that define a high clock interval immediately following the falling edge of the pulse, the sampling clock is disabled; A phase error indicator is determined based on the relative position between the falling edge of the pulse and one of the plurality of clock cycles in the sampling clock; and The digital sample count is determined based on the sampling counter and the phase error indicator.

2. The pulse width determination circuit according to claim 1, comprising: The first flip-flop circuit is configured as follows: The sampling clock is enabled in response to the detection of the rising edge of the pulse; and In response to the detection of a rising edge and a falling edge of a clock that define a high clock interval immediately following the falling edge of the pulse, the sampling clock is disabled; A second trigger circuit is configured to determine the phase error indicator; as well as The sampling counter circuit is configured as follows: The sampling counter is incremented for each of the plurality of clock cycles of the sampling clock; and The digital sample count is determined, and the pulse width of the pulse is determined based on the digital sample count.

3. The pulse width determination circuit according to claim 2, wherein: The first flip-flop circuit includes a pair of first flip-flops, the pair of first flip-flops being configured to detect the rising edge and the falling edge of the clock in each of the plurality of clock cycles, respectively; and The second trigger circuit includes a pair of second triggers configured to track the relative position between the falling edge of the pulse and the same rising edge and falling edge of one of the plurality of clock cycles, thereby determining the phase error indicator.

4. The pulse width determination circuit according to claim 1, further configured to determine the pulse width of the pulse based on the digital sample count and the clock rate of the sampling clock.

5. The pulse width determination circuit according to claim 1, further configured as follows: Enabling a half-rate clock as the sampling clock saves sampling power; and Using a full-rate clock with a speed twice that of the half-rate clock as the sampling clock improves sampling accuracy.

6. The pulse width determination circuit of claim 1, further configured to increment the sampling counter by two, i.e., 2, for each of the plurality of clock cycles of the sampling clock.

7. The pulse width determination circuit of claim 6, further configured to increment the sampling counter in response to the detection of the falling edge of the clock in each of the plurality of clock cycles.

8. The pulse width determination circuit according to claim 1, further configured as follows: When the falling edge of the pulse is within the low clock interval, the phase error indicator is determined to be true; and When the falling edge of the pulse is within the high clock interval, the phase error indicator is determined to be false.

9. The pulse width determination circuit according to claim 8, further configured as follows: In response to the phase error indicator being true, the digital sample count is determined to be equal to the value of the sample counter minus one, i.e., 1; and In response to the phase error indicator being false, the digital sample count is determined to be equal to the value of the sample counter minus two, i.e., 2.

10. A method for determining the pulse width of a pulse, comprising: Receive the pulse defined by the rising edge and falling edge of the pulse; A sampling clock with multiple clock cycles is enabled in response to the detection of the rising edge of the pulse, each clock cycle including a high clock interval defined by the rising edge and the falling edge of the clock and a subsequent low clock interval. The sampling counter is incremented for each of the plurality of clock cycles of the sampling clock; In response to the detection of a rising edge and a falling edge of a clock that define a high clock interval immediately following the falling edge of the pulse, the sampling clock is disabled; A phase error indicator is determined based on the relative position between the falling edge of the pulse and one of the plurality of clock cycles in the sampling clock; as well as The digital sample count is determined based on the sampling counter and the phase error indicator.

11. The method of claim 10, further comprising determining the pulse width of the pulse based on the digital sample count and the clock rate of the sampling clock.

12. The method of claim 10, further comprising: Enable a half-rate clock as the sampling clock to save sampling power; as well as Using a full-rate clock with a speed twice that of the half-rate clock as the sampling clock improves sampling accuracy.

13. The method of claim 10, further comprising incrementing the sampling counter by two, i.e., 2, for each of the plurality of clock cycles of the sampling clock.

14. The method of claim 13, further comprising incrementing the sampling counter in response to detecting the falling edge of the clock in each of the plurality of clock cycles.

15. The method of claim 10, further comprising: When the falling edge of the pulse is within the low clock interval, the phase error indicator is determined to be true; as well as When the falling edge of the pulse is within the high clock interval, the phase error indicator is determined to be false.

16. The method of claim 15, further comprising: In response to the phase error indicator being true, the digital sample count is determined to be equal to the value of the sample counter minus one, i.e., 1; as well as In response to the phase error indicator being false, the digital sample count is determined to be equal to the value of the sample counter minus two, i.e., 2.

17. A wireless device comprising a single-wire bus device, the single-wire bus device comprising: The main circuit is coupled to a single-wire bus consisting of a single conductor and is configured to transmit multiple bus telegrams, each bus telegram preceded by a sequence of SOS sequences, the SOS sequences including synchronization pulses defined by rising and falling edges of pulses. as well as Multiple slave circuits, each coupled to the single-wire bus and including pulse width determination circuitry, the pulse width determination circuitry being configured to: The synchronization pulse is received via the single-wire bus; A sampling clock with multiple clock cycles is enabled in response to the detection of the rising edge of the pulse, each clock cycle including a high clock interval defined by the rising edge and the falling edge of the clock and a subsequent low clock interval. The sampling counter is incremented for each of the plurality of clock cycles of the sampling clock; In response to the detection of a rising edge and a falling edge of a clock that define a high clock interval immediately following the falling edge of the pulse, the sampling clock is disabled; A phase error indicator is determined based on the relative position between the falling edge of the pulse and one of the plurality of clock cycles in the sampling clock; and The digital sample count is determined based on the sampling counter and the phase error indicator.

18. The wireless device of claim 17, wherein the pulse width determination circuit comprises: The first flip-flop circuit is configured as follows: The sampling clock is enabled in response to the detection of the rising edge of the pulse; and In response to the detection of a rising edge and a falling edge of a clock that define a high clock interval immediately following the falling edge of the pulse, the sampling clock is disabled; A second trigger circuit is configured to determine the phase error indicator; as well as The sampling counter circuit is configured as follows: The sampling counter is incremented for each of the plurality of clock cycles of the sampling clock; and The digital sampling count is determined, and the pulse width of the synchronization pulse is determined based on the digital sampling count.

19. The wireless device according to claim 18, wherein: The first flip-flop circuit includes a pair of first flip-flops, the pair of first flip-flops being configured to detect the rising edge and the falling edge of the clock in each of the plurality of clock cycles, respectively; and The second trigger circuit includes a pair of second triggers configured to track the relative position between the falling edge of the pulse and the same rising edge and falling edge of one of the plurality of clock cycles, thereby determining the phase error indicator.

20. The wireless device of claim 17, wherein the pulse width determination circuit is further configured to determine the pulse width of the synchronization pulse based on the digital sample count and the clock rate of the sampling clock.

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