Layout optimization method, system, electronic device, storage medium and program product

Abstract

A layout optimization method, system, electronic device, storage medium and program product, the layout optimization method comprising: obtaining a conflict pattern group that does not conform to a layout parameter rule in a target layout; within a lithography limit process window, shrinking the feature size of a pattern in the conflict pattern group to an optimized feature size to obtain an optimized target layout. Since the shrinking of the feature size will affect the pitch, the method of adjusting the feature size of the pattern in the conflict pattern group to the optimized feature size within the lithography limit process window improves the process capability limitation problem, and easily makes the optimized target layout conform to the process requirement; moreover, the method of adjusting the feature size of the pattern to improve the process capability limitation problem also reduces the demand for re-drawing the layout, which is also conducive to reducing the probability of repetitive work caused by the information gap between the layout design party and the manufacturer, thereby improving the work efficiency.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and more particularly to a layout optimization method, system, electronic device, storage medium, and program product. Background Technology

[0002] Patterning is an essential process in semiconductor manufacturing. This involves transferring the pattern from the design layout of the semiconductor device onto photoresist using photolithography.

[0003] However, with the development of semiconductor technology, the integration density of integrated circuits is increasing, the critical dimension (CD) of patterns is gradually decreasing, and the spacing between patterns is also gradually decreasing. Correspondingly, the requirements for manufacturing processes are becoming increasingly precise, and the number and density of target patterns on the layout are increasing dramatically. It is becoming increasingly impossible to expose all target patterns onto the wafer at once during photolithography. Therefore, multi-patterning (MP) technology has become a necessary means to ensure that the exposed patterns meet the process requirements of each node. MP technology splits the relatively dense target patterns originally placed on a single layout into multiple sub-layouts, and uses these multiple sub-layouts for separate exposure to complete the transfer of the target patterns.

[0004] However, in existing technologies, when a relatively dense target graphic is split into multiple sub-patterns, there are still many problems with the target graphic on the sub-patterns. Therefore, the multi-mask technology still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a layout optimization method, system, electronic device, storage medium and program product, which makes it easy for the optimized target layout to meet process requirements and helps to improve the efficiency of layout optimization.

[0006] To address the aforementioned problems, this invention provides a layout optimization method, comprising: obtaining a target layout to be optimized, the target layout including multiple graphics; obtaining a group of conflicting graphics in the target layout that do not conform to layout parameter rules, the layout parameter rules including spacing rules or pitch rules; shrinking the feature dimensions of the graphics in the conflicting graphic group in the conflict direction within a photolithography limit process window to adjust them to optimized feature dimensions, thereby obtaining an optimized target layout.

[0007] Accordingly, this invention also provides a layout optimization system, comprising: a first layout acquisition module for acquiring a target layout to be optimized, the target layout including multiple graphics; a conflict graphic group acquisition module for acquiring conflict graphic groups in the target layout that do not conform to layout parameter rules, the layout parameter rules including spacing rules or pitch rules; and an adjustment module for shrinking the feature size of the graphics in the conflict graphic group in the conflict direction within a photolithography limit process window to adjust it to the optimized feature size, thereby obtaining the optimized target layout.

[0008] Accordingly, embodiments of the present invention also provide an electronic device, including at least one memory and at least one processor, wherein the memory stores one or more computer instructions, and the one or more computer instructions are executed by the processor to implement the layout optimization method of any embodiment of the present invention.

[0009] Accordingly, embodiments of the present invention also provide a computer program product, including computer instructions, which, when executed by a processor, are used to implement the layout optimization method of any embodiment of the present invention.

[0010] Accordingly, embodiments of the present invention also provide a storage medium storing one or more computer instructions, which are used to implement the layout optimization method of any embodiment of the present invention.

[0011] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0012] This invention provides a layout optimization method, comprising: obtaining a target layout to be optimized, the target layout including multiple graphics; obtaining a group of conflicting graphics in the target layout that do not conform to layout parameter rules, the layout parameter rules including space rules or pitch rules; and shrinking the feature dimensions of the graphics in the conflicting graphic group in the conflict direction within a lithography limit process window to adjust them to optimized feature dimensions, thereby obtaining an optimized target layout. Since shrinking the feature dimensions of the graphics in the conflicting graphic group affects the space, this invention improves the process capability limitation problem by adjusting the feature dimensions of the graphics in the conflicting graphic group to optimized feature dimensions within the lithography limit process window. This makes it easier for the optimized target layout to meet process requirements, thereby improving product performance. Furthermore, improving the process capability limitation problem by adjusting the feature dimensions of the graphics also reduces the need to redraw the layout, which in turn reduces the probability of repetitive work caused by information asymmetry between the layout designer and the manufacturer (FAB), thus improving work efficiency. Attached Figure Description

[0013] Figure 1 This is a flowchart of a method for partitioning a map;

[0014] Figure 2 This is a flowchart of an embodiment of the layout optimization method of the present invention;

[0015] Figure 3 This is a schematic diagram of the original layout in one embodiment of the layout optimization method of the present invention;

[0016] Figure 4 This is a schematic diagram of the partitioning result after partitioning based on the original layout in one embodiment of the layout optimization method of the present invention;

[0017] Figure 5 This is a schematic diagram of the target layout to be optimized in one embodiment of the layout optimization method of the present invention;

[0018] Figure 6 This is a schematic diagram of a conflicting graphic group in one embodiment of the layout optimization method of the present invention;

[0019] Figure 7 yes Figure 6 Enlarged view of the area within the dashed box;

[0020] Figure 8 This is a schematic diagram of the splitting result after layout optimization in one embodiment of the layout optimization method of the present invention;

[0021] Figure 9 This is a reference data table for the extreme process within the photolithography extreme process window according to an embodiment of the present invention;

[0022] Figure 10 This is a functional block diagram of an embodiment of the layout optimization system of the present invention;

[0023] Figure 11 This is a hardware structure diagram of an embodiment of the electronic device provided by the present invention. Detailed Implementation

[0024] As the background technology indicates, the multi-mask technology still needs improvement. This paper analyzes the reasons why the multi-mask technology still needs improvement, using a layout splitting method as an example.

[0025] Figure 1 This is a flowchart of a method for dividing a map.

[0026] refer to Figure 1 The methods for dividing the map include:

[0027] Step s1: Obtain the layout to be split, which includes multiple target graphics;

[0028] Step s2: According to the layout splitting restriction rules, the layout to be split is split into multiple sub-layouts so that each target graphic is set on a different sub-layout, and the splitting result is obtained;

[0029] Step s3: Perform a layout design rule check on the multiple sub-layouts to determine whether the target graphics in the multiple sub-layouts all meet the design rules;

[0030] Step s4: If the target graphics in multiple sub-layouts all satisfy the design rules, then the splitting result is taken as the final splitting result;

[0031] Step s5: If the target graphic of any of the multiple sub-layouts does not meet the design rules, then the current sub-layout to be split is discarded.

[0032] Research has shown that if a target graphic that does not meet the design rules is found in the split sub-layout, the sub-layout to be split needs to be returned to the designer, who will then redraw it. The splitting will then be carried out again based on the redrawn sub-layout, and this process will be repeated multiple times until all the sub-layouts obtained after splitting meet the design rules. Therefore, this can easily lead to a waste of a lot of manpower, material resources and time, thus affecting work efficiency.

[0033] Moreover, if there is an information gap between the designer and the manufacturer, it can easily affect the redrawing of the layout, resulting in repetitive work.

[0034] To address the aforementioned technical problems, embodiments of the present invention provide a layout optimization method.

[0035] refer to Figure 2 , Figure 2 This is a flowchart of an embodiment of the layout optimization method of the present invention. The layout optimization method of the present invention includes the following basic steps:

[0036] Step S1: Obtain the target layout to be optimized, wherein the target layout includes multiple graphics;

[0037] Step S2: Obtain conflicting graphic groups in the target layout that do not conform to the layout parameter rules, wherein the layout parameter rules include spacing rules or pitch rules;

[0038] Step S3: Within the photolithography limit process window, shrink the feature size of the pattern in the conflict pattern group in the conflict direction to adjust it to the optimized feature size, and obtain the optimized target layout.

[0039] In the solutions disclosed in the embodiments of the present invention, since the shrinkage of the feature size of the graphics in the conflicting graphic group affects the spacing, the present invention improves the process capability limitation problem by adjusting the feature size of the graphics in the conflicting graphic group to the optimized feature size within the lithography limit process window. This makes it easier for the optimized target layout to meet process requirements, thereby improving product performance. Moreover, improving the process capability limitation problem by adjusting the feature size of the graphics also reduces the need to redraw the layout, which in turn reduces the probability of repetitive work caused by information gaps between the layout designer and the manufacturer, thereby improving work efficiency.

[0040] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0041] Figures 3 to 8 This is a schematic diagram showing the various steps in one embodiment of the layout optimization method of the present invention. Figure 9 This is a reference data table for the extreme process within the photolithography extreme process window of an embodiment of the present invention.

[0042] refer to Figure 2 and in conjunction with references Figures 3 to 5 , Figure 3 This is a schematic diagram of the original layout in one embodiment of the layout optimization method of the present invention. Figure 4 This is a schematic diagram of the layout optimization method of the present invention after splitting the layout based on the original layout. Figure 5 This is a schematic diagram of the target layout to be optimized in one embodiment of the layout optimization method of the present invention. Step S1: Obtain the target layout 100 to be optimized (e.g., Figure 5 As shown), the target layout 100 includes multiple graphics 101.

[0043] Obtain the target layout 100 to be optimized, which provides a technological basis for the subsequent layout optimization steps of the target layout 100 to be optimized.

[0044] In this embodiment, the graphic of the target layout 100 is a two-dimensional graphic. The feature size direction of the two-dimensional graphic includes the X direction and the Y direction, and the X direction and the Y direction are perpendicular to each other.

[0045] Two-dimensional graphics often have high density and a large number of graphics, which can easily lead to excessively small critical dimensions and spacing of the two-dimensional graphics in a single layout. This can cause the structure formed after the two-dimensional graphics are transferred to the wafer to merge or break with the adjacent structure. In other words, it is relatively more difficult to ensure that the critical dimensions and spacing of all two-dimensional graphics in a single layout meet the process manufacturing capabilities. Correspondingly, through subsequent layout optimization methods, it is easier to make the optimized target layout meet the process requirements; moreover, it can significantly reduce the need to redraw the layout, thereby improving work efficiency.

[0046] As an example, the graphic 101 of the target layout 100 to be optimized is a square graphic. It can be understood that the graphic 101 of the target layout 100 is the design graphic.

[0047] As one embodiment, the pattern 101 of the target layout 100 to be optimized includes a hole pattern. The hole pattern includes a via pattern or a contact hole pattern.

[0048] In the semiconductor manufacturing process, through-hole patterns are used to form conductive through-holes, which provide space for forming through-hole interconnect structures. Contact hole patterns are used to form contact holes, which provide space for forming contact plugs. Through-hole interconnect structures or contact plugs are used to achieve electrical connections between different components.

[0049] As an example, the hole pattern is a through-hole pattern.

[0050] When the hole pattern is transferred to the wafer via a photomask, if the hole pattern cannot meet the layout parameter rules, for example, if the spacing between adjacent hole patterns is too small, causing bridging problems in the structure formed on the wafer, or if the feature size of the hole pattern is too small, causing open circuit problems in the corresponding structure formed on the wafer, then in mid-process or back-end processes, contact resistance and bulk resistance are the main factors affecting the performance of semiconductor structures. Therefore, optimizing the layout corresponding to the hole pattern is beneficial to improving the process window of the manufacturing process and thus improving the performance of the semiconductor structure.

[0051] It should be noted that in other embodiments, the target layout to be optimized may be other types of layout graphics, which are not limited here.

[0052] In this embodiment, the step of obtaining the target layout 100 to be optimized includes: referencing Figure 3 Step S11: Provide the original layout 200, which includes multiple original design graphics 201; Step S12: Refer to Figure 4According to the layout splitting restriction rules, the original layout 200 is split into multiple sub-layouts, so that each original design graphic 201 is set on a different sub-layout; execute step S13: refer to Figure 5 Sub-landscapes that do not meet the landscape splitting restriction rules are selected as target landscapes 100 to be optimized.

[0053] It should be noted that after splitting the original layout 200 into multiple sub-layouts, the sub-layouts that do not meet the layout splitting restriction rules are selected as the target layout 100 to be optimized, which can quickly and directly obtain the target layout 100 to be optimized, thereby improving the efficiency of the target layout 100 optimization.

[0054] The original layout 200 is the initial layout to be split into layouts. The original layout 200 is the layout obtained by drawing the layout. Therefore, the original layout 200 contains all the original design graphics 201 of the corresponding layout layers.

[0055] The original design pattern 201 is used to fabricate a photomask, which is then used for photolithography to transfer the original design pattern 201 onto a wafer to form a corresponding structure.

[0056] In this embodiment, the original design pattern 201 is transferred to the wafer using multiple photomask technology; therefore, the number of sub-patterns is greater than or equal to two.

[0057] It should be noted that the number of sub-plots is determined based on the actual situation. For example, the number of sub-plots can be two, three, or four. Figure 4 As shown, as an example, there are three sub-plots, for example, the first sub-plot M1, the second sub-plot M2, and the third sub-plot M3.

[0058] As an example, pattern 101 in the target layout 100 is a via pattern; therefore, the original layout 200 is a via layout, and the original design pattern 201 is a via design pattern. In the semiconductor field, the pattern density of conductive vias is usually high. By splitting the multiple original design patterns 201 used to form conductive vias, it is beneficial to significantly increase the process window.

[0059] In other embodiments, the original design pattern 201 can also be used to form other types of structures such as contact holes, based on actual process requirements.

[0060] In this embodiment, the original layout 200 is divided into multiple sub-layouts based on the process capabilities specified in the design rule, so that the original design pattern 201 is distributed on different photomasks.

[0061] It should be noted that design rules usually include layout splitting constraints, that is, the rules that graphics within the same photomask must meet.

[0062] Specifically, the layout splitting restriction rules include: the spacing between adjacent original design graphics 201 in the same sub-layout must meet the minimum spacing requirement.

[0063] More specifically, based on the layout splitting constraint rule that the spacing between adjacent original design graphics 201 in the same sub-layout meets the minimum spacing requirement, the original layout 200 is split into multiple sub-layouts, which helps ensure that the graphics in each sub-layout can meet the tolerance of the exposure process.

[0064] It should be noted that the target layout 100 in this embodiment is one of the sub-layouts of the original layout 200 after layout splitting. It can be understood that when there are multiple sub-layouts that do not meet the layout splitting restriction rules, corresponding layout optimizations are performed on multiple target layouts respectively.

[0065] In other embodiments, depending on the actual situation, the target layout can also be the original layout. For example, if the optimized original layout can meet the process capabilities specified in the design rules by adjusting the feature size of the graphics in the original layout, then the original layout may not need to be split.

[0066] refer to Figure 2 And continue to refer to Figure 5 Step S2: Obtain conflicting graphic groups 102 in the target layout 100 that do not conform to the layout parameter rules, the layout parameter rules including spacing rules or pitch rules.

[0067] It should be noted that along the feature size direction, the pitch is equal to the sum of the feature size of the graphic and the spacing. When optimizing the layout, either the spacing rule or the pitch rule can be selected based on the actual situation. As an example, the layout parameter rule can be a spacing rule.

[0068] It should be noted that by obtaining the conflicting graphic group 102 in the target layout 100 that does not conform to the layout parameter rules, in the layout optimization step, only the feature size of the conflicting graphic group 102 needs to be adjusted, which reduces the need to redraw the layout and thus improves work efficiency.

[0069] It should also be noted that, Figure 6 A conflict graphic group 102 is illustrated. In other embodiments, multiple conflict graphic groups may appear in the same target layout.

[0070] Furthermore, when there are multiple conflicting graphic groups in the target map, the multiple conflicting graphic groups can be independent of each other, or any two conflicting graphic groups can share a single graphic.

[0071] In this embodiment, in the step of obtaining conflicting graphic groups 102 in the target layout 100 that do not conform to the layout parameter rules, when there are graphics shared by multiple conflicting graphic groups 102, the graphics shared by multiple conflicting graphic groups 102 are regarded as common conflicting graphics.

[0072] refer to Figure 2 and in conjunction with references Figures 6 to 7 , Figure 6 This is a schematic diagram of a conflicting graphic group in one embodiment of the layout optimization method of the present invention. Figure 7 yes Figure 6 Enlarged view of the area within the dashed frame. Step S3: Within the photolithography limit process window, shrink the feature size of the pattern in the conflict pattern group 102 in the conflict direction to adjust it to the optimized feature size, and obtain the optimized target layout 103.

[0073] The photolithography limit process window refers to the smallest acceptable process window in actual photolithography processes.

[0074] Here, the conflict direction refers to the arrangement direction of the edges of the graphics in the conflict graphic group 102 where a conflict occurs.

[0075] It should be noted that since the shrinkage of the feature size of any graphic in the conflicting graphic group 102 will affect the spacing between adjacent graphics, in this embodiment of the invention, the method of adjusting the feature size of the graphics in the conflicting graphic group 102 to the optimized feature size within the photolithography limit process window improves the process capability limitation problem, making it easier for the optimized target layout 103 to meet process requirements, thereby improving product performance; moreover, by adjusting the feature size of the graphics to improve the process capability limitation problem, the need to redraw the layout is also reduced, which also helps to reduce the probability of repetitive work caused by the information gap between the layout designer and the manufacturer, thereby improving work efficiency.

[0076] Moreover, by optimizing the feature size, the layout can be optimized without readjusting the global layout, thereby increasing the freedom of graphic placement.

[0077] The feature size of the graphic in the conflict graphic group 102 refers to the current feature size of the graphic in the conflict graphic group 102, which is also the design feature size of the graphic.

[0078] It should be noted that shrinking the feature size of the graphics in the conflict graphic group 102 makes it easier to meet design rules, thereby reducing the need to redraw the layout. At the same time, shrinking the feature size of the graphics in the conflict graphic group 102 reduces the probability of increasing the layout area and the number of photomasks, thus reducing costs.

[0079] In this embodiment, the feature dimensions of each graphic in the conflict graphic group 102 in the conflict direction are shrunk.

[0080] like Figure 7 As shown, Figure 7 The dashed outline in the figure represents the initial outline of the figures in the conflict figure group 102 before shrinking. By shrinking the feature size of the figures in the X direction, the spacing between the figures in the conflict figure group 102 is increased.

[0081] It should also be noted that shrinking the feature size of the graphics in the conflicting graphic group 102 helps to reduce the impact on other graphics 101 on the target layout 100, thereby reducing the risk of adding other conflicting graphic groups 102. At the same time, shrinking the feature size of the graphics in the conflicting graphic group 102 helps to increase the spacing between adjacent graphics in the conflicting graphic group 102, thereby reducing the probability that the structure formed after the graphics in the conflicting graphic group 102 are transferred to the wafer will come into contact or merge with another adjacent structure.

[0082] In this embodiment, the step of shrinking the feature size of the pattern in the conflict pattern group 102 in the conflict direction within the photolithography limit process window includes: obtaining the limit feature size that matches the current spacing as the optimized feature size of the pattern in the conflict pattern group 102 in the conflict direction based on the preset correspondence between the spacing of the pattern in the photolithography limit process window and the limit feature size, and the current spacing of the pattern in the conflict pattern group 102; and adjusting the feature size of the pattern in the conflict pattern group 102 in the conflict direction based on the optimized feature size.

[0083] Based on the preset correspondence between the spacing of the patterns within the photolithography limit process window and the limit feature size, and the current spacing of the patterns in the conflict pattern group 102, the limit feature size that matches the current spacing is obtained as the optimized feature size of the patterns in the conflict pattern group 102 in the conflict direction, which is used to prepare for the subsequent step of adjusting the feature size of the patterns in the conflict pattern group 102.

[0084] In the preset correspondence, the limit feature size corresponding to the spacing refers to the feature size that can be selected within the photolithography process window under certain spacing conditions. This means that under certain spacing conditions, it is safe to set the feature size of the pattern to the limit feature size corresponding to the spacing, and the limit feature size corresponding to the spacing can ensure the process window of the photolithography process.

[0085] It should be noted that, in the preset correspondence, the limit feature size refers to the design size (CD) of the graphic. design ).

[0086] Moreover, due to the existence of the preset correspondence, once the current spacing of the graphics in the conflict graphic group 102 is known, the limit feature size corresponding to the spacing can be obtained quickly and accurately according to the preset correspondence. This helps to reduce the complexity of adjusting the feature size of the graphics in the conflict graphic group 102 and improve the efficiency of the layout optimization method.

[0087] Specifically, the step of obtaining the optimized feature size of the pattern in the conflict pattern group 102 in the conflict direction based on the preset correspondence between the spacing of the pattern within the photolithography limit process window and the limit feature size, and the current spacing of the pattern in the conflict pattern group 102, includes: obtaining limit process reference data within the photolithography limit process window, the limit process reference data including the limit feature size corresponding to the pattern under different spacing conditions; and obtaining the optimized feature size of the pattern in the conflict pattern group 102 in the conflict direction based on the limit process reference data and the current spacing of the pattern in the conflict pattern group 102.

[0088] It should be noted that by using the extreme process reference data to characterize the preset correspondence between the spacing of the patterns and the extreme feature size within the lithography extreme process window, the complexity of obtaining the preset correspondence is reduced (for example, the optimized feature size of the patterns in the conflict pattern group 102 can be obtained by querying). Moreover, it is convenient to update the extreme process reference data at any time as needed.

[0089] It should also be noted that the limiting feature size of the pattern may be the same or different under different spacing conditions. It is difficult to guarantee that the spacing and the limiting feature size will necessarily have a linear relationship under the same photolithography limiting process window. Therefore, using the limiting process reference data is also convenient for accurately obtaining the correspondence between spacing and limiting feature size.

[0090] In this embodiment, the graphic of the target layout 100 is a two-dimensional graphic. The feature size direction of the two-dimensional graphic includes the X direction and the Y direction, and the X direction and the Y direction are perpendicular to each other. Therefore, in the preset correspondence between the spacing and the limit feature size, the spacing is a combination of spacing, and the spacing combination includes the spacing in the X direction and the spacing in the Y direction. The limit feature size is a combination of limit feature sizes, and the limit feature size combination includes the limit feature size in the X direction and the limit feature size in the Y direction.

[0091] The preset correspondence includes four-dimensional variables: X-direction spacing, Y-direction spacing, X-direction limit feature size, and Y-direction limit feature size. Once the X-direction spacing and Y-direction spacing of the graphics in the conflict graphic group 102 are determined, the acceptable limit feature size of the graphics in both directions can be obtained simultaneously. Therefore, based on the spacing of the graphics in the conflict graphic group 102 in the conflict direction, the acceptable limit feature size in the conflict direction can be obtained accurately and quickly, thereby improving the efficiency and accuracy of obtaining the optimized feature size.

[0092] As an example, reference Figure 9 The extreme process reference data within the photolithography extreme process window is a tabular database. In this database, each row represents a different X-direction spacing, each column represents a different Y-direction spacing, and each spacing combination corresponds to a specific extreme feature size combination.

[0093] It should be noted that the solution of using a tabular database for the extreme process reference data within the photolithography extreme process window is simpler and easier to implement.

[0094] It should also be noted that the extreme process reference data in the photolithography extreme process window is a tabular database, which is conducive to clearly and accurately recording the extreme feature size corresponding to the pattern under different spacing conditions. This makes it easy to quickly and accurately obtain the optimized feature size of the pattern in the conflict pattern group 102 based on the current spacing of the pattern in the conflict pattern group 102, thereby improving the efficiency of optimizing the feature size of the pattern in the conflict pattern group 102.

[0095] Furthermore, since the spacing combination includes spacing in the X direction and spacing in the Y direction, the tabular database includes the limiting feature dimensions of the graphic under different spacing conditions in different directions, and the limiting feature dimensions correspondingly include the limiting feature dimensions in different directions.

[0096] Understandable, Figure 9 The illustrated tabular database is merely one specific representation of the preset correspondence, but the representation of the preset correspondence is not limited to a tabular database. For example, in other embodiments, the preset correspondence between the spacing of patterns within the lithography limit process window and the limit feature size can also be obtained by building a model.

[0097] In this embodiment, the method for obtaining the preset correspondence between the spacing of patterns and the limiting feature size within the lithography limit process window includes: using an optical proximity correction model to obtain the process variation bandwidth of test patterns of each lithographic feature size under different spacings in the feature size direction, wherein multiple test patterns have different feature sizes in the feature size direction, and the test patterns of each feature size have different spacings, and the test patterns include the pattern 101 of the target layout 100; based on the lithographic feature size corresponding to the process variation bandwidth that satisfies the process variation bandwidth threshold condition, the preset correspondence between the spacing of patterns and the lithographic feature size within the lithography limit process window is obtained, and each lithographic feature size has a corresponding process variation bandwidth threshold condition; based on the preset correspondence between the spacing of patterns and the lithographic feature size within the lithography limit process window, and the etching deviation, the preset correspondence between the spacing of patterns and the limiting feature size within the lithography limit process window is obtained.

[0098] Etching deviation refers to the difference between the feature size after photolithography and the feature size after etching.

[0099] It should be noted that the method in this embodiment of the invention is used to optimize the pattern on the layout. The bandwidth of the process variation is the result of the pattern after photolithography. In the preset correspondence, the limit feature size refers to the design size (CD) of the pattern. design The design dimensions of the graphic on the layout can be considered equal to the feature dimensions after etching. Therefore, after obtaining the preset correspondence between the spacing of the graphic within the photolithography limit process window and the feature dimensions after photolithography, size compensation is performed based on the etching deviation to obtain the design dimensions.

[0100] By using the optical proximity correction model, it is possible to automatically acquire the process variation bandwidth of test patterns of each lithographic feature size in the feature size direction at different spacings, reducing manual operation and thus improving the efficiency and accuracy of acquiring the process variation bandwidth of test patterns of each lithographic feature size in the feature size direction at different spacings.

[0101] The process variation band (PV band) refers to the deviation in feature size between the outermost and innermost exposure contours of different exposed patterns obtained after exposing the same pattern under different exposure conditions (e.g., different focus points, exposure doses, etc.).

[0102] It should be noted that multiple test patterns have different feature sizes in the feature size direction, and the test patterns of each feature size have different spacing. This is beneficial for collecting a large amount of data on the process variation bandwidth of test patterns of each post-lithographic feature size in the feature size direction under different spacings. This provides more reliable source data for the subsequent step of selecting the preset correspondence between the spacing of the patterns and the post-lithographic feature size within the lithographic limit process window based on the process variation bandwidth threshold condition.

[0103] It should also be noted that the test pattern includes the pattern 101 of the target layout 100, and the multiple test patterns have different feature sizes in the feature size direction, and the test patterns of each feature size have different spacing, so as to obtain test patterns in various environments. This makes the collected data on the process variation bandwidth of the test patterns of each post-lithography feature size under different spacings more comprehensive, so that the data on the process variation bandwidth of the test patterns of each post-lithography feature size under different spacings in the feature size direction can be applied to the optimization of the target layout 100.

[0104] In this embodiment, each post-lithographic feature size has a corresponding process variation bandwidth threshold condition, that is, the process variation bandwidth threshold condition corresponds one-to-one with the post-lithographic feature size. On the one hand, this helps to reduce the amount of computation, and on the other hand, it can provide multiple limit feature sizes, which can provide more options for adjusting the feature size of different shapes of graphics on the layout.

[0105] In this embodiment, the process variation bandwidth threshold condition corresponding to each post-lithography feature size is [Pvband]. min Pvband Threshold ], where Pvband min Pvband is the minimum acceptable process variation bandwidth corresponding to the minimum value within the post-lithographic feature size range to which the post-lithographic feature size belongs. Threshold The maximum acceptable process variation bandwidth corresponds to the maximum value in the feature size range after photolithography.

[0106] It should be noted that the process variation bandwidth threshold condition is a process variation bandwidth range, which is beneficial for accommodating graphics within a certain feature size range, so that the screening conditions are not too strict. This makes it easy to obtain feature sizes and their corresponding spacings that meet the process variation bandwidth threshold condition from a large amount of collected data.

[0107] In this embodiment, the upper bound of the process variation bandwidth threshold condition is determined by the formula Pvband. Threshold =Pvband min +a*CD ADI We obtain, among which, CD ADIis the maximum value in the feature size range after photolithography, and 'a' is a constant coefficient with a value ranging from 0.05 to 0.1.

[0108] It should be noted that, generally, the larger the feature size after photolithography, the greater the bandwidth of process variation. Therefore, the upper bound of the threshold condition for the bandwidth of process variation can be calculated using the above formula.

[0109] It should also be noted that the feature size CD after photolithography... ADI After segmenting the data to obtain multiple post-lithography feature size intervals, for any given post-lithography feature size interval, the process variation bandwidth corresponding to the smallest post-lithography feature size within that interval is taken as the Pvband. min The largest post-lithographic feature size within the range of post-lithographic feature sizes is taken as the CD of this formula. ADI Therefore, by using the largest post-lithography feature size in the post-lithography feature size range, the upper bound of the process variation bandwidth threshold condition corresponding to the post-lithography feature size range can be quickly determined, making the method of obtaining the process variation bandwidth threshold condition more convenient.

[0110] In this embodiment, in the preset correspondence between spacing and limit feature size, each spacing corresponds to multiple limit feature sizes; accordingly, in the step of obtaining the limit feature size that matches the current spacing as the optimized feature size of the graphic in the conflict graphic group 102 in the conflict direction, one limit feature size is selected from the many limit feature sizes that match the current spacing as the optimized feature size of the graphic in the conflict graphic group 102 in the conflict direction.

[0111] It should be noted that in the preset correspondence between spacing and limit feature size, each spacing corresponds to multiple limit feature sizes, which improves the flexibility and diversity of optimizing the feature size of the graphics in the conflict graphic group 102, and can provide more options for adjusting the layout of different process nodes.

[0112] Specifically, in the step of obtaining the limit feature size that matches the current spacing as the optimized feature size of the graphic in the conflict graphic group 102 in the conflict direction, the best limit feature size is selected from multiple limit feature sizes that match the current spacing as the optimized feature size of the graphic in the conflict graphic group 102. This helps to reduce the impact of process parameter fluctuations on the actual process, thereby improving product performance.

[0113] In this embodiment, the optimal limit feature size is selected from multiple limit feature sizes that are compatible with the current spacing according to the preset filtering rules. The preset filtering rules include a first type of rule, which is that in the conflict direction, the selected limit feature size is less than or equal to the feature size of the graphic in the conflict graphic group 102.

[0114] If the feature size of the pattern in the conflict pattern group 102 is adjusted to the optimized feature size according to the first type of rule, the feature size of the pattern in the conflict pattern group 102 will not increase, thereby reducing the probability of adding other conflict pattern groups 102. Moreover, it is beneficial to reduce the probability of the structure formed after the pattern in the conflict pattern group 102 is transferred to the wafer and bridging or merging with another adjacent structure.

[0115] It should be noted that, in this embodiment, the pattern 101 of the target layout 100 to be optimized includes a hole pattern. The hole pattern is used to form through holes or contact holes. The feature size of the hole pattern is limited by the associated layers located at its top and bottom. The feature size of the hole pattern is usually designed based on the feature size of the associated layers. Therefore, by filtering based on the first type of rule, the probability of bridging between associated layers can be avoided or reduced. For example, taking a through hole pattern as an example, the associated layers are the metal layers located at the top and bottom of the through hole interconnect structure, respectively.

[0116] In this embodiment, the preset filtering rules also include a second type of rule, and the first type of rule has a higher priority than the second type of rule. The second type of rule is: the selected limit feature size is used to maximize the area of ​​the corresponding graphic after the graphic in the conflict graphic group 102 is adjusted to the optimized feature size.

[0117] It should be noted that the pattern 101 of the target layout 100 to be optimized includes hole patterns, which are used to form through holes or contact holes. Therefore, the selected limit feature size is used to maximize the corresponding pattern area of ​​the pattern in the conflict pattern group 102 after it is adjusted to the optimized feature size, which is beneficial to reduce the resistance of the structure formed after the pattern in the conflict pattern group 102 is transferred to the wafer.

[0118] In this embodiment, the preset screening rules also include a third type of rule, and the second type of rule has a higher priority than the third type of rule. The third type of rule is: the selected limit feature size is used to minimize the corresponding process change bandwidth of the pattern in the conflict pattern group 102 after it is adjusted to the optimized feature size. This indicates that the optimized pattern in the conflict pattern group 102 has a higher tolerance for fluctuations in the photolithography process after it is adjusted to the optimized feature size, which is beneficial to improving the performance of the actual product.

[0119] It should be noted that, in other embodiments, any one of the multiple limiting feature sizes that are adapted to the current spacing can be arbitrarily selected as the optimized feature size of the graphics in the conflicting graphic group.

[0120] In this embodiment, when there is a graphic shared by multiple conflict graphic groups 102, the graphic shared by multiple conflict graphic groups 102 is regarded as a common conflict graphic. Therefore, in the step of obtaining the optimized target layout 100, the feature size of the common conflict graphic is adjusted to the minimum value among multiple optimized feature sizes, wherein the multiple optimized feature sizes correspond one-to-one with the multiple conflict graphic groups 102 to which the common conflict graphic belongs.

[0121] It should be noted that when adjusting the feature size of the graphics in the conflict graphic group 102 to the optimized feature size, each graphic in each conflict graphic group 102 is configured with an optimized feature size. Since a common conflict graphic is a graphic shared by multiple conflict graphic groups 102, it has multiple optimized feature sizes depending on the number of conflict graphic groups 102 to which it belongs. Therefore, it is necessary to select one of the multiple optimized feature sizes as the final optimized feature size.

[0122] Meanwhile, in order to take into account all conflict graphic groups 102, the feature size of the common conflict graphic is adjusted to the minimum value among multiple optimized feature sizes, so that the multiple conflict graphic groups 102 to which the common conflict graphic belongs can meet the design rules after feature size optimization, and thus the optimized target layout 100 can meet the actual process requirements.

[0123] In this embodiment, we continue to refer to Figure 2 After obtaining the optimized target layout 100, the process further includes: performing step S4 to check the design rules of multiple sub-layouts, where the multiple sub-layouts include the optimized target layout 100.

[0124] It should be noted that by performing design rule checks on the optimized target layout 100, the probability of graphics that do not meet the design rules in the optimized target layout 100 can be reduced. This ensures that all graphics 102 in the final optimized target layout 100 meet the design rules, thereby increasing the probability that the optimized target layout 100 can meet the process requirements.

[0125] In addition, by performing design rule checks, data such as the characteristic size range and minimum spacing value of graphics in each sub-layout can be obtained, which can be used as reference data in subsequent optical proximity correction operations.

[0126] Reference Figure 8 After passing the design rule check, the final splitting result is output.

[0127] Accordingly, embodiments of the present invention also provide a layout optimization system. Figure 10 This is a functional block diagram of an embodiment of the layout optimization system of the present invention.

[0128] refer to Figure 10 and in conjunction with references Figures 3 to 9 The layout optimization system of the present invention includes: a first layout acquisition module 500, used to acquire a target layout 100 to be optimized, the target layout 100 including multiple graphics 101; a conflict graphic group acquisition module 501, used to acquire conflict graphic groups 102 in the target layout 100 that do not conform to the layout parameter rules, the layout parameter rules including spacing rules or pitch rules; and an adjustment module 502, used to shrink the feature size of the graphics in the conflict graphic group 102 in the conflict direction within the photolithography limit process window, so as to adjust it to the optimized feature size, to obtain the optimized target layout 103.

[0129] The first layout acquisition module 500 acquires the target layout 100 to be optimized, providing a technological basis for the layout optimization steps of the target layout 100.

[0130] In this embodiment, the graphic of the target layout 100 is a two-dimensional graphic. The feature size direction of the two-dimensional graphic includes the X direction and the Y direction, and the X direction and the Y direction are perpendicular to each other.

[0131] As one embodiment, the pattern 101 of the target layout 100 to be optimized includes a hole pattern. The hole pattern includes a through-hole pattern or a contact hole pattern. As an example, the hole pattern is a through-hole pattern.

[0132] It should be noted that in other embodiments, the target layout to be optimized may be other types of layout graphics, which are not limited here.

[0133] In this embodiment, the first layout acquisition module 500 includes: an original layout acquisition unit (not shown), used to provide an original layout 200, the original layout 200 including multiple original design graphics 201 (such as... Figure 3 (As shown); the splitting unit (not shown in the figure) is used to split the original layout 200 into multiple sub-layouts according to the layout splitting restriction rules, so that each original design graphic 201 is set on a different sub-layout (e.g., Figure 4 (As shown); Select a cell (not shown in the figure) to select sub-layouts that do not meet the layout splitting constraint rules as the target layout 100 to be optimized (e.g., Figure 5 (As shown).

[0134] In this embodiment, the original design pattern 201 is transferred to the wafer using multi-mask technology; therefore, the number of sub-patterns is greater than or equal to two. It should be noted that the number of sub-patterns is determined based on the actual situation. For example, the number of sub-patterns can be two, three, or four. Figure 4As shown, as an example, there are three sub-plots, for example, the first sub-plot M1, the second sub-plot M2, and the third sub-plot M3.

[0135] As an example, pattern 101 in target layout 100 is a through-hole pattern; therefore, original layout 200 is a through-hole layout, and original design pattern 201 is a through-hole design pattern. In other embodiments, based on actual process requirements, original design pattern 201 can also be used to form other types of structures such as contact holes.

[0136] The splitting unit splits the original layout 200 into multiple sub-layouts based on the process capabilities specified in the design rules, thereby distributing the original design graphic 201 on different photomasks.

[0137] Specifically, the layout splitting restriction rules include: the spacing between adjacent original design graphics 201 in the same sub-layout must meet the minimum spacing requirement.

[0138] The conflict graphic group acquisition module 501 acquires the conflict graphic group 102 in the target layout 100 that does not conform to the layout parameter rules.

[0139] It should be noted that when optimizing the layout, either spacing rules or pitch rules can be selected based on the actual situation. As an example, the layout parameter rules can be spacing rules.

[0140] By obtaining the conflicting graphic group 102 in the target layout 100 that does not conform to the layout parameter rules, in the layout optimization step, only the feature size of the conflicting graphic group 102 needs to be adjusted, which reduces the need to redraw the layout and thus improves work efficiency.

[0141] It should also be noted that, Figure 6 A conflict graphic group 102 is illustrated. In other embodiments, multiple conflict graphic groups may appear in the same target layout.

[0142] Furthermore, when there are multiple conflicting graphic groups in the target map, the multiple conflicting graphic groups can be independent of each other, or any two conflicting graphic groups can share a single graphic.

[0143] In this embodiment, when there is a graphic that is shared by multiple conflicting graphic groups 102, the graphic shared by multiple conflicting graphic groups 102 is regarded as a common conflicting graphic.

[0144] Reference Figures 6 to 7 In this embodiment, the adjustment module 502 is used to shrink the feature size of each graphic in the conflict graphic group 102 in the conflict direction.

[0145] like Figure 7 As shown, Figure 7 The dashed outline in the figure represents the initial outline of the figures in the conflict figure group 102 before shrinking. By shrinking the feature size of the figures in the X direction, the spacing between the figures in the conflict figure group 102 is increased.

[0146] In this embodiment, the adjustment module 502 includes: an optimized feature size acquisition unit (not shown), used to acquire an optimized feature size in the conflict direction of the graphics in the conflict graphic group 102 based on the preset correspondence between the spacing of the graphics in the photolithography limit process window and the limit feature size, and the current spacing of the graphics in the conflict graphic group 102; and a feature size adjustment unit (not shown), used to adjust the feature size of the graphics in the conflict graphic group 102 in the conflict direction based on the optimized feature size.

[0147] It should be noted that in the preset correspondence, the limit feature size refers to the design size of the graphic.

[0148] Specifically, the optimized feature size acquisition unit is used to acquire the extreme process reference data within the photolithography extreme process window. The extreme process reference data includes the extreme feature size corresponding to the pattern under different spacing conditions. It is also used to acquire the optimized feature size of the pattern in the conflict pattern group 102 in the conflict direction based on the extreme process reference data and the current spacing of the patterns in the conflict pattern group 102.

[0149] In this embodiment, the graphic of the target layout 100 is a two-dimensional graphic. The feature size direction of the two-dimensional graphic includes the X direction and the Y direction, and the X direction and the Y direction are perpendicular to each other. Therefore, in the preset correspondence between the spacing and the limit feature size, the spacing is a combination of spacing, and the spacing combination includes the spacing in the X direction and the spacing in the Y direction. The limit feature size is a combination of limit feature sizes, and the limit feature size combination includes the limit feature size in the X direction and the limit feature size in the Y direction.

[0150] The preset correspondence includes four-dimensional variables: X-direction spacing, Y-direction spacing, X-direction limit feature size, and Y-direction limit feature size. Once the X-direction spacing and Y-direction spacing of the graphics in the conflict graphic group 102 are determined, the acceptable limit feature size of the graphics in both directions can be obtained simultaneously. Therefore, based on the spacing of the graphics in the conflict graphic group 102 in the conflict direction, the acceptable limit feature size in the conflict direction can be obtained accurately and quickly, thereby improving the efficiency and accuracy of obtaining the optimized feature size.

[0151] As an example, reference Figure 9The extreme process reference data within the photolithography extreme process window is a tabular database. In this database, each row represents a different X-direction spacing, each column represents a different Y-direction spacing, and each spacing combination corresponds to a specific extreme feature size combination.

[0152] It should be noted that, since the spacing combination includes spacing in the X direction and spacing in the Y direction, the tabular database includes the limiting feature dimensions of the graphic under different spacing conditions in different directions, and the limiting feature dimensions include the limiting feature dimensions in different directions.

[0153] Understandable, Figure 9 The illustrated tabular database is merely one specific representation of the preset correspondence, but the representation of the preset correspondence is not limited to a tabular database. For example, in other embodiments, the preset correspondence between the spacing of patterns within the lithography limit process window and the limit feature size can also be obtained by building a model.

[0154] In this embodiment, the method for obtaining the preset correspondence between the spacing of patterns and the limiting feature size within the lithography limit process window includes: using an optical proximity correction model to obtain the process variation bandwidth of test patterns of each lithographic feature size under different spacings in the feature size direction, wherein multiple test patterns have different feature sizes in the feature size direction, and the test patterns of each feature size have different spacings, and the test patterns include the pattern 101 of the target layout 100; based on the lithographic feature size corresponding to the process variation bandwidth that satisfies the process variation bandwidth threshold condition, the preset correspondence between the spacing of patterns and the lithographic feature size within the lithography limit process window is obtained, and each lithographic feature size has a corresponding process variation bandwidth threshold condition; based on the preset correspondence between the spacing of patterns and the lithographic feature size within the lithography limit process window, and the etching deviation, the preset correspondence between the spacing of patterns and the limiting feature size within the lithography limit process window is obtained.

[0155] Etching deviation refers to the difference between the feature size after photolithography and the feature size after etching.

[0156] It should be noted that the method in this embodiment of the invention is used to optimize the pattern on the layout. The process variation bandwidth is the result of the pattern after photolithography. In the preset correspondence, the limit feature size refers to the design size of the pattern. The design size of the pattern on the layout and the feature size after etching can be regarded as equal. Therefore, after obtaining the preset correspondence between the spacing of the pattern in the photolithography limit process window and the feature size after photolithography, size compensation is performed based on the etching deviation to obtain the design size.

[0157] In this embodiment, each post-lithography feature size has a corresponding process variation bandwidth threshold condition, that is, the process variation bandwidth threshold condition corresponds one-to-one with the post-lithography feature size range.

[0158] Specifically, the post-lithographic feature size of the test pattern is divided into multiple post-lithographic feature size intervals, and corresponding process variation bandwidth threshold conditions are configured for different post-lithographic feature size intervals.

[0159] In this embodiment, the process variation bandwidth threshold condition corresponding to each post-lithography feature size is [Pvband]. min Pvband Threshold ], where Pvband min Pvband is the minimum acceptable process variation bandwidth corresponding to the minimum value within the post-lithographic feature size range to which the post-lithographic feature size belongs. Threshold The maximum acceptable process variation bandwidth corresponds to the maximum value in the feature size range after photolithography.

[0160] It should be noted that the process variation bandwidth threshold condition is a process variation bandwidth range, which is beneficial for accommodating graphics within a certain feature size range, so that the screening conditions are not too strict. This makes it easy to obtain feature sizes and their corresponding spacings that meet the process variation bandwidth threshold condition from a large amount of collected data.

[0161] In this embodiment, the upper bound of the process variation bandwidth threshold condition is determined by the formula Pvband. Threshold =Pvband min +a*CD ADI We obtain, among which, CD ADI is the maximum value in the feature size range after photolithography, and 'a' is a constant coefficient with a value ranging from 0.05 to 0.1.

[0162] In this embodiment, in the preset correspondence between spacing and limit feature size, each spacing corresponds to multiple limit feature sizes; accordingly, in the step of obtaining the limit feature size that matches the current spacing as the optimized feature size of the graphic in the conflict graphic group 102 in the conflict direction, one limit feature size is selected from the many limit feature sizes that match the current spacing as the optimized feature size of the graphic in the conflict graphic group 102 in the conflict direction.

[0163] It should be noted that in the preset correspondence between spacing and limit feature size, each spacing corresponds to multiple limit feature sizes, which improves the flexibility and diversity of optimizing the feature size of the graphics in the conflict graphic group 102, and can provide more options for adjusting the layout of different process nodes.

[0164] Specifically, the adjustment module 502 is also used to select the best limit feature size from a plurality of limit feature sizes that are adapted to the current spacing, as the optimized feature size of the graphics in the conflict graphic group 102. This helps to reduce the impact of fluctuations in process parameters on the actual process, thereby improving the performance of the product.

[0165] In this embodiment, the adjustment module 502 is used to select the best limit feature size from a plurality of limit feature sizes that are compatible with the current spacing according to a preset filtering rule. The preset filtering rule includes a first type of rule, which is: in the conflict direction, the selected limit feature size is less than or equal to the feature size of the graphic in the conflict graphic group 102.

[0166] If the feature size of the pattern in the conflict pattern group 102 is adjusted to the optimized feature size after the screening according to the first type of rule, the feature size of the pattern in the conflict pattern group 102 will not increase, thereby reducing the probability of adding other conflict pattern groups. Moreover, it is beneficial to reduce the probability of the structure formed after the pattern in the conflict pattern group 102 is transferred to the wafer bridging or merging with another adjacent structure.

[0167] It should be noted that, in this embodiment, the pattern 101 of the target layout 100 to be optimized includes a hole pattern. The hole pattern is used to form through holes or contact holes. The feature size of the hole pattern is limited by the associated layers located at its top and bottom. The feature size of the hole pattern is usually designed based on the feature size of the associated layers. Therefore, by filtering based on the first type of rule, the probability of bridging between associated layers can be avoided or reduced. For example, taking a through hole pattern as an example, the associated layers are the metal layers located at the top and bottom of the through hole interconnect structure, respectively.

[0168] In this embodiment, the preset filtering rules also include a second type of rule, and the first type of rule has a higher priority than the second type of rule. The second type of rule is: the selected limit feature size is used to maximize the area of ​​the corresponding graphic after the graphic in the conflict graphic group 102 is adjusted to the optimized feature size.

[0169] It should be noted that the pattern 101 of the target layout 100 to be optimized includes hole patterns, which are used to form through holes or contact holes. Therefore, the selected limit feature size is used to maximize the corresponding pattern area of ​​the pattern in the conflict pattern group 102 after it is adjusted to the optimized feature size, which is beneficial to reduce the resistance of the structure formed after the pattern in the conflict pattern group 102 is transferred to the wafer.

[0170] In this embodiment, the preset screening rules also include a third type of rule, and the second type of rule has a higher priority than the third type of rule. The third type of rule is: the selected limit feature size is used to minimize the corresponding process change bandwidth of the pattern in the conflict pattern group 102 after it is adjusted to the optimized feature size. This indicates that the optimized pattern in the conflict pattern group 102 has a higher tolerance for fluctuations in the photolithography process after it is adjusted to the optimized feature size, which is beneficial to improving the performance of the actual product.

[0171] It should be noted that, in other embodiments, the adjustment module may also arbitrarily select one of the multiple limit feature sizes that are adapted to the current spacing as the optimized feature size of the graphics in the conflicting graphic group.

[0172] In this embodiment, when there is a graphic shared by multiple conflict graphic groups 102, the graphic shared by multiple conflict graphic groups 102 is regarded as a common conflict graphic. Therefore, in the step of obtaining the optimized target layout 100, the feature size of the common conflict graphic is adjusted to the minimum value among multiple optimized feature sizes, wherein the multiple optimized feature sizes correspond one-to-one with the multiple conflict graphic groups 102 to which the common conflict graphic belongs.

[0173] It should be noted that when adjusting the feature size of the graphics in the conflict graphic group to the optimized feature size, each graphic in each conflict graphic group 102 is configured with an optimized feature size. Since the common conflict graphic is a graphic shared by multiple conflict graphic groups 102, it has multiple optimized feature sizes depending on the number of conflict graphic groups 102 to which it belongs. Therefore, it is necessary to select one of the multiple optimized feature sizes as the final optimized feature size.

[0174] Meanwhile, in order to take into account all conflict graphic groups 102, the feature size of the common conflict graphic is adjusted to the minimum value among multiple optimized feature sizes, so that the multiple conflict graphic groups 102 to which the common conflict graphic belongs can meet the design rules after feature size optimization, and thus the optimized target layout 100 can meet the actual process requirements.

[0175] The layout optimization system of the present invention further includes: an inspection module 503, used to perform design rule checks on multiple sub-layouts, wherein the multiple sub-layouts include the optimized target layout 100.

[0176] It should be noted that performing design rule checks on the optimized target layout 100 helps reduce the probability of graphics that do not meet the design rules appearing in the optimized target layout 100, and can ensure that all graphics 102 in the final optimized target layout 100 meet the design rules, thereby increasing the probability that the optimized target layout 100 can meet the process requirements.

[0177] In addition, by performing design rule checks, data such as the characteristic size range and minimum spacing value of graphics in each sub-layout can be obtained, which can be used as reference data in subsequent optical proximity correction operations.

[0178] Reference Figure 8 After passing the design rule check, the final splitting result is output.

[0179] It should be noted that the layout optimization system in the embodiments of the present invention can be used to execute the layout optimization method of the foregoing embodiments, or other optimization systems can be used to execute the layout optimization method of the foregoing embodiments. For a detailed description of the layout optimization system in the embodiments of the present invention, please refer to the relevant records of the layout optimization method of the foregoing embodiments.

[0180] Figure 11 This is a hardware structure diagram of an embodiment of the electronic device provided by the present invention.

[0181] This invention also provides an electronic device, including at least one memory 03 and at least one processor 01. The memory 03 stores one or more computer instructions, wherein the one or more computer instructions are executed by the processor 01 to implement the layout optimization method of any embodiment of this invention.

[0182] An optional hardware structure for the electronic device provided in this embodiment of the invention can be as follows: Figure 11 As shown, it includes: at least one processor 01, at least one communication interface 02, at least one memory 03, and at least one communication bus 04.

[0183] In this embodiment, the number of processor 01, communication interface 02, memory 03, and communication bus 04 is at least one, and processor 01, communication interface 02, and memory 03 communicate with each other through communication bus 04.

[0184] Communication interface 02 can be an interface for a communication module used for network communication, such as the interface of a GSM module.

[0185] Processor 01 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the layout optimization method of the embodiments of the present invention.

[0186] Memory 03 may include high-speed RAM memory, and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0187] The memory 03 stores one or more computer instructions, which are executed by the processor 01 to implement the layout optimization method of any embodiment of the present invention.

[0188] It should be noted that the above-described implementing electronic device may also include other devices (not shown) that may not be essential to understanding the content disclosed in the embodiments of the present invention; given that these other devices may not be essential to understanding the content disclosed in the embodiments of the present invention, the embodiments of the present invention will not describe them one by one.

[0189] This invention also provides a computer program product, including computer instructions, which, when executed by a processor, are used to implement the layout optimization method of any embodiment of this invention.

[0190] This invention also provides a storage medium storing one or more computer instructions for implementing the layout optimization method of any embodiment of this invention.

[0191] The embodiments of the present invention described above are combinations of elements and features of the present invention. Unless otherwise stated, elements or features may be considered optional. Individual elements or features may be practiced without combination with other elements or features. Furthermore, embodiments of the present invention may be constructed by combining some elements and / or features. The order of operations described in the embodiments of the present invention may be rearranged. Some constructions of any embodiment may be included in another embodiment and may be replaced by corresponding constructions of another embodiment. It will be apparent to those skilled in the art that claims in the appended claims that are not explicitly referenced in each other may be combined to form embodiments of the present invention, or may be incorporated as new claims in amendments made after the filing of this application.

[0192] Embodiments of the present invention can be implemented by various means, such as hardware, firmware, software, or combinations thereof. In a hardware configuration, the method according to an exemplary embodiment of the present invention can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, etc.

[0193] In firmware or software configuration, embodiments of the present invention can be implemented in the form of modules, processes, functions, etc. Software code can be stored in a memory unit and executed by a processor. The memory unit is located inside or outside the processor and can send data to and receive data from the processor via various known means.

[0194] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A layout optimization method, characterized in that, include: Obtain the target layout to be optimized, which includes multiple graphics; Obtain conflicting graphic groups in the target layout that do not conform to the layout parameter rules, wherein the layout parameter rules include spacing rules or pitch rules; Within the photolithography limit process window, the feature size of the pattern in the conflict pattern group in the conflict direction is shrunk to adjust to the optimized feature size, thus obtaining the optimized target layout.

2. The layout optimization method as described in claim 1, characterized in that, In the step of obtaining conflicting graphic groups that do not conform to the layout parameter rules in the target layout, when there are graphics shared by multiple conflicting graphic groups, the graphics shared by multiple conflicting graphic groups are regarded as common conflicting graphics. In the step of obtaining the optimized target layout, the feature size of the common conflict graphic is adjusted to the minimum value among multiple optimized feature sizes, wherein the multiple optimized feature sizes correspond one-to-one with the multiple conflict graphic groups to which the common conflict graphic belongs.

3. The layout optimization method as described in claim 1, characterized in that, The step of shrinking the feature size of the pattern in the conflict direction within the photolithography limit process window includes: Based on the preset correspondence between the spacing of the patterns within the photolithography limit process window and the limit feature size, and the current spacing of the patterns in the conflict pattern group, the limit feature size that matches the current spacing is obtained as the optimized feature size of the patterns in the conflict pattern group in the conflict direction. Based on the optimized feature size, the feature size of the graphics in the conflict graphic group is adjusted in the conflict direction.

4. The layout optimization method as described in claim 3, characterized in that, Based on the preset correspondence between the spacing of patterns within the photolithography limit process window and the limit feature size, and the current spacing of patterns in the conflicting pattern group, the step of obtaining the limit feature size adapted to the current spacing as the optimized feature size of the patterns in the conflicting pattern group in the conflicting pattern direction includes: Obtain the extreme process reference data within the photolithography extreme process window, the extreme process reference data including the extreme feature dimensions corresponding to the pattern under different spacing conditions; Based on the extreme process reference data and the current spacing of the graphics in the conflicting graphic group, the optimized feature size of the graphics in the conflicting graphic group is obtained.

5. The layout optimization method as described in claim 3, characterized in that, In the preset correspondence between the spacing and the limit feature size, each spacing corresponds to multiple limit feature sizes; In the step of obtaining the limiting feature size that matches the current spacing as the optimized feature size of the graphic in the conflict graphic group in the conflict direction, one limiting feature size is selected from a plurality of limiting feature sizes that match the current spacing as the optimized feature size of the graphic in the conflict graphic group in the conflict direction.

6. The layout optimization method as described in claim 5, characterized in that, In the step of obtaining the limiting feature size that matches the current spacing as the optimized feature size of the graphic in the conflict graphic group in the conflict direction, the best limiting feature size is selected from multiple limiting feature sizes that match the current spacing as the optimized feature size of the graphic in the conflict graphic group.

7. The layout optimization method as described in claim 6, characterized in that, According to a preset filtering rule, the optimal limit feature size is selected from a plurality of limit feature sizes that are compatible with the current spacing. The preset filtering rule includes a first type of rule, which is that in the conflict direction, the selected limit feature size is less than or equal to the feature size of the graphic in the conflict graphic group.

8. The layout optimization method as described in claim 7, characterized in that, The preset filtering rules also include a second type of rules, and the first type of rules have a higher priority than the second type of rules. The second type of rules is: the selected limit feature size is used to maximize the area of ​​the corresponding graphic after the graphic in the conflict graphic group is adjusted to the optimized feature size.

9. The layout optimization method as described in claim 8, characterized in that, The preset filtering rules also include a third type of rule, and the second type of rule has a higher priority than the third type of rule; the third type of rule is: the selected limit feature size is used to minimize the corresponding process change bandwidth of the graphics in the conflicting graphic group after the graphics are adjusted to the optimized feature size.

10. The layout optimization method as described in claim 3, characterized in that, The target layout is a two-dimensional graphic, and the characteristic dimensions of the two-dimensional graphic include the X direction and the Y direction, and the X direction and the Y direction are perpendicular to each other; In the preset correspondence between the spacing and the limit feature size, the spacing is a combination of spacings, and the combination of spacings includes the spacing in the X direction and the spacing in the Y direction. The limit feature size is a combination of limit feature sizes, and the combination of limit feature sizes includes the limit feature size in the X direction and the limit feature size in the Y direction.

11. The layout optimization method according to any one of claims 1 to 10, characterized in that, The methods for obtaining the preset correspondence between the spacing of the patterns within the photolithography limit process window and the limit feature size include: An optical proximity correction model is used to obtain the process variation bandwidth of test patterns of each lithographic feature size in the feature size direction at different spacings. The test patterns have different feature sizes in the feature size direction, and the test patterns of each feature size have different spacings. The test patterns include the pattern of the target layout. Based on the post-lithographic feature size corresponding to the process variation bandwidth that satisfies the process variation bandwidth threshold condition, the preset correspondence between the spacing of the pattern in the photolithography limit process window and the post-lithography feature size is obtained, and each post-lithography feature size has a corresponding process variation bandwidth threshold condition. Based on the preset correspondence between the spacing of the patterns within the photolithography limit process window and the feature size after photolithography, as well as the etching deviation, the preset correspondence between the spacing of the patterns within the photolithography limit process window and the limit feature size is obtained.

12. The layout optimization method as described in claim 11, characterized in that, The bandwidth threshold condition for the process variation corresponding to each post-lithography feature size is [Pvband] min Pvband Threshold ], where Pvband min Pvband is the minimum acceptable process variation bandwidth corresponding to the minimum value within the post-lithographic feature size range to which the post-lithographic feature size belongs. Threshold The maximum acceptable process variation bandwidth corresponds to the maximum value in the feature size range after photolithography.

13. The layout optimization method as described in claim 12, characterized in that, The upper bound of the bandwidth threshold condition for process variation is given by the formula Pvband. Threshold =Pvband min +a*CD ADI We obtain, among which, CD ADI is the maximum value in the feature size range after photolithography, and 'a' is a constant coefficient with a value ranging from 0.05 to 0.

1.

14. The layout optimization method according to any one of claims 1 to 10, characterized in that, The steps for obtaining the target layout to be optimized include: providing an original layout, which includes multiple original design graphics; According to the layout splitting restriction rules, the original layout is split into multiple sub-layouts so that each original design graphic is set on a different sub-layout; Sub-plots that do not meet the plot splitting restriction rules are selected as target plots to be optimized.

15. The layout optimization method as described in claim 14, characterized in that, The layout splitting restriction rules include: the spacing between adjacent original design graphics in the same sub-layout must meet the minimum spacing requirement.

16. The layout optimization method as described in claim 14, characterized in that, After obtaining the optimized target layout, the method further includes: performing design rule checks on multiple sub-layouts, wherein the multiple sub-layouts include the optimized target layout.

17. The layout optimization method according to any one of claims 1 to 10, characterized in that, In the step of obtaining the target layout to be optimized, the pattern of the target layout to be optimized includes a hole pattern, which is used to form through holes or contact holes.

18. A layout optimization system, characterized in that, include: The first map acquisition module is used to acquire the target map to be optimized, the target map including multiple graphics; The conflict graphic group acquisition module is used to acquire conflict graphic groups in the target layout that do not conform to the layout parameter rules, the layout parameter rules including spacing rules or pitch rules. The adjustment module is used to shrink the feature size of the pattern in the conflict direction in the conflict pattern group within the photolithography limit process window, so as to adjust it to the optimized feature size and obtain the optimized target layout.

19. An electronic device, characterized in that, It includes at least one memory and at least one processor, the memory storing one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the layout optimization method as described in any one of claims 1 to 17.

20. A computer program product, characterized in that, It includes computer instructions, which, when executed by a processor, are used to implement the layout optimization method as described in any one of claims 1 to 17.

21. A storage medium, characterized in that, The storage medium stores one or more computer instructions, which are used to implement the layout optimization method as described in any one of claims 1 to 17.

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