Control circuit board, electronic device, and control method for circuit board

Abstract

The application discloses a control circuit board, an electronic device and a control method of the circuit board. The control circuit board comprises a relay, a field programmable gate array (FPGA) chip and a lock control circuit. The relay is connected to a relay power supply through a switch circuit. The FPGA chip is connected to a working power supply and the relay. The lock control circuit is connected to the working power supply, the switch circuit and the FPGA chip. In response to abnormal working of the working power supply or the FPGA chip, the lock control circuit controls the switch circuit to be disconnected, so that the relay is in a locked state. According to the scheme, the relay lock control is realized through joint control of multiple signals, such as a working power supply abnormal signal and an FPGA chip abnormal signal, the relay misoperation is effectively prevented, and the reliability of the circuit is improved. The relay lock is realized by cutting off the power supply circuit of the relay power supply to the relay, the problem of unstable lock caused by internal faults or external interference of the relay is avoided, and the stability of the circuit is improved.

Description

Technical Field

[0001] This application relates to the field of electronic circuits, specifically to control circuit boards, electronic devices, and control methods for circuit boards. Background Technology

[0002] As a key component in electrical control systems, relays are widely used in power, communication, new energy vehicles and other fields. In order to ensure the safety of circuits and equipment, prevent misoperation and improve system stability, specific circuit designs are required to enable relays to lock out under specific conditions and keep the circuit connected or disconnected.

[0003] Existing relay interlocking control methods mainly control the on / off state of the relay switch directly, lacking mechanisms such as logic judgment and feedback control. They cannot cope with the problem of relay mis-triggering under various conditions. Moreover, once the relay misoperates, the system often cannot detect and correct it in time, thus affecting the safety and reliability of the circuit. Summary of the Invention

[0004] This application provides at least one control circuit board, electronic device, and control method for the circuit board.

[0005] This application provides a control circuit board, which includes: a relay connected to a relay power supply via a switching circuit; a field programmable gate array (FPGA) chip connected to the operating power supply and the relay; and a latching control circuit connected to the operating power supply, the switching circuit, and the FPGA chip. The latching control circuit is used to control the switching circuit to disconnect in response to an abnormal operation of the operating power supply or the FPGA chip, so that the relay is in a latched state.

[0006] In the above scheme, the interlocking control circuit disconnects the switch circuit when the power supply or FPGA chip malfunctions, thereby cutting off the power supply circuit from the relay to the relay and putting the relay in a locked state. This scheme achieves relay interlocking control through the combined control of multiple signals, such as power supply malfunction signals and FPGA chip malfunction signals, effectively preventing relay malfunction and improving circuit reliability. By cutting off the power supply circuit from the relay to the relay, compared to directly controlling the relay switch to achieve interlocking, it avoids interlocking instability caused by internal relay faults or external interference, thus enhancing circuit stability.

[0007] In some embodiments, the switching circuit includes a first switch, and a latching control circuit is used to detect whether the working power supply and the FPGA chip are malfunctioning based on the working voltage signal output by the working power supply and the FPGA status signal output by the FPGA chip; the latching control circuit is used to respond to the working voltage signal and the FPGA status signal indicating that at least one of the working power supply or the FPGA chip is malfunctioning, and output a first latching control signal in a first state to control the first switch to open, so that the relay is in a latching state.

[0008] In the above scheme, by real-time detection of the working voltage signal output by the working power supply and the FPGA status signal output by the FPGA chip, abnormalities of the working power supply or FPGA chip can be quickly detected; the on and off states of the first switch are controlled by the state of the first interlock signal, achieving precise control and improving the reliability and safety of the interlock control circuit.

[0009] In some embodiments, the latching control circuit includes: a trigger circuit configured to receive a working voltage signal and an FPGA status signal, and generate a corresponding trigger signal; and a logic control circuit configured to receive the trigger signal and generate a corresponding first latching control signal; wherein the working voltage signal and the FPGA status signal represent at least one of the working power supply or the FPGA chip malfunctioning, and the output first latching control signal is in a first state.

[0010] In the above scheme, the status of the power supply and FPGA chip is monitored in real time through a logic control circuit, and a rapid response is made when an anomaly is detected, causing the relay to enter a lockout state. Through precise logical judgment, normal operation and abnormal conditions can be accurately distinguished, avoiding false lockout under normal conditions, and timely lockout measures can be taken under abnormal conditions. Compared with existing lockout schemes that lack logical judgment mechanisms, this scheme can adapt to a variety of complex fault conditions, improving the robustness and reliability of the system.

[0011] In some embodiments, the logic control circuit is further configured to have a trigger pin for receiving an external trigger signal, and when the trigger pin receives an external trigger signal, a first latching control signal is placed in a first state.

[0012] In the above scheme, by introducing an external trigger signal, the logic control circuit can respond more flexibly to external events or changes in conditions, making the interlocking control circuit of this application applicable to more complex application scenarios, such as automated systems that need to trigger interlocking actions based on external interlocking signals.

[0013] In some embodiments, the switching circuit further includes a second switch, which is connected in series with the first switch between the relay power supply and the relay; the FPGA chip receives the status detection signal of the relay and generates a corresponding second latching control signal, wherein the FPGA chip responds to the status detection signal indicating that the relay is in an abnormal state, and the output second latching control signal is in a first state to control the second switch to open, so that the relay is in a latching state.

[0014] In the above scheme, the relay status is monitored in real time to provide feedback control for the relay's lockout state. By introducing a second switch to form a series circuit with the first switch, when the relay status is abnormal, the second lockout control signal controls the second switch to open, thereby ensuring that the relay is in a lockedout state. Compared with lockout methods that lack feedback control, this scheme can significantly improve the reliability and flexibility of the control circuit board.

[0015] In some embodiments, the trigger circuit includes: a trigger, a first input terminal of which is configured to receive an operating voltage signal, a second input terminal of which is configured to receive an FPGA status signal, and an output terminal of which is configured to output a trigger signal; a first resistor, a first end of which is connected to an external resistor pin of the trigger, and a second end of which is connected to an operating power supply; and a first capacitor, a first end of which is connected to an external capacitor pin of the trigger and ground, and a second end of which is connected to the first end of the first resistor.

[0016] In the above scheme, the trigger adjusts the trigger signal based on the working voltage signal and the FPGA status signal; by adjusting the values ​​of the first resistor and the first capacitor, the trigger hold time of the trigger can be precisely adjusted, which improves the stability and flexibility of the circuit.

[0017] In some embodiments, the hold time of a single triggering is greater than the period of the pulse width square wave signal output by the FPGA chip.

[0018] In the above scheme, by making the hold time of the trigger longer than the period of the pulse width square wave signal output by the FPGA, it can help reduce false triggering caused by signal fluctuations or noise interference, and improve the reliability and anti-interference capability of the circuit.

[0019] In some embodiments, the logic control circuit includes: a logic gate, the logic gate being configured to receive a trigger signal, the trigger pin of the logic gate being configured to receive an external trigger signal, and the output terminal of the logic gate being configured to output a first latching control signal.

[0020] In the above scheme, the state of the first interlocking control signal is determined by the state of the trigger signal and the external trigger signal through the logic operation function of the logic gate, thereby realizing the interlocking control of the relay.

[0021] In some embodiments, the latching control circuit is further configured to: in response to the start-up of the operating power supply, control the switching circuit to disconnect so that the relay is in a latching state.

[0022] In the above solution, this application avoids accidental triggering during the startup initialization phase by placing the relay in a locked state when the working power supply starts and the board is powered on and initialized.

[0023] In some embodiments, this application provides an electronic device that includes a control circuit board as described above.

[0024] This application also provides a control method for a circuit board, the circuit board including a relay, a field-programmable gate array (FPGA) chip, and a latching control circuit; the relay is connected to a relay power supply through a switching circuit, and the FPGA chip is connected to the operating power supply and the relay; the latching control circuit is connected to the operating power supply, the switching circuit, and the FPGA chip respectively; the control method includes: detecting whether the operating power supply or the FPGA chip is malfunctioning through the latching control circuit; and in response to the malfunction of the operating power supply or the FPGA chip, disconnecting the switching circuit to put the relay in a latched state.

[0025] In some embodiments, the step of detecting whether the working power supply or the FPGA chip is malfunctioning through the latching control circuit includes: detecting whether the working power supply or the FPGA chip is malfunctioning based on the working voltage signal output by the working power supply and the FPGA status signal output by the FPGA chip through the latching control circuit.

[0026] The steps of disconnecting the switching circuit to put the relay in a latched state in response to an abnormality in the operating power supply or FPGA chip include: determining that there is an abnormality in the operating power supply or FPGA chip in response to an abnormality in the operating voltage signal and the FPGA status signal indicating that at least one of the operating power supply or FPGA chip is abnormal; controlling the first latching control signal output by the latching control circuit to be in a first state to control the switching circuit to disconnect and put the relay in a latched state.

[0027] In some embodiments, the latching control circuit includes a trigger circuit and a logic control circuit. The trigger circuit is connected to the FPGA chip and the operating power supply; the logic control circuit is connected to the trigger circuit and the switching circuit. Before the step of detecting whether the operating power supply and the FPGA chip are abnormal based on the operating voltage signal output by the operating power supply and the FPGA status signal output by the FPGA chip through the latching control circuit, the circuit further includes: receiving the operating voltage signal and the FPGA status signal through the trigger circuit and generating a corresponding trigger signal; receiving the trigger signal through the logic control circuit and generating a corresponding first latching control signal; wherein, when the operating voltage signal and the FPGA status signal indicate that at least one of the operating power supply or the FPGA chip is abnormal, the first latching control signal is in a first state.

[0028] In some embodiments, the logic control circuit is further configured to have a trigger pin for receiving an external trigger signal; the control method further includes: detecting whether the trigger pin receives an external trigger signal through the logic control circuit; and setting a first latching control signal to a first state in response to the trigger pin receiving an external trigger signal.

[0029] In some embodiments, the control method further includes: receiving a state detection signal of a relay via an FPGA chip and generating a corresponding second latching control signal; in response to the state detection signal indicating an abnormality in the relay, controlling the second latching control signal output by the FPGA chip to be in a first state, so as to control the switch circuit to be disconnected and the relay to be in a latching state.

[0030] In the above scheme, the interlocking control circuit disconnects the switch circuit when the power supply or FPGA chip malfunctions, thereby cutting off the power supply circuit from the relay to the relay and putting the relay in a locked state. This scheme achieves relay interlocking control through the combined control of multiple signals, such as power supply malfunction signals and FPGA chip malfunction signals, effectively preventing relay malfunction and improving circuit reliability. By cutting off the power supply circuit from the relay to the relay, compared to directly controlling the relay switch to achieve interlocking, it avoids interlocking instability caused by internal relay faults or external interference, enhancing the stability of the interlocking circuit.

[0031] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this application. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] in:

[0034] Figure 1 This is a first structural schematic diagram of a control circuit board provided in some embodiments of this application;

[0035] Figure 2 This is a schematic diagram of the second structure of the control circuit board provided in some embodiments of this application;

[0036] Figure 3 This is a third structural schematic diagram of the control circuit board provided in some embodiments of this application;

[0037] Figure 4 These are schematic diagrams of the structure of electronic devices provided in some embodiments of this application.

[0038] Figure 5 This is a first flowchart illustrating a circuit board control method provided in some embodiments of this application;

[0039] Figure 6 This is a second flowchart illustrating a circuit board control method provided in some embodiments of this application;

[0040] Figure 7 This is a third flowchart illustrating a circuit board control method provided in some embodiments of this application;

[0041] Figure 8 This is a fourth flowchart illustrating the circuit board control method provided in some embodiments of this application;

[0042] Figure 9 This is a schematic diagram of the control circuit board process provided in some embodiments of this application. Detailed Implementation

[0043] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, it should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, not all structures. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0044] The terms "first," "second," etc., used in this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0045] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0046] Existing relay interlocking control methods mainly control the on / off state of the relay switch directly, lacking mechanisms such as logic judgment and feedback control. They cannot cope with the problem of relay mis-triggering under various conditions. Moreover, once the relay misoperates, the system often cannot detect and correct it in time, thus affecting the safety and reliability of the circuit.

[0047] Therefore, this application proposes a control circuit board that controls the switching circuit to disconnect when the operating power supply or FPGA chip malfunctions, thereby disconnecting the power supply circuit from the relay power supply and putting the relay in a locked state. This solution achieves relay lockout control through the combined control of multiple signals, such as an abnormal operating power supply signal and an abnormal FPGA chip malfunction signal, effectively preventing relay malfunction and improving circuit reliability. By cutting off the power supply circuit from the relay power supply to the relay, compared to directly controlling the relay switch to achieve lockout, it avoids lockout instability caused by internal relay faults or external interference, enhancing the stability of the lockout circuit.

[0048] Please see Figure 1 , Figure 1 This is a first structural schematic diagram of a control circuit board provided in some embodiments of this application. The control circuit board 100 includes: a relay 10, a switching circuit 20, an FPGA chip 30, and a latching control circuit 40. The relay 10 is connected to a relay power supply 50 through the switching circuit 20; the FPGA chip 30 is connected to a working power supply 60 and the relay 10; the latching control circuit 40 is connected to the working power supply 60, the switching circuit 20, and the FPGA chip 30. The latching control circuit 40 is used to control the switching circuit 20 to disconnect in response to an abnormal operation of the working power supply 60 or the FPGA chip 30, so that the relay 10 is in a latched state.

[0049] Among them, the Field Programmable Gate Array (FPGA) is a very large-scale programmable logic device, which consists of programmable logic resources, programmable interconnect resources, and programmable input / output resources. The FPGA chip 30 is connected to the relay 10 and is mainly used to realize the logic control and signal transmission of the circuit. Through programming, the FPGA chip 30 can control the switching state of the relay 10, thereby realizing the control of the external circuit. Different latching logic can also be set to ensure that the relay 10 can only be activated or closed under specific conditions. The FPGA chip 30 can also monitor the status of the relay 10 in real time to ensure that it is within the normal operating range.

[0050] For example, the control circuit board 100 can be a digital output control board used to provide digital output to control external devices. It typically uses a relay 10 as the output driving element, and controls the external devices by rapidly switching the circuit state inside the relay 10.

[0051] Relay 10 is an electromagnetic switch whose contact state is controlled by the voltage or current of the coil. When the coil voltage or current reaches a certain threshold, the contacts of relay 10 will close or open. Existing relay control methods typically achieve relay on / off switching by controlling the relay coil. However, this method makes the relay susceptible to external signal interference, leading to malfunctions. For example, during the initialization phase of the system when the control circuit board 100 is powered on, due to power instability or circuit component initialization, the level states of each signal interface may experience brief fluctuations and resets. These fluctuations may cause instability in the voltage or current of the relay coil, resulting in malfunctions of its contacts. Alternatively, when the board's power supply 60 malfunctions or the FPGA chip 30 malfunctions, causing abnormal output pulse width square wave signals, the relay may also be falsely triggered.

[0052] This application connects the working power supply 60, the switching circuit 20 and the FPGA chip 30 through the interlocking control circuit 40. When the working power supply 60 or the FPGA chip 30 is abnormal, the interlocking control circuit 40 controls the switching circuit 20 to disconnect, thereby disconnecting the power supply circuit from the relay power supply 50 to the relay 10, so that the relay 10 is in a locked state.

[0053] In the above scheme, the interlocking control circuit 40 controls the switch circuit 20 to disconnect when the working power supply 60 or the FPGA chip 30 malfunctions, thereby disconnecting the power supply circuit from the relay power supply 50 to the relay 10, and putting the relay 10 in a locked state. This scheme achieves interlocking control of the relay 10 through the joint control of multiple signals, such as the working power supply 60 abnormal signal and the FPGA chip 30 abnormal signal, effectively preventing the relay 10 from malfunctioning and thus improving the reliability of the circuit. By cutting off the power supply circuit from the relay power supply 50 to the relay 10 to achieve the interlocking function, compared with directly controlling the on / off state of the relay 10 to achieve interlocking, it avoids the interlocking instability problem caused by internal faults of the relay 10 or external interference, and enhances the stability of the interlocking circuit.

[0054] In some embodiments, the switching circuit 20 includes a first switch 21, and the latching control circuit 40 is used to detect whether the working power supply 60 and the FPGA chip 30 are malfunctioning based on the working voltage signal VCC output by the working power supply 60 and the FPGA chip status signal FPGA_STALL_BS output by the FPGA chip 30. The latching control circuit 40 is used to respond to the working voltage signal VCC and the FPGA chip status signal FPGA_STALL_BS indicating that at least one of the working power supply 60 or the FPGA chip 30 is malfunctioning, and output a first latching control signal in a first state to control the first switch 21 to open, so that the relay 10 is in a latching state.

[0055] In one embodiment, the first switch 21 may include a plurality of switches connected in series (e.g., Figure 3 The first switch Q10 and the second switch Q11 shown are connected via a first voltage divider unit (e.g., Figure 3 R11 and R12 are connected in series. The first terminal of the first switching transistor Q10 is connected to the relay power supply 50; the first terminal of the first voltage divider unit is connected to the first terminal of the first switching transistor Q10, and the voltage divider node of the first voltage divider unit is connected to the control terminal of the first switching transistor Q10; the first terminal of the second switching transistor Q11 is connected to the second terminal of the first voltage divider unit, the second terminal of the second switching transistor Q11 is grounded, and the control terminal of the second switching transistor Q11 can also be connected through the second voltage divider unit (e.g., R11 and R12). Figure 3 R13 and R14 are connected to the latching control circuit 40. Exemplarily, the first switch Q10 and the second switch Q11 can be MOS transistors. Specifically, the first switch Q10 can be a PMOS transistor and the second switch Q11 can be an NMOS transistor. In other embodiments, the first switch 21 can also be a transistor or other semiconductor device, which will not be listed here.

[0056] The FPGA chip status signal FPGA_STALL_BS indicates the status of the fixed-width square wave signal output from the I / O (input / output) pins of the FPGA chip 30. For example, when abnormal situations occur such as the square wave signal pulse width changing beyond the preset range, waveform distortion, or signal loss, the FPGA chip status signal FPGA_STALL_BS indicates an abnormality in the FPGA chip 30. The operating voltage signal VCC reflects the status of the operating power supply 60. When the operating voltage signal VCC is too high, too low, or interrupted, it indicates an abnormality in the operating power supply 60. The relay power supply 50 is coupled to the relay 10 through the first switch 21. The first state refers to the high or low level of the first latching control signal. The opening and closing of the first switch 21 is controlled by the change in the level of the first latching control signal.

[0057] In some application scenarios, taking the FPGA chip 30 malfunction as an example, when the square wave signal output by the FPGA chip 30 is distorted (the waveform becomes sharp, flat, or produces glitches, etc.), the FPGA chip status signal FPGA_STALL_BS indicates that the FPGA chip 30 is malfunctioning. The first latching signal output by the latching control circuit 40 is at a low level, the first switch 21 is open, which makes the power supply circuit from the relay power supply 50 to the relay 10 conduct, and the relay 10 is in a latching state to prevent the relay 10 from being falsely triggered due to the FPGA chip 30 malfunction.

[0058] In the above scheme, by real-time detection of the working voltage signal VCC output by the working power supply 60 and the FPGA chip status signal FPGA_STALL_BS output by the FPGA chip 30, abnormalities of the working power supply 60 and the FPGA chip 30 can be quickly detected; the on and off states of the first switch 21 are controlled by the state of the first interlocking signal, achieving precise control and improving the reliability and safety of the interlocking control circuit 40.

[0059] In some embodiments, please refer to Figure 2 The latching control circuit 40 includes a trigger circuit 41 and a logic control circuit 42. The trigger circuit 41 is configured to receive the operating voltage signal VCC and the FPGA chip status signal FPGA_STALL_BS, and generate a corresponding trigger signal FPGA_NoWork_BS. The logic control circuit 42 is configured to receive the trigger signal FPGA_NoWork_BS and generate a corresponding first latching control signal. The operating voltage signal VCC and the FPGA chip status signal FPGA_STALL_BS indicate that at least one of the operating power supply 60 or the FPGA chip 30 is malfunctioning, and the output first latching control signal is in a first state.

[0060] When the control board is powered on, the power supply 60 outputs the working voltage signal VCC, and the FPGA chip 30 outputs a fixed pulse width square wave signal through the software-set input / output pins. The trigger circuit 41 generates a corresponding trigger signal FPGA_NoWork_BS based on the received input signal. This trigger signal FPGA_NoWork_BS is the result of logical processing of the input signals (i.e., the working voltage signal VCC and the FPGA chip status signal FPGA_STALL_BS), and is used to indicate whether an abnormality is detected in the working power supply 60 or the FPGA chip 30 signal. The logic control circuit 42 uses integrated logic circuits to accurately perform logical judgments and generate the first latching control signal.

[0061] In some application scenarios, when the power supply 60 is normal and the FPGA chip 30 is in normal working condition (i.e., the working voltage signal VCC remains within the normal range, and the FPGA chip status signal FPGA_STALL_BS also indicates that the FPGA chip 30 is working normally), the trigger circuit 41 receives these signals and generates a high-level trigger signal FPGA_NoWork_BS (indicating no abnormality). Upon receiving the normal trigger signal FPGA_NoWork_BS, the logic control circuit 42 generates a high-level first latching control signal, and the first switch 21 is in the on state. In other application scenarios, when the power supply 60 is abnormal (voltage too high, too low, or interrupted, etc.) or the FPGA chip 30 is abnormal (e.g., abnormal square wave signal), the working voltage signal VCC and the FPGA chip status signal FPGA_STALL_BS will change. Upon detecting these changes, the trigger circuit 41 generates a low-level trigger signal FPGA_NoWork_BS, indicating an abnormality. Upon receiving the low-level trigger signal FPGA_NoWork_BS, the logic control circuit 42 immediately generates a low-level first latching control signal, indicating that the relay 10 needs to enter the latching state and immediately disconnects the first switch 21.

[0062] In the above scheme, the logic control circuit 42 monitors the status of the power supply 60 and the FPGA chip 30 in real time, and responds quickly when an anomaly is detected, causing the relay 10 to enter the lockout state. Through precise logical judgment, it can accurately distinguish between normal operation and abnormal conditions, avoiding false lockout under normal conditions, and also taking timely lockout measures under abnormal conditions. Compared with existing lockout schemes that lack logical judgment mechanisms, this scheme can be used for a variety of complex fault conditions, improving the robustness and reliability of the system.

[0063] In some embodiments, the logic control circuit 42 is further configured to have a trigger pin for receiving an external trigger signal BS_RX, and to set a first latching control signal to a first state when the trigger pin receives the external trigger signal BS_RX.

[0064] The external trigger signal BS_RX can be the latching signal sent by the upstream relay 10, specifically an MCU (Microcontroller Unit). The logic control circuit 42 performs logical judgment on the trigger signal NoWork_BS generated by the trigger circuit 41 and the external trigger signal BS_RX. When these two change, such as a change in level, the logic control circuit 42 controls the state of the first latching control signal to change based on this level change.

[0065] In the above scheme, by introducing an external trigger signal BS_RX, the logic control circuit 42 can respond more flexibly to external events or changes in conditions, making the interlocking control circuit 40 of this application applicable to more complex application scenarios, such as automated systems that need to trigger interlocking actions based on external interlocking signals.

[0066] In some embodiments, the switching circuit 20 further includes a second switch 22, which is connected in series with the first switch 21 between the relay power supply 50 and the relay 10. The FPGA chip 30 receives the status detection signal of the relay 10 and generates a corresponding second latching control signal. In response to the status detection signal indicating that the relay 10 is in an abnormal state, the FPGA chip outputs a second latching control signal in a first state to control the second switch 22 to open, so that the relay 10 is in a latched state.

[0067] The status detection signal of relay 10 is a self-test signal of relay 10, which can detect the closed and open states of relay 10. For example, the state of relay 10 can be determined by detecting the voltage across the contacts of relay 10. When relay 10 is closed, the voltage across the contacts should be close to zero. When relay 10 is open, the voltage across the contacts should be equal to the power supply voltage. Alternatively, the state of relay 10 can be determined by measuring the current of relay 10. When relay 10 is closed, a certain current will flow. When relay 10 is open, the current should be zero. The specific detection method is not limited here.

[0068] In some application scenarios, when the FPGA chip 30 receives a relay 10 closing signal from an external device (e.g., an MCU), if the control circuit board 100 is functioning normally (e.g., the power supply 60 and FPGA chip 30 are functioning normally), the first switch 21 is in the ON state. The FPGA chip 30 controls the second switch 22 to close, and after the power supply circuit from the relay power supply 50 to the relay 10 is connected, the FPGA chip 30 outputs a control signal to close the relay 10. The relay 10 performs a self-test and sends a status detection signal to the FPGA chip 30. If the status detection signal indicates that the relay 10 is in an abnormal state and has not closed normally, it means that the relay 10 has not closed according to the relay 10 closing signal issued by the FPGA chip 30. The second latching signal generated by the FPGA chip 30 is in the first state, controlling the second switch 22 to open, thereby disconnecting the power supply circuit from the relay power supply 50 to the relay 10, and the relay 10 is in the latching state.

[0069] In the above scheme, the state of relay 10 is detected in real time to provide feedback control of the latching state of relay 10; by introducing a second switch 22 to form a series circuit with the first switch 21, when the state of relay 10 is abnormal, the second latching control signal controls the second switch 22 to open, thereby ensuring that relay 10 is in the latching state; compared with latching methods that lack feedback control, this scheme can significantly improve the reliability and flexibility of control circuit board 100.

[0070] In some embodiments, please refer to Figure 3 The trigger circuit 41 includes: a trigger U1, a first resistor R21, and a first capacitor C21. The first input terminal 1RD of the trigger U1 is configured to receive the working voltage signal VCC, the second input terminal 1A of the trigger U1 is configured to receive the FPGA chip status signal FPGA_STALL_BS, and the output terminal 1Q of the trigger U1 is configured to output the trigger signal FPGA_NoWork_BS. The third input terminal 1B of the trigger U1 is connected to a resistor (e.g., Figure 3 R23 is connected to the working power supply 60; the first end of the first resistor R21 is connected to the external resistor terminal 1REXT of the trigger U1, and the second end of the first resistor R21 is connected to the working power supply 60; the first end of the first capacitor C21 is connected to the external capacitor terminal 1CEXT of the trigger U1 and ground, and the second end of the first capacitor C21 is connected to the first end of the first resistor R21.

[0071] The trigger U1 can be a monostable trigger, which has a stable state and a metastable state. Under the action of an external pulse, it can flip from a stable state to a metastable state. After being triggered by the edge of the input signal, it generates a stable output signal during the hold time of the trigger. For example, when the working power supply 60 is normal, the working voltage signal VCC is high, and the trigger signal FPGA_NoWork_BS output by the output terminal 1Q of the trigger U1 remains high. When the working power supply 60 is abnormal, the working voltage signal VCC changes from high to low. At the falling edge of the working voltage signal VCC, the trigger U1 enters the metastable state, and the output signal flips to low during the hold time of the trigger. The hold time of the trigger can be set by adjusting the resistance value of the first resistor R21 and the capacitance value of the first capacitor C21.

[0072] In the above scheme, the trigger U1 adjusts the trigger signal FPGA_NoWork_BS based on the working voltage signal VCC and the FPGA chip status signal FPGA_STALL_BS; by adjusting the values ​​of the first resistor R21 and the first capacitor C21, the trigger hold time can be precisely adjusted, which improves the stability and flexibility of the trigger circuit 41.

[0073] In some embodiments, the hold time of a single triggering of trigger U1 is greater than the period of the pulse width square wave signal output by the FPGA chip.

[0074] Since the hold time of a single triggering of trigger U1 is greater than the period of the pulse width square wave signal output by the FPGA chip, trigger U1 will always maintain a high level output when both the power supply 60 and the FPGA chip 30 are working normally, thus ensuring the normal operation of the control circuit board 100.

[0075] In some application scenarios, the pulse width square wave signal output by the FPGA chip 30 received by the second input terminal 1A of the trigger U1 becomes abnormal after three cycles. The trigger signal FPGA_NoWork_BS output by the output terminal 1Q of the trigger U1 remains at a high level for a period of time after the falling edge of the third cycle of the pulse width square wave signal (trigger hold time), and then becomes low.

[0076] In the above scheme, by making the hold time of a single triggering of the trigger U1 longer than the period of the FPGA chip status signal FPGA_STALL_BS, it can help reduce false triggering caused by signal fluctuations or noise interference, and improve the reliability and anti-interference capability of the circuit.

[0077] In some embodiments, please refer to Figure 3The logic control circuit 42 includes: a logic gate 42, the first input terminal of the logic gate 42 is configured to receive a trigger signal FPGA_NoWork_BS, the trigger pin of the logic gate 42 is configured to receive an external trigger signal BS_RX, and the output terminal of the logic gate 42 is configured to output a first latching control signal.

[0078] For example, logic gate 42 can be an AND gate, which has multiple input terminals and one output terminal. It can receive multiple input signals. When all input signals are high, the output signal is high. If any input information is low, its output is low.

[0079] When either the trigger signal FPGA_NoWork_BS or the external trigger signal BS_RX is low, the logic control circuit 42 outputs a low level. To ensure the integrity of the input signal and achieve impedance matching, a resistor can be connected to the input of the logic gate 42.

[0080] In the above scheme, the state of the first interlocking control signal is determined by the logic operation function of logic gate 42 based on the state of the trigger signal FPGA_NoWork_BS and the external trigger signal BS_RX, thereby realizing the interlocking control of relay 10.

[0081] In some embodiments, the latching control circuit is further configured to: in response to the start-up of the operating power supply 60, control the switch circuit to disconnect so that the relay is in a latching state.

[0082] In the above solution, this application avoids accidental triggering during the startup initialization phase by placing the relay in a locked state when the working power supply 60 starts up and the board is powered on and initialized.

[0083] Please see Figure 4 , Figure 4 This is a schematic diagram of the structure of an electronic device provided in some embodiments of this application. The electronic device 1000 includes the control circuit board 100 as described above, which will not be repeated here.

[0084] In the above scheme, the interlocking control circuit disconnects the switch circuit when the power supply or FPGA chip malfunctions, thereby cutting off the power supply circuit from the relay to the relay and putting the relay in a locked state. This scheme achieves relay interlocking control through the combined control of multiple signals, such as power supply malfunction signals and FPGA chip malfunction signals, effectively preventing relay malfunction and improving circuit reliability. By cutting off the power supply circuit from the relay to the relay, compared to directly controlling the relay switch to achieve interlocking, it avoids interlocking instability caused by internal relay faults or external interference, enhancing the stability of the interlocking circuit.

[0085] See Figure 5 , Figure 5 This is a first flowchart illustrating a circuit board control method provided in some embodiments of this application; the circuit board includes a relay, a field-programmable gate array (FPGA) chip, and a latching control circuit; the relay is connected to a relay power supply via a switching circuit, and the FPGA chip is connected to the operating power supply and the relay; the latching control circuit is connected to the operating power supply, the switching circuit, and the FPGA chip respectively; as shown... Figure 5 As shown, the control method includes:

[0086] Step S51: Detect whether the working power supply or FPGA chip is malfunctioning through the interlocking control circuit.

[0087] Step S52: In response to a power supply malfunction or FPGA chip malfunction, disconnect the switching circuit to put the relay in a locked state.

[0088] In some embodiments, step S51 may include the following steps: detecting whether the working power supply or the FPGA chip is abnormal based on the working voltage signal output by the working power supply and the FPGA status signal output by the FPGA chip through the latching control circuit.

[0089] In some embodiments, step S52 may include the following steps: in response to the operating voltage signal and the FPGA status signal characterizing the operating power supply or at least one of the FPGA chip being malfunctioning, determine that there is an abnormality in the operating power supply or the FPGA chip; control the first latching control signal output by the latching control circuit to be in a first state to control the switch circuit to be disconnected, so that the relay is in a latching state.

[0090] See Figure 6 , Figure 6 This is a second flowchart illustrating a circuit board control method provided in some embodiments of this application; the latching control circuit includes a trigger circuit and a logic control circuit, the trigger circuit being connected to the FPGA chip and the power supply; the logic control circuit being connected to the trigger circuit and the switching circuit; as shown... Figure 6 As shown, before the step of detecting whether the working power supply and FPGA chip are abnormal through the interlocking control circuit based on the working voltage signal output by the working power supply and the FPGA status signal output by the FPGA chip, the following steps are also included:

[0091] Step S61: Receive the operating voltage signal and FPGA status signal through the trigger circuit, and generate the corresponding trigger signal.

[0092] Step S62: Receive the trigger signal through the logic control circuit and generate the corresponding first latching control signal.

[0093] When the operating voltage signal and the FPGA status signal indicate that at least one of the operating power supply or the FPGA chip is malfunctioning, the first latching control signal is in the first state.

[0094] See Figure 7 , Figure 7 This is a third flowchart illustrating a circuit board control method provided in some embodiments of this application. In some embodiments, the logic control circuit is further configured to have a trigger pin for receiving external trigger signals, such as... Figure 7 As shown, the control method also includes:

[0095] Step S71: Detect whether the trigger pin receives an external trigger signal through the logic control circuit;

[0096] Step S72: In response to receiving an external trigger signal on the trigger pin, the first latching control signal is set to the first state.

[0097] See Figure 8 , Figure 8 This is a fourth flowchart illustrating a circuit board control method provided in some embodiments of this application, such as... Figure 8 As shown, the control method also includes:

[0098] Step S81: Receive the status detection signal of the relay through the FPGA chip and generate the corresponding second interlocking control signal.

[0099] Step S82: In response to the state detection signal indicating a relay malfunction, the second latching control signal output by the control FPGA chip is in the first state to control the switch circuit to open, so that the relay is in the latching state.

[0100] In some embodiments, see Figure 9 First, the board is powered on. It first checks whether the working power supply 60 is normal. If it is normal, the FPGA chip 30 is started. If it is abnormal, the relay 10 is locked. After the FPGA chip 30 is started, it determines whether the relay 10 is in the locked state. If it is locked, it does not send the relay 10 action signal until the relay 10 lock signal is released. At the same time, after the FPGA chip 30 is started, it loads the preset program and outputs the pulse width square wave signal. If the square wave signal is abnormal, the relay 10 is locked.

[0101] Then, if the square wave signal is normal and the relay 10 is not locked, when the FPGA chip 30 receives both the lock signal of the relay 10 and the closing signal of the external relay 10, it first checks whether the relay 10 is locked. If it is locked, the closing signal of the external relay 10 is ignored; if it is not locked, the power supply closing signal is output first, the relay power supply 50 is started, and then the FPGA chip 30 outputs the closing signal of the relay 10, the relay 10 is energized, and the digital output is realized.

[0102] Finally, relay 10 performs status detection and sends a feedback signal to FPGA chip 30. If FPGA chip 30 determines that relay 10 outputs abnormally, it will lock relay 10.

[0103] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0104] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0105] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0106] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A control circuit board, characterized in that, include: The relay is connected to the relay power supply via a switching circuit; A field-programmable gate array (FPGA) chip is connected to the power supply and the relay. A latching control circuit is connected to the power supply, the switching circuit, and the FPGA chip. The latching control circuit is used to control the switching circuit to disconnect in response to an abnormal operation of the power supply or the FPGA chip, so that the relay is in a latched state.

2. The control circuit board according to claim 1, characterized in that, The switching circuit includes a first switch, and the interlocking control circuit is used to detect whether the working power supply and the FPGA chip are malfunctioning based on the working voltage signal output by the working power supply and the FPGA status signal output by the FPGA chip. The latching control circuit is used to respond to the working voltage signal and the FPGA status signal indicating that at least one of the working power supply or the FPGA chip is malfunctioning. The output first latching control signal is in a first state to control the first switch to open, so that the relay is in a latching state.

3. The control circuit board according to claim 2, characterized in that, The interlocking control circuit includes: The trigger circuit is configured to receive the operating voltage signal and the FPGA status signal, and generate a corresponding trigger signal; A logic control circuit is configured to receive the trigger signal and generate a corresponding first latching control signal; The operating voltage signal and the FPGA status signal indicate that at least one of the operating power supply or the FPGA chip is malfunctioning, and the output first latching control signal is in a first state.

4. The control circuit board according to claim 3, characterized in that, The logic control circuit is further configured to have a trigger pin for receiving an external trigger signal, and when the trigger pin receives the external trigger signal, the first latching control signal is placed in the first state.

5. The control circuit board according to claim 1, characterized in that, The switching circuit further includes a second switch, and the second switch and the first switch are connected in series between the relay power supply and the relay. The FPGA chip receives the status detection signal of the relay and generates a corresponding second latching control signal. In response to the status detection signal indicating that the relay is abnormal, the FPGA chip outputs a second latching control signal in a first state to control the second switch to open, thereby putting the relay in a latching state.

6. The control circuit board according to claim 3, characterized in that, The trigger circuit includes: A trigger, wherein the first input terminal of the trigger is configured to receive the operating voltage signal, the second input terminal of the trigger is configured to receive the FPGA status signal, and the output terminal of the trigger is configured to output the trigger signal; A first resistor, the first end of which is connected to the external resistor pin of the trigger, and the second end of which is connected to the operating power supply; A first capacitor, the first end of which is connected to the external capacitor pin of the trigger and ground, and the second end of which is connected to the first end of the first resistor.

7. The control circuit board according to claim 6, characterized in that, The hold time of a single triggering of the trigger is greater than the period of the pulse width square wave signal output by the FPGA chip.

8. The control circuit board according to claim 4, characterized in that, The logic control circuit includes: A logic gate is configured to receive the trigger signal, the trigger pin of the logic gate is configured to receive the external trigger signal, and the output terminal of the logic gate is configured to output the first latching control signal.

9. The control circuit board according to claim 1, characterized in that, The interlocking control circuit is further configured to: in response to the start-up of the operating power supply, control the switching circuit to disconnect so that the relay is in a interlocked state.

10. An electronic device, characterized in that, The electronic device includes a control circuit board as described in any one of claims 1-9.

11. A control method for a circuit board, characterized in that, The circuit board includes a relay, a field-programmable gate array (FPGA) chip, and a latching control circuit; the relay is connected to a relay power supply via a switching circuit, and the FPGA chip is connected to the operating power supply and the relay; the latching control circuit is connected to the operating power supply, the switching circuit, and the FPGA chip respectively; the control method includes: The lockout control circuit detects whether the power supply or the FPGA chip is malfunctioning. In response to an abnormality in the operating power supply or the FPGA chip, the switching circuit is disconnected to put the relay in a locked state.

12. The control method for the circuit board according to claim 11, characterized in that, The step of detecting whether the power supply or the FPGA chip is malfunctioning through the lockout control circuit includes: The interlocking control circuit detects whether the working power supply or the FPGA chip is abnormal based on the working voltage signal output by the working power supply and the FPGA status signal output by the FPGA chip. The step of disconnecting the switching circuit to put the relay in a locked state in response to an abnormality in the operating power supply or the FPGA chip includes: In response to the operating voltage signal and the FPGA status signal indicating that at least one of the operating power supply or the FPGA chip is malfunctioning, it is determined that the operating power supply or the FPGA chip is malfunctioning. The first lockout control signal output by the lockout control circuit is in a first state to control the switch circuit to open, so that the relay is in a lockout state.

13. The control method for the circuit board according to claim 12, characterized in that, The interlocking control circuit includes a trigger circuit and a logic control circuit. The trigger circuit is connected to the FPGA chip and the power supply. The logic control circuit is connected to the trigger circuit and the switching circuit. Before the step of detecting whether the working power supply and the FPGA chip are abnormal through the interlocking control circuit based on the working voltage signal output by the working power supply and the FPGA status signal output by the FPGA chip, the method further includes: The trigger circuit receives the operating voltage signal and the FPGA status signal, and generates a corresponding trigger signal. The logic control circuit receives the trigger signal and generates the corresponding first latching control signal. When the operating voltage signal and the FPGA status signal indicate that at least one of the operating power supply or the FPGA chip is malfunctioning, the first latching control signal is in a first state.

14. The control method for the circuit board according to claim 13, characterized in that, The logic control circuit is further configured to have a trigger pin for receiving an external trigger signal; the control method further includes: The logic control circuit detects whether the trigger pin receives an external trigger signal. In response to the external trigger signal being received by the trigger pin, the first latching control signal is set to the first state.

15. The control method for the circuit board according to claim 11, characterized in that, The control method further includes: The FPGA chip receives the status detection signal of the relay and generates a corresponding second interlocking control signal. In response to the status detection signal indicating that the relay is abnormal, the second latching control signal output by the FPGA chip is controlled to be in the first state, so as to control the switching circuit to be disconnected and the relay is in the latching state.

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