Adaptive low-loss full-bridge rectifier circuit

Abstract

This invention discloses an adaptive low-loss full-bridge rectifier circuit, including a first AC input terminal, a second AC input terminal, a positive DC output terminal, a negative DC output terminal, and a rectifier bridge power circuit. The rectifier bridge power circuit includes an upper bridge arm and a lower bridge arm. The upper bridge arm includes a structurally symmetrical left upper bridge arm and a right upper bridge arm, and the lower bridge arm includes a structurally symmetrical left lower bridge arm and a right lower bridge arm. The left lower bridge arm has a first switching node, and the right lower bridge arm has a second switching node. The potentials of the first and second switching nodes adaptively adjust with changes in the AC input voltage, thereby controlling the turn-off of the left and right lower bridge arms to achieve DC voltage output. This invention adaptively turns on the corresponding MOSFET during the main energy transmission stage, allowing the main current to flow through the low on-resistance channel of the MOSFET, resulting in low voltage drop loss. This invention also features low cost and high reliability.

Description

Technical Field

[0001] This invention relates to the field of electronic power technology, and specifically to an adaptive low-loss full-bridge rectifier circuit. Background Technology

[0002] The full-bridge rectifier circuit is one of the most fundamental AC-DC conversion topologies in power electronics, widely used in switching power supplies, chargers, motor drives, solar thermal equipment, and component manufacturing. Traditional full-bridge rectifier circuits typically consist of four high-voltage diodes (such as...). Figure 1 As shown, diodes utilize the unidirectional conductivity of diodes to achieve AC-to-DC conversion. However, diodes have an inherent forward voltage drop (typically 0.7V to 1.5V) during operation, which generates significant conduction losses when carrying large currents. This leads to reduced system efficiency and increased heat generation, especially in high-power applications, placing higher demands on heat dissipation design and limiting further improvements in system power density.

[0003] To overcome the problem of high rectification losses in diodes, existing technologies have proposed synchronous rectification technology, which uses MOSFETs (metal-oxide-semiconductor field-effect transistors) to replace diodes (such as...). Figure 2 As shown, the MOSFET utilizes its low on-resistance (Rds(on)) characteristic to reduce conduction losses. The key to synchronous rectification technology lies in accurately controlling the on and off timing of the MOSFET, ensuring it conducts when the current is forward and turns off when it is reverse, simulating the unidirectional conductivity of a diode. This typically requires independent drive circuits on each bridge arm and dead-time control, resulting in complex circuit structures and high costs. Furthermore, in the AC input voltage zero-crossing region or during polarity transitions, improper control timing can easily lead to problems such as uncertain switching states and mis-conduction of the body diode, resulting in additional losses or even circuit failures.

[0004] Therefore, how to design a rectifier circuit that has low loss characteristics, simplifies control logic, improves commutation reliability, and has low cost has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] This invention provides an adaptive low-loss full-bridge rectifier circuit to solve the problems of high conduction loss, high cost, complex structure and poor control reliability in the prior art.

[0006] To achieve the objective of this invention, this invention provides an adaptive low-loss full-bridge rectifier circuit, including a first AC input terminal, a second AC input terminal, a positive DC output terminal, a negative DC output terminal, and a rectifier bridge power circuit. The rectifier bridge power circuit includes an upper bridge arm and a lower bridge arm. The upper bridge arm includes a structurally symmetrical upper left bridge arm and an upper right bridge arm. The lower bridge arm includes a structurally symmetrical lower left bridge arm and a lower right bridge arm. The first end of the upper left bridge arm and the second end of the lower left bridge arm are respectively connected to a first AC input terminal. The second end of the upper left bridge arm and the second end of the upper right bridge arm are respectively connected to the positive terminal of the DC output terminal. The first end of the upper right bridge arm and the second end of the lower right bridge arm are respectively connected to a second AC input terminal. The first end of the lower left bridge arm and the first end of the lower right bridge arm are respectively connected to the negative terminal of the DC output terminal. The lower left bridge arm is provided with a first switch node, and the lower right bridge arm is provided with a second switch node; The potentials of the first and second switching nodes are adaptively adjusted according to the change of AC input voltage, thereby controlling the turn-off of the lower left and lower right bridge arms and realizing the output of DC voltage.

[0007] The beneficial effects of this invention are as follows: The rectifier bridge power circuit of this invention adaptively turns on the corresponding MOSFET during the main energy transfer stage (|Vac|>Vdc) by comparing the magnitude of the input AC voltage and the output DC voltage in real time. This allows the main current to flow through the low on-resistance channel of the MOSFET, avoiding the high forward voltage drop loss of traditional diode rectification. This significantly improves efficiency, especially in low-voltage, high-current applications. Furthermore, since no independent driver chip is required on each bridge arm, the system design is greatly simplified, and costs are reduced.

[0008] On the other hand, the third to sixth field-effect transistors in the lower arm of the present invention constitute a state-locking network. When the fourth field-effect transistor is turned on, it clamps the potential of the first switching node to near 0V; when the sixth field-effect transistor is turned on, it clamps the potential of the second switching node to near 0V, ensuring that the lower arm conduction path is unique during the stable transmission phase.

[0009] In addition, during the freewheeling phase after each half-cycle of transmission, the upper bridge arm automatically turns off while the lower bridge arm remains on, providing a low-impedance freewheeling path for the load inductor without the need for an additional freewheeling diode. This also enables the smooth release of electromagnetic energy, reducing voltage spikes and electromagnetic interference. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a traditional full-bridge rectifier circuit.

[0011] Figure 2 This is a schematic diagram of the existing full-bridge rectifier circuit.

[0012] Figure 3 This is a structural block diagram of the present invention.

[0013] Figure 4This is a schematic diagram of the rectifier bridge power circuit of the present invention.

[0014] Figure 5 This is a schematic diagram of the current and voltage waveforms under different operating states of the present invention.

[0015] Figure 6 This is a circuit diagram of the first working state of the present invention.

[0016] Figure 7 This is a circuit diagram of the second working state of the present invention.

[0017] Figure 8 This is a circuit diagram of the third working state of the present invention.

[0018] Figure 9 This is a circuit diagram of the fourth working state of the present invention.

[0019] Figure 10 This is a circuit diagram of the fifth working state of the present invention. Detailed Implementation

[0020] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Please see Figure 3 This embodiment provides an adaptive low-loss full-bridge rectifier circuit, including a first AC input terminal ACL, a second AC input terminal ACR, a positive DC output terminal DC+, a negative DC output terminal DC-, and a rectifier bridge power circuit 100, wherein the rectifier main power circuit 100 includes an upper bridge arm 110 and a lower bridge arm 120.

[0022] The rectifier bridge power circuit 100 is connected to the AC input terminal ACL and the second AC input terminal ACR respectively to receive the AC input voltage Vac. The positive DC+ and negative DC- output terminals are used to output the DC voltage Vdc and connect it to the load (not shown in the figure).

[0023] like Figure 3 , Figure 4As shown, the upper bridge arm 110 includes a structurally symmetrical upper left bridge arm 111 and upper right bridge arm 112. The upper left bridge arm 111 includes a first diode LD1 and a first field-effect transistor Q1. The first diode LD1 is an N-channel low-voltage Schottky diode with a small forward voltage drop. Its anode is connected to the first AC input terminal ACL, and its cathode is connected to the source of the first field-effect transistor Q1. The gate of the first field-effect transistor Q1 is connected to the first AC input terminal ACL, and its drain is connected to the positive DC output terminal DC+. The upper right bridge arm 112 includes a second diode LD2 and a second field-effect transistor Q2. The second diode LD2 is an N-channel low-voltage Schottky diode with a small forward voltage drop. Its anode is connected to the second AC input terminal ACR, and its cathode is connected to the source of the second field-effect transistor Q2. The gate of the second field-effect transistor Q2 is connected to the second AC input terminal ACR, and its drain is connected to the positive DC output terminal DC+. In the embodiment, the first field-effect transistor Q1 and the second field-effect transistor Q2 are both high-voltage power GaN HEMTs and are both normally open field-effect transistors. That is, the first field-effect transistor Q1 and the second field-effect transistor Q2 are in the on state by default, and the first field-effect transistor Q1 and the second field-effect transistor Q2 are in the on state when the gate voltage is zero, and a negative voltage needs to be applied to turn them off.

[0024] like Figure 3 , Figure 4 As shown, the lower bridge arm 120 includes a structurally symmetrical left lower bridge arm 121 and a right lower bridge arm 122. The left lower bridge arm 121 includes a third field-effect transistor (FET) Q3 and a fourth field-effect transistor (FET) Q4, and the right lower bridge arm 122 includes a fifth field-effect transistor (FET) Q5 and a sixth field-effect transistor (FET) Q6. FETs Q3 and Q5 are high-voltage power GaN HEMTs and are normally-on FETs, meaning they are in a default conducting state. FETs Q3 and Q5 are in a conducting state when the gate voltage is zero and require a negative voltage to turn off. FETs Q4 and Q6 are N-channel low-voltage MOSFETs and are normally-off FETs. Normally-off FETs are in a non-conductive state when the gate voltage is zero and require a positive gate voltage to turn on.

[0025] Specifically, the drain of the third field-effect transistor Q3 is connected to the first AC input terminal ACL, and its source is connected to the drain of the fourth field-effect transistor Q4 and the gate of the sixth field-effect transistor Q6, forming the first switching node m1. The gate of the third field-effect transistor Q3 is connected to the negative DC output terminal DC-. The gate of the fourth field-effect transistor Q4 is connected to the drain of the sixth field-effect transistor Q6 and the source of the fifth field-effect transistor Q5, forming the second switching node m2. The source of the fourth field-effect transistor Q4 is connected to the negative DC output terminal DC-. The drain of the fifth field-effect transistor Q5 is connected to the second AC input terminal ACR, and its gate and the source of the sixth field-effect transistor Q6 are connected to the negative DC output terminal DC-.

[0026] Through the above connection method, the third field-effect transistor Q3, the fourth field-effect transistor Q4, the fifth field-effect transistor Q5 and the sixth field-effect transistor Q6 of the lower bridge arm constitute a logic control network with a self-locking function. Its state is determined by the potential of the first switch node m1 and the second switch node m2, thereby controlling the switching of the main current path.

[0027] Since the gate of the first field-effect transistor Q1 is controlled by the voltage of the first AC input terminal ACL, the gate of the second field-effect transistor Q2 is controlled by the voltage of the second AC input terminal ACR, the gates of the third field-effect transistor Q3 and the fifth field-effect transistor Q5 are controlled by the voltage of the negative DC output terminal DC-, the gate of the sixth field-effect transistor Q6 is controlled by the potential of the first switching node m1, and the gate of the fourth field-effect transistor Q4 is controlled by the potential of the second switching node m2, the potentials of the above nodes are adaptively adjusted with the change of AC input voltage, thus realizing the coordinated control of the on / off state of all six field-effect transistors.

[0028] The working principle of the full-bridge rectifier circuit in this embodiment is explained below. For ease of description, the voltage between the first AC input terminal ACL and the second AC input terminal ACR is defined as Vac(LR). A positive Vac(LR) indicates that the first AC input terminal ACL is positive relative to the second AC input terminal ACR. Vt represents the threshold voltage of the fourth field-effect transistor Q4 and the sixth field-effect transistor Q6. The potentials of the first switching node m1 and the second switching node m2 can be adaptively adjusted according to the change of AC input voltage, thereby automatically switching the operating state of the circuit. Specifically, the operating state of the circuit can be divided into the following cases.

[0029] Operating State 1, Follow-through phase after the start of the positive half-cycle transmission: Vdc > Vac (LR) > Vt like Figure 5 , Figure 6As shown, when the AC input voltage of the positive half-cycle begins to rise or fall, and it is higher than Vt but lower than Vdc, i.e., VDC>VAC(LR)>Vt, the potential of the first switching node m1 is pulled up, making Vm1>Vt, and the potential of the second switching node m2 is pulled down to a low potential. In this embodiment, the potential of the second switching node m2 is pulled down to near 0V, making Vm2≈0. At this time: Since the voltage Vac(LR) between the first AC input terminal ACL and the second AC input terminal ACR is less than Vdc, the first diode LD1 is turned off due to reverse bias, and the first field-effect transistor Q1 is turned off; at the same time, the second diode LD2 is turned off due to reverse bias, and the second field-effect transistor Q2 is turned off.

[0030] The gate-source voltage of the fifth field-effect transistor Q5 is approximately zero, and Q5 is turned on. Subsequently, the potential of the second switching node m2 approaches 0V (equal to Vacr).

[0031] The gate-source voltage of the fourth field-effect transistor Q4 is affected by Vm2. Since Vm2≈0, the fourth field-effect transistor Q4 is turned off, and the potential of the first switching node m1 is pulled up, making Vm1>Vt.

[0032] The gate-source voltage of the sixth field-effect transistor Q6 is affected by Vm1. Since Vm1 > Vt, the sixth field-effect transistor Q6 is turned on.

[0033] The gate-source voltage of the third field-effect transistor Q3 is affected by Vm1. As Vm1 increases, the third field-effect transistor Q3 is turned off.

[0034] In this state, the AC input voltage is less than the DC output voltage, and the main current cannot be transmitted through the MOSFET channel of the upper bridge arm 110. The freewheeling circuit is entirely formed by the lower bridge arm and does not pass through the AC source; the freewheeling path is: DC output terminal negative DC- → sixth field-effect transistor Q6 → second switching node m2 → fifth field-effect transistor Q5 → second AC input terminal ACR.

[0035] During this stage, the third MOSFET Q3 and the fourth MOSFET Q4 are turned off to prevent current from bypassing from the first AC input terminal ACL to the negative DC output terminal DC-, ensuring the correct freewheeling direction. The fifth MOSFET Q5 and the sixth MOSFET Q6 provide a low-impedance freewheeling path from the negative DC output terminal DC- to the second AC input terminal ACR. Operating State 2, Positive Half-Cycle Transmission Phase: Vac(LR) > Vdc like Figure 5 , Figure 7As shown, when the AC input voltage is in the positive half-cycle and its instantaneous value is higher than the DC output voltage, i.e., Vac(LR) > Vdc, the potential of the first switching node m1 remains greater than Vt, and the potential of the second switching node m2 remains low. In this embodiment, the potential of the second switching node m2 is maintained close to 0V. At this time: Since the voltage Vac(LR) between the first AC input terminal ACL and the second AC input terminal ACR is greater than Vdc, the first diode LD1 is forward biased and conducts. The gate-source voltage of the first field-effect transistor Q1 is greater than 0, so Q1 conducts. The second diode LD2 is reverse biased and cut off, so Q2 is turned off.

[0036] Since the potentials Vm1 of the first switching node m1 and Vm2 of the second switching node m2 remain unchanged, the third field-effect transistor Q3 remains off, the fourth field-effect transistor Q4 remains off, the fifth field-effect transistor Q5 remains on, and the sixth field-effect transistor Q6 remains on.

[0037] At this time, the main current path is as follows: the current starts from the first AC input terminal ACL, flows into the channel of the first field-effect transistor Q1 through the first diode LD1, and is output to the positive DC output terminal DC+ through the drain of the first field-effect transistor Q1; after flowing through the load, it flows out from the negative DC output terminal DC-; then it flows into the channel of the fifth field-effect transistor Q5 through the sixth field-effect transistor Q6, and finally returns from the second AC input terminal ACR, forming a complete loop.

[0038] In this circuit, both the first diode LD1 and the first field-effect transistor Q1 are turned on, forming the synchronous rectification path of the upper bridge arm 110. Since the total voltage drop across the on-resistance of the first diode LD1 (as a low-voltage Schottky diode, its forward voltage drop is much smaller than that of a traditional rectifier bridge diode) and the first field-effect transistor Q1 is still smaller than the on-resistance of a traditional diode rectifier bridge, the upper bridge arm has lower losses and higher efficiency when the rectifier circuit is turned on.

[0039] The fifth MOSFET Q5 and the sixth MOSFET Q6 serve as the return path for the lower bridge arm 120, connecting the negative DC- terminal of the DC output to the second AC input terminal ACR. The current in the lower bridge arm 120 flows through the channels of the fifth MOSFET Q5 and the sixth MOSFET Q6. The forward voltage drop of the channels of the fifth MOSFET Q5 and the sixth MOSFET Q6 is much smaller than that of a traditional diode rectifier bridge. Therefore, when this rectifier circuit is turned on, the loss in the lower bridge arm is lower and the efficiency is higher.

[0040] Both the third field-effect transistor Q3 and the fourth field-effect transistor Q4 are turned off, thereby isolating the first AC input terminal ACL from the negative DC output terminal DC- and preventing short circuits.

[0041] Operating state three, zero-crossing commutation stage: Vdc > |Vac(L - R)| < Vt As Figure 5 , Figure 8 shown, when the absolute value of the input voltage is less than the DC output voltage and less than the threshold voltage of the enhancement-mode field-effect transistor, i.e., Vdc > |Vac(L - R)| < Vt. At this time: The potential of the first switch node m1, Vm1 < Vt, and the potential of the second switch node m2, Vm2 < Vt. No current path is formed, achieving electrical isolation in the zero-crossing commutation stage.

[0042] Operating state four, freewheeling stage after the start of negative half-cycle transmission: Vdc > Vac(R - L) > Vt As Figure 5 , Figure 9 shown, when the AC input voltage in the negative half-cycle starts to rise, higher than Vt but lower than Vdc, i.e., Vdc > Vac(R - L) > Vt, the potential of the second switch node m2 is pulled up, making Vm2 > Vt, and the potential of the first switch node m1 is pulled down to a low potential. In this embodiment, the potential of the first switch node m1 is pulled down to be close to 0V, making Vm1 ≈ 0. At this time: Since the voltage between the second AC input terminal ACR and the first AC input terminal ACL is Vac(R - L) which is less than Vdc, the first diode LD1 is cut off due to reverse bias, and the first field-effect transistor Q1 is turned off; at the same time, the second diode LD2 is cut off due to reverse bias, and the second field-effect transistor Q2 is turned off.

[0043] The gate-source voltage of the third field-effect transistor Q3 is approximately equal to zero, and the third field-effect transistor Q3 is turned on. Subsequently, the potential of the first switch node m1 is close to 0V (equal to Vacl).

[0044] The gate-source voltage of the sixth field-effect transistor Q6 is affected by Vm1. Since Vm1 ≈ 0, the sixth field-effect transistor Q6 is turned off. Subsequently, the potential of the second switch node m2 is pulled up, making Vm2 > Vt.

[0045] The gate-source voltage of the fourth field-effect transistor Q4 is affected by Vm2. Since Vm2 > Vt, the fourth field-effect transistor Q4 is turned on.

[0046] The gate-source voltage of the fifth field-effect transistor Q5 is affected by Vm2. Since Vm2 increases, the fifth field-effect transistor Q5 is turned off.

[0047] In this state, the AC input voltage is less than the DC output voltage, and the main current cannot be transmitted through the field-effect transistor channels of the upper bridge arm 110. The freewheeling loop is completely composed of the lower bridge arm and does not pass through the AC source; the freewheeling path is: DC output terminal negative DC → fourth field-effect transistor Q4 → first switching node m1 → third field-effect transistor Q3 → first AC input terminal ACL.

[0048] During this stage, both the third MOSFET Q3 and the fourth MOSFET Q4 are turned on, providing a low-impedance freewheeling path from DC- to ACL. The fifth MOSFET Q5 and the sixth MOSFET Q6 are turned off, preventing current from bypassing from the second AC input terminal ACR to the negative DC output terminal DC-, ensuring the correct freewheeling direction.

[0049] Operating State 5, Negative Half-Cycle Transmission Phase: Vac(RL) > Vdc like Figure 5 , Figure 10 As shown, when the AC input voltage is in the negative half-cycle (i.e., the second AC input terminal ACR is positive relative to the first AC input terminal ACL), and its instantaneous value is higher than the DC output voltage, i.e., Vac(RL) > Vdc, the potential of the second switching node m2 is maintained at a level greater than Vt, and the potential of the first switching node m1 is maintained at a low potential. In this embodiment, the potential of the first switching node m1 is maintained close to 0V. At this time: Since the voltage Vac(RL) between the second AC input terminal ACR and the first AC input terminal ACL is greater than Vdc, the second diode LD2 is forward biased and conducts. The gate-source voltage of the first field-effect transistor Q2 is greater than 0, so Q2 conducts. The first diode LD1 is reverse biased and cut off, so Q1 is turned off.

[0050] Since the potentials Vm1 of the first switching node m1 and Vm2 of the second switching node m2 remain unchanged, the third field-effect transistor Q3 remains on, the fourth field-effect transistor Q4 remains on, the fifth field-effect transistor Q5 remains off, and the sixth field-effect transistor Q6 remains off.

[0051] At this time, the main current path is as follows: the current starts from the second AC input terminal ACR, flows into the channel of the second field-effect transistor Q2 through the second diode LD2, and is output to the positive DC output terminal DC+ through the drain of the second field-effect transistor Q2; after flowing through the load, it flows out from the negative DC output terminal DC-; then it flows into the channel of the third field-effect transistor Q3 through the fourth field-effect transistor Q4, and finally returns from the first AC input terminal ACL, forming a complete loop.

[0052] In this circuit, both the second diode LD2 and the second field-effect transistor Q2 are turned on, forming the synchronous rectification path of the upper bridge arm 110. Since the total voltage drop across the on-resistance of the second diode LD2 (as a low-voltage Schottky diode, its forward voltage drop is much smaller than that of a traditional rectifier bridge diode) and the second field-effect transistor Q2 is still smaller than the on-resistance of a traditional diode rectifier bridge, the upper bridge arm has lower losses and higher efficiency when the rectifier circuit is turned on.

[0053] The third MOSFET Q3 and the fourth MOSFET Q4 serve as the return path for the lower bridge arm 120, connecting the negative DC- terminal of the DC output to the first AC input terminal ACL. The current in the lower bridge arm 120 flows through the channels of the third MOSFET Q3 and the fourth MOSFET Q4. The forward voltage drop of the channels of the third MOSFET Q3 and the fourth MOSFET Q4 is much smaller than that of a traditional diode rectifier bridge. Therefore, when this rectifier circuit is turned on, the loss in the lower bridge arm is lower and the efficiency is higher.

[0054] Both the fifth field-effect transistor Q5 and the sixth field-effect transistor Q6 are turned off, thereby isolating the second AC input terminal ACR from the negative DC output terminal DC- and preventing short circuits.

[0055] In summary, the adaptive low-loss full-bridge rectifier circuit of this embodiment, through the series connection of the depletion-type first field-effect transistor Q1 and the second field-effect transistor Q2 in the upper bridge arm 110 with the low-voltage first diode LD1 and the second diode LD2 respectively, and the self-locking logic network formed by the depletion-type third field-effect transistor Q3 and the fifth field-effect transistor Q5 in the lower bridge arm 120 with the enhancement-type fourth field-effect transistor Q4 and the sixth field-effect transistor Q6 respectively, enables the potentials of the first switching node m1 and the second switching node m2 to adaptively adjust according to the relationship between the AC input voltage Vac (LR) and the DC output voltage Vdc, thereby automatically switching the five operating states of the rectifier bridge power circuit 100.

[0056] This design effectively avoids the high forward voltage drop losses of traditional diode rectifier bridges and the high cost of existing dedicated driver chips. It also overcomes the problems of complex control and false triggering that easily occur during commutation in all-MOSFET rectifier bridges. Overall, this embodiment can achieve full-wave synchronous rectification without complex external driver circuitry, effectively reducing conduction losses, improving conversion efficiency, achieving a smooth release of electromagnetic energy after each half-cycle, and also possessing good zero-crossing commutation reliability and electrical safety.

[0057] Although the present invention has been disclosed through the above embodiments, the scope of protection of the present invention is not limited thereto. Any modifications or substitutions made to the above components without departing from the concept of the present invention shall fall within the scope of the claims of the present invention.

Claims

1. An adaptive low-loss full-bridge rectifier circuit, characterized in that, It includes a first AC input terminal, a second AC input terminal, a positive DC output terminal, a negative DC output terminal, and a rectifier bridge power circuit; The rectifier bridge power circuit includes an upper bridge arm and a lower bridge arm. The upper bridge arm includes a structurally symmetrical upper left bridge arm and an upper right bridge arm. The lower bridge arm includes a structurally symmetrical lower left bridge arm and a lower right bridge arm. The first end of the upper left bridge arm and the second end of the lower left bridge arm are respectively connected to a first AC input terminal. The second end of the upper left bridge arm and the second end of the upper right bridge arm are respectively connected to the positive terminal of the DC output terminal. The first end of the upper right bridge arm and the second end of the lower right bridge arm are respectively connected to a second AC input terminal. The first end of the lower left bridge arm and the first end of the lower right bridge arm are respectively connected to the negative terminal of the DC output terminal. The lower left bridge arm is provided with a first switch node, and the lower right bridge arm is provided with a second switch node; The potentials of the first and second switching nodes are adaptively adjusted according to the change of AC input voltage, thereby controlling the turn-off of the lower left and lower right bridge arms and realizing the output of DC voltage.

2. The adaptive low-loss full-bridge rectifier circuit as described in claim 1, characterized in that, The upper left bridge arm includes a first diode and a first field-effect transistor. The anode of the first diode is connected to the first AC input terminal, and its cathode is connected to the source of the first field-effect transistor. The gate of the first field-effect transistor is connected to the first AC input terminal, and its drain is connected to the positive terminal of the DC output terminal.

3. The adaptive low-loss full-bridge rectifier circuit as described in claim 2, characterized in that, The upper right bridge arm includes a second diode and a second field-effect transistor. The anode of the second diode is connected to the second AC input terminal, and its cathode is connected to the source of the second field-effect transistor. The gate of the second field-effect transistor is connected to the second AC input terminal, and its drain is connected to the positive terminal of the DC output terminal.

4. The adaptive low-loss full-bridge rectifier circuit as described in claim 3, characterized in that, The lower left bridge arm includes a third field-effect transistor and a fourth field-effect transistor, and the lower right bridge arm includes a fifth field-effect transistor and a sixth field-effect transistor; the drain of the third field-effect transistor is connected to the first AC input terminal, and its source is connected to the drain of the fourth field-effect transistor and the gate of the sixth field-effect transistor, respectively, to form the first switching node. The gate of the third field-effect transistor is connected to the negative terminal of the DC output terminal; the gate of the fourth field-effect transistor is connected to the drain of the sixth field-effect transistor and the source of the fifth field-effect transistor, forming the second switching node; the source of the fourth field-effect transistor is connected to the negative terminal of the DC output terminal; the drain of the fifth field-effect transistor is connected to the second AC input terminal, and its gate and the source of the sixth field-effect transistor are connected to the negative terminal of the DC output terminal.

5. The adaptive low-loss full-bridge rectifier circuit as described in claim 4, characterized in that, The first field-effect transistor and the second field-effect transistor switch their operating states according to the voltage changes at the first AC input terminal and the second AC input terminal. Furthermore, based on the voltage changes at the first and second AC input terminals, the potentials of the first and second switching nodes are adaptively adjusted, thereby enabling the third, fourth, fifth, and sixth field-effect transistors to switch operating states, achieving adaptive switching of operating states. The operating states include: the freewheeling phase after the start of the positive half-cycle transmission, the positive half-cycle transmission phase, the zero-crossing commutation phase, the freewheeling phase after the start of the negative half-cycle transmission, and the negative half-cycle transmission phase.

6. The adaptive low-loss full-bridge rectifier circuit as described in claim 5, characterized in that, When the rectifier bridge power circuit is in the freewheeling phase after the start of the positive half-cycle transmission, the AC input voltage during the positive half-cycle is higher than the threshold voltage of the fourth field-effect transistor and the sixth field-effect transistor but lower than the DC output voltage. The potential of the first switching node is pulled up to be higher than the threshold voltage, and the potential of the second switching node is pulled down to be close to 0V. The first field-effect transistor is turned off, the second field-effect transistor is turned off, the third field-effect transistor is turned off, the fourth field-effect transistor is turned on, the fifth field-effect transistor is turned on, and the sixth field-effect transistor is turned on, so as to provide a freewheeling path from the negative terminal of the DC output terminal through the sixth field-effect transistor, the second switching node, the fifth field-effect transistor to the second AC input terminal.

7. The adaptive low-loss full-bridge rectifier circuit as described in claim 5, characterized in that, When the rectifier bridge power circuit is in the positive half-cycle transmission phase, the AC input voltage is higher than the DC output voltage, and the potentials of the first and second switching nodes remain unchanged. The first field-effect transistor is turned on, the second field-effect transistor is turned off, the third field-effect transistor is turned off, the fourth field-effect transistor is turned on, the fifth field-effect transistor is turned on, and the sixth field-effect transistor is turned on, forming a main current path from the first AC input terminal through the first diode, the first field-effect transistor, the load, the sixth field-effect transistor, and the fifth field-effect transistor back to the second AC input terminal.

8. The adaptive low-loss full-bridge rectifier circuit as described in claim 5, characterized in that, When the rectifier bridge power circuit is in the zero-crossing commutation stage, the absolute value of the AC input voltage is less than the DC output voltage and less than the threshold voltages of the fourth and sixth field-effect transistors. The potentials of the first and second switching nodes are both pulled down to below the threshold voltages, and no current path is formed, thus achieving electrical isolation during the zero-crossing commutation stage.

9. The adaptive low-loss full-bridge rectifier circuit as described in claim 5, characterized in that, When the rectifier bridge power circuit is in the freewheeling phase after the start of the negative half-cycle transmission, the negative half-cycle AC input voltage is higher than the threshold voltage of the fourth field-effect transistor and the sixth field-effect transistor but lower than the DC output voltage. The potential of the second switching node is pulled up to be higher than the threshold voltage, and the potential of the first switching node is pulled down to be close to 0V. The first field-effect transistor is turned off, the second field-effect transistor is turned off, the third field-effect transistor is turned on, the fourth field-effect transistor is turned on, the fifth field-effect transistor is turned off, and the sixth field-effect transistor is turned off, so as to provide a freewheeling path from the negative terminal of the DC output terminal through the fourth field-effect transistor, the first switching node, the third field-effect transistor to the first AC input terminal.

10. The adaptive low-loss full-bridge rectifier circuit as described in claim 5, characterized in that, When the rectifier bridge power circuit is in the negative half-cycle transmission phase, the negative half-cycle AC input voltage is higher than the DC output voltage, and the potentials of the first switching node and the second switching node remain unchanged. The first field-effect transistor is turned off, the second field-effect transistor is turned on, the third field-effect transistor is turned on, the fourth field-effect transistor is turned on, the fifth field-effect transistor is turned off, and the sixth field-effect transistor is turned off, forming a main current path from the second AC input terminal through the second diode, the second field-effect transistor, the load, the fourth field-effect transistor, and the third field-effect transistor back to the first AC input terminal.

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