A self-biased equalization circuit, integrated chip and device thereof

Abstract

The application provides a self-bias equalization circuit, a core particle integrated chip and a device, and relates to the technical field of core particle interconnection. At least comprising a core amplification unit for converting and amplifying an input signal; a frequency response shaping network unit connected with the core amplification unit, for equalizing the voltage gain of the signal in the self-bias equalization circuit; and a self-bias generation unit connected with the core amplification unit, for extracting a common-mode voltage and feeding back to the core amplification unit through a feedback voltage node to form a feedback loop. The common-mode negative feedback loop of the application detects and suppresses the fluctuation of the output common-mode level in real time, so that the self-bias equalization circuit can still maintain a very high common-mode rejection ratio under the common-mode interference such as power supply noise and substrate coupling.

Description

Technical Field

[0001] This invention belongs to the field of chip interconnect technology, specifically relating to a self-biased equalization circuit and its chip integrated chip and device. Background Technology

[0002] Currently, in chip-to-chip interconnect architectures, data transmission suffers from severe frequency-dependent losses during transmission, leading to inter-symbol interference (ISI). Therefore, self-biased equalizers are essential for signal compensation. Traditional continuous-time linear equalizers (CTLEs) are primarily designed for differential inputs. However, when applied to mainstream single-ended signal transmission chip-to-chip interconnect interfaces, their limited common-mode rejection capability means that common-mode noise can translate into output differential offset, interfering with subsequent decision circuits and increasing the bit error rate. To improve common-mode rejection performance, common-mode feedback modules or precise external biasing are typically added to the CTLE circuit. However, these methods further increase system complexity and area overhead, and are sensitive to external bias noise. Summary of the Invention

[0003] This invention is made to solve the above-mentioned problems, and aims to provide a self-biased equalization circuit and its chip integrated chip and device, which can maintain an extremely high common-mode rejection ratio under common-mode interference such as power supply noise and substrate coupling.

[0004] This invention provides a self-biased equalization circuit, characterized by comprising: a core amplification unit for converting and amplifying the input signal; a frequency response shaping network unit connected to the core amplification unit for equalizing the voltage gain of the signal in the self-biased equalization circuit; and a self-bias generation unit connected to the core amplification unit for extracting the common-mode voltage and feeding it back to the core amplification unit through a feedback voltage node to form a feedback loop.

[0005] In one embodiment of the present invention, the core amplification unit includes a differential pair transistor assembly, a resistive load assembly, and a tail current source assembly. The differential pair transistor assembly is used to receive the input signal. The resistive load assembly is electrically connected to the output terminal of the differential pair transistor assembly. The drain of the tail current source assembly is electrically connected to the source of the differential pair transistor assembly, and the gate is electrically connected to the feedback voltage node.

[0006] In one embodiment of the present invention, when the differential pair transistor assembly uses an N-type transistor and the tail current source assembly uses an N-type transistor, the resistive load assembly is connected between the drain of the differential pair transistor assembly and the power supply; when the differential pair transistor assembly uses a P-type transistor and the tail current source assembly uses a P-type transistor, the resistive load assembly is connected between the drain of the differential pair transistor assembly and ground.

[0007] In one embodiment of the present invention, the differential pair transistor assembly includes a first transistor and a second transistor, wherein the first transistor is used to receive high-frequency data signals and the second transistor is used to receive a reference voltage.

[0008] In one embodiment of the present invention, the frequency response shaping network unit includes a source degradation capacitor and two source degradation resistors. The two source degradation resistors are electrically connected to the tail current source component through the same node. The two source degradation resistors are connected in series with each other, and the source degradation capacitor is connected in parallel with the two source degradation resistors.

[0009] In one embodiment of the present invention, the resistive load component and / or tail current source component are configurable structures.

[0010] In one embodiment of the present invention, the resistive load component includes multiple parallel load resistor branches, and each load resistor branch is controlled by a switch to determine whether it is connected to the circuit.

[0011] In one embodiment of the present invention, the tail current source component includes multiple parallel tail current source branches, and each tail current source branch is controlled by a switch to determine whether it is connected to the circuit.

[0012] The present invention also provides a chip-integrated chip, characterized by comprising: a packaging substrate; a plurality of chips interconnected and integrated on the packaging substrate, wherein at least one of the plurality of chips integrates a self-bias equalization circuit as described above.

[0013] The present invention also provides an electronic device having the features described above, including the chip integrated chip.

[0014] The role and effect of invention

[0015] According to the self-biased equalization circuit and its integrated chip and device involved in this invention, the invention forms a common-mode negative feedback loop by generating a bias internally to detect and suppress fluctuations in the output common-mode level in real time. Thus, it can maintain an extremely high common-mode rejection ratio under common-mode interference such as power supply noise and substrate coupling. Compared with traditional technical solutions that rely on external bias, the output signal of this invention is purer and more symmetrical, effectively reducing common-mode to differential offset in single-ended input mode, significantly improving eye diagram quality and enhancing the system's error resistance.

[0016] Meanwhile, this invention also fully retains the core equalization function of the CTLE circuit. Through a frequency response shaping network composed of source degradation resistors and capacitors, the circuit can simultaneously achieve low-frequency attenuation and high-frequency boost gain characteristics, effectively compensating for channel loss and restoring high-quality signals. Furthermore, the circuit of this invention can be expanded to support digitally configurable bandwidth, further enhancing its applicability in multi-rate interfaces. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the self-biased equalization circuit in an embodiment of the present invention.

[0019] Figure 2 This is a circuit diagram of the self-biased equalization circuit in the embodiment of the present invention when the N-type MOS transistor is input.

[0020] Figure 3 This is a circuit diagram of the self-biased equalization circuit when the P-type MOS transistor is input in an embodiment of the present invention.

[0021] Explanation of reference numerals in the attached figures 100 - Self-biased equalization circuit, 110 - Self-biased generation unit, 120 - Frequency response shaping network unit, 130 - Core amplification unit, 131 - Resistive load assembly, 132 - Differential pair transistor group, 133 - Tail current source assembly. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0024] In this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0025] To make the technical means, creative features, objectives and effects of the present invention easy to understand, the following embodiments, in conjunction with the accompanying drawings, provide a detailed description of the self-biased equalization circuit, its chip and device.

[0026] The self-biased equalization circuit 100 of the present invention has significant application value in the physical layer implementation of high-speed data transmission interfaces between chips due to its core advantages such as no need for external bias, high common-mode rejection ratio and strong PVT robustness. It can also be used in other circuits and systems that require this function, and is especially suitable for interconnection scenarios with single-ended input, poor common-mode noise, and sensitivity to area and power consumption.

[0027] Specifically, the self-biasing equalization circuit 100 can be widely used in products requiring signal equalization and common-mode suppression, such as chip interconnect interface chips, high-performance computing chips, and automotive electronic interface chips. Chip interconnect interface related chips include HBM-compliant storage chip interface chips, UCIe chip bridging chips, computing chip and storage chip interconnect chips, and I / O chip and core chip interface chips. High-performance computing and AI chips include GPU high-speed interconnect chips, NPU cluster interconnect chips, FPGA chip-based interface chips, and high-performance server CPU cache interconnect chips. Automotive electronic high-speed interface chips include automotive Ethernet receiver chips, LiDAR data transmission interface chips, autonomous driving domain controller interconnect chips, and automotive high-definition camera and processor interface chips. Furthermore, the self-biasing equalization circuit 100 can also be applied to high-speed camera GigE Vision interface chips and robot controller interconnect chips in industrial automation equipment, as well as high-definition image transmission interface chips in medical equipment, where high-speed signal compensation and common-mode interference suppression are required.

[0028] The chip-integrated chip of this invention includes multiple chips integrated on a packaging substrate and interconnected thereon, wherein at least one chip integrates as shown in the figure. Figure 1 The self-biased equalization circuit 100 is shown. From Figure 1 As can be seen, the self-biased equalization circuit 100 includes a core amplification unit 130 for converting and amplifying the input signal, a frequency response shaping network unit 120 for equalizing the voltage gain of the signal in the circuit, and a self-biasing generation unit 110 for extracting the common-mode voltage and feeding it back to the core amplification unit 130 to form a feedback loop. The core amplification unit 130 includes a differential pair transistor assembly 132 for receiving the input signal, a resistive load assembly 131 connected to the output terminal of the differential pair transistor assembly 132, and a tail current source assembly 133 disposed between the source and ground of the differential pair transistor assembly 132 and electrically connected to the feedback voltage node Vb.

[0029] It is worth noting that this application does not impose specific limitations on the differential pair assembly 132, the resistive load assembly 131, and the tail current source assembly 133. Both the differential pair assembly 132 and the tail current source assembly 133 can be implemented using N-type MOS transistors or both using P-type MOS transistors. The resistive load assembly 131 can be a separate load resistor or a configurable structure, such as multiple parallel load resistor branches. The tail current source assembly 133 can be a separate third transistor M3 or a configurable structure, such as multiple parallel tail current source branches. The resistive load assembly 131 and the tail current source assembly 133 can be freely combined and cooperate with each other, specifically to ensure the reliability of the circuit operation under different configurations.

[0030] like Figure 2 As shown, in one embodiment, this embodiment provides a self-biased equalization circuit 100 with an N-type MOS transistor input, wherein the differential pair component 132 and the tail current source component 133 can both be N-type MOS transistors. In this embodiment, the core amplification unit 130 serves as the core of signal conversion and amplification of the self-biased equalization circuit 100, and includes the differential pair component 132, the resistive load component 131, and the third transistor M3.

[0031] like Figure 2 As shown, the differential pair transistor assembly 132 consists of two symmetrical N-type MOS transistors, namely transistor M1 and transistor M2, which together form an input differential pair. The gate of transistor M1 serves as the input terminal for the high-frequency data signal Vi, while the gate of transistor M2 receives a fixed reference voltage Vref. This structure allows the single-ended input high-frequency data signal Vi to be converted into a differential signal for subsequent processing. Furthermore, the sources of transistors M1 and M2 are connected to the tail current source assembly 133, forming a unified current path.

[0032] like Figure 2 As shown, the resistive load assembly 131 consists of a fifth resistor R5 and a sixth resistor R6. The fifth resistor R5 is connected between the power supply voltage VDD and the drain of the first transistor M1, corresponding to the first output node Von. The sixth resistor R6 is connected between the power supply voltage VDD and the drain of the second transistor M2, corresponding to the second output node Vop. The core function of the fifth resistor R5 and the sixth resistor R6 is to provide a DC load and simultaneously convert the current change of the differential pair assembly 132 into a differential output voltage, thereby amplifying the signal voltage.

[0033] like Figure 2As shown, the tail current source component 133 is a single N-type MOS transistor, denoted as the third transistor M3. The source of the third transistor M3 is grounded. The drain of the third transistor M3 is electrically connected to the source degradation resistor of the subsequent frequency response shaping network unit 120 through a common node, and thus indirectly connected to the source of the differential pair assembly 132. The gate of the third transistor M3 is connected to the feedback voltage node Vb, providing a dynamically adjustable tail current to the differential pair assembly 132. The magnitude of the current is controlled in real time by the voltage of the feedback voltage node Vb. When the output common-mode voltage fluctuates due to process, voltage, temperature (PVT) changes or common-mode interference, the voltage of the feedback voltage node Vb will adjust synchronously: if the voltage of the feedback voltage node Vb decreases, the gate-source voltage Vgs of the third transistor M3 decreases, its conduction capability weakens, and the drain current decreases accordingly; if the Vb voltage increases, the gate-source voltage Vgs increases, its conduction capability strengthens, and the drain current increases synchronously. This dynamic adjustment effectively counteracts the current fluctuation trend of the differential pair transistor assembly 132, stabilizing the output common-mode voltage and strongly suppressing common-mode interference.

[0034] like Figure 2 As shown, the frequency response shaping network unit 120 is connected in parallel between the sources of the first transistor M1 and the second transistor M2. Its core consists of a first capacitor C1 and two source degradation resistors, denoted as first resistor R1 and second resistor R2. Specifically, first resistor R1 and second resistor R2 are connected in series, with their common node electrically connected to the drain of the third transistor M3. The first capacitor C1 forms a parallel structure with these two series-connected source degradation resistors, jointly achieving the frequency response shaping function. The working mechanism of this unit is based on the characteristic of capacitor impedance changing with frequency: for low-frequency signals, the impedance of the first capacitor C1 is extremely high, at which point the first resistor R1 and second resistor R2 play a dominant role, introducing strong source negative feedback to the circuit, thereby reducing the low-frequency gain of the circuit; for high-frequency signals, the impedance of the first capacitor C1 decreases significantly, weakening the effect of source negative feedback, thus improving the high-frequency gain of the circuit. Through the characteristics of low-frequency attenuation and high-frequency boost, the loss of high-frequency signals in the transmission link is compensated, realizing the frequency equalization function of the circuit.

[0035] It is worth noting that the present invention does not limit the specific types of the source degradation resistor and the first capacitor C1. As a preferred embodiment, the source degradation resistor can be a precision resistor with a low temperature coefficient to ensure the stability of the feedback strength; the first capacitor C1 can be of a type with small parasitic parameters to avoid generating additional interference to high-frequency signals.

[0036] like Figure 2As shown, the core function of the self-biasing generation unit 110 is to automatically generate and stabilize the bias voltage of the feedback voltage node Vb without the need for an external biasing circuit, and then feed it back to the gate of the third transistor M3 to form a complete negative feedback loop. This unit consists of two self-biasing generation resistors and a second capacitor C2. The two self-biasing generation resistors are denoted as the third resistor R3 and the fourth resistor R4. The third resistor R3 is connected between the first output node Von and the feedback voltage node Vb, and the fourth resistor R4 is connected between the second output node Vop and the feedback voltage node Vb. The third resistor R3 and the fourth resistor R4 together constitute a common-mode voltage sampling network. The common-mode voltage sampling network can extract the DC common-mode voltage of the differential signal at the first output node Von and the second output node Vop in real time, and feed the extracted common-mode voltage to the feedback voltage node Vb, which is then transmitted to the gate of the third transistor M3, forming a stable feedback path. The second capacitor C2 is connected between the feedback voltage node Vb and ground. Its function is to work with the two self-biasing generating resistors to construct the poles of the feedback loop, thereby improving the stability of the feedback loop and preventing loop oscillation.

[0037] It is worth noting that the present invention does not specifically limit the material and capacitance value of the second capacitor C2. The second capacitor C2 may include silicon oxide capacitors, silicon nitride capacitors, etc., and its capacitance value can be designed according to the stability requirements of the feedback loop, with the principle of ensuring that the feedback loop has no oscillation.

[0038] In this embodiment, as Figure 2 As shown, a self-biased equalization circuit 100 with N-type MOS transistor input is used. The non-inverting input of the self-biased equalization circuit 100 receives a high-frequency data signal Vi and is connected to the gate of the first transistor M1. The inverting input of the self-biased equalization circuit 100 receives a fixed reference voltage Vref and is connected to the gate of the second transistor M2. The drain of the first transistor M1 is connected to the first output node Von, and the drain of the second transistor M2 is connected to the second output node Vop. A fifth resistor R5 is connected between the power supply voltage VDD and the first output node Von. A sixth resistor R6 is connected between the power supply voltage VDD and the second output node Vop. Two source degradation resistors are connected in series, and the two source degradation resistors are connected in parallel with a first capacitor C1. One end of this parallel network is connected to the source of the first transistor M1, and the other end is connected to the source of the second transistor M2. Figure 2 As shown, the drain of the third transistor M3 is connected to the first resistor R1 and the second resistor R2. The source of the third transistor M3 is grounded. The gate of the third transistor M3 is connected to the feedback voltage node Vb. The third resistor R3 is connected between the first output node Von and the feedback voltage node Vb. The fourth resistor R4 is connected between the second output node Vop and the feedback voltage node Vb. The second capacitor C2 is connected between the feedback voltage node Vb and ground.

[0039] It is worth noting that the present invention does not impose restrictions on the specific structure of each component in the self-bias equalization circuit 100, as long as the principle of realizing its function is met.

[0040] In this embodiment, the stability principle of the self-biasing equalization circuit 100 is as follows: When process deviations, power supply voltage VDD fluctuations, or temperature changes occur, causing an increasing trend in the current of the first transistor M1 and the second transistor M2, the self-biasing equalization circuit 100 responds as follows: The increased current of the first transistor M1 and the second transistor M2 means an increased current flowing through the fifth resistor R5 and the sixth resistor R6, resulting in an increased voltage drop. This causes a decreasing trend in the DC common-mode voltage of the first output node Von and the second output node Vop. The common-mode voltage is extracted through the third resistor R3 and the fourth resistor R4 and then fed back to the feedback voltage node Vb on the gate of the third transistor M3. As the output common-mode voltage decreases, the voltage of the feedback voltage node Vb also decreases, causing the gate-source voltage Vgs of the third transistor M3 to decrease, weakening its conduction capability, thereby reducing the drain current. This current reduction counteracts the initial increasing trend of the current of the first transistor M1 and the second transistor M2.

[0041] In this embodiment, the superior common-mode rejection performance of the self-biased equalization circuit 100 is based on the following principle: When common-mode interference attempts to reduce the common-mode voltage of the first output node Von and the second output node Vop, this change is sampled through the third resistor R3 and the fourth resistor R4 and fed back to the feedback voltage node Vb on the gate of the third transistor M3, thereby weakening the conduction of the third transistor M3, reducing the drain current of the third transistor M3, and pulling the output common-mode level higher to counteract the influence of the interference. Conversely, the negative feedback loop of the self-biased equalization circuit 100 is specifically used to stabilize the output common-mode level, thereby greatly suppressing the common-mode signal gain.

[0042] It is worth noting that this embodiment does not limit the type of common-mode interference; for example, it could be power supply noise. Traditional CTLEs require an externally provided precise bias voltage. Any small deviation or noise in the external bias voltage can lead to a decrease in the common-mode rejection ratio. However, in the self-biasing equalization circuit 100 of this invention, the voltage at the feedback voltage node Vb is automatically generated by the circuit's own symmetrical structure through negative feedback. This is the most suitable bias point for the differential pair under the current PVT conditions, thus ensuring the symmetry of the self-biasing equalization circuit 100 from the source. This is the foundation for achieving high gain and low offset in high-output differential signals.

[0043] In summary, since the common-mode gain is effectively suppressed while the differential gain is retained, the common-mode rejection ratio of the self-biased equalization circuit 100 of this invention is significantly improved. It can also be directly converted into a purer and more symmetrical output differential signal, reducing the performance requirements of subsequent circuits and helping to reduce the bit error rate.

[0044] In another embodiment, to adapt to the equalizer bandwidth requirements of different data rates, a specific implementation of a configurable resistor load component 131 is provided. In this embodiment, both the fifth resistor R5 and the sixth resistor R6 can adopt this configurable structure, and the structures of the fifth resistor R5 and the sixth resistor R6 are identical. For ease of explanation, the following description uses the sixth resistor R6 adopting this configurable structure as an example, replacing the sixth resistor R6 in Embodiment 1 with multiple load resistor branches arranged in parallel. Each load resistor branch includes a PMOS switch and a load resistor. Taking any one of the branches as an example: the source of the PMOS switch is coupled to the power supply voltage VDD, and the drain of the PMOS switch is coupled to one end of the corresponding load resistor; the other end of the load resistor is jointly coupled to the second output node Vop. The gate of each PMOS switch is used to receive independent digital control signals to control the on / off state of the branch.

[0045] In practical operation, by applying corresponding digital control signals to the gates of each PMOS switch, the corresponding load resistor branch can be turned on or off. When a PMOS switch is turned on, its load resistor branch is connected to the circuit; when the PMOS switch is turned off, its branch is disconnected from the circuit. By configuring the combination of these digital control signals, the number of parallel load resistor branches can be dynamically adjusted, thereby changing the total equivalent resistance value of the sixth resistor R6. This allows for flexible configuration of circuit gain and bandwidth to adapt to different application scenarios and data rate requirements.

[0046] In another embodiment, this application provides an implementation of a configurable tail current source component 133, which can be implemented using such a configurable structure. The third transistor M3 in Embodiment 1 is replaced with multiple parallel tail current source branches, each including a selection switch circuit and an N-type MOS transistor. Taking one branch as an example: the source of the N-type MOS transistor in the tail current source branch is grounded, and its drain is connected to a source degradation resistor network; the selection switch circuit is used to selectively connect the feedback voltage node Vb to the gate of the corresponding N-type MOS transistor. In this embodiment, the selection switch circuit can be implemented using an NMOS switch, with the drain of the NMOS switch connected to the feedback voltage node Vb and the source connected to the gate of the N-type MOS transistor, the gate receiving an independent digital control signal. By applying corresponding control signals to the gates of each NMOS switch, the conduction and cutoff of each tail current source branch can be controlled: when the NMOS switch is on, the N-type MOS transistor of that tail current source branch is controlled by the voltage at the feedback voltage node Vb, and the tail current source branch is activated and contributes current; when the NMOS switch is off, that tail current source branch is disabled. By digitally controlling the on / off state of different branches, the total output current capability of the tail current source component 133 can be flexibly adjusted, thereby adapting to different bandwidth and gain requirements.

[0047] In another embodiment, the configurable design of the tail current source component 133 and the configurable design of the resistive load component 131 can work together to achieve digital control of circuit performance. By synchronously adjusting the tail current magnitude and load resistance value through digital control signals, the bias conditions, gain, and bandwidth of the circuit can be precisely configured, thereby optimizing its equalization characteristics to match different data transmission rates and channel loss conditions. During this adjustment process, the self-bias feedback mechanism built into this invention continues to function, automatically maintaining the stability of the output common-mode level and avoiding DC operating point drift introduced by configuration switching, thereby ensuring the reliability and signal integrity of the circuit in different operating modes.

[0048] In another embodiment, the self-biasing equalization circuit 100 uses a P-type MOS transistor as input, and the power supply and ground connection relationship of the self-biasing equalization circuit 100 are adjusted accordingly.

[0049] like Figure 3As shown, specifically, the first transistor M1 and the second transistor M2 are replaced with P-type MOS transistors. The third transistor M3 is replaced with a P-type MOS transistor. The source of the third transistor M3 is replaced with the power supply voltage VDD instead of ground. The fifth resistor R5, which was previously connected between the power supply voltage VDD and the first output node Von, is now connected between ground and the first output node Von. The sixth resistor R6, which was previously connected between the power supply voltage VDD and the second output node Vop, is now connected between ground and the second output node Vop. This P-type MOS transistor input architecture, while maintaining the same self-biasing mechanism, common-mode rejection, and frequency equalization functions as in Embodiment 1, provides an alternative circuit implementation option to adapt to different process preferences or system power planning requirements.

[0050] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0051] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A self-biased equalization circuit, characterized in that, include: The core amplification unit is used to convert and amplify the input signal; A frequency response shaping network unit, connected to the core amplification unit, is used to balance the voltage gain of the signal in the self-biased equalization circuit. The self-bias generation unit is connected to the core amplification unit and is used to extract the common-mode voltage and feed it back to the core amplification unit through the feedback voltage node to form a feedback loop.

2. The self-biased equalization circuit according to claim 1, characterized in that: The core amplification unit includes a differential pair transistor assembly, a resistive load assembly, and a tail current source assembly. The differential pair transistor assembly is used to receive input signals; The resistive load component is electrically connected to the output terminal of the differential pair transistor component; The drain of the tail current source component is electrically connected to the source of the differential pair transistor component, and the gate is electrically connected to the feedback voltage node.

3. The self-biased equalization circuit according to claim 2, characterized in that: When the differential pair transistor assembly uses an N-type transistor and the tail current source assembly uses an N-type transistor, the resistive load assembly is connected between the drain of the differential pair transistor assembly and the power supply. When the differential pair transistor assembly uses a P-type transistor and the tail current source assembly uses a P-type transistor, the resistive load assembly is connected between the drain of the differential pair transistor assembly and ground.

4. The self-biased equalization circuit according to claim 2, characterized in that: The differential pair assembly includes a first transistor and a second transistor, wherein the first transistor is used to receive high-frequency data signals and the second transistor is used to receive a reference voltage.

5. The self-biased equalization circuit according to claim 2, characterized in that: The frequency response shaping network unit includes a source degradation capacitor and two source degradation resistors. The two source degradation resistors are electrically connected to the tail current source component through the same node. The two source degradation resistors are connected in series with each other, and the source degradation capacitor is connected in parallel with the two source degradation resistors.

6. The self-biased equalization circuit according to claim 2, characterized in that: The resistive load assembly and / or the tail current source assembly are configurable structures.

7. The self-biased equalization circuit according to claim 6, characterized in that: The resistive load assembly includes multiple parallel load resistor branches, and each load resistor branch is controlled by a switch to determine whether it is connected to the circuit.

8. The self-biased equalization circuit according to claim 6, characterized in that: The tail current source assembly includes multiple parallel tail current source branches, and each tail current source branch is controlled by a switch to determine whether it is connected to the circuit.

9. A chip-integrated chip, characterized in that, include: Packaging substrate; Multiple chips are interconnected and integrated on the packaging substrate, wherein at least one of the multiple chips integrates a self-biasing equalization circuit as described in any one of claims 1-8.

10. An electronic device, characterized in that, Includes the chip-integrated chip as described in claim 9.

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