Relaxation oscillator based on switched capacitor array and peak feedback structure and stabilization method

Abstract

The application discloses a relaxation oscillator based on a switched capacitor array and a peak feedback structure and a stabilizing method, the oscillator comprising a reference source, a switched capacitor array, a peak voltage feedback module, a comparator and a digital logic circuit, the switched capacitor array comprising two symmetric charge-discharge branches, each branch having a main charging capacitor and a tracking holding capacitor, and the peak voltage feedback module being composed of an operational amplifier, a feedback capacitor and a sampling switch. In operation, the capacitor voltage of one branch charged alternately is compared with a dynamic threshold, and the peak voltage on the tracking holding capacitor of the other branch is sampled to the feedback module at the switching moment, the comparator threshold is dynamically adjusted through the integral action, and finally the capacitor peak voltage is locked to the fixed reference voltage, so that the influence of non-ideal factors such as comparator delay on the oscillation period is systematically offset. The application also adopts a chopping comparator to eliminate the offset. The architecture significantly improves the stability of the oscillation frequency to the power supply voltage and temperature, and helps to realize low phase noise, and is suitable for high-precision on-chip clock sources.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, specifically to a relaxation oscillator and stabilization method based on a switched capacitor array and peak feedback structure. Background Technology

[0002] RC relaxation oscillators are widely used as clock sources in various on-chip systems due to their simple structure, ease of integration, and low power consumption. Their basic principle is to generate a square wave clock signal by periodically charging and discharging a capacitor and using a comparator to monitor the capacitor voltage to trigger a flip-flop.

[0003] However, the performance of traditional RC relaxation oscillators is limited by several non-ideal factors. Their oscillation period, Tosc, is determined not only by the ideal RC time constant but also by the comparator's propagation delay td, the delay of the logic control circuit, and the error time introduced by the non-ideal characteristics of the switches. These delays td are not constant; they vary significantly with power supply voltage, ambient temperature, and process variations, directly leading to unstable output frequency and making it difficult to meet the requirements of high-precision applications. Specifically, temperature changes affect the mobility and threshold voltage of the MOSFET, thus altering the comparator's response speed; fluctuations in the power supply voltage directly affect the charging and discharging rate of internal nodes and the reference level.

[0004] Furthermore, the inherent nonlinear switching mechanism of relaxation oscillators typically results in inferior phase noise performance compared to resonant structures such as LC oscillators. Input noise and charging current noise in comparators can interfere with accurate flip-flop timing, translating into phase jitter or frequency noise in the output clock. As communication systems evolve towards higher frequencies, the requirements for the spectral purity of clock signals become increasingly stringent, making phase noise reduction a pressing issue.

[0005] To improve stability, existing technologies have proposed various solutions. For example, average voltage feedback is used, and an integrator converts delay variations into threshold adjustments; or feedforward period control is used, which simulates and compensates for delays through a replication path. However, these solutions either suffer from limitations in compensation accuracy due to matching degree, or come at the cost of complex circuitry and longer startup times. Therefore, a novel oscillator architecture is needed that can efficiently compensate for delays while also reducing phase noise. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a relaxation oscillator and stabilization method based on a switched capacitor array and peak feedback structure. Through a unique peak sampling and feedback mechanism, the non-ideal delay in the loop is dynamically offset, so that the oscillation period returns to the ideal model dominated by RC parameters, thereby significantly improving the stability of frequency to power supply voltage and temperature, and laying the foundation for further optimization of phase noise performance.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] A relaxation oscillator based on a switched capacitor array and a peak feedback structure includes: a reference source module, a switched capacitor array, a peak voltage feedback module, a comparator, and a digital logic circuit. The reference source module generates a stable reference voltage Vset and provides a reference current to bias the entire system. The switched capacitor array is the core of the oscillator, receiving the charging current provided by the reference source module and operating alternately under the control of a two-phase non-overlapping clock signal generated by the digital logic circuit to generate a sawtooth wave voltage signal. The input of the peak voltage feedback module is connected to a tracking node in the switched capacitor array to sample and hold the peak voltage of the sawtooth wave voltage signal. Its output is connected to one input of the comparator to provide a dynamically adjusted comparator threshold voltage. The other input of the comparator is connected to the output of the current operating branch of the switched capacitor array, and its output is connected to the digital logic circuit. The peak voltage feedback module dynamically adjusts the comparator threshold voltage by comparing and integrating the sampled peak voltage with the fixed reference voltage provided by the reference source module, so that the peak value of the sawtooth wave voltage signal is locked to the fixed reference voltage.

[0009] Furthermore, the switched capacitor array includes two symmetrical charging and discharging branches. One charging and discharging branch includes: a first NMOS transistor, a main charging capacitor, a tracking and holding capacitor, a first control switch, a third control switch, and a sixth control switch. The gate input of the first NMOS transistor is a NOR gate logic signal of a first clock signal Φ1 and a first clock delay signal Φ1d. The drain of the first NMOS transistor intersects with one end of the main charging capacitor and one end of the third control switch, and is connected to one end of the first control switch. The other end of the first control switch is connected to the output node of the charging current Icharge provided by the reference source module. The source of the first NMOS transistor and the other end of the main charging capacitor are grounded. The other end of the three control switches intersects with one end of the tracking and holding capacitor and is connected to one end of the sixth control switch. The other end of the tracking and holding capacitor is grounded. The other end of the sixth control switch is connected to one input terminal of the peak voltage feedback module. The first control switch and the third control switch are controlled by the first clock signal Φ1, and the sixth control switch is controlled by the second clock signal Φ2. The gate input in the other charging and discharging branch is a NOR gate logic signal of the second clock signal Φ2 and the second clock delay signal Φ2d. The control switches of the first control switch and the third control switch at the corresponding positions in the other charging and discharging branch are controlled by the second clock signal Φ2, and the control switches of the sixth control switch at the corresponding positions are controlled by the first clock signal Φ1.

[0010] Furthermore, the capacitance ratio of the tracking and holding capacitor to the main charging capacitor is 1:4.

[0011] Furthermore, the control switches in the switched capacitor array adopt a CMOS transmission gate structure.

[0012] Furthermore, the peak voltage feedback module includes: an operational amplifier and a feedback capacitor; the non-inverting input of the operational amplifier is connected to the fixed reference voltage, its inverting input is connected to the output of the switched capacitor array, and its output is connected to its inverting input through the feedback capacitor, serving as the output node of the comparator threshold voltage.

[0013] Furthermore, the comparator includes a pre-amplification and positive feedback stage and an output buffer stage; wherein,

[0014] The pre-amplification and positive feedback stage includes: a fifth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a sixth NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor as tail current sources. The third and fourth NMOS transistors form a differential input pair, and their sources are connected to the drain of the fifth NMOS transistor. The first PMOS transistor is connected between the drain of the third NMOS transistor and the power supply, and the second PMOS transistor is connected between the drain of the fourth NMOS transistor and the power supply. The third PMOS transistor and the sixth NMOS transistor are cross-coupled to form a positive feedback latch, that is, the gate of the third PMOS transistor is connected to the drain of the sixth NMOS transistor, and the gate of the sixth NMOS transistor is connected to the drain of the third PMOS transistor to quickly amplify and lock the state after detecting the input difference, thereby accelerating the comparison toggle process.

[0015] The output buffer stage is connected to the output node of the pre-amplification and positive feedback stage, and is used to shape and drive the comparison result. It includes a fourth PMOS transistor, a fifth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a sixth PMOS transistor, and a ninth NMOS transistor. The fourth and fifth PMOS transistors provide bias voltages. The source of the fourth PMOS transistor is connected to the power supply, and its gate and drain are shorted. The drain of the fourth PMOS transistor is connected to the drain of the first PMOS transistor. The source of the fifth PMOS transistor is connected to the power supply, and its gate is connected to the gate of the fourth PMOS transistor. Its drain is connected to the output voltage VOUT. The seventh and eighth NMOS transistors provide bias voltages. The source of the seventh NMOS transistor is grounded, and its gate and drain are shorted. The seventh NMOS transistor's gate is connected to the gate of the third PMOS transistor, and the eighth NMOS transistor's source is grounded. Its gate and drain are shorted, and its drain is connected to the drain of the fourth NMOS transistor. Its gate is connected to the gate of the sixth NMOS transistor. The branch formed by the ninth NMOS transistor and the sixth PMOS transistor converts the input current into a bias voltage VB. The source of the sixth PMOS transistor is connected to the power supply, and its drain is connected to the drain of the ninth NMOS transistor. The gate and drain of the ninth NMOS transistor are shorted, and its source receives the input current from an external bias circuit. The connection node of the ninth NMOS transistor and the sixth PMOS transistor outputs a bias voltage VB, which is connected to the gate of the fifth NMOS transistor to provide bias for the tail current source. The output buffer stage provides a full-amplitude digital output signal. This comparator structure achieves low latency while its positive feedback mechanism helps reduce noise sensitivity.

[0016] Furthermore, the comparator is a chopper-stabilized comparator, whose non-inverting input and inverting input are respectively connected to the current working branch output of the switched capacitor array and the output of the peak voltage feedback module through a set of analog switches controlled by the two-phase clock signals Φ1 and Φ2.

[0017] A method for stabilizing the oscillation frequency using the relaxation oscillator, comprising:

[0018] Step S1: Use the constant charging current provided by the reference source module to charge the main charging capacitor and the tracking and holding capacitor of the first charging and discharging branch in the switched capacitor array;

[0019] Step S2: The comparator compares the ramp voltage Vramp generated by charging the switched capacitor array with the dynamic threshold voltage Vth output by the peak voltage feedback module. When the dynamic threshold voltage is reached, the logic switching of the digital logic circuit is triggered, the charging of the first charging and discharging branch is stopped, and the constant charging current output by the reference source module is used to charge the main charging capacitor and tracking and holding capacitor of the second charging and discharging branch.

[0020] Step S3: At the moment of switching, the switched capacitor array samples and holds the peak voltage Vpeak on the tracking holding capacitor in the first charge and discharge branch, and sends it to the negative input terminal of the operational amplifier in the peak voltage feedback module. The positive input terminal of the operational amplifier is connected to the fixed reference voltage Vset provided by the reference source module.

[0021] Step S4: The operational amplifier integrates the error voltage between the peak voltage and the fixed reference voltage through its virtual short characteristic and the connected feedback capacitor, and adjusts its output voltage, i.e., the dynamic threshold voltage.

[0022] Step S5: Repeat steps S1 to S4. After several cycles, the sampled peak voltage is locked to the fixed reference voltage Vset to stabilize the oscillation period.

[0023] Compared with the prior art, the present invention has the following advantages:

[0024] (1) By introducing a peak voltage feedback loop, this invention can automatically detect and dynamically compensate for period errors introduced by comparator delay, logic delay, etc., which greatly reduces the sensitivity of the oscillation frequency to power supply voltage changes and temperature drift, and achieves extremely high frequency stability. This architecture simplifies the factors that determine the period from complex expressions that include delay to only those related to RC parameters and the reference, reducing the stringent requirements on high-speed, low-delay comparators and providing room for power consumption optimization.

[0025] (2) This invention combines chopping technology to eliminate the influence of comparator offset, and through a systematic design that optimizes charging current and capacitor parameters (such as increasing the charging slope), it provides an effective way to obtain low phase noise performance. The entire architecture is clearly modular, and all circuits can be implemented using standard CMOS technology, exhibiting good integrability and practicality. Attached Figure Description

[0026] Figure 1 This is a block diagram of the overall system architecture of the relaxation oscillator provided in an embodiment of the present invention.

[0027] Figure 2 This is a detailed circuit diagram of the core components of the invention: the switched capacitor array and the peak voltage feedback module.

[0028] Figure 3 This is a schematic diagram of the ideal operating waveform of the key nodes of the oscillator under steady state after adopting the peak voltage feedback mechanism of the present invention.

[0029] Figure 4 This is a specific circuit implementation diagram of the comparator with positive feedback acceleration function used in this invention.

[0030] Figure 5This is a schematic diagram showing the input connection switching of the chopper-stabilized comparator used in this invention. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this invention clearer, the embodiments of this invention will be described in further detail below with reference to the accompanying drawings. It should be noted that the embodiments of this invention are designed using TSMC 180nm CMOS technology, but this should not be construed as limiting the scope of protection of the invention.

[0032] refer to Figure 1 The high-precision RC relaxation oscillator in this embodiment mainly includes a reference source module VI, a switched capacitor array SC array, a peak voltage feedback module PVF, a comparator CMP, and digital logic circuitry. The reference source module generates a reference voltage Vset of approximately 800mV and a precise charging current Icharge. The entire system operates at a power supply voltage of 1.8V. The switched capacitor array receives the charging current Icharge provided by the reference source module and operates alternately under the control of a two-phase non-overlapping clock signal generated by the digital logic circuit, generating a sawtooth wave voltage signal. The input of the peak voltage feedback module is connected to the tracking node in the switched capacitor array to sample and hold the peak voltage Vpeak of the sawtooth wave voltage signal. Its output is connected to one input of the comparator to provide a dynamically adjusted comparator threshold voltage Vth. The other input of the comparator is connected to the output Vramp of the current operating branch of the switched capacitor array, and its output is connected to the digital logic circuit. The peak voltage feedback module dynamically adjusts the comparator threshold voltage by comparing and integrating the sampled peak voltage with a fixed reference voltage Vset, thereby locking the peak value of the sawtooth wave voltage signal to the fixed reference voltage. Figure 3 .

[0033] refer to Figure 2 The core oscillation circuit is shown in detail. The switched capacitor array consists of two symmetrical structures. Taking the upper branch as an example: (Refer to...) Figure 2Each path includes: a main charging capacitor Cref, one end of which is grounded, and the other end is connected to the output node of the charging current Icharge through a charging switch controlled by a clock signal; a tracking and holding capacitor Cs, connected in parallel with the main charging capacitor Cref, one end of which is grounded, and the other end is connected to the non-grounded terminal of the main charging capacitor through a sampling switch; and a charging switch and a sampling switch controlled by the two non-overlapping first clock signals Φ1 and Φ2; wherein Φ1 controls switches K1, K3, and K5, and Φ2 controls switches K2, K4, and K6, and the capacitance value of the tracking and holding capacitor is smaller than the capacitance value of the main charging capacitor. The first NMOS transistor M1 and the second NMOS transistor M2 form the discharge branch, which is controlled by the OR NOT gate logic output of Φ1 and Φ2 and their delay signals Φ1d and Φ2d.

[0034] The current source that provides the charging current to the switched capacitor array adopts a common source cascode current mirror structure.

[0035] The ratio of the tracking and holding capacitor to the main charging capacitor is 1:4 to ensure that Cs can effectively track and reduce errors caused by charge redistribution. The control switch and sampling switch in the switched capacitor array adopt a CMOS transmission gate structure to reduce on-resistance and improve switching linearity.

[0036] The peak voltage feedback module includes an operational amplifier AMP and an integrating capacitor Cint. The non-inverting input of the operational amplifier is connected to the fixed reference voltage, and its inverting input is selectively connected to one of the tracking and holding capacitors in the switched capacitor array through sampling switches K5 and K6. Its output is connected to its inverting input through the feedback capacitor and serves as the output node of the comparator threshold voltage.

[0037] The positive input of the operational amplifier AMP is connected to Vset. When clock Φ2 is high, the NMOS sampling switch controlled by it is turned on, connecting the voltage Vc1s held on Cs1 to the negative input of the AMP. The output Vth of the AMP serves as the comparator threshold. At the end of each half-cycle, the tracking and holding capacitor Cs of the currently charged branch is disconnected from the main charging capacitor Cref, and the peak voltage Vramp_peak held on it is connected to the inverting input of the operational amplifier AMP through the sampling switch. The output of the operational amplifier AMP is connected to its inverting input through the integrating capacitor Cint, forming an integrator. This output is also provided to the comparator as the dynamic threshold voltage Vth.

[0038] refer to Figure 3 , combined Figure 2 Explain its steady-state operating process:

[0039] During the t0-t1 phase (Φ1=1): the charging current Icharge charges Cref1 and Cs1 through the conducting K1, and Vramp2 rises linearly. The voltage Vc1s on Cs1 synchronously tracks Vramp2.

[0040] At time t1: Vramp2 reaches the current dynamic threshold Vth(n), the comparator CMP starts to flip, and after a short delay td, the digital logic circuit pulls Φ1 low and Φ2 high, entering the next stage.

[0041] During the t1-t2 phase (Φ2=1): K1 is off, K2 is on, and the current redirects to charge Cref2 and Cs2. Simultaneously, the sampling switch K6, controlled by Φ2, is on, sending the peak voltage of Cs1, Vc1s_peak = Vramp2(t1) = Vset + ΔV (where ΔV is caused by the delay td), to the negative terminal of the AMP. Due to the virtual short of the AMP, its negative terminal voltage is forcibly pulled to Vset, causing the charge on Cs1 (corresponding to ΔV) to rapidly transfer to Cint, resulting in a decrease in the AMP output voltage Vth, i.e., Vth(n+1). <Vth(n)。

[0042] At time t2 and beyond: In the new half-cycle, Cref2 starts charging from 0. Due to the lower threshold Vth(n+1), its voltage Vramp1 will reach the threshold in a shorter time, thus compensating for the delay of the previous cycle. After several cycles of adjustment, ΔV approaches zero, Vramp_peak is locked at Vset, and the system enters a steady state. At this time, the oscillation period Tosc = 2 * Cref * Vset / Icharge, which is independent of the delay td.

[0043] refer to Figure 4 A specific circuit diagram of the high-speed comparator CMP used in this invention is provided. This comparator comprises a two-stage structure: a pre-amplifier and positive feedback stage, and an output buffer stage, and introduces internal positive feedback to accelerate switching; wherein...

[0044] The first stage, pre-amplification and positive feedback stage, consists of a differential input pair formed by the third NMOS transistor M12 and the fourth NMOS transistor M13, whose sources are connected to the drain of the tail current source, the fifth NMOS transistor M5. The drains of the input pair transistors are connected to the drains of the load transistors, the first PMOS transistor M6 and the second PMOS transistor M7, respectively. The third PMOS transistor M8 and the sixth NMOS transistor M9 form a cross-coupled positive feedback latch, where the gate of the third PMOS transistor M8 is connected to the drain node B of the sixth NMOS transistor M9, and the gate of the sixth NMOS transistor M9 is connected to the drain node A of the third PMOS transistor M8. This positive feedback mechanism can quickly pull the voltages at nodes A and B to opposite logic levels when the differential input voltage exceeds a certain threshold, thereby greatly accelerating the comparison process. The specific topology is as follows: It includes a fourth PMOS transistor M3, a fifth PMOS transistor M4, a seventh NMOS transistor M10, an eighth NMOS transistor M11, a sixth PMOS transistor M14, and a ninth NMOS transistor M15. The fourth PMOS transistor M3 and the fifth PMOS transistor M4 provide bias voltages. The source of the fourth PMOS transistor M3 is connected to the power supply, and its gate and drain are shorted. The drain of the fourth PMOS transistor M3 is connected to the drain of the first PMOS transistor M6. The source of the fifth PMOS transistor M4 is connected to the power supply, and its gate is connected to the gate of the fourth PMOS transistor M3. Its drain is connected to the output voltage VOUT. The seventh NMOS transistor M10 and the eighth NMOS transistor M11 provide bias voltages. The source of the seventh NMOS transistor M10 is grounded, and its gate and drain are shorted. Its drain is connected to the drain of the third NMOS transistor M12. The gate of the seventh NMOS transistor M10 is connected to the gate of the third PMOS transistor M8. The source of the eighth NMOS transistor M11 is grounded, and its gate and drain are shorted. Its drain is connected to the drain of the fourth NMOS transistor M13, and its gate is connected to the gate of the sixth NMOS transistor M9. The branch formed by the ninth NMOS transistor M15 and the sixth PMOS transistor M14 converts the input current into a bias voltage VB. The source of the sixth PMOS transistor M14 is connected to the power supply, and its drain is connected to the drain of the ninth NMOS transistor M15. The gate and drain of the ninth NMOS transistor M15 are shorted, and its source receives the input current from the external bias circuit. The connection node of the ninth NMOS transistor M15 and the sixth PMOS transistor M14 outputs a bias voltage VB, which is connected to the gate of the fifth NMOS transistor M5 to provide bias for the tail current source.

[0045] The second-stage output buffer includes the fourth PMOS transistor M3, the fifth PMOS transistor M4, the seventh NMOS transistor M10, the eighth NMOS transistor M11, the sixth PMOS transistor M14, and the ninth NMOS transistor M15. The fourth PMOS transistor M3 and the fifth PMOS transistor M4 provide bias voltages. The source of the fourth PMOS transistor M3 is connected to the power supply, and its gate and drain are shorted. The drain of the fourth PMOS transistor M3 is connected to the drain of the first PMOS transistor M6. The source of the fifth PMOS transistor M4 is connected to the power supply, and its gate is connected to the gate of the fourth PMOS transistor M3. Its drain is connected to the output voltage VOUT. The seventh NMOS transistor M10 and the eighth NMOS transistor M11 provide bias voltages. The source of the seventh NMOS transistor M10 is grounded, and its gate and drain are shorted. Its drain is connected to the drain of the third NMOS transistor M12. The gate of the seventh NMOS transistor M10 is connected to the gate of the third PMOS transistor M8. The source of the eighth NMOS transistor M11 is grounded, its gate and drain are shorted, its drain is connected to the drain of the fourth NMOS transistor M13, and its gate is connected to the gate of the sixth NMOS transistor M9. The branch formed by the ninth NMOS transistor M15 and the sixth PMOS transistor M14 converts the input current into a bias voltage VB. The source of the sixth PMOS transistor M14 is connected to the power supply, and its drain is connected to the drain of the ninth NMOS transistor M15. The gate and drain of the ninth NMOS transistor M15 are shorted, and its source receives the input current from the external bias circuit. The connection node of the ninth NMOS transistor M15 and the sixth PMOS transistor M14 outputs a bias voltage VB, which is connected to the gate of the fifth NMOS transistor M5 to provide bias for the tail current source.

[0046] The output stage, consisting of the fifth PMOS transistor M4 and the second PMOS transistor M7, forms an inverter structure to shape and drive the logic level of the first stage output, providing rail-to-rail output swing. The seventh NMOS transistor M10 and the eighth NMOS transistor M11 provide appropriate bias for the output stage.

[0047] This comparator is designed to achieve high-speed, low-latency switching to meet the high-frequency operation requirements of the oscillator, while its internal positive feedback structure helps reduce sensitivity to input noise.

[0048] One input of the comparator is connected to the dynamic threshold voltage Vth, and the other input is connected to the voltage Vramp on the main charging capacitor Cref of the branch currently being charged. When Vramp rises to Vth, the comparator output flips, triggering the digital logic control module to switch the clock phase and end the current half-cycle.

[0049] The system operates as a dynamic adjustment process: due to the inherent delay td in circuits such as the comparator, the capacitor voltage Vramp will exceed the ideal threshold Vset, generating an overshoot voltage Vramp_peak - Vset. This overshoot voltage is sampled by the tracking capacitor Cs and fed into the peak voltage feedback module. The virtual short characteristic of the operational amplifier AMP pulls its inverting input to Vset, forcing the excess charge on Cs to transfer to the integrating capacitor Cint, causing the output voltage Vth of the AMP to drop. The dropped Vth will cause the comparator of the next half-cycle to flip earlier, thus compensating for the delay td of the previous cycle. After several cycles of iterative feedback, the system reaches equilibrium, locking the sampled peak voltage Vramp_peak to the reference voltage Vset, at which point the effect of the delay td is completely canceled out. In steady state, the oscillation period Tosc is determined by the following formula:

[0050] Tosc≈2*Cref*Vset / Icharge

[0051] Frequency stability depends primarily on the stability of Vset and Icharge provided by the reference source, as well as the accuracy of capacitor Cref.

[0052] To eliminate the impact of comparator input offset voltage on frequency accuracy, the comparator is a chopper-stabilized comparator, referenced... Figure 5 Its non-inverting and inverting input terminals are alternately connected to the output of the currently operating branch of the switched capacitor array and the output of the peak voltage feedback module via a set of analog switches controlled by the two-phase clock signal. Φ1 controls switches SW1 and SW2, and Φ2 controls SW3 and SW4. (Reference) Figure 5 This demonstrates the input connection method of a chopper comparator. The comparator CMP itself has a positive input terminal V+ and a negative input terminal V-. A switching network is formed by four analog switches SW1-SW4. When Φ1=1, V+ is connected to Vramp2 and V- is connected to Vth. When Φ2=1, V+ is connected to Vth and V- is connected to Vramp1. In this way, the signal connection relationship of the comparator input terminals is interchanged in adjacent half-cycles, so that the inherent offset voltage Vos has opposite effects on the flip threshold in two consecutive half-cycles (once Vth+Vos, once Vth-Vos), thus canceling each other out during period accumulation.

[0053] In this embodiment, all key switches in the switched capacitor array (such as the sampling switch) employ CMOS transmission gates (parallel NMOS and PMOS transistors). The charging current Icharge is generated by a common-source cascode current mirror in the reference source module, whose specific structure includes series-connected PMOS transistors, ensuring good current matching and high output impedance, and ensuring constant current during charging.

[0054] This embodiment also provides a method for stabilizing the oscillation frequency of a relaxation oscillator based on a switched capacitor array and peak feedback, referencing... Figure 3 The method is characterized by comprising:

[0055] Step S1: Charge the first main charging capacitor and its parallel tracking and holding capacitor using a constant current.

[0056] Step S2: Compare the ramp voltage Vramp generated by charging with a dynamic threshold voltage Vth. When the dynamic threshold voltage is reached, trigger a logic switch to stop charging the first channel and start charging the second main charging capacitor and its parallel tracking and holding capacitor using the constant current.

[0057] Step S3: At the moment of switching, sample and hold the peak voltage Vpeak on the first tracking and holding capacitor, and send it to the negative input terminal of an operational amplifier, the positive input terminal of which is connected to a fixed reference voltage Vset;

[0058] Step S4: The operational amplifier integrates the error voltage between the peak voltage and the fixed reference voltage through its virtual short characteristic and the connected feedback capacitor, thereby adjusting its output voltage, i.e., the dynamic threshold voltage;

[0059] Step S5: Repeat steps S1 to S4. After several cycles, the sampled peak voltage is locked to the fixed reference voltage Vset, thereby stabilizing the oscillation period.

[0060] The comparison process is performed by a chopper comparator, whose two inputs switch their connections with the ramp voltage Vramp and the dynamic threshold voltage Vth in adjacent half-cycles to cancel out the comparator's own input offset voltage.

[0061] When the oscillator of this invention is operating, the voltage of one alternately charged capacitor is compared with a dynamic threshold. At the instant of switching, the peak voltage on the tracking capacitor of the other capacitor is sampled and fed to the feedback module. Through integration, the comparator threshold is dynamically adjusted, ultimately locking the peak capacitor voltage to a fixed reference voltage. This systematically counteracts the influence of non-ideal factors such as comparator delay on the oscillation period. This invention also employs a chopper comparator to eliminate offset. This architecture significantly improves the stability of the oscillation frequency to power supply voltage and temperature, and helps achieve low phase noise, making it suitable for high-precision on-chip clock sources.

[0062] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A relaxation oscillator based on a switched capacitor array and a peak feedback structure, characterized in that, include: Reference source module, switched capacitor array, peak voltage feedback module, comparator and digital logic circuit; The reference source module provides charging current and a fixed reference voltage. The switched capacitor array receives the charging current from the reference source module and operates alternately under the control of a two-phase non-overlapping clock signal generated by the digital logic circuit to generate a sawtooth wave voltage signal. The input of the peak voltage feedback module is connected to the tracking node in the switched capacitor array to sample and hold the peak voltage of the sawtooth wave voltage signal. Its output is connected to one input of the comparator to provide a dynamically adjusted comparator threshold voltage. The other input of the comparator is connected to the output of the current operating branch of the switched capacitor array, and its output is connected to the digital logic circuit. The peak voltage feedback module dynamically adjusts the comparator threshold voltage by comparing and integrating the sampled peak voltage with the fixed reference voltage provided by the reference source module, so that the peak value of the sawtooth wave voltage signal is locked to the fixed reference voltage.

2. The relaxation oscillator according to claim 1, characterized in that, The switched capacitor array includes two symmetrical charging and discharging branches. One charging and discharging branch includes: a first NMOS transistor (M1), a main charging capacitor (Cref1), a tracking and holding capacitor (Cs1), a first control switch (K1), a third control switch (K3), and a first sampling switch (K6). The gate input of the first NMOS transistor (M1) is a NOR gate logic signal of a first clock signal Φ1 and a first clock delay signal Φ1d. The drain terminal of the first NMOS transistor (M1) intersects with one end of the main charging capacitor (Cref1) and one end of the third control switch (K3), and is connected to one end of the first control switch (K1). The other end of the first control switch (K1) is connected to the output node of the charging current Icharge provided by the reference source module. The source terminal of the first NMOS transistor (M1) and the main charging capacitor (Cref1) are connected... The other end is grounded. The other end of the third control switch (K3) intersects with one end of the tracking and holding capacitor (Cs1) and is connected to one end of the first sampling switch (K6). The other end of the tracking and holding capacitor (Cs1) is grounded. The other end of the first sampling switch (K6) is connected to one input terminal of the peak voltage feedback module. The first control switch (K1) and the third control switch (K3) are controlled by the first clock signal Φ1. The first sampling switch (K6) is controlled by the second clock signal Φ2. The gate input in the other charging and discharging branch is a NOR gate logic signal of the second clock signal Φ2 and the second clock delay signal Φ2d. The control switches of the first control switch (K1) and the third control switch (K3) at the corresponding positions in the other charging and discharging branch are controlled by the second clock signal Φ2. The control switches of the first sampling switch (K6) at the corresponding positions are controlled by the first clock signal Φ1.

3. The relaxation oscillator according to claim 2, characterized in that, The capacitance ratio of the tracking and holding capacitor (Cs1) to the main charging capacitor is 1:

4.

4. The relaxation oscillator according to claim 2, characterized in that, The control switches in the switched capacitor array adopt a CMOS transmission gate structure.

5. The relaxation oscillator according to claim 2, characterized in that, The peak voltage feedback module includes: an operational amplifier (AMP) and a feedback capacitor (Cint); the non-inverting input of the operational amplifier is connected to the fixed reference voltage, its inverting input is connected to the output of the switched capacitor array, and its output is connected to its inverting input through the feedback capacitor, serving as the output node of the comparator threshold voltage.

6. The relaxation oscillator according to claim 1, characterized in that, The comparator includes a pre-amplification and positive feedback stage and an output buffer stage; wherein... The pre-amplification and positive feedback stage includes: a fifth NMOS transistor (M5), a first PMOS transistor (M6), a second PMOS transistor (M7), a third PMOS transistor (M8), a sixth NMOS transistor (M9), a third NMOS transistor (M12), and a fourth NMOS transistor (M13) serving as tail current sources. The third NMOS transistor (M12) and the fourth NMOS transistor (M13) form a differential input pair, with their sources connected to the drain of the fifth NMOS transistor (M5). The first PMOS transistor (M6) is connected between the drain of the third NMOS transistor (M12) and the power supply, and the second PMOS transistor (M7) is connected between the drain of the fourth NMOS transistor (M13) and the power supply. The third PMOS transistor (M8) and the sixth NMOS transistor (M9) are cross-coupled to form a positive feedback latch, i.e., the gate of the third PMOS transistor (M8) is connected to the drain of the sixth NMOS transistor (M9), and the gate of the sixth NMOS transistor (M9) is connected to the drain of the third PMOS transistor (M8). The output buffer stage is connected to the output node of the pre-amplification and positive feedback stage, and is used to shape and drive the comparison result. It includes a fourth PMOS transistor (M3), a fifth PMOS transistor (M4), a seventh NMOS transistor (M10), an eighth NMOS transistor (M11), a sixth PMOS transistor (M14), and a ninth NMOS transistor (M15). The fourth PMOS transistor (M3) and the fifth PMOS transistor (M4) provide bias voltages. The source of the fourth PMOS transistor (M3) is connected to the power supply, and its gate and drain are shorted. The drain of the fourth PMOS transistor (M3) is connected to the drain of the first PMOS transistor (M6). The source of the fifth PMOS transistor (M4) is connected to the power supply, and its gate is connected to the gate of the fourth PMOS transistor (M3). Its drain is connected to the output voltage VOUT. The seventh NMOS transistor (M10) and the eighth NMOS transistor (M11) provide bias voltages. The source of the seventh NMOS transistor (M10) is grounded, and its gate and drain are shorted. The drain of the NMOS transistor is connected to the drain of the third NMOS transistor (M12). The gate of the seventh NMOS transistor (M10) is connected to the gate of the third PMOS transistor (M8). The source of the eighth NMOS transistor (M11) is grounded, and its gate and drain are shorted. The drain of the eighth NMOS transistor (M11) is connected to the drain of the fourth NMOS transistor (M13), and its gate is connected to the gate of the sixth NMOS transistor (M9). The branch formed by the ninth NMOS transistor (M15) and the sixth PMOS transistor (M14) converts the input current into a bias voltage VB. The source of the sixth PMOS transistor (M14) is connected to the power supply, and its drain is connected to the drain of the ninth NMOS transistor (M15). The gate and drain of the ninth NMOS transistor (M15) are shorted, and its source receives the input current from the external bias circuit. The connection node of the ninth NMOS transistor (M15) and the sixth PMOS transistor (M14) outputs a bias voltage VB, which is connected to the gate of the fifth NMOS transistor (M5) to provide bias for the tail current source.

7. The relaxation oscillator according to claim 6, characterized in that, The comparator is a chopper-stabilized comparator, whose non-inverting input and inverting input are respectively connected to the current working branch output of the switched capacitor array and the output of the peak voltage feedback module through a set of analog switches controlled by the two-phase clock signals Φ1 and Φ2.

8. A method for stabilizing the oscillation frequency using any one of the relaxation oscillators described in claims 1-7, characterized in that, include: Step S1: Use the constant charging current provided by the reference source module to charge the main charging capacitor and the tracking and holding capacitor of the first charging and discharging branch in the switched capacitor array; Step S2: The comparator compares the ramp voltage Vramp generated by charging the switched capacitor array with the dynamic threshold voltage Vth output by the peak voltage feedback module. When the dynamic threshold voltage is reached, the logic switching of the digital logic circuit is triggered, the charging of the first charging and discharging branch is stopped, and the constant charging current output by the reference source module is used to charge the main charging capacitor and tracking and holding capacitor of the second charging and discharging branch. Step S3: At the moment of switching, the switched capacitor array samples and holds the peak voltage Vpeak on the tracking holding capacitor in the first charge and discharge branch, and sends it to the negative input terminal of the operational amplifier in the peak voltage feedback module. The positive input terminal of the operational amplifier is connected to the fixed reference voltage Vset provided by the reference source module. Step S4: The operational amplifier integrates the error voltage between the peak voltage and the fixed reference voltage through its virtual short characteristic and the connected feedback capacitor, and adjusts its output voltage, i.e., the dynamic threshold voltage. Step S5: Repeat steps S1 to S4. After several cycles, the sampled peak voltage is locked to the fixed reference voltage Vset to stabilize the oscillation period.

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