Dual-input cascode device and method of controlling the same

Abstract

This invention discloses a dual-input cascaded common-source cascode device connected to a controller, comprising a first low-voltage MOSFET, a second low-voltage MOSFET, and a high-voltage MOSFET. The first and second low-voltage MOSFETs are independently controlled by the controller, enabling precise management of the composite cascaded switching device, thereby optimizing its performance under extreme conditions and significantly improving reliability and robustness. This invention also discloses a control method for the dual-input cascaded common-source cascode device under various operating states, including on-state, high-current turn-off, and short-circuit conditions. This method adds "intelligent protection" and "flexible buffering" functions for extreme conditions without sacrificing normal performance. It is particularly suitable for applications requiring high short-circuit tolerance and low turn-off overshoot voltage.

Description

Technical Field

[0001] This invention relates to the field of semiconductor power device technology, specifically to a dual-input common-source cascade device and its control method. Background Technology

[0002] High-voltage MOSFETs are increasingly being used in high-efficiency, high-power-density power electronic converters due to their superior switching speed and low conduction losses. However, traditional high-voltage MOSFETs typically need to be packaged in a cascaded manner with a low-voltage silicon MOSFET to form a normally-off device, as shown in the diagram. Figure 1 As shown.

[0003] In traditional cascaded structures, when a short-circuit fault such as bridge arm shoot-through occurs, its on-resistance is mainly determined by the low-voltage silicon MOSFET. These MOSFETs are typically designed with very high saturation current to achieve extremely low on-resistance. Once a short circuit occurs, a huge DC bus voltage is directly applied across the device, causing the current to surge to an extremely high peak within 1-2 microseconds, generating alarming instantaneous power dissipation. The device can be damaged within a few microseconds due to rapid heat accumulation, posing a severe challenge to system reliability. On the other hand, traditional cascaded devices typically employ extremely fast turn-off speeds to achieve high-speed switching performance. At the instant of turning off a large current, the parasitic inductance of the loop generates a very high induced voltage, which, combined with the DC bus voltage, forms voltage spikes and oscillations that threaten device safety and increase electromagnetic interference (EMI). This often requires complex absorption circuits for suppression.

[0004] Therefore, how to effectively improve the short-circuit withstand time of cascaded devices and suppress turn-off voltage spikes without sacrificing switching performance has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] This invention provides a dual-input common-source cascaded device to solve the problems of short short-circuit withstand time, high voltage spikes and oscillations when turning off from high current in existing cascaded switching devices.

[0006] The present invention also provides a control method for a dual-input common-source cascade device.

[0007] To achieve the objectives of this invention, a dual-input common-source common-gate cascaded device is provided, connected to a controller, comprising a first low-voltage field-effect transistor, a second low-voltage field-effect transistor, and a high-voltage field-effect transistor. The first low-voltage field-effect transistor has low on-resistance. The gate of the first low-voltage field-effect transistor serves as the first gate terminal of the switching device to receive the voltage signal from the controller. The source of the first low-voltage field-effect transistor is connected to the gate of the high-voltage field-effect transistor, and its drain is connected to the source of the high-voltage field-effect transistor. The second low-voltage field-effect transistor has a low saturation current. The gate of the second low-voltage field-effect transistor serves as the second gate terminal of the switching device to receive the voltage signal from the controller. The source of the second low-voltage field-effect transistor is connected to the gate of the high-voltage field-effect transistor, and its drain is connected to the source of the high-voltage field-effect transistor. The gate of the high-voltage field-effect transistor serves as the source terminal of the switching device, and its drain serves as the drain terminal of the switching device.

[0008] Furthermore, the saturation current ratio of the first low-voltage field-effect transistor to the second low-voltage field-effect transistor is 8:1 to 12:1.

[0009] Preferably, the saturation current ratio of the first low-voltage field-effect transistor to the second low-voltage field-effect transistor is 10:1.

[0010] The present invention also provides a control method for the above-mentioned dual-input common-source cascaded device, including a short-circuit current limiting mode: When the switching device is in a short-circuit or overcurrent state, the controller turns off the first low-voltage field-effect transistor by pulling the voltage signal at the first gate terminal down to the off level, and turns on the second low-voltage field-effect transistor by maintaining the voltage signal at the second gate terminal at a high level.

[0011] Furthermore, the short-circuit current of the switching device is the saturation current of the second low-voltage field-effect transistor.

[0012] This invention provides a control method for the aforementioned dual-input cascode cascaded device, including a soft-shutdown control mode: When it is necessary to turn off the switching device from a high current state, the controller turns off the first low-voltage field-effect transistor by pulling the first gate voltage signal down to the off level, and turns on the second low-voltage field-effect transistor by maintaining the second gate voltage signal at a high level; after a preset delay, the controller then pulls the second gate voltage signal down from the high level to the off level, turning off the second low-voltage field-effect transistor.

[0013] Furthermore, the delay time is between 50 nanoseconds and 500 nanoseconds.

[0014] Furthermore, the preset delay time is adjustable to regulate the rate of change of the turn-off current.

[0015] This invention provides a control method for the aforementioned dual-input cascode cascaded device, including an on-mode: When the controller receives the turn-on command, the controller generates two independent gate drive signals. The controller first switches the voltage signal applied to the second gate terminal from low level to high level to turn on the second low-voltage field-effect transistor. After a delay, the controller switches the voltage signal applied to the first gate terminal from low level to high level to turn on the first field-effect transistor.

[0016] The delay time is from 5 nanoseconds to 20 nanoseconds.

[0017] The beneficial effects of this invention are as follows: This invention controls two independent first and second gate terminals through a controller, thereby achieving separate control of the switching of the first and second low-voltage field-effect transistors. This enables precise management of the operating state of the composite cascaded device, and adds "intelligent protection" and "flexible buffering" functions for extreme operating conditions without sacrificing normal performance.

[0018] When a short-circuit fault is detected, the controller immediately shuts off the first low-voltage MOSFET while keeping the second low-voltage MOSFET on, thus actively and quickly clamping the short-circuit current to a safe level preset by the device's own characteristics. This reduces instantaneous power consumption during a short circuit by more than 60%, significantly slows down the chip's temperature rise rate, and extends the device's short-circuit withstand time from the traditional few microseconds to tens of microseconds. This order-of-magnitude improvement provides ample and reliable response time windows for the driver chip protection circuit, digital controller, and even system-level protection, fundamentally avoiding the "inadequate protection" failure mode and greatly enhancing the survivability and overall reliability of the power conversion system under severe faults.

[0019] When a high-current shutdown is required, the controller first turns off the first low-voltage MOSFET while keeping the second low-voltage MOSFET on. Utilizing the saturation characteristics of the second low-voltage MOSFET, a soft landing of the current is achieved initially. After a preset delay, the second low-voltage MOSFET is completely turned off. This process actively and precisely controls the current drop rate during shutdown, thereby suppressing shutdown voltage spikes caused by parasitic inductance within a safe range from the source. This not only reduces reliance on expensive buffer circuits and simplifies system design, but also significantly reduces voltage oscillations and the resulting conducted and radiated EMI, improving the system's electromagnetic compatibility, while avoiding potential device damage due to overvoltage stress.

[0020] Furthermore, during normal conduction, the controller first turns on the second low-voltage MOSFET, then turns on the first low-voltage MOSFET, ensuring that the high-voltage MOSFET can reliably turn on first under any circumstances, achieving normally-off characteristics. Simultaneously, the on-resistances of the first and second low-voltage MOSFETs are in parallel, making the total on-resistance of the composite device essentially equivalent to that of a traditional cascaded structure, thus ensuring low on-state losses and high efficiency for the vast majority of operating times. Attached Figure Description

[0021] Figure 1 This is a circuit diagram of an existing common-source cascaded switching device.

[0022] Figure 2 This is a structural block diagram of the present invention.

[0023] Figure 3 This is a circuit diagram of the present invention.

[0024] Figure 4a This is a schematic diagram of the on-resistance of the first low-voltage field-effect transistor when the switching device of the present invention is turned on.

[0025] Figure 4b This is a schematic diagram of the on-resistance of the second low-voltage field-effect transistor when the switching device of the present invention is turned on.

[0026] Figure 4c This is a schematic diagram of the on-resistance when the switching device of the present invention is turned on.

[0027] Figure 5 This is a timing diagram of the switching device of the present invention being turned off.

[0028] Figure 6 This is a schematic diagram of the current change when the switching device of the present invention is turned off.

[0029] Figure 7 This is a schematic diagram of the current when an existing common-source cascaded switching device is short-circuited.

[0030] Figure 8 This is a schematic diagram of the current when the switching device of the present invention is short-circuited. Detailed Implementation

[0031] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] Please see Figure 2This embodiment provides a dual-input cascode cascaded device 100 connected to a controller 200, which includes a first low-voltage MOSFET 10, a second low-voltage MOSFET 20, and a high-voltage MOSFET 30. The first low-voltage MOSFET 10 and the second low-voltage MOSFET 20 are independently controlled by the controller, enabling precise management of the operating state of the dual-input cascode cascaded device 100. This optimizes its performance under extreme conditions, significantly improving reliability and robustness, and is particularly suitable for applications requiring high short-circuit withstand capability and low turn-off overshoot voltage.

[0033] like Figure 2 , Figure 3 As shown, the first low-voltage MOSFET 10 serves as the main current path and is connected to both the controller 200 and the high-voltage MOSFET 30. It is preferably an enhancement-mode silicon-based MOSFET with low on-resistance, providing the lowest possible on-state voltage drop to minimize conduction losses when the dual-input cascaded device 100 is normally turned on. The second low-voltage MOSFET 20 acts as an adjustable "valve," connected to both the controller 200 and the high-voltage MOSFET 30. It is preferably an enhancement-mode silicon-based MOSFET with low saturation current. The saturation current ratio of the first low-voltage MOSFET 10 to the second low-voltage MOSFET 20 is 8:1 to 12:1. In this embodiment, the saturation current ratio is 10:1. Through the specific transconductance characteristics of the second low-voltage MOSFET 20, the saturation current can be limited to a preset safe level under a specific gate-source voltage. The high-voltage field-effect transistor 30 is connected to the first low-voltage field-effect transistor 10 and the second low-voltage field-effect transistor 20, respectively. It is preferably a depletion-type gallium nitride high electron mobility transistor (GaN HEMT), which has high breakdown voltage, high electron mobility and fast inherent switching characteristics, and constitutes the high-voltage main switching channel of the device.

[0034] Specifically, such as Figure 2 , Figure 3 As shown, the gate of the first low-voltage MOSFET 10 serves as the first gate terminal of the dual-input cascaded device 100, used to receive the first gate drive voltage signal from the controller 200. The source of the first low-voltage MOSFET 10 is connected to the gate of the high-voltage MOSFET 30, and its drain is connected to the source of the high-voltage MOSFET 30. The gate of the second low-voltage MOSFET 20 serves as the second gate terminal of the dual-input cascaded device 100, used to receive the second gate drive voltage signal from the controller 200. The source of the second low-voltage MOSFET 20 is connected to the gate of the high-voltage MOSFET 30, and its drain is connected to the source of the high-voltage MOSFET 30. The gate of the high-voltage MOSFET 30 serves as the source terminal of the dual-input cascaded device 100, and its drain serves as the drain terminal of the dual-input cascaded device 100.

[0035] When the dual-input common-source common-gate cascaded device 100 is operating normally, it is required to achieve efficient power transfer and ensure that it has on-state performance that competes with traditional cascaded devices. Specifically, when the controller 200 receives the turn-on command, it generates two corresponding gate drive signals, and then simultaneously switches the voltage signals applied to the first gate terminal of the first low-voltage field-effect transistor 10 and the second gate terminal of the second low-voltage field-effect transistor 20 from low level to high level, so that the first low-voltage field-effect transistor 10 and the second low-voltage field-effect transistor 20 are turned on synchronously and quickly.

[0036] In some embodiments, the controller 200 may first switch the voltage signal applied to the second gate terminal from a low level to a high level, turning on the second low-voltage field-effect transistor 20. After a delay, the controller then switches the voltage signal applied to the first gate terminal from a low level to a high level, turning on the first field-effect transistor 10, to ensure that the high-voltage field-effect transistor 30 can reliably turn on first under any circumstances. It should be noted that the delay time for turning on the second low-voltage field-effect transistor 20 and the first low-voltage field-effect transistor 10 needs to be sufficiently small, for example, it can be 5 nanoseconds to 20 nanoseconds, so that its impact on switching losses and efficiency is negligible. When the first low-voltage MOSFET 10 and the second low-voltage MOSFET 20 are turned on, current flows through the channel of the first low-voltage MOSFET 10 and then through the channel of the second low-voltage MOSFET 20. Since both the first low-voltage MOSFET 10 and the second low-voltage MOSFET 20 are in a low-resistance state, the on-resistance of the entire dual-input cascaded device 100 is very small (the resistance formed by the parallel connection of the on-resistance of the first low-voltage MOSFET 10 and the on-resistance of the second low-voltage MOSFET 20) (e.g. Figure 4a , Figure 4b and Figure 4c As shown in the figure, the horizontal axis represents the gate drive voltage of the low-voltage MOSFET, and the vertical axis represents the on-resistance of the device under different gate voltages. In this state, the overall conduction loss of the dual-input cascaded device 100 is comparable to that of a conventional cascaded structure, ensuring high efficiency during normal operation without any additional conduction loss disadvantage.

[0037] When it is necessary to turn off the dual-input cascode cascaded device 100 from a high-current state, the voltage stress and electromagnetic interference problems caused by excessively fast turn-off in traditional high-speed switching devices are solved by actively managing the turn-off transient. Specifically, after receiving the turn-off command, the controller 200 turns off the first low-voltage MOSFET 10 and the second low-voltage MOSFET 20 according to a preset two-step turn-off sequence. The first step is to turn off the first low-voltage MOSFET 10. Figure 5As shown, at time t0, the controller 200 first rapidly pulls the voltage signal applied to the first gate terminal from a high level to its off level, turning off the first low-voltage field-effect transistor 10. Simultaneously, the controller 200 maintains the voltage signal applied to the second gate terminal at a high level, ensuring that the second low-voltage field-effect transistor 20 remains fully on. The second step is to turn off the second low-voltage field-effect transistor 20. After turning off the first low-voltage field-effect transistor 10, the controller 200 initiates a preset delay Δt. This delay can be set according to actual needs and is adjustable to regulate the rate of change of the turn-off current. In this embodiment, Δt ranges from 50 nanoseconds to 500 nanoseconds. After this delay, at time t1, the controller 200 then pulls the voltage signal at the second gate terminal from a high level to the off level, completely turning off the second low-voltage field-effect transistor 20.

[0038] like Figure 5 , Figure 6 As shown, before t0, the dual-input cascaded device 100 is fully on, and the load current mainly flows through the low-resistance path, specifically: high-voltage MOSFET 30 - first low-voltage MOSFET 10 and second low-voltage MOSFET 20. During t0-t1, the first low-voltage MOSFET 10 is turned off, and its channel resistance rapidly becomes extremely high, cutting off the original low-resistance main current path. The load current is entirely transferred to the series path formed by the high-voltage MOSFET 30 and the second low-voltage MOSFET 20. Since the gate of the second low-voltage MOSFET 20 is still fully driven, the operating point of the second low-voltage MOSFET 20 moves from the fully on region to the saturation region, resulting in a rapid rise in the drain voltage of the second low-voltage MOSFET 20. The second low-voltage MOSFET 20 behaves as a current source in its saturation region, and its maximum current is clamped by its inherent saturation current characteristics. Therefore, the load current rapidly decreases from its original high value and is precisely limited to near the preset saturation current value of the second low-voltage MOSFET 20. This process achieves a "soft landing" from high current to a lower, stable current. The rate of current change in the first stage is significantly reduced; as shown by the formula V = L * di / dt, the turn-off voltage spike caused by the parasitic inductance is greatly reduced. At time t1, the gate voltage of the second low-voltage MOSFET 20 is removed, and its channel begins to turn off. At this point, the current drops from the saturation current value of the second low-voltage MOSFET 20 to zero. Since the initial current value has already decreased significantly, the final rate of current change di / dt is very small, and the current smoothly decreases to zero, completing the entire turn-off process.

[0039] This embodiment employs a two-stage turn-off mechanism, first turning off the first low-voltage MOSFET 10 and then turning off the second low-voltage MOSFET 20. The total voltage spike is decomposed into the sum of contributions from the two stages, and the di / dt of each stage is significantly suppressed, thereby achieving a smooth and reliable turn-off and greatly improving the turn-off stability of the switching device.

[0040] When a short circuit occurs, the current flowing through the dual-input common-source cascade device 100 will rise sharply. Traditional single-transistor or conventional cascaded devices have very high saturation currents and will withstand enormous currents and power during a short circuit (e.g., Figure 7 As shown at point S1, the temperature rises sharply, typically causing damage within microseconds. To address this issue, in this embodiment, upon detecting a short-circuit fault, the controller 200 switches from normal operating mode to active short-circuit current limiting mode. At this time, the controller 200 pulls the voltage signal applied to the first gate terminal low to the off level, rapidly turning off the first low-voltage MOSFET 10. Simultaneously, the controller 200 ensures that the voltage signal applied to the second gate terminal remains high, keeping the second low-voltage MOSFET 20 fully on.

[0041] like Figure 8 As shown, since the first low-voltage MOSFET 10 is turned off, the low-resistance current path is completely removed, and the current is forced to flow through the series path formed by the high-voltage MOSFET 30 and the second low-voltage MOSFET 20. Because the second low-voltage MOSFET 20 has a low saturation current, its drain voltage rises rapidly under short-circuit conditions, causing it to immediately operate in the saturation region (e.g., ...). Figure 8 (Point S2 shown). At this time, the short-circuit current I of the dual-input cascaded device 100 is... SC_limited The current is no longer determined by the external circuit and the high-voltage field-effect transistor 30, but is clamped by the saturation current characteristics of the second low-voltage field-effect transistor 20, that is: I SC_limited ≈I dsat2 ; Among them, I SC_limited I is the short-circuit current of the dual-input cascode cascaded device 100. dsat2 This is the saturation current of the second low-voltage field-effect transistor 20.

[0042] Through design, I dsat2 It can be set to a safe value that is much lower than the short-circuit current of conventional devices, for example, only 2-4 times the rated current, or accurately calculated based on the thermal design capacity. In this embodiment, the saturation current of the second low-voltage field-effect transistor 20 is only 1 / 10 of the saturation current of the first low-voltage field-effect transistor 10.

[0043] During a short circuit, the power consumed by the dual-input cascaded device 100 is mainly converted into heat. The limited short-circuit power is: P SC_limited =V bus ×I SC_limited； Among them, P SC_limited V represents the limited short-circuit power. bus The voltage of the switching device, due to I SC_limitedMuch smaller than the I of traditional devices SC Therefore P SC_limited This also significantly reduces the rate of temperature rise compared to the same period last year (e.g., by 60%-80%). According to the heat capacity formula, the rate of temperature rise of the chip is proportional to the instantaneous power consumption. Therefore, the rate of temperature rise is significantly reduced compared to the same period last year. This allows the time from the start of a short circuit to reaching the dangerous junction temperature, i.e., the Short Circuit Withstand Time (SCWT), of the dual-input cascaded device 100 can be significantly extended. Experimental data shows that the SCWT can be extended from 3-5 microseconds in the conventional structure to 20-50 microseconds or even longer in this invention. The extended SCTW provides a crucial time margin for the protection levels of the entire system: for example, it allows the protection circuits such as desaturation detection and overcurrent comparators in the driver chip sufficient time (usually 5-15μs to complete detection and logic judgment) to confirm the fault and issue a shutdown command, thereby ensuring reliable operation of the protection circuit. At the same time, the controller 200 can execute a safe shutdown sequence in an orderly manner after confirming the fault (e.g., shutting down the faulty phase first, and then shutting down other phases), avoiding voltage overshoot caused by hasty shutdown. In addition, more complex fault handling strategies such as "multiple attempts" or "pulse current limiting" can be introduced to enable advanced protection, distinguish between transient disturbances and permanent faults, and further improve system availability.

[0044] Therefore, when a short circuit occurs, because the saturation current of the second low-voltage MOSFET 20 is designed to be low, even if the output is short-circuited, the current of the entire dual-input cascaded device 100 will be limited to near the saturation current value of the second low-voltage MOSFET 20, and will not increase indefinitely. The heat loss generated by the limited short-circuit current is much smaller than that of conventional devices, thus greatly slowing down the device's temperature rise rate. This provides a longer response time for protection circuits, such as the short-circuit detection and shutdown mechanism of the driver chip, thereby improving the system's reliability under short-circuit conditions.

[0045] Although the present invention has been disclosed through the above embodiments, the scope of protection of the present invention is not limited thereto. Any modifications or substitutions made to the above components without departing from the concept of the present invention shall fall within the scope of the claims of the present invention.

Claims

1. A dual-input common-source common-gate cascaded device, connected to a controller, characterized in that, Including a first low-voltage field-effect transistor, a second low-voltage field-effect transistor, and a high-voltage field-effect transistor. The first low-voltage field-effect transistor has low on-resistance. The gate of the first low-voltage field-effect transistor serves as the first gate terminal of the switching device to receive the voltage signal from the controller. The source of the first low-voltage field-effect transistor is connected to the gate of the high-voltage field-effect transistor, and its drain is connected to the source of the high-voltage field-effect transistor. The second low-voltage field-effect transistor has a low saturation current. The gate of the second low-voltage field-effect transistor serves as the second gate terminal of the switching device to receive the voltage signal from the controller. The source of the second low-voltage field-effect transistor is connected to the gate of the high-voltage field-effect transistor, and its drain is connected to the source of the high-voltage field-effect transistor. The gate of the high-voltage field-effect transistor serves as the source terminal of the switching device, and its drain serves as the drain terminal of the switching device. The operating modes of the dual-input common-source cascade device include short-circuit current limiting mode, soft-turn-off control mode, and conduction mode. The controller switches the operating modes by switching the turn-off and conduction states of the first low-voltage MOSFET and the second low-voltage MOSFET respectively.

2. The dual-input common-source cascaded device as described in claim 1, characterized in that, The saturation current ratio between the first low-voltage field-effect transistor and the second low-voltage field-effect transistor is 8:1 to 12:

1.

3. The dual-input common-source cascaded device as described in claim 2, characterized in that, The saturation current ratio of the first low-voltage field-effect transistor to the second low-voltage field-effect transistor is 10:

1.

4. A control method for a dual-input common-source cascaded device as described in any one of claims 1 to 3, characterized in that, Including short-circuit current limiting mode: When the switching device is in a short-circuit or overcurrent state, the controller turns off the first low-voltage field-effect transistor by pulling the voltage signal at the first gate terminal down to the off level, and turns on the second low-voltage field-effect transistor by keeping the voltage signal at the second gate terminal high.

5. The method as described in claim 4, characterized in that, The short-circuit current of the switching device is the saturation current of the second low-voltage field-effect transistor.

6. A control method for a dual-input cascaded device as described in any one of claims 1 to 3, characterized in that, Including soft shutdown control mode: When it is necessary to turn off the switching device from a high current state, the controller turns off the first low-voltage field-effect transistor by pulling the first gate voltage signal down to the turn-off level, and turns on the second low-voltage field-effect transistor by maintaining the second gate voltage signal at a high level. After a preset delay, the controller pulls the voltage signal at the second gate terminal down from a high level to a turn-off level, thereby turning off the second low-voltage field-effect transistor.

7. The method as described in claim 6, characterized in that, The delay time is from 50 nanoseconds to 500 nanoseconds.

8. The method as described in claim 7, characterized in that, The preset delay time is adjustable to regulate the rate of change of the turn-off current.

9. A control method for a dual-input common-source cascaded device as described in any one of claims 1 to 3, characterized in that, Including conduction modes: When the controller receives the turn-on command, the controller generates two independent gate drive signals. The controller first switches the voltage signal applied to the second gate terminal from low level to high level to turn on the second low-voltage field-effect transistor. After a delay, the controller switches the voltage signal applied to the first gate terminal from low level to high level to turn on the first field-effect transistor.

10. The method as described in claim 9, characterized in that, The delay time is from 5 nanoseconds to 20 nanoseconds.

Images