Method of fabricating a semiconductor structure
By using isotropic etching gases with different selectivity ratios to gradually etch the floating gate layer and the inter-gate dielectric layer, the problem of oxide and nitride residues in the NOR Flash process was solved, and the chip yield was improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUALI INTEGRATED CIRCUIT CORP
- Filing Date
- 2026-03-30
- Publication Date
- 2026-06-23
Smart Images
Figure CN122269705A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit manufacturing technology, and in particular to a method for fabricating a semiconductor structure. Background Technology
[0002] In NOR flash memory technology, an etching process is required to remove the floating gate layer and inter-gate dielectric layer in the peripheral device area. Currently, the typical NOR flash process includes the following steps for etching the floating gate layer and inter-gate dielectric layer:
[0003] (1) Provide a silicon wafer that has formed an active region (AA), shallow trench isolation (STI), floating gate layer and inter-gate dielectric layer structure, and perform photolithography to open the part that needs to be etched;
[0004] (2) Breakthrough step: Use anisotropic gas with no selectivity to etch the inter-gate dielectric layer;
[0005] (3) Main etch: Use low selectivity gas to etch the floating gate layer;
[0006] (4) Overetch: Use a gas with a high selectivity to etch the residual floating gate layer;
[0007] (5) Remove photoresist.
[0008] However, in some special NOR Flash products, due to the height difference between the floating gate layer and the STI, the inter-gate dielectric layer will also be deposited on the side of the floating gate layer. After etching, oxide and nitride residues in the inter-gate dielectric layer will appear, resulting in a high horn of the STI. After subsequent wet cleaning, material peeling and contaminant residues are likely to occur, which will directly affect the chip yield. Summary of the Invention
[0009] The purpose of this application is to provide a method for fabricating a semiconductor structure, which solves the problems of residual oxides and nitrides in the inter-gate dielectric layer on the side of the floating gate layer after etching in some special NOR Flash products in the prior art, as well as the further STI horn problem, and the problems of material delamination and contaminant residue after subsequent wet cleaning.
[0010] To address the aforementioned technical problems, this application provides a method for fabricating a semiconductor structure, which may include at least the following steps:
[0011] A substrate is provided, the substrate including a peripheral device region, a plurality of shallow trench isolation structures are formed in the substrate, a floating gate layer and an inter-gate dielectric layer are formed on the substrate, the top surface of the floating gate layer is higher than the top surface of the shallow trench isolation structure, the inter-gate dielectric layer covers the top surface and side surface of the floating gate layer, and the inter-gate dielectric layer has an oxide-nitride-oxide structure.
[0012] A first etching process is performed on the inter-gate dielectric layer of the peripheral device region using an isotropic etching gas with a first selectivity, such that after the first etching process is completed, some oxide in the inter-gate dielectric layer remains on the side of the floating gate layer, and the first selectivity is the selectivity between the inter-gate dielectric layer and the floating gate layer.
[0013] A second etching process is performed on the floating gate layer of the peripheral device region using an etching gas with a second selectivity ratio to partially remove the floating gate layer, the oxide in the remaining inter-gate dielectric layer, and the shallow trench isolation structure, so as to fully expose the oxide in the remaining inter-gate dielectric layer. The shallow trench isolation structure forms a bull's horn in the region near the floating gate layer. The second selectivity ratio is the selectivity ratio between the floating gate layer and the oxide in the inter-gate dielectric layer or the oxide in the shallow trench isolation structure.
[0014] A third etching process is performed on the floating gate layer, the bullhorn, and the shallow trench isolation structure of the peripheral device region using an isotropic etching gas with a third selectivity to remove the bullhorn, and the top surfaces of the floating gate layer and the shallow trench isolation structure are flush. The third selectivity is the selectivity between the floating gate layer and the oxide in the bullhorn or the shallow trench isolation structure.
[0015] Furthermore, after performing the third etching process, the process also includes:
[0016] A fourth etching process is performed on the floating gate layer of the peripheral device region using an etching gas with a fourth selectivity ratio to completely remove the floating gate layer. The fourth selectivity ratio is the selectivity ratio between the floating gate layer and the oxide in the shallow trench isolation structure.
[0017] Furthermore, the fourth selection ratio is greater than the second selection ratio, the second selection ratio is greater than the first selection ratio, and the first selection ratio is equal to the third selection ratio.
[0018] Furthermore, the isotropic etching gas having a first selectivity includes a mixture of CF4 and O2.
[0019] Furthermore, the etching gas of the second selectivity includes a mixture of SF6 and CH2F2.
[0020] Furthermore, the isotropic etching gas with a third selectivity includes a mixture of CF4 and O2.
[0021] Furthermore, the fourth selectivity of the etching gas includes a mixture of HBr and O2.
[0022] Furthermore, the semiconductor structure is either flash memory or not.
[0023] Furthermore, the material of the floating gate layer includes polycrystalline silicon and amorphous silicon.
[0024] Furthermore, after performing the second etching process, the top surface of the floating gate layer is level with or lower than the top surface of the shallow trench isolation structure.
[0025] Compared with the prior art, the technical solution of this application has at least one of the following beneficial effects:
[0026] In the semiconductor structure fabrication method provided in this application, a first etching process is performed on the inter-gate dielectric layer of the peripheral device region using an isotropic etching gas with a first selectivity ratio. After the first etching process is completed, only a small amount of oxide remains on the side of the floating gate layer, with no nitride residue, which facilitates subsequent removal. Then, a second etching process is performed on the floating gate layer of the peripheral device region using an etching gas with a second selectivity ratio to partially remove the floating gate layer, the oxides in the remaining inter-gate dielectric layer, and the shallow trench isolation structure, so that the oxides in the remaining inter-gate dielectric layer are fully exposed, and the shallow trench isolation forms a horn shape in the region near the floating gate layer. Finally, a third etching process is performed on the floating gate layer, the horn shape, and the shallow trench isolation of the peripheral device region using an isotropic etching gas with a third selectivity ratio to remove the horn shape, making the shallow trench isolation basically flat, avoiding material delamination and contaminant residue after subsequent wet cleaning, which would affect the chip yield.
[0027] Furthermore, a fourth etching process is performed on the floating gate layer of the peripheral device region using an etching gas with a fourth selectivity ratio to completely remove the floating gate layer and ensure that no floating gate layer residue remains. Attached Figure Description
[0028] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings:
[0029] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application;
[0030] Figures 2-6This is a schematic diagram of the fabrication process of a semiconductor structure fabrication method provided in one embodiment of this application.
[0031] in, Figures 2-6 The specific reference numerals in the attached figures are as follows:
[0032] 100 - Substrate; 101 - Shallow trench isolation structure; 102 - Tunneling oxide layer; 103 - Floating gate layer; 104 - Inter-gate dielectric layer; 104a - Residual oxide / horn.
[0033] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation
[0034] To make the technical solutions and advantages of the embodiments of this application clearer, the technical solutions of this application will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this application are shown in the accompanying drawings, it should be understood that this application can be implemented in various forms and should not be limited to the implementation methods described herein. Rather, these implementation methods are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.
[0035] The present application is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present application will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and are only used to facilitate and clarify the illustration of the embodiments of the present application. It is understood that the meanings of "on," "above," and "over" in the present application should be interpreted in the broadest sense, such that "on" not only means "on" something without any intervening feature or layer (i.e., directly on something), but also includes "on" something with an intervening feature or layer. In the embodiments of the present application, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of the present application can be arbitrarily combined without conflict.
[0036] As described in the background section, in the NOR Flash process, an etching process is required to remove the floating gate layer and inter-gate dielectric layer in the peripheral device area. However, in some special NOR Flash products, due to the height difference between the floating gate layer and the STI (Surface Mount Technology), the inter-gate dielectric layer will also be deposited on the side of the floating gate layer. After etching, oxide and nitride residues in the inter-gate dielectric layer will appear, resulting in a high degree of angularity in the STI. Subsequent wet cleaning is prone to material delamination and contaminant residue, which will directly affect the chip yield.
[0037] To address the above issues, this application proposes an improved solution: First, an isotropic etching gas with a first selectivity ratio is used to perform a first etching process on the inter-gate dielectric layer of the peripheral device region. After the first etching process, only a small amount of oxide remains on the side of the floating gate layer, with no nitride residue, facilitating subsequent removal. Then, a second etching process is performed on the floating gate layer of the peripheral device region using an etching gas with a second selectivity ratio to partially remove the floating gate layer, the oxides in the remaining inter-gate dielectric layer, and the shallow trench isolation structure. This fully exposes the oxides in the remaining inter-gate dielectric layer, and the shallow trench isolation forms a horn shape in the region near the floating gate layer. Finally, a third etching process is performed on the floating gate layer, the horn shape, and the shallow trench isolation in the peripheral device region using an isotropic etching gas with a third selectivity ratio to remove the horn shape, making the shallow trench isolation essentially flat and preventing material delamination and contaminant residue after subsequent wet cleaning, which could affect chip yield.
[0038] refer to Figure 1 , Figure 1 This is a schematic flowchart illustrating the method for fabricating the semiconductor structure provided in the embodiments of this application; as shown Figure 1 As shown, the method for fabricating the semiconductor structure may include the following steps:
[0039] Step S101: Provide a substrate, the substrate including a peripheral device region, a plurality of shallow trench isolation structures formed in the substrate, a floating gate layer and an inter-gate dielectric layer formed on the substrate, the top surface of the floating gate layer being higher than the top surface of the shallow trench isolation structure, the inter-gate dielectric layer covering the top surface and side surface of the floating gate layer, the inter-gate dielectric layer having an oxide-nitride-oxide structure;
[0040] Step S102: A first etching process is performed on the inter-gate dielectric layer of the peripheral device region using an isotropic etching gas with a first selectivity, so that after the first etching process is completed, some oxide in the inter-gate dielectric layer remains on the side of the floating gate layer. The first selectivity is the selectivity between the inter-gate dielectric layer and the floating gate layer.
[0041] Step S103: A second etching process is performed on the floating gate layer of the peripheral device region using an etching gas with a second selectivity ratio to partially remove the floating gate layer, the oxide in the remaining inter-gate dielectric layer, and the shallow trench isolation structure, so that the oxide in the remaining inter-gate dielectric layer is fully exposed. The shallow trench isolation structure forms a bull's horn in the region near the floating gate layer. The second selectivity ratio is the selectivity ratio between the floating gate layer and the oxide in the inter-gate dielectric layer or the oxide in the shallow trench isolation structure.
[0042] Step S104: A third etching process is performed on the floating gate layer, the bullhorn, and the shallow trench isolation structure of the peripheral device region using an isotropic etching gas with a third selectivity ratio to remove the bullhorn, and the top surfaces of the floating gate layer and the shallow trench isolation structure are flush. The third selectivity ratio is the selectivity ratio between the floating gate layer and the oxide in the bullhorn or the shallow trench isolation structure.
[0043] Step S105: A fourth etching process is performed on the floating gate layer of the peripheral device region using an etching gas with a fourth selectivity ratio to completely remove the floating gate layer. The fourth selectivity ratio is the selectivity ratio between the floating gate layer and the oxide in the shallow trench isolation structure.
[0044] The method for fabricating the semiconductor structure proposed in this application will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this application will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this application. Many specific details are set forth in the following description to provide a thorough understanding of this application; however, this application may also be implemented in other ways different from those described herein, and therefore this application is not limited to the specific embodiments disclosed below.
[0045] In this embodiment, the semiconductor structure is either NOR flash memory or not, see [reference]. Figure 2In step S101 above, a substrate 100 is first provided. The substrate 100 includes a memory cell region (not shown) and a peripheral device region 100b. Specifically, the substrate 100 can be any suitable substrate material known in the art, such as at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors. It can also include multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). Alternatively, it can be a double-sided polished wafer (DSP), or a ceramic substrate such as alumina, a quartz substrate, or a glass substrate. Exemplarily, the substrate 100 in this embodiment is preferably a silicon wafer. Multiple shallow trench isolation structures 101 are formed within the substrate 100 to define multiple active regions. A tunneling oxide layer 102, a floating gate layer 103, and an inter-gate dielectric layer 104 are formed on the substrate 100. The top surface of the floating gate layer 103 is higher than the top surface of the shallow trench isolation 101. The inter-gate dielectric layer 104 covers the top and side surfaces of the floating gate layer 103. The tunneling oxide layer 102 is located below the floating gate layer 103. The thickness of the tunneling oxide layer 102 in the vertical direction ranges from 7.5 nm to 9.5 nm, and the material includes silicon dioxide. The thickness of the inter-gate dielectric layer 104 ranges from 9 nm to 12 nm and has an oxide-nitride-oxide structure. To simplify the drawings, the drawings in this embodiment only show the inter-gate dielectric layer 104 as a single film layer. The thickness of the floating gate layer 103 in the vertical direction ranges from 130nm to 150nm. The material includes polycrystalline silicon and amorphous silicon, and may be doped with elements such as carbon and phosphorus. To simplify the drawings, the peripheral device region 100b in the drawings of this embodiment contains only one active region, but in other embodiments, the peripheral device region 100b may contain multiple active regions.
[0046] Following step S101 above, the method for fabricating a semiconductor structure provided in this application embodiment further includes:
[0047] Step S101.1: A layer of positive photoresist is coated on the inter-gate dielectric layer 104. Then, the substrate 100 is loaded into a photolithography machine for alignment and exposure. Finally, the exposed substrate 100 is sent to a developing machine to remove the photoresist on the peripheral device region 100b by developing, while retaining the photoresist on the memory cell region to withstand the physicochemical attack of the memory cell region by subsequent etching processes.
[0048] See Figure 3 In step S102 above, an isotropic etching gas with a first selectivity is used to perform a first etching process on the inter-gate dielectric layer 104 of the peripheral device region 100b, so that after the first etching process is completed, the oxide in the inter-gate dielectric layer 104 has some residue on the side of the floating gate layer 103, i.e., residual oxide 104a, but no nitride residue, which is convenient for subsequent removal; wherein, the first selectivity is the selectivity ratio between the inter-gate dielectric layer 104 and the floating gate layer 103, and the first selectivity is preferably no selectivity, i.e., selectivity ≈ 1:1; the isotropic etching gas with the first selectivity is preferably a mixture of CF4 and O2. During the first etching process, a large number of neutral free radicals (e.g., fluorine free radicals) are generated. The nitrides (e.g., silicon nitride) in the inter-gate dielectric layer 104 react with the fluorine free radicals to generate SiF4 and N2. N2 is a gas and is highly volatile, so it will not remain on the surface. The oxides (e.g., silicon oxide) in the inter-gate dielectric layer 104 react with the fluorine free radicals to generate SiF4 and O. On the top surface of the floating gate layer 103, these oxygen atoms quickly combine to form oxygen and are removed. However, on the bottom side of the floating gate layer 103, the oxygen atoms do not have time to combine to form oxygen and are likely to be re-adsorbed onto the bottom side of the floating gate layer 103, forming a passivation layer. This prevents the fluorine free radicals from contacting the silicon oxide under the passivation layer, causing the etching rate of silicon oxide to drop sharply or even stop. As a result, after the first etching process is completed, a small amount of oxide remains on the bottom side of the floating gate layer 103, i.e., residual oxide 104a, while no nitride remains.
[0049] See Figure 4In step S103 above, a second etching process is performed on the floating gate layer 103 of the peripheral device region 100b using an etching gas with a second selectivity ratio, partially removing the oxides in the floating gate layer 103, the residual inter-gate dielectric layer 104, and the shallow trench isolation structure 101, so that the residual oxides 104a are fully exposed. The shallow trench isolation structure 101 forms horns 104a in the region near the floating gate layer 103. The second selectivity ratio is the selectivity ratio between the floating gate layer 103 and the oxides in the inter-gate dielectric layer 104 or the oxides in the shallow trench isolation structure 101. The range of the second selectivity ratio is greater than 1:1 and less than or equal to 2:1. The etching gas with the second selectivity ratio is preferably a mixture of SF6 and CH2F2. In this embodiment, after performing the second etching process, the top surface of the floating gate layer 103 is flush with the top surface of the shallow trench isolation structure 101. However, in other embodiments, the top surface of the floating gate layer 103 may be lower than the top surface of the shallow trench isolation structure 101. After performing the second etching process, the thickness of the floating gate layer 103 in the vertical direction ranges from 40nm to 60nm. In the second etching process, it is essential to ensure that the residual oxide 104a is fully exposed. This is because only when there are no obstructions on either side of the residual oxide 104a will the residual oxide 104a be gradually etched flat in subsequent step S104. If the floating gate layer 103 partially blocks the residual oxide 104a, the etching rate of the blocked residual oxide 104a will be similar to the etching rate of the shallow trench isolation structure 101, and it will only be pushed downwards along with the shallow trench isolation structure 101, unable to be gradually etched flat.
[0050] See Figure 5 In step S104 above, an isotropic etching gas with a third selectivity is used to perform a third etching process on the floating gate layer 103, the bullhorn 104a, and the shallow trench isolation structure 101 of the peripheral device region 100b to remove the bullhorn 104a. The top surfaces of the floating gate layer 103 and the shallow trench isolation structure 101 are flush. The third selectivity is the selectivity between the floating gate layer 103 and the oxide in the bullhorn 104a or the shallow trench isolation structure 101. The third selectivity is preferably no selectivity, i.e., selectivity ≈ 1:1. The isotropic etching gas with a third selectivity is preferably a mixture of CF4 and O2. Because an isotropic etching gas with a third selectivity is used for etching, the floating gate layer 103 on both sides of the bull's horn 104a and the shallow trench isolation structure 101 will be etched and pushed down equally, so the bull's horn 104a will always be exposed and slowly be etched flat.
[0051] See Figure 6In step S105 above, a fourth etching process is performed on the floating gate layer 103 of the peripheral device region 100b using an etching gas with a fourth selectivity ratio to completely remove the floating gate layer 103. The fourth selectivity ratio is the ratio between the floating gate layer 103 and the oxide in the shallow trench isolation structure 101, and the range of the fourth selectivity ratio is greater than or equal to 5:1. The etching gas with the fourth selectivity ratio is preferably a mixture of HBr and O2. Because the etching rate for the floating gate layer 103 is greater than the etching rate for the shallow trench isolation structure 101, the floating gate layer 103 can be completely removed.
[0052] In summary, the semiconductor structure fabrication method provided in this application involves performing a first etching process on the inter-gate dielectric layer of the peripheral device region using an isotropic etching gas with a first selectivity ratio. This ensures that after the first etching process, only a small amount of oxide remains on the side of the floating gate layer, with no nitride residue, facilitating subsequent removal. Then, a second etching process is performed on the floating gate layer of the peripheral device region using an etching gas with a second selectivity ratio, partially removing the floating gate layer, the remaining oxide in the inter-gate dielectric layer, and the shallow trench isolation structure. This fully exposes the remaining oxide in the inter-gate dielectric layer, and the shallow trench isolation forms a horn-like shape in the region near the floating gate layer. Finally, a third etching process is performed on the floating gate layer, the horn-like shape, and the shallow trench isolation in the peripheral device region using an isotropic etching gas with a third selectivity ratio to remove the horn-like shape, making the shallow trench isolation essentially flat. This avoids material delamination and contaminant residue after subsequent wet cleaning, which could affect chip yield.
[0053] Furthermore, a fourth etching process is performed on the floating gate layer of the peripheral device region using an etching gas with a fourth selectivity ratio to completely remove the floating gate layer and ensure that no floating gate layer residue remains.
[0054] It should be noted that although preferred embodiments have been disclosed above in this application, these embodiments are not intended to limit this application. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of this application based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application, without departing from the content of the technical solutions of this application, shall still fall within the scope of protection of the technical solutions of this application.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a peripheral device region, a plurality of shallow trench isolation structures are formed in the substrate, a floating gate layer and an inter-gate dielectric layer are formed on the substrate, the top surface of the floating gate layer is higher than the top surface of the shallow trench isolation structure, the inter-gate dielectric layer covers the top surface and side surface of the floating gate layer, and the inter-gate dielectric layer has an oxide-nitride-oxide structure. A first etching process is performed on the inter-gate dielectric layer of the peripheral device region using an isotropic etching gas with a first selectivity, such that after the first etching process is completed, some oxide in the inter-gate dielectric layer remains on the side of the floating gate layer, and the first selectivity is the selectivity between the inter-gate dielectric layer and the floating gate layer. A second etching process is performed on the floating gate layer of the peripheral device region using an etching gas with a second selectivity ratio to partially remove the floating gate layer, the oxide in the remaining inter-gate dielectric layer, and the shallow trench isolation structure, so as to fully expose the oxide in the remaining inter-gate dielectric layer. The shallow trench isolation structure forms a bull's horn in the region near the floating gate layer. The second selectivity ratio is the selectivity ratio between the floating gate layer and the oxide in the inter-gate dielectric layer or the oxide in the shallow trench isolation structure. A third etching process is performed on the floating gate layer, the bullhorn, and the shallow trench isolation structure of the peripheral device region using an isotropic etching gas with a third selectivity to remove the bullhorn, and the top surfaces of the floating gate layer and the shallow trench isolation structure are flush. The third selectivity is the selectivity between the floating gate layer and the oxide in the bullhorn or the shallow trench isolation structure.
2. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, After performing the third etching process, the process further includes: A fourth etching process is performed on the floating gate layer of the peripheral device region using an etching gas with a fourth selectivity ratio to completely remove the floating gate layer. The fourth selectivity ratio is the selectivity ratio between the floating gate layer and the oxide in the shallow trench isolation structure.
3. The method for fabricating a semiconductor structure as described in claim 2, characterized in that, The fourth selection ratio is greater than the second selection ratio, the second selection ratio is greater than the first selection ratio, and the first selection ratio is equal to the third selection ratio.
4. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The isotropic etching gas having a first selectivity includes a mixture of CF4 and O2.
5. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The etching gas of the second selectivity ratio includes a mixture of SF6 and CH2F2.
6. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The isotropic etching gas with a third selectivity includes a mixture of CF4 and O2.
7. The method for fabricating a semiconductor structure as described in claim 2, characterized in that, The fourth selectivity etching gas includes a mixture of HBr and O2.
8. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The semiconductor structure is either flash memory or non-flash memory.
9. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The materials of the floating gate layer include polycrystalline silicon and amorphous silicon.
10. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, After the second etching process is performed, the top surface of the floating gate layer is either level with or lower than the top surface of the shallow trench isolation structure.