Semiconductor structure and three-dimensional memory

Abstract

The present disclosure provides a semiconductor structure and a three-dimensional memory, and relates to the technical field of semiconductor chips, aiming to improve the yield and reliability of the three-dimensional memory and reduce the manufacturing difficulty of the three-dimensional memory. The semiconductor structure comprises a substrate, a storage stack structure, at least one first wall structure and at least one second wall structure. The storage stack structure is located on one side of the substrate and has a step region and a core array region arranged along a first direction; the first wall structure extends along the first direction; the second wall structure extends along a second direction intersecting the first direction; all the first wall structures and all the second wall structures are located in the step region; the height of at least one second wall structure is less than the height of the first wall structure. The above semiconductor structure is applied to the three-dimensional memory to realize the read and write operations of data.

Description

[0001] This application is a divisional application of Chinese invention patent application filed on October 26, 2021, with application number 2021112492613 and title "Semiconductor Structure and Three-Dimensional Memory". Technical Field

[0002] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and a three-dimensional memory. Background Technology

[0003] As the feature size of memory cells approaches the lower limit of the process, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit.

[0004] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed memory with a three-dimensional structure (3D NAND), which increases storage density by arranging storage cells three-dimensionally on a substrate.

[0005] To achieve higher storage density, the number of stacked layers in 3D memory has increased significantly, for example, from 32 layers to 64 layers, then to 96 layers, and even 128 layers. However, with the increase in the number of stacked layers in 3D memory, stress problems in the stepped regions become increasingly severe, such as deformation of the gate lines and the stepped structure. These problems reduce the yield and reliability of 3D memory. To solve these problems, the structure of 3D memory needs to be improved. However, the increased number of stacked layers in 3D memory inevitably brings difficulties to the fabrication of the improved 3D memory.

[0006] Therefore, it is hoped that the structure of 3D memory can be improved to increase its yield and reliability, as well as reduce the difficulty of its fabrication. Summary of the Invention

[0007] The embodiments of this disclosure provide a semiconductor structure and a three-dimensional memory, which aim to improve the yield and reliability of the three-dimensional memory and reduce the fabrication difficulty of the three-dimensional memory.

[0008] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions: On one hand, a semiconductor structure is provided. The semiconductor structure includes a substrate, a memory stack structure, at least one first wall structure, and at least one second wall structure. The memory stack structure is located on one side of the substrate and has a stepped region and a core array region disposed along a first direction. The first wall structure extends along the first direction; the second wall structure extends along a second direction, which intersects with the first direction. All first wall structures and all second wall structures are located in the stepped region; the height of at least one second wall structure is less than the height of the first wall structure.

[0009] The semiconductor structure provided by the above embodiments of this disclosure, by providing the first wall structure and the second wall structure in the stepped region to provide support, can avoid stress problems at the location of the memory stack structure in the stepped region, thereby improving the yield and reliability of the three-dimensional memory. Furthermore, by ensuring that the height of at least one of the second wall structures is less than the height of the first wall structure, not only can development problems caused by excessive height difference between the second wall structure and the location of the memory stack structure in the stepped region be avoided, thus improving the yield of the three-dimensional memory, but the operating space during the fabrication of the semiconductor structure can also be increased, thereby reducing fabrication difficulty.

[0010] In some embodiments, the height of all the second wall structures is less than the height of the first wall structure.

[0011] In some embodiments, the height of all the second wall structures is greater than or equal to half the height of the first wall structure.

[0012] In some embodiments, all the first wall structures have the same height.

[0013] In some embodiments, the storage stack structure includes a plurality of storage blocks, all extending along the first direction and arranged sequentially along the second direction. Each storage block includes a plurality of stepped structures, all located in the step area and arranged sequentially along the first direction; the plurality of stepped structures are provided with a first wall structure on one or both sides along the second direction; and a second wall structure is provided between two adjacent stepped structures.

[0014] In some embodiments, the heights of the plurality of stepped structures are different; the height of the second wall structure is greater than the maximum height of the stepped structure adjacent to the second wall structure.

[0015] In some embodiments, one of the plurality of stepped structures includes a plurality of steps, the height of which decreases and then increases along the first direction, and the heights of the plurality of steps are different.

[0016] In some embodiments, the semiconductor structure further includes a stop layer and an insulating fill layer. The stop layer is located on the surface of the plurality of stepped structures away from the substrate. The insulating fill layer covers the stop layer and the second wall structure.

[0017] In some embodiments, the semiconductor structure further includes a plurality of gate spacer structures. The plurality of gate spacer structures are arranged sequentially along the second direction and all extend along the first direction; the plurality of gate spacer structures divide the memory stack structure into the plurality of memory blocks; the plurality of gate spacer structures include at least one first gate spacer structure and at least one second gate spacer structure. The first gate spacer structure penetrates the step region and the core array region; the second gate spacer structure penetrates the area of ​​the step region excluding the area where the first wall structure is located and the core array region; at least one first gate spacer structure is present between two adjacent second gate spacer structures.

[0018] In some embodiments, the semiconductor structure further includes a plurality of sub-gate spacer structures. The plurality of sub-gate spacer structures are arranged sequentially along the second direction and all extend along the first direction. At least one sub-gate spacer structure is provided in one of the memory blocks, and the sub-gate spacer structure penetrates the core array region to divide the memory block into a plurality of finger-like structures.

[0019] In some embodiments, the semiconductor structure further includes at least one first support structure and / or at least one second support structure. The first support structure penetrates the first wall structure in a direction perpendicular to the substrate; the second support structure penetrates the second wall structure in a direction perpendicular to the substrate.

[0020] In some embodiments, both the first support structure and the second support structure are channel structures.

[0021] In some embodiments, the channel structure includes a channel aperture and a storage functional layer and a channel layer sequentially formed within the channel aperture.

[0022] On the other hand, a three-dimensional memory is provided. The three-dimensional memory includes a first semiconductor structure and a second semiconductor structure coupled together. The first semiconductor structure or the second semiconductor structure is a semiconductor structure as described in some of the embodiments above.

[0023] In some embodiments, the first semiconductor structure and the second semiconductor structure are co-bonded.

[0024] It is understood that the beneficial effects of the three-dimensional memory with semiconductor structure provided in the above embodiments of this disclosure can be referred to the beneficial effects of semiconductor structure described above, and will not be repeated here. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0026] Figure 1 A structural diagram of a three-dimensional memory provided in some embodiments of this disclosure; Figure 2 A structural diagram of a semiconductor structure provided in some embodiments of this disclosure; Figure 3A This is a structural diagram of another semiconductor structure provided in some embodiments of the present disclosure; Figure 3B for Figure 3A Enlarged view of section AA'; Figure 4 A structural diagram of yet another semiconductor structure provided in some embodiments of this disclosure; Figure 5 This is a structural diagram of yet another semiconductor structure provided in some embodiments of the present disclosure; Figure 6 This is a structural diagram of yet another semiconductor structure provided in some embodiments of the present disclosure; Figure 7 This is a structural diagram of yet another semiconductor structure provided in some embodiments of the present disclosure; Figure 8 This is a structural diagram of yet another semiconductor structure provided in some embodiments of the present disclosure; Figure 9 This is a structural diagram of yet another semiconductor structure provided in some embodiments of the present disclosure; Figure 10 This is a structural diagram of yet another semiconductor structure provided in some embodiments of the present disclosure; Figure 11 A flowchart illustrating a method for fabricating a semiconductor structure according to some embodiments of this disclosure; Figure 12 A flowchart illustrating a method for fabricating a channel structure according to some embodiments of this disclosure; Figure 13This is a flowchart illustrating a method for preparing a virtual channel structure according to some embodiments of the present disclosure. Detailed Implementation

[0027] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0028] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0029] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0030] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0031] In describing some embodiments, the term "connection" and its derivative expressions may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0032] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0033] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0034] The use of “configured as” in this article implies an open and inclusive language that does not preclude devices from being configured to perform additional tasks or steps.

[0035] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0036] As used herein, “approximately” includes the values ​​stated and the average value within an acceptable range of deviation from the given values, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0037] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0038] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0039] As used herein, the term "substrate" refers to a material on which subsequent layers of material can be added. The substrate itself can be patterned. The material added to the substrate can be patterned or left unpatterned.

[0040] The term "three-dimensional memory" refers to a semiconductor device formed by strings of memory cell transistors (referred to herein as "memory cell strings," such as NAND memory cell strings) arranged in an array on the main surface of a substrate and extending in a direction perpendicular to the substrate. As used herein, the term "perpendicularly" means nominally perpendicular to the main surface of the substrate (i.e., the lateral surface).

[0041] This disclosure provides a three-dimensional memory 1000 according to some embodiments. See also... Figure 1 The three-dimensional memory 1000 includes a first semiconductor structure 200 and a second semiconductor structure 300 that are combined with each other. It should be noted that there can be various ways of combining them, and this disclosure does not limit them.

[0042] For example, the above-described bonding method is a hybrid bonding, which may include, for example, both metal-metal bonding and dielectric-dielectric bonding.

[0043] In some examples, please refer to [link / reference]. Figure 1 One of the first semiconductor structure 200 and the second semiconductor structure 300 includes an array device 20, and the other includes a peripheral device 30.

[0044] The following illustration uses an example where the first semiconductor structure 200 includes an array device 20, and the second semiconductor structure 300 includes a peripheral device 30. Please refer to [link / reference]. Figure 1 The peripheral device 30 is located on one side of the array device 20 and is electrically connected to the array device 20.

[0045] For example, please continue reading Figure 1 The peripheral device 30 includes a substrate 301 and a peripheral circuit layer 302. The peripheral circuit layer 302 is located on the side of the substrate 301 closer to the array device 20 and is electrically connected to the array device 20; the peripheral circuit layer 302 is configured to control and sense the array device 20.

[0046] It should be noted that the type of the aforementioned peripheral circuit layer 302 includes various types, which can be selected according to actual needs. The aforementioned peripheral circuit layer 302 may include, for example, page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), or any active (or passive) components of the circuit (e.g., transistors, diodes, resistors, and capacitors).

[0047] The aforementioned peripheral circuit layer 302 may include, for example, a plurality of transistors. Exemplarily, at least a portion of the transistors are formed in the substrate 301 (e.g., below the top surface of the substrate 301), and / or are formed directly on the substrate 301.

[0048] Furthermore, the aforementioned peripheral circuit layer 302 may also include any other circuitry compatible with advanced logic processes. For example, the peripheral circuit layer 302 may include logic circuitry (e.g., processors and programmable logic devices), and / or storage circuitry (e.g., static random access memory).

[0049] This disclosure provides a semiconductor structure 100 in some embodiments, which can be applied to the aforementioned three-dimensional memory 1000. That is, the semiconductor structure 100 can be one of the first semiconductor structure 200 and the second semiconductor structure 300, which includes the array device 20. Of course, the semiconductor structure 100 can also be applied to other memories, and this disclosure does not limit it.

[0050] Please see Figure 1 The semiconductor structure 100 includes a substrate 1 and a memory stack structure 2 located on one side of the substrate 1.

[0051] In some examples, substrate 1 is a semiconductor substrate.

[0052] For example, substrate 1 is a single-crystal silicon substrate, a single-crystal germanium substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate, etc.

[0053] As another example, substrate 1 is a P-type doped polycrystalline silicon substrate or an N-type doped polycrystalline silicon substrate. In this case, substrate 1 can, for example, serve as an array common source (ACS) structure.

[0054] As another example, substrate 1 is a gallium arsenide substrate, an indium phosphide substrate, or a silicon carbide substrate, etc. Furthermore, substrate 1 may also include, for example, a high-voltage P-type well region, a high-voltage N-type well region, or a deep N-well, etc.

[0055] In other examples, substrate 1 is made of a non-conductive material, which may include, for example, glass, plastic, or sapphire wafers.

[0056] In some examples, please refer to Figure 1 , Figure 2 and Figures 6-10 The storage stack structure 2 has a stepped area SS and a core array area C arranged along the first direction X.

[0057] Please refer to Figure 2 In the storage stack structure 2, multiple storage cell strings A can be formed in the part located in the core array area C for information storage.

[0058] For example, please refer to Figure 2 Multiple memory cell strings A penetrate the memory stack structure 2 along the direction Z perpendicular to the substrate 1, and are arranged sequentially along the first direction X and the second direction Y.

[0059] It should be noted that this disclosure does not impose any restrictions on the location of the step region SS and the core array region C.

[0060] For example, please refer to Figures 6-10 The core array region C includes a first core array region C1 and a second core array region C2 arranged along the first direction X; the step region SS is located between the first core array region C1 and the second core array region C2. In this case, the driving mode of the three-dimensional memory 1000 is center-driven.

[0061] For another example, see Figure 1 and Figure 2 The stepped region SS is located on one or both sides of the core array region C. In this case, the three-dimensional memory 1000 is driven by word line terminals.

[0062] In some examples, please refer to Figure 1 and Figure 2 The memory stack structure 2 includes multiple insulating layers 21 and multiple gate layers 22 that are alternately stacked along a direction Z perpendicular to the substrate 1.

[0063] For example, please refer to Figure 1 Each gate layer 22 includes a plurality of gate lines 221 and a wrapping layer 222 sequentially surrounding the gate lines 221. The gate lines 221 may be word lines, for example, and extend from the core array region C to the step region SS along a first direction X. The wrapping layer 222 may include a gate dielectric layer and an adhesive layer sequentially surrounding the gate lines 221.

[0064] Based on this, multiple word line connection contacts 24 can be formed in the step region SS of the memory stack structure 2. Each word line connection contact 24 is connected to a word line (e.g., gate line 221) and is configured to transmit control information to the word line (e.g., gate line 221) to realize the reading and writing of information in the core array region C.

[0065] For example, the insulating layer 21 may be made of an insulating material, which may include at least one of silicon oxide, silicon nitride and silicon oxynitride; the gate layer 22 may be made of a conductive material, which may include at least one of tungsten, cobalt, copper, aluminum, doped polycrystalline silicon, doped monocrystalline silicon and silicide.

[0066] It should be noted that in the memory stack structure 2, the thicknesses of the multiple insulating layers 21 can be approximately the same or different; the thicknesses of the multiple gate layers 22 can also be approximately the same or different; the selection can be made according to actual needs. Furthermore, the number of stacked layers in the memory stack structure 2 determines the number of memory cells in the direction Z perpendicular to the substrate 1; the number of stacked layers in the memory stack structure 2 can be, for example, 32, 64, 96, or 128 layers. The more stacked layers in the memory stack structure 2, the higher the integration density, that is, the more memory cells. The specific number of stacked layers and stacking height of the memory stack structure 2 can be designed according to actual memory requirements, and this disclosure does not impose specific limitations in this regard.

[0067] Figure 3A This is a structural diagram of another semiconductor structure 100 provided in some embodiments of this disclosure. Figure 3B for Figure 3A A magnified view of the area at AA'. Figure 4 This is a structural diagram of another semiconductor structure 100 provided in some embodiments of the present disclosure.

[0068] In some embodiments, please refer to Figure 3A and Figure 3B The storage stack structure 2 is divided into multiple storage blocks 23. The multiple storage blocks 23 all extend along the first direction X and are arranged sequentially along the second direction Y.

[0069] One of the storage blocks 23 includes multiple step structures 231, all of which are located in the step area SS and are arranged sequentially along the first direction X.

[0070] In some examples, please refer to Figure 4 The heights of the multiple stepped structures 231 are different.

[0071] It should be noted that word line connection contacts 24 can be formed on the multiple step structures 231, for example. Each word line connection contact 24 is connected to a word line (e.g., gate line 221), and the multiple word lines (e.g., gate lines 221) in the same memory block 23 are located in different gate layers 22. Therefore, in some of the examples above, by controlling the different heights of the multiple step structures 231, it is more convenient to connect the multiple word line connection contacts 24 to word lines (e.g., gate lines 221) located in different gate layers.

[0072] In some examples, please refer to [link / reference]. Figure 4 One of the multiple stepped structures 231 includes multiple steps 2311, the height of which decreases and then increases along the first direction X.

[0073] In a stepped structure 231, the height variation of multiple steps 2311 can be uniform or non-uniform.

[0074] For example, in a stepped structure 231, the height difference between any two adjacent steps 2311 is approximately equal, and the height variation of multiple steps 2311 is uniform.

[0075] For further examples, please refer to [link / reference]. Figure 4 In a stepped structure 231, the step with the smallest height is the first step 2311', located on both sides of the first step 2311', and the height difference between the two steps 2311 adjacent to the first step 2311' is not equal. In this case, the height variation of multiple steps 2311 is uneven.

[0076] It should be noted that the height of the aforementioned stepped structure 231 can be, for example, the vertical distance from the side of the stepped structure 231 away from the substrate 1 to the substrate 1. Similarly, the height of the aforementioned step 2311 can be, for example, the vertical distance from the side of the step 2311 away from the substrate 1 to the substrate 1.

[0077] In some examples, please refer to Figure 1 The semiconductor structure 100 further includes a stop layer 5 and an insulating fill layer 6. The stop layer 5 is located on the surface of the plurality of stepped structures 231 away from the substrate 1; the insulating fill layer 6 covers the stop layer 5.

[0078] It should be noted that the method for forming the insulating fill layer 6 can be, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), high-density plasma-chemical vapor deposition (HDP-CVD), or atomic layer deposition (ALD). The material of the insulating fill layer 6 can be, for example, the same as that of the insulating layer 21, and the material of the insulating fill layer 6 can be, for example, silicon oxide. Furthermore, the surface of the insulating fill layer 6 away from the substrate 1 can be planarized, for example, by a chemical mechanical polishing (CMP) process.

[0079] The inventors of this disclosure have discovered through preliminary research that when the height of a certain step structure 231 among multiple step structures 231 is too small, the thickness of the portion of the insulating filling layer 6 located above the step structure 231 is too large. This results in excessive gravity on the portion of the insulating filling layer 6 located above the step structure 231, that is, excessive pressure is applied to the step structure 231, increasing the probability of deformation of the step structure 231, thereby reducing the yield and reliability of the three-dimensional memory 1000.

[0080] Based on this, please refer to some embodiments of this disclosure. Figure 3A , Figure 3B and Figure 4 The semiconductor structure 100 further includes at least one first wall structure 3 and at least one second wall structure 4.

[0081] In this configuration, at least one first wall structure 3 and at least one second wall structure 4 are located in the step area SS; the first wall structure 3 extends along the first direction X; the second wall structure 4 extends along the second direction Y, and the second direction Y intersects with the first direction X.

[0082] In some of the above embodiments, by setting a first wall structure 3 and a second wall structure 4 in the step area SS, the first wall structure 3 and the second wall structure 4 can assist the multiple step structures 231 in supporting the insulating filling layer 6. The first wall structure 3 and the second wall structure 4 share the pressure applied by the insulating filling layer 6, avoiding the problem of deformation of the multiple step structures 231 due to excessive pressure applied by the insulating filling layer 6, thereby improving the yield and reliability of the three-dimensional memory 1000.

[0083] In some examples, please refer to [link / reference]. Figure 3A , Figure 3B and Figure 4 The first wall structure 3 and the second wall structure 4 are arranged in an intersecting manner.

[0084] In some examples, please refer to [link / reference]. Figure 3A , Figure 3B and Figure 4 The first direction X is perpendicular to the second direction Y.

[0085] In some embodiments, please continue reading Figure 3A , Figure 3B and Figure 4 Multiple stepped structures 231 are provided with a first wall structure 3 on one or both sides along the second direction Y; a second wall structure 4 is provided between two adjacent stepped structures 231.

[0086] It should be noted that word line connection contacts 24 may be formed on the multiple step structures 231, and each word line connection contact 24 is connected to a word line (e.g., gate line 221). A word line connection contact 24 may, for example, be located on a step 2311.

[0087] Therefore, in some of the above embodiments, by limiting the first wall structure 3 to be disposed on one or both sides of the plurality of stepped structures 231, and the second wall structure 4 to be located between two adjacent stepped structures 231, it is possible to ensure that the first wall structure 3 and the second wall structure 4 assist the plurality of stepped structures 231 in supporting the insulating filling layer 6, while avoiding the first wall structure 3 and the second wall structure 4 from affecting the connection between the word line connection contact point 24 and the word line (e.g., gate line 221) on the step 2311.

[0088] In some examples, where the semiconductor structure 100 includes a stop layer 5 and an insulating fill layer 6, the insulating fill layer 6 fills the cavity defined by the first wall structure 3, the second wall structure, and the stepped structure 231.

[0089] For example, please refer to Figure 4 The height of all first wall structures 3 is approximately equal to the height of all second wall structures 4.

[0090] It should be noted that the height of the first wall structure 3 can be, for example, the vertical distance from the surface of the first wall structure 3 away from the substrate 1 to the substrate 1. Similarly, the height of the second wall structure 4 can be, for example, the vertical distance from the surface of the second wall structure 4 away from the substrate 1 to the substrate 1.

[0091] Based on this, the inventors of this disclosure have discovered through in-depth research that: on the one hand, since a stop layer 5 can be fabricated on the surface of the multiple stepped structures 231 away from the substrate 1, when the height of one of the stepped structures 231 is too small, the height difference between the stepped structure 231 and the second wall structure 4 adjacent to the stepped structure 231 is too large, making it easy for material deposition to occur and development problems to occur when fabricating the stop layer 5 on the surface of the stepped structure 231, thus affecting the fabrication effect; on the other hand, since the insulating filler layer 6 can be planarized on the surface of the insulating filler layer 6 away from the substrate 1 by chemical mechanical polishing (CMP), the surface will be blocked by the first wall structure 3 and the second wall structure 4 at the same time, reducing the operating area when performing the chemical mechanical polishing (CMP) process, thereby increasing the difficulty of the chemical mechanical polishing (CMP) process.

[0092] Based on this, please refer to some embodiments of this disclosure. Figure 5 At least one of the second wall structures 4 has a height less than the height of the first wall structure 3.

[0093] In some of the above embodiments, by reducing the height of at least one second wall structure 4, the height difference between the second wall structure 4 and the stepped structure 231 adjacent to the second wall structure 4 can be reduced to a certain extent, thereby avoiding the development problem caused by material deposition when manufacturing the stop layer 5 on the surface of the stepped structure 231, thus improving the manufacturing effect; and it can also increase the operating area when performing chemical mechanical polishing (CMP) on the insulating filler layer 6, thereby reducing the difficulty of the chemical mechanical polishing (CMP) process.

[0094] In some examples, please refer to [link / reference]. Figure 5 The height of all second wall structures 4 is less than the height of the first wall structure 3.

[0095] In some of the examples above, by reducing the height of all the second wall structures 4, it is possible not only to further avoid the development problem caused by material deposition when manufacturing the stop layer 5 on the surface of the stepped structure 231, thereby improving the manufacturing effect, but also to further increase the operating area when performing chemical mechanical polishing (CMP) on the insulating filler layer 6, thereby reducing the difficulty of the chemical mechanical polishing (CMP) process.

[0096] In some examples, please refer to [link / reference]. Figure 5 The height of all second wall structures 4 is greater than or equal to half the height of the first wall structure 3.

[0097] The height of the first wall structure 3 mentioned above can be, for example, the height of any one of the first wall structures 3.

[0098] It should be noted that one of the purposes of setting up the second wall structure 4 is to improve the support effect, thereby sharing the pressure exerted by the insulation filling layer 6 on the multiple stepped structures 231. However, when the second wall structure 4 is too small, the second wall structure 4 cannot play the role of improving the support effect to share the pressure.

[0099] Therefore, in some of the examples above, by controlling that the height of all the second wall structures 4 is greater than or equal to half the height of the first wall structure 3, it is possible to avoid development problems caused by material deposition when manufacturing the stop layer 5 on the surface of the step structure 231, and reduce the difficulty of the chemical mechanical polishing (CMP) process, while ensuring that the second wall structures 4 assist multiple step structures 231 in supporting the insulating fill layer 6.

[0100] In some examples, please refer to [link / reference]. Figure 5 When the heights of multiple stepped structures 231 are different, the height of the second wall structure 4 is greater than the maximum height of the stepped structure 231 adjacent to the second wall structure 4.

[0101] It should be noted that one of the purposes of setting up the second wall structure 4 is to improve the support effect, thereby sharing the pressure exerted by the insulating filling layer 6 on the multiple stepped structures 231. However, when the height of the second wall structure 4 is less than or equal to the maximum height of the stepped structure 231 adjacent to the second wall structure 4, the second wall structure 4 cannot play the role of improving the support effect to share the pressure.

[0102] Therefore, in some of the above examples, by controlling the height of the second wall structure 4 to be greater than the maximum height of the stepped structure 231 adjacent to the second wall structure 4, it is possible to avoid development problems caused by material deposition when manufacturing the stop layer 5 on the surface of the stepped structure 231, while ensuring that the second wall structure 4 assists multiple stepped structures 231 in supporting the insulating filler layer 6, and to reduce the difficulty of the chemical mechanical polishing (CMP) process.

[0103] In some examples, the insulating filler layer 6 covers the stop layer 5 and the second wall structure 4.

[0104] In some examples, please refer to Figure 11 The method for fabricating the semiconductor structure 100 includes steps S100 and S200.

[0105] S100, Multiple sacrificial layers and multiple insulating layers 21 are alternately and repeatedly formed on substrate 1 to form a stacked structure.

[0106] It should be noted that the sacrificial layer and the insulating layer 21 can be formed, for example, by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDP-CVD), atomic layer deposition (ALD), or sputtering.

[0107] The insulating layer 21 and the sacrificial layer have different etch selectivity ratios, making the sacrificial layer easy to remove in subsequent processes to form a sacrificial gap. The gate layer 22 can be formed in the sacrificial gap by filling material, for example, to obtain the memory stack structure 2.

[0108] The process for removing the sacrificial layer can be, for example, a wet etching process; the material of the sacrificial layer can be, for example, silicon nitride or polysilicon; the number of stacked layers of the insulating layer 21 and the sacrificial layer can be determined, for example, according to the number of gate lines 221 in the required gate layer 22.

[0109] S200, A stepped structure is formed at the edge of the stacked structure. The stepped structure can be formed by performing multiple trim-etch cycles on multiple insulating layers 21 and multiple sacrificial layers of the stacked structure.

[0110] It should be noted that after the above process, the area corresponding to the stepped structure can be called the stepped area SS.

[0111] For example, the first wall structure 3 may be obtained by removing the sacrificial layer and forming the gate layer 22 after partially retaining the stacked structure when forming the stepped structure. In this case, the number of stacked layers and the stacking order of the insulating layer 21 and the gate layer 22 in the first wall structure 3 may be the same as the number of stacked layers and the stacking order of the insulating layer 21 and the gate layer 22 in the storage stack structure 2.

[0112] Similarly, the second wall structure 4 can be obtained, for example, by removing the sacrificial layer and forming the gate layer 22 from the partially retained stacked structure during the formation of the stepped structure. In this case, the number of stacked layers and the stacking order of the insulating layer 21 and the gate layer 22 in the second wall structure 4 can be, for example, the same as the number of stacked layers and the stacking order of the insulating layer 21 and the gate layer 22 in the storage stack structure 2.

[0113] In some examples, please refer to Figure 5 All the first wall structures 3 have approximately the same height.

[0114] In some of the examples above, by controlling that the height of all the first wall structures 3 is approximately equal, the manufacturing process of the first wall structure 3 can be simplified.

[0115] In some embodiments, please refer to Figure 3B and Figures 6-10 The semiconductor structure 100 further includes a plurality of gate spacer structures 7. The plurality of gate spacer structures 7 are arranged sequentially along the second direction Y and all extend along the first direction X. The plurality of gate spacer structures 7 divide the memory stack structure 2 into a plurality of memory blocks 23.

[0116] It should be noted that when forming multiple gate spacer structures 7, an anisotropic etching method can be used, which may include, for example, dry etching. Specifically, the etching time can be controlled to stop the etching at the surface of the substrate 1.

[0117] Furthermore, when forming the sacrificial gap, for example, the gate trench structure 7 can be used as a channel for the etchant, and the sacrificial layer can be removed by isotropic etching to form a cavity that accommodates the gate layer 22. This isotropic etching may include, for example, selective wet etching or vapor phase etching.

[0118] In some examples, the gate trench structure 7 is filled to form a gate separation structure, which includes a conductive wall and an insulating layer surrounding the conductive wall. The end of the conductive wall near the substrate 1 is connected to the substrate 1. The conductive wall can be, for example, an array common source (ACS) structure, which may include, for example, a polysilicon layer and a tungsten metal layer sequentially stacked along a direction Z away from and perpendicular to the substrate 1. The end of the array common source near the substrate 1 can be led out as a source through the substrate 1.

[0119] In some examples, please refer to [link / reference]. Figure 3B and Figures 6-10 The plurality of gate spacer structures 7 include at least one first gate spacer structure 71 and at least one second gate spacer structure 72.

[0120] The first gate partition structure 71 penetrates the step region SS and the core array region C; the second gate partition structure 72 penetrates the area of ​​the step region SS except for the area where the first wall structure 3 is located and the core array region C.

[0121] It should be noted that both the first gate spacer structure 71 and the second gate spacer structure 72 can serve a separating function. The limitation on the penetration area of ​​the first gate spacer structure 71 and the second gate spacer structure 72 is related to their placement within the semiconductor structure 100. For example, please refer to... Figures 6-10 Compared to the second gate partition structure 72, the first gate partition structure 71 is closer to the middle part of the semiconductor structure. Therefore, in order to achieve a better separation effect, the first gate partition structure 71 needs to penetrate the entire step region SS and the core array region C, while the second gate partition structure 72 does not need to penetrate the area where both the first wall structure 3 and the second wall structure 4 are located.

[0122] For example, please continue reading Figure 3B and Figures 6-10 There is at least one first gate spacer structure 71 between two adjacent second gate spacer structures 72.

[0123] For example, please see Figures 6-10 There are two first gate slot structures 71 between two adjacent second gate slot structures 72.

[0124] In some examples, please refer to Figure 3B and Figures 6-10 The semiconductor structure 100 further includes a plurality of sub-gate spacer structures 8. The plurality of sub-gate spacer structures 8 are arranged sequentially along the second direction Y and all extend along the first direction X.

[0125] In one of the memory blocks 23, at least one sub-gate partition structure 8 is provided, which extends through the core array region C to divide the memory block 231 into multiple finger structures 232.

[0126] In some of the examples above, by setting the sub-gate trench structure 8, the memory block 23 can be divided into multiple finger structures 232, thereby improving operating efficiency.

[0127] For example, please continue reading Figure 3B and Figures 6-10 There is at least one sub-gate spacer structure 8 between two adjacent second gate spacer structures 72. There is at least one first gate spacer structure 71 between two adjacent sub-gate spacer structures 8.

[0128] For example, please see Figures 6-10 There are three sub-gate spacers 8 between two adjacent second gate spacers 72; there is a first gate spacer 71 between two adjacent sub-gate spacers 8.

[0129] In some embodiments, please refer to Figure 1 , Figure 2 and Figures 6-10 The semiconductor structure 100 further includes a plurality of channel structures 11 extending through the memory stack structure 2 in a direction perpendicular to the substrate 1, at least a portion of the plurality of channel structures 11 being located in the core array region C.

[0130] It should be noted that a channel structure 11 can be, for example, a string A constituting a storage cell. In this case, the three-dimensional memory 1000 can implement data storage functionality through the channel structure 11.

[0131] In some examples, please refer to Figure 1 and Figure 2 The channel structure 11 contacts the gate layer from its sidewall and forms a memory cell; the end of the channel structure 11 away from the substrate 1 is led out as the drain and connected to the bit line; the end of the channel structure 11 close to the substrate 1 is led out through the substrate 1 as the source.

[0132] In some examples, please refer to Figure 1 The channel structure 11 includes: a channel hole 111 and a storage functional layer 112 and a channel layer 113 sequentially formed within the channel hole 111.

[0133] The storage functional layer 112 may include, for example, a barrier dielectric layer, a charge storage layer and a tunneling dielectric layer sequentially formed within the channel hole 111.

[0134] For example, an oxide-nitride-oxide-polysilicon (ONOP) structure may be sequentially stacked within the channel 111. In this case, the material of the barrier dielectric layer may be, for example, silicon oxide, the material of the charge storage layer may be, for example, silicon nitride, the material of the tunneling dielectric layer may be, for example, silicon oxide, and the material of the channel layer 113 may be, for example, polysilicon.

[0135] In some examples, please refer to Figure 12 The preparation method of the above-mentioned channel structure 11 includes S10~S20.

[0136] S10. Forming channel holes 111 in the stacked structure.

[0137] It should be noted that the channel holes 111 can be formed in the stacked structure, for example, by dry etching or wet etching processes.

[0138] S20. A barrier dielectric layer, a charge storage layer, a tunneling dielectric layer and a channel layer 112 are sequentially formed inside the channel hole 111 to form a channel structure 11; wherein, the barrier dielectric layer, the charge storage layer and the tunneling dielectric layer constitute the storage function layer 112.

[0139] It should be noted that the methods for forming the barrier dielectric layer, charge storage layer, tunneling dielectric layer and channel layer 112 can include chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDP-CVD), or atomic layer deposition (ALD).

[0140] Furthermore, it should be noted that the formation of the channel structure 11 can be carried out, for example, before S200 (that is, the step of forming a stepped structure at the edge of the stacked structure) or after S200, and this disclosure does not limit it in this way.

[0141] In some embodiments, please refer to Figure 1 The semiconductor structure 100 further includes a plurality of virtual channel structures 12 extending through the memory stack structure 2 in a direction perpendicular to the substrate 1, at least a portion of the plurality of virtual channel structures 12 being located in the step region SS.

[0142] It should be noted that the virtual channel structure 12 may not actually be used as a storage cell, but may serve, for example, to support the storage stack structure 2, so as to ensure that each process in the formation process inside the semiconductor structure 100 can be carried out safely and effectively.

[0143] In some examples, please refer to [link / reference]. Figure 1The virtual channel structure 12 includes a virtual channel hole 121 and an insulating material 122 filling the virtual channel hole 121. The insulating material 122 is not removed when the sacrificial layer is removed, so the insulating material 122 can support the memory stack structure 2, making the semiconductor structure 100 less prone to collapse.

[0144] For example, the insulating material 122 can be an oxide, such as silicon oxide.

[0145] In some examples, please refer to Figure 13 The method for preparing the virtual channel structure 12 includes steps S10' to S20'.

[0146] S10', A virtual channel hole 121 is formed in the stacked structure.

[0147] It should be noted that the virtual channel hole 121 can be formed in the stacked structure, for example, by using a dry etching process or a wet etching process.

[0148] S20' Fill the interior of the virtual channel hole 121 with insulating material 122 to form a virtual channel structure 12.

[0149] It should be noted that the formation of the virtual channel structure 12 can be performed, for example, before S200 (that is, the step of forming a stepped structure at the edge of the stacked structure) or after S200, and this disclosure does not limit it.

[0150] In some examples, the dimensions of the virtual channel structure 12 are approximately the same as those of the channel structure 11. In this case, the virtual channel structure 12 and the channel structure 11 can be formed, for example, using the same manufacturing process.

[0151] In some embodiments, please refer to Figures 6-10 The semiconductor structure 100 further includes at least one first support structure 9 and / or at least one second support structure 10. The first support structure 9 penetrates the first wall structure 3 in a direction perpendicular to the substrate 1; the second support structure 10 penetrates the second wall structure 4 in a direction perpendicular to the substrate 1.

[0152] In some of the above embodiments, by providing a first support structure 9 (or a second support structure 10) in the first wall structure 3 (or the second wall structure 4), the first wall structure 3 (or the second wall structure 4) can further assist the multiple stepped structures 231 in supporting the insulating filling layer 6, better preventing deformation of the multiple stepped structures 231, thereby further improving the yield and reliability of the three-dimensional memory 1000.

[0153] In some examples, please refer to [link / reference]. Figures 6-10The first support structure 9 is a virtual channel structure 12 or a channel structure 11; the second support structure is a virtual channel structure 12 or a channel structure 11.

[0154] It should be noted that the aforementioned first support structure 9 is a virtual channel structure 12 or a channel structure 11. For example, it means that a portion of a plurality of virtual channel structures 12 or a portion of a plurality of channel structures 11 constitutes at least one first support structure 9. Similarly, the aforementioned second support structure 10 is a virtual channel structure 12 or a channel structure 11. For example, it means that a portion of a plurality of virtual channel structures 12 or a portion of a plurality of channel structures 11 constitutes at least one second support structure 10.

[0155] For example, please refer to Figure 6 and Figure 10 Both the first support structure 9 and the second support structure 10 are virtual channel structures 12.

[0156] This design, employing virtual channel structure 12 as the first support structure 9 and the second support structure 10, allows the insulating material filled in the virtual channel structure 12 to better support the insulating filling layer 6 through multiple stepped structures 231, further preventing deformation of the multiple stepped structures 231 and thus further improving the yield and reliability of the three-dimensional memory 1000. In this case, the first support structure 9 and the second support structure 10 can be formed simultaneously with the fabrication of multiple virtual channel structures 12, simplifying the manufacturing process.

[0157] For another example, see Figure 7 The first support structure 9 is a virtual channel structure, and the second support structure 10 is a channel structure.

[0158] For another example, please refer to Figure 8 The first support structure 9 is a channel structure, and the second support structure 10 is a virtual channel structure.

[0159] For another example, please refer to Figure 9 Both the first support structure 9 and the second support structure 10 are channel structures.

[0160] This design, because the storage functional layer 112 and the channel layer 113 in the channel structure 11 are more rigid than the insulating material 122 in the virtual channel structure 12, allows the channel structure 11 to be used as the first support structure 9 and / or the second support structure 10. This further assists the multiple stepped structures 231 in supporting the insulating filling layer 6, further preventing deformation of the multiple stepped structures 231, thereby further improving the yield and reliability of the three-dimensional memory 1000. In this case, the first support structure 9 and / or the second support structure 10 can be formed simultaneously with the fabrication of multiple channel structures 11, simplifying the manufacturing process.

[0161] In some examples, please refer to Figure 10 The semiconductor structure 100 further includes at least one third support structure 13. The third support structure 13 extends through the portion of the memory stack structure 2 located in the step region SS in a direction perpendicular to the substrate 1.

[0162] It should be noted that the aforementioned third support structure 13 is a virtual channel structure 12, for example, a portion of a plurality of virtual channel structures 12 constitutes at least one third support structure 13.

[0163] In some of the examples above, by providing a third support structure 13 in the step region SS of the storage stack structure 2, the multiple step structures 231 are further assisted in supporting the insulating filling layer 6, and deformation of the multiple step structures 231 is further avoided, thereby further improving the yield and reliability of the three-dimensional memory 1000.

[0164] For example, please continue reading Figure 10 The third support structure 13 is a virtual channel structure 12.

[0165] With this design, the third support structure 13 can be formed simultaneously when multiple virtual channel structures 12 are manufactured, simplifying the manufacturing process.

[0166] In summary, the semiconductor structure 100 provided in some embodiments of this disclosure, by providing at least one of the first support structure 9, the second support structure 10, and the third support structure 11, can better assist the multiple stepped structures 231 in supporting the insulating filling layer 5, avoid deformation of the multiple stepped structures 231, and thus improve the yield and reliability of the three-dimensional memory 1000.

[0167] Based on this, using the channel structure 11 or the virtual channel structure 12 as the first support structure 9 allows the first support structure 9 to be formed simultaneously with the fabrication of the channel structure 11 or the virtual channel structure 12, simplifying the manufacturing process. Similarly, using the channel structure 11 or the virtual channel structure 12 as the second support structure 10 allows the second support structure 10 to be formed simultaneously with the fabrication of the channel structure 11 or the virtual channel structure 12, also simplifying the manufacturing process. Furthermore, using the virtual channel structure 12 as the third support structure 13 allows the third support structure 13 to be formed simultaneously with the fabrication of multiple virtual channel structures 12, further simplifying the manufacturing process.

[0168] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A memory stack structure located on one side of the substrate, the memory stack structure having a stepped region and a core array region disposed along a first direction; At least one first wall structure located in the stepped area, the first wall structure extending along the first direction; as well as, At least one second wall structure located in the stepped area, the second wall structure extending along a second direction intersecting the first direction; Both the first wall structure and the second wall structure include: insulating material and conductive material alternately layered in sequence; The semiconductor structure further includes: at least one first support structure, the first support structure penetrating the first wall structure in a direction perpendicular to the substrate; and / or, at least one second support structure, the second support structure penetrating the second wall structure in a direction perpendicular to the substrate.

2. The semiconductor structure according to claim 1, characterized in that, The first support structure and the second support structure are formed simultaneously.

3. The semiconductor structure according to claim 1, characterized in that, Both the first support structure and the second support structure include columnar structures extending in a direction perpendicular to the substrate.

4. The semiconductor structure according to claim 1, characterized in that, The dimension of the first support structure along the first direction is the same as the dimension of the second support structure along the first direction; And / or, The dimension of the first support structure along the second direction is the same as the dimension of the second support structure along the second direction.

5. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes at least one third support structure, which penetrates the step region of the memory stack structure in a direction perpendicular to the substrate.

6. The semiconductor structure according to claim 1, characterized in that, The height of the second wall structure is equal to the height of the first wall structure.

7. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes multiple channel structures, at least a portion of which penetrates the core array region of the memory stack structure along a direction perpendicular to the substrate; The channel structure includes a channel hole and a storage functional layer and a channel layer formed sequentially within the channel hole.

8. The semiconductor structure according to any one of claims 1 to 7, characterized in that, The storage stack structure includes multiple storage blocks, all of which extend along the first direction and are arranged sequentially along the second direction; One of the storage blocks includes multiple stepped structures, all of which are located in the step area and are arranged sequentially along the first direction; the multiple stepped structures are provided with the first wall structure on one or both sides along the second direction; and the second wall structure is provided between two adjacent stepped structures.

9. The semiconductor structure according to claim 8, characterized in that, The heights of the multiple stepped structures are different; the height of the second wall structure is greater than the maximum height of the stepped structure adjacent to the second wall structure.

10. The semiconductor structure according to claim 8, characterized in that, One of the multiple stepped structures includes multiple steps, the height of which decreases and then increases along the first direction.

11. The semiconductor structure according to claim 8, characterized in that, Also includes: Multiple gate spacer structures are arranged sequentially along the second direction and all extend along the first direction; The plurality of gate slot structures divide the memory stack structure into the plurality of memory blocks.

12. A three-dimensional memory, characterized in that, include: A first semiconductor structure and a second semiconductor structure that are combined with each other; Wherein, the first semiconductor structure or the second semiconductor structure is a semiconductor structure as described in any one of claims 1 to 11.

13. The three-dimensional memory according to claim 13, characterized in that, The first semiconductor structure and the second semiconductor structure are mixed-bonded.

14. A method for manufacturing a semiconductor structure, characterized in that, include: Provide substrate; A memory stack structure is formed on one side of the substrate, the memory stack structure having a stepped region and a core array region disposed along a first direction; At least one first wall structure is formed in the stepped area, and the first wall structure extends along the first direction; as well as, At least one second wall structure is formed in the stepped area, the second wall structure extending along a second direction, the second direction intersecting the first direction; Both the first wall structure and the second wall structure include: insulating material and conductive material alternately layered in sequence; At least one first support structure is formed, the first support structure penetrating the first wall structure in a direction perpendicular to the substrate; At least one second support structure is formed, the second support structure penetrating the second wall structure in a direction perpendicular to the substrate.

15. The method for manufacturing a semiconductor structure according to claim 14, characterized in that, The first support structure and the second support structure are formed simultaneously.

16. The method for manufacturing a semiconductor structure according to claim 14, characterized in that, The method further includes: At least one third support structure is formed, the third support structure penetrating the step region of the memory stack structure in a direction perpendicular to the substrate; The first support structure, the second support structure, and the third support structure are formed simultaneously.

Images