Semiconductor device with guard ring

Abstract

A semiconductor device can include a first circuit structure having a first active region and a first guard ring region, and a second circuit structure located on the first circuit structure and having a second active region and a second guard ring region. The first circuit structure can include a lower guard ring located in the first guard ring region and a lower insulating bond layer extending in both the first active region and the first guard ring region. The second circuit structure can include an upper insulating bond layer located on the lower insulating bond layer, and an upper guard ring. The lower insulating bond layer can be disposed in the first guard ring region between the lower guard ring and the upper guard ring. The upper insulating bond layer can be disposed in the second guard ring region between the lower guard ring and the upper guard ring.

Description

[0001] Cross-reference to related applications This application claims priority to Korean Application No. 10-2024-0190187, filed on December 18, 2024, the entire contents of which are incorporated herein by reference for all purposes as fully set forth herein. Technical Field

[0002] The embodiments of this disclosure generally relate to semiconductor technology, and more specifically, to a semiconductor device with a guard ring and a method for forming the same. Background Technology

[0003] Recently, to achieve higher integration in semiconductor devices, a technique has been proposed involving bonding a wafer with memory cells onto another wafer with peripheral circuitry. However, the bonding between wafers needs to be sufficiently strong, and a good electrical connection needs to be provided between the memory cells and the peripheral circuitry. These areas require further improvement. Summary of the Invention

[0004] Embodiments of this disclosure may provide a semiconductor device with a guard ring and a method for forming the same.

[0005] The embodiments described herein are not limited to those set forth herein, and other unmentioned embodiments will be apparent to those skilled in the art from the following description.

[0006] Embodiments of this disclosure may provide a semiconductor device comprising: a first circuit structure having a first active region and a first guard ring region; and a second circuit structure bonded to the first circuit structure and having a second active region and a second guard ring region. The first circuit structure may include: a lower insulating layer; a lower wire disposed in the lower insulating layer within the first active region; a lower guard ring disposed in the lower insulating layer within the first guard ring region; a lower insulating bonding layer disposed on the lower insulating layer and extending between the first active region and the first guard ring region; and a lower bonding pad disposed in the lower insulating bonding layer within the first active region and connected to the lower wire. The second circuit structure may include: an upper insulating bonding layer disposed in the second active region and the second guard ring region, and bonded to the lower insulating bonding layer; an upper bonding pad disposed in the upper insulating bonding layer in the second active region, and bonded to the lower bonding pad; an upper insulating layer on the upper insulating bonding layer; an upper line disposed in the upper insulating layer in the second active region and connected to the upper bonding pad; and an upper guard ring disposed in the upper insulating layer in the second guard ring region. The lower insulating bonding layer may be disposed in a first guard ring region between the lower guard ring and the upper guard ring. The upper insulating bonding layer may be disposed in a second guard ring region between the lower guard ring and the upper guard ring.

[0007] Embodiments of this disclosure may provide a semiconductor device comprising: a first circuit structure having a first active region and a first guard ring region; and a second circuit structure bonded to the first circuit structure and having a second active region and a second guard ring region. The first circuit structure may include: a lower insulating layer; a lower wire disposed in the lower insulating layer within the first active region; a lower guard ring disposed in the lower insulating layer within the first guard ring region; and a lower insulating bonding layer disposed in the first active region and the first guard ring region, and formed on the lower insulating layer. The second circuit structure may include: an upper insulating bonding layer disposed in the second active region and the second guard ring region, and bonded to the lower insulating bonding layer; an upper insulating layer on the upper insulating bonding layer; an upper wire disposed in the upper insulating layer within the second active region; and an upper guard ring disposed in the upper insulating layer within the second guard ring region. The lower insulating bonding layer may extend into the first guard ring region between the lower guard ring and the upper guard ring. The upper insulating bonding layer can extend into the second protective ring region between the lower protective ring and the upper protective ring.

[0008] Embodiments of this disclosure may provide a semiconductor device comprising: a first circuit structure having a first active region and a first guard ring region; and a second circuit structure bonded to the first circuit structure and having a second active region and a second guard ring region. The first circuit structure may include: a lower transistor on a substrate; a lower insulating layer on the substrate and the lower transistor; a lower line disposed in the lower insulating layer in the first active region; a lower guard ring disposed in the lower insulating layer in the first guard ring region; a lower insulating bonding layer disposed in the first active region and the first guard ring region, and formed on the lower insulating layer; and a lower bonding pad disposed in the lower insulating bonding layer in the first active region and connected to the lower line. The second circuit structure may include: an upper insulating bonding layer disposed in the second active region and the second guard ring region, and bonded to the lower insulating bonding layer; an upper bonding pad disposed in the upper insulating bonding layer in the second active region, and bonded to the lower bonding pad; an upper insulating layer on the upper insulating bonding layer; an upper line disposed in the upper insulating layer in the second active region and connected to the upper bonding pad; a stacked structure disposed in the upper insulating layer in the second active region; a channel structure penetrating the stacked structure; a common source line disposed on the stacked structure and connected to the channel structure; and an upper guard ring disposed in the upper insulating layer in the second guard ring region. The lower insulating bonding layer may extend into a first guard ring region between the lower guard ring and the upper guard ring. The upper insulating bonding layer may extend into a second guard ring region between the lower guard ring and the upper guard ring.

[0009] According to embodiments of the present disclosure, a semiconductor device with a guard ring and a method for forming the same can be provided.

[0010] The embodiments disclosed herein are not limited to the foregoing embodiments, and other embodiments will be apparent to those skilled in the art from the following detailed description. Attached Figure Description

[0011] Embodiments of this disclosure will be more fully understood from the following detailed description and accompanying drawings, which are for illustrative purposes only and are not intended to limit the embodiments.

[0012] Figure 1 This is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure; Figures 2 to 5 This is a plan view illustrating a semiconductor device according to an embodiment of the present disclosure; Figure 6 It is shown Figure 1 A portion of the view; Figure 7 This is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure; and Figures 8 to 20 This is a cross-sectional view illustrating a method for forming a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0013] In the following, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. When assigning reference numerals to components in each figure, the same reference numerals may be assigned to the same components, even if these components are shown in different figures. Details of known techniques or functions may be skipped when the subject matter of the present disclosure is unclear. As used herein, a component may have other components when it “comprises”, “has”, or “is composed of” another component, unless the term “meets only” is used with the terms “comprises,” “has,” or “is composed of.” As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” are intended to also include the plural forms.

[0014] Labels such as “first”, “second”, “A”, “B”, “(a)”, and “(b)” may be used to describe components of this disclosure. These labels are provided merely to distinguish one component from another, and the nature, order, or number of components is not limited by the labels.

[0015] When describing the positional relationship between components, when two or more components are described as “connected,” “coupled,” or “linked,” these two or more components may be directly “connected,” “coupled,” or “linked,” or another component may be interposed therebetween. Here, the other component may be included in one or more of the two or more components that are “connected,” “coupled,” or “linked” to each other.

[0016] When terms such as “after,” “next,” and “before” are used to describe time-series relationships related to components, operating methods, and manufacturing methods, they may include discontinuous relationships unless the terms “immediately” or “directly” are used.

[0017] When a component is specified using a numerical value or its corresponding information (e.g., a grade), that numerical value or corresponding information can be interpreted as including tolerances due to various factors (e.g., process parameters, internal or external influences, or noise).

[0018] Various embodiments of this disclosure are described in detail below with reference to the accompanying drawings.

[0019] Figure 1This is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure. Figures 2 to 5 This is a plan view illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 6 It is shown Figure 1 A portion of a 200-fold view. In an embodiment, Figure 1 It can be along Figures 2 to 5 A cross-sectional view taken from line II′. In embodiments, semiconductor devices according to embodiments of this disclosure may include non-volatile memory devices such as flash memory.

[0020] refer to Figure 1 The semiconductor device according to embodiments of this disclosure may include a first circuit structure CS1 and a second circuit structure CS2 bonded to the first circuit structure CS1. The first circuit structure CS1 may include a first active region AR1 and a first guard ring region GR1. The first guard ring region GR1 may be continuous with the side surface of the first active region AR1. The second circuit structure CS2 may include a second active region AR2 and a second guard ring region GR2. The second guard ring region GR2 may be continuous with the side surface of the second active region AR2. The second guard ring region GR2 may be superimposed on the first guard ring region GR1.

[0021] The first circuit structure CS1 may include a first substrate 21, a component isolation layer 23, a lower source region 25, a lower drain region 27, a lower channel region 29, a lower gate insulating layer 32, a lower gate electrode 33, a gate capping layer 37, a gate spacer 39, a first lower insulating layer 42, a lower line 45, a lower line guard ring 45G, a second lower insulating layer 52, a lower contact plug 56, a lower contact guard ring 56G, a lower insulating bonding layer 62, and a lower bonding pad 67. The lower line 45 may be disposed in the first active region AR1, and the lower line guard ring 45G may be disposed in the first guard ring region GR1. The lower insulating bonding layer 62 extends in the first active region AR1 and the first guard ring region GR1.

[0022] A component isolation layer 23 may be disposed in the first substrate 21. A first lower insulating layer 42, a second lower insulating layer 52, and a lower insulating bonding layer 62 may be sequentially stacked on the first substrate 21 and the component isolation layer 23. Each of the first substrate 21, the component isolation layer 23, the first lower insulating layer 42, the second lower insulating layer 52, and the lower insulating bonding layer 62 may extend from the first active region AR1 to the first guard ring region GR1. A lower source region 25, a lower drain region 27, a lower channel region 29, a lower gate insulating layer 32, a lower gate electrode 33, a gate capping layer 37, a gate spacer 39, a lower line 45, a lower contact plug 56, and a lower bonding pad 67 may be disposed in the first active region AR1. A lower line guard ring 45G and a lower contact guard ring 56G may be disposed in the first guard ring region GR1.

[0023] The second circuit structure CS2 may include an upper insulating bonding layer 72, a first upper insulating layer 74, an upper bonding pad 78, a second upper insulating layer 82, a third upper insulating layer 84, a first upper contact plug 89, a first upper contact protection ring 89G, a fourth upper insulating layer 92, a bit line 93, a first upper line 93′, a first upper line protection ring 93G, a fifth upper insulating layer 96, a bit contact plug 97, a second upper contact plug 97′, a second upper contact protection ring 97G, a sixth upper insulating layer 102, a stacked structure ST, a third upper contact plug 105, a third upper contact protection ring 105G, a common source line 118, a seventh upper insulating layer 122, a fourth upper contact plug 125, a fourth upper contact protection ring 125G, a second upper line 129, a second upper line protection ring 129G, and multiple channel structures 169. The stacked structure ST may include multiple alternately stacked molding layers 112 and multiple horizontal electrodes 115.

[0024] Upper insulating layer 72, first upper insulating layer 74, second upper insulating layer 82, third upper insulating layer 84, fourth upper insulating layer 92, fifth upper insulating layer 96, sixth upper insulating layer 102, and seventh upper insulating layer 122 can be sequentially stacked on the first circuit structure CS1. Upper insulating layer 72 can be bonded to lower insulating layer 62. An interface IF can be formed between upper insulating layer 72 and lower insulating layer 62. Each of upper insulating layer 72, first upper insulating layer 74, second upper insulating layer 82, third upper insulating layer 84, fourth upper insulating layer 92, fifth upper insulating layer 96, sixth upper insulating layer 102, and seventh upper insulating layer 122 can extend from the second active region AR2 to the second guard ring region GR2.

[0025] Upper bonding pad 78, first upper contact plug 89, bit line 93, first upper line 93', bit contact plug 97, second upper contact plug 97', stack structure ST, third upper contact plug 105, common source line 118, fourth upper contact plug 125, second upper line 129, and multiple channel structures 169 can be disposed in the second active region AR2. First upper contact guard ring 89G, first upper line guard ring 93G, second upper contact guard ring 97G, third upper contact guard ring 105G, fourth upper contact guard ring 125G, and second upper line guard ring 129G can be disposed in the second guard ring region GR2.

[0026] refer to Figure 2 The first guard ring region GR1 can surround the edge of the first active region AR1. A second lower insulating layer 52 can be disposed in the first active region AR1 and the first guard ring region GR1. Multiple lower contact plugs 56 can be disposed in the second lower insulating layer 52 in the first active region AR1. A lower contact guard ring 56G can be disposed in the second lower insulating layer 52 in the first guard ring region GR1. The lower contact guard ring 56G can surround the first active region AR1.

[0027] refer to Figure 3 The lower insulating bonding layer 62 can be disposed in the first active region AR1 and the first guard ring region GR1. Multiple lower bonding pads 67 can be disposed in the lower insulating bonding layer 62 in the first active region AR1, spaced apart from each other. The lower insulating bonding layer 62 can completely cover the first guard ring region GR1.

[0028] refer to Figure 4 The second guard ring region GR2 may surround the edge of the second active region AR2. An upper insulating bonding layer 72 may be disposed in the second active region AR2 and the second guard ring region GR2. A plurality of upper bonding pads 78 may be disposed in the upper insulating bonding layer 72 in the second active region AR2. The upper insulating bonding layer 72 may completely cover the second guard ring region GR2.

[0029] refer to Figure 5 The second upper insulating layer 82 can be disposed in the second active region AR2 and the second guard ring region GR2. A plurality of first upper contact plugs 89 can be disposed in the second upper insulating layer 82 in the second active region AR2. A first upper contact guard ring 89G can be disposed in the second upper insulating layer 82 in the second guard ring region GR2. The first upper contact guard ring 89G can surround the second active region AR2.

[0030] refer to Figure 6The semiconductor device 200 according to embodiments of this disclosure may include a stacked structure ST, a fifth upper insulating layer 96, a bit contact plug 97, a common source line 118, and a channel structure 169. The stacked structure ST may include a plurality of alternately stacked molded layers 112 and a plurality of horizontal electrodes 115. Each of the uppermost and lowermost layers of the stacked structure ST may be one of the plurality of molded layers 112. The common source line 118 may be disposed on the stacked structure ST.

[0031] The channel structure 169 may include an information storage pattern 157, a channel pattern 164, a core layer 166, and a drain pad 168. The information storage pattern 157 may include a tunnel layer 151, a charge trapping layer 153, and a barrier layer 155. The channel structure 169 may extend vertically through the stack structure ST and into the common source line 118. The core layer 166 may extend through the stack structure ST and into the common source line 118, meaning that the top surface of the core layer 166 may be located above the bottom surface of the common source line 118. However, because the core layer 166 is surrounded by the channel pattern 164, the core layer 166 may not contact the common source line 118. More specifically, the channel pattern 164 may surround the side surfaces and top surface (also referred to as the upper surface) of the core layer 166. The channel pattern 164 may extend into the common source line 118. The channel pattern 164 may directly contact the common source line 118.

[0032] Information storage pattern 157 may surround the side surface of channel pattern 164. Channel pattern 164 may be disposed between information storage pattern 157 and core layer 166. Information storage pattern 157 may be disposed between channel pattern 164 and stack structure ST. In an embodiment, tunnel layer 151 may be disposed on the side surface of channel pattern 164. Tunnel layer 151 may contact channel pattern 164. Tunnel layer 151 may be disposed between channel pattern 164 and charge trapping layer 153. Tunnel layer 151 may contact charge trapping layer 153.

[0033] A charge trapping layer 153 may be disposed on a side surface of the tunnel layer 151. The charge trapping layer 153 may be disposed between the tunnel layer 151 and the barrier layer 155. The barrier layer 155 may be disposed on a side surface of the charge trapping layer 153. The barrier layer 155 may be disposed between the charge trapping layer 153 and the stacked structure ST. The barrier layer 155 may extend between the charge trapping layer 153 and the plurality of horizontal electrodes 115 and between the charge trapping layer 153 and the plurality of molding layers 112.

[0034] Drain pad 168 can be disposed on the lower surface (also called the bottom surface) of core layer 166 and channel pattern 164. Drain pad 168 can directly contact channel pattern 164. Fifth upper insulating layer 96 can be disposed on the lower surface of stack structure ST and channel structure 169. Bit contact plug 97 can be disposed in fifth upper insulating layer 96. Bit contact plug 97 can be connected to drain pad 168.

[0035] In an embodiment, the plurality of horizontal electrodes 115 may include a plurality of word lines, a plurality of select lines, and at least one gate-induced drain leakage (GIDL) control line. Memory cells may be formed at the intersection of the channel structure 169 and the plurality of word lines. At least one of the plurality of horizontal electrodes 115 adjacent to the common source line 118 may correspond to the source select line. At least one of the plurality of horizontal electrodes 115 adjacent to the drain pad 168 may correspond to the drain select line. One of the plurality of horizontal electrodes 115 adjacent to the common source line 118 and / or one of the plurality of horizontal electrodes 115 adjacent to the drain pad 168 may correspond to the GIDL control line. The plurality of word lines may be disposed between at least one drain select line and at least one source select line among the plurality of horizontal electrodes 115.

[0036] Return to reference Figures 1 to 6 A first substrate 21 may be disposed within a first active region AR1 and a first guard ring region GR1. The first substrate 21 may extend from the first active region AR1 to the first guard ring region GR1. A device isolation layer 23 may be configured to extend from the upper surface of the first substrate 21 to a predetermined depth. A lower source region 25, a lower drain region 27, and a lower channel region 29 may be confined within the first substrate 21 by the device isolation layer 23. The lower source region 25 and the lower drain region 27 may be separated from each other. The lower channel region 29 may be confined between the lower source region 25 and the lower drain region 27.

[0037] A lower gate insulating layer 32 may be disposed on the lower channel region 29. A lower gate electrode 33 may be disposed on the lower gate insulating layer 32. A gate capping layer 37 may be disposed on the lower gate electrode 33. A gate spacer 39 may be disposed on the side surfaces of the gate capping layer 37 and the lower gate electrode 33. A first lower insulating layer 42 may cover the first substrate 21, the device isolation layer 23, the lower source region 25, the lower drain region 27, the lower channel region 29, the lower gate insulating layer 32, the lower gate electrode 33, the gate capping layer 37, and the gate spacer 39.

[0038] The lower line 45 and the lower line guard ring 45G may be disposed in the first lower insulating layer 42. The lower line 45 may include a plurality of horizontal lines, a plurality of vertical lines, or a combination thereof. One of the lower lines 45 may pass through the first lower insulating layer 42 to contact the lower drain region 27. Another of the lower lines 45 may pass through the first lower insulating layer 42 to contact the lower source region 25. Yet another of the lower lines 45 may pass through the first lower insulating layer 42 and the gate capping layer 37 to contact the lower gate electrode 33.

[0039] The lower wire guard ring 45G can pass vertically through the first lower insulating layer 42 in the first guard ring region GR1 to contact the first substrate 21. The uppermost end of the lower wire 45, the uppermost end of the lower wire guard ring 45G, and the uppermost end of the first lower insulating layer 42 can form the same plane or substantially the same plane. The lower wire guard ring 45G can include the same material as the lower wire 45 and is formed simultaneously with the lower wire 45.

[0040] The second lower insulating layer 52 may cover the first lower insulating layer 42, the lower wire 45, and the lower wire protection ring 45G. The lower contact plug 56 and the lower contact protection ring 56G may be disposed within the second lower insulating layer 52. The lower contact plug 56 may pass through the second lower insulating layer 52 to contact the lower wire 45. The lower contact protection ring 56G may pass through the second lower insulating layer 52 in the first protection ring region GR1 to contact the lower wire protection ring 45G.

[0041] The upper ends of the lower contact plug 56, the lower contact guard ring 56G, and the second lower insulating layer 52 may form a coplanar or substantially coplanar plane. The lower contact guard ring 56G may comprise the same material as the lower contact plug 56 and may be formed simultaneously with the lower contact plug 56. The lower contact guard ring 56G may have substantially the same thickness as the lower contact plug 56.

[0042] The lower insulating bonding layer 62 may cover the second lower insulating layer 52, the lower contact plug 56, and the lower contact guard ring 56G. A lower bonding pad 67 may be disposed within the lower insulating bonding layer 62. The lower bonding pad 67 may extend through the lower insulating bonding layer 62 in the first active region AR1 to contact the lower contact plug 56. The uppermost end of the lower bonding pad 67 and the uppermost end of the lower insulating bonding layer 62 may form a coplanar or substantially coplanar plane.

[0043] A lower insulating bonding layer 62 may be disposed within the first active region AR1 and the first guard ring region GR1. The lower insulating bonding layer 62 may extend from the first active region AR1 to the first guard ring region GR1. The lower insulating bonding layer 62 may completely cover the second lower insulating layer 52 and the lower contact guard ring 56G in the first guard ring region GR1. The lower insulating bonding layer 62 may completely fill the area above the second lower insulating layer 52 and the lower contact guard ring 56G in the first guard ring region GR1. The lower insulating bonding layer 62 may completely cover the upper surface of the lower contact guard ring 56G. The lower surface of the lower insulating bonding layer 62 may contact the upper surface of the lower contact guard ring 56G. In an embodiment, the lowermost surface of the lower insulating bonding layer 62 may contact the uppermost surface of the lower contact guard ring 56G.

[0044] In this embodiment, some or all of the first lower insulating layer 42 and the second lower insulating layer 52 may be referred to as lower insulating layers. Some or all of the lower wire 45 and the lower contact plug 56 may be referred to as lower wires. Some or all of the lower wire protection ring 45G and the lower contact protection ring 56G may be referred to as lower protection rings.

[0045] The lower source region 25, lower drain region 27, lower channel region 29, lower gate insulating layer 32, and lower gate electrode 33 can constitute a lower transistor. The lower bonding pad 67 can be connected to the lower transistor via the lower contact plug 56 and lower line 45. Multiple lower transistors can be disposed inside and / or above the first substrate 21. The lower transistor can be part of peripheral circuitry (such as a page buffer). The first circuit structure CS1 can include peripheral circuitry such as a page buffer and / or a decoder. The lower transistor can include a planar transistor, a recessed channel transistor, a vertical transistor, a finFET (fin field-effect transistor), a gate all-round (GAA) transistor, a multi-bridge channel transistor, or a combination thereof.

[0046] An upper insulating bonding layer 72 may be disposed in the second active region AR2 and the second guard ring region GR2. The upper insulating bonding layer 72 may extend from the second active region AR2 to the second guard ring region GR2. The upper insulating bonding layer 72 may be bonded to the lower insulating bonding layer 62. The upper insulating bonding layer 72 may completely cover the lower insulating bonding layer 62 in the first guard ring region GR1. In an embodiment, the upper insulating bonding layer 72 may comprise the same material as the lower insulating bonding layer 62.

[0047] The first upper insulating layer 74 can be disposed on the upper insulating bonding layer 72. The first upper insulating layer 74 can be disposed in the second active region AR2 and the second guard ring region GR2. The first upper insulating layer 74 can extend from the second active region AR2 to the second guard ring region GR2. The first upper insulating layer 74 can completely cover the upper insulating bonding layer 72 in the second guard ring region GR2.

[0048] The upper bonding pad 78 may be disposed within the upper insulating bonding layer 72 and the first upper insulating layer 74. The upper bonding pad 78 may pass through the upper insulating bonding layer 72 and the first upper insulating layer 74. The upper bonding pad 78 may be bonded to the lower bonding pad 67. The lowermost end of the upper bonding pad 78 and the lowermost end of the upper insulating bonding layer 72 may form the same plane or substantially the same plane.

[0049] The second upper insulating layer 82 and the third upper insulating layer 84 may be sequentially stacked on the first upper insulating layer 74. A first upper contact plug 89 and a first upper contact guard ring 89G may be disposed within the second upper insulating layer 82 and the third upper insulating layer 84. The first upper contact plug 89 may pass through the second upper insulating layer 82 and the third upper insulating layer 84 to contact the upper bonding pad 78. The first upper contact guard ring 89G may pass through the second upper insulating layer 82 and the third upper insulating layer 84 in the second guard ring region GR2 to contact the first upper insulating layer 74. In an embodiment, the lowermost surface of the first upper contact guard ring 89G may contact the uppermost surface of the first upper insulating layer 74. The first upper insulating layer 74 may completely cover the lower surface of the first upper contact guard ring 89G.

[0050] The first upper contact protection ring 89G may comprise the same material as the first upper contact plug 89 and be formed simultaneously with the first upper contact plug 89. The first upper contact protection ring 89G may have substantially the same thickness as the first upper contact plug 89. The lowermost end of the first upper contact plug 89, the lowermost end of the first upper contact protection ring 89G, and the lowermost end of the second upper insulating layer 82 may form the same plane or substantially the same plane.

[0051] In this embodiment, the lower insulating bonding layer 62 may extend into the first protection ring region GR1, located between the lower contact protection ring 56G and the first upper contact protection ring 89G. The upper insulating bonding layer 72 may extend into the second protection ring region GR2, located between the lower contact protection ring 56G and the first upper contact protection ring 89G. The first upper insulating layer 74 may extend into the second protection ring region GR2, located between the lower contact protection ring 56G and the first upper contact protection ring 89G.

[0052] In this embodiment, the lower insulating bonding layer 62 can completely fill the interior of the first protective ring region GR1 between the lower contact protective ring 56G and the first upper contact protective ring 89G. The upper insulating bonding layer 72 and the first upper insulating layer 74 can completely fill the interior of the second protective ring region GR2 between the lower contact protective ring 56G and the first upper contact protective ring 89G. The upper insulating bonding layer 72 and the first upper insulating layer 74 can completely cover the lower surface of the first upper contact protective ring 89G. The first upper insulating layer 74 can completely fill the interior of the second protective ring region GR2 between the first upper contact protective ring 89G and the upper insulating bonding layer 72.

[0053] The fourth upper insulating layer 92 can be disposed on the third upper insulating layer 84, the first upper contact plug 89, and the first upper contact protection ring 89G. The bit line 93, the first upper line 93', and the first upper line protection ring 93G can be disposed within the fourth upper insulating layer 92. The bit line 93 can contact one of the corresponding first upper contact plugs 89. The first upper line 93' can contact the other corresponding first upper contact plug 89. The first upper line protection ring 93G can contact the first upper contact protection ring 89G. The bit line 93, the first upper line 93', and the first upper line protection ring 93G can comprise the same material and be formed simultaneously. The bit line 93, the first upper line 93', and the first upper line protection ring 93G can have substantially the same thickness. The lowermost ends of the fourth upper insulating layer 92, the bit line 93, the first upper line 93', and the first upper line protection ring 93G can form the same plane or substantially the same plane.

[0054] A fifth upper insulating layer 96 may be disposed on the fourth upper insulating layer 92, the bit line 93, the first upper line 93', and the first upper line protection ring 93G. A bit contact plug 97, a second upper contact plug 97', and a second upper contact protection ring 97G may be disposed within the fifth upper insulating layer 96. The bit contact plug 97 may pass through the fifth upper insulating layer 96 to contact the bit line 93. The second upper contact plug 97' may pass through the fifth upper insulating layer 96 to contact the first upper line 93'. The second upper contact protection ring 97G may pass through the fifth upper insulating layer 96 to contact the first upper line protection ring 93G. The bit contact plug 97, the second upper contact plug 97', and the second upper contact protection ring 97G may comprise the same material and be formed simultaneously. The bit contact plug 97, the second upper contact plug 97', and the second upper contact protection ring 97G may have substantially the same thickness. The bottom end of the fifth upper insulating layer 96, the bottom end of the position contact plug 97, the bottom end of the second upper contact plug 97′, and the bottom end of the second upper contact protection ring 97G can form the same plane or substantially the same plane.

[0055] The sixth upper insulating layer 102 and the stacked structure ST can be disposed on the fifth upper insulating layer 96, the bit contact plug 97, the second upper contact plug 97', and the second upper contact guard ring 97G. The drain pad 168 of the channel structure 169 can contact the bit contact plug 97. The sixth upper insulating layer 102 can be disposed on the side surface of the stacked structure ST. The third upper contact plug 105 and the third upper contact guard ring 105G can be disposed in the sixth upper insulating layer 102. The third upper contact plug 105 can pass through the sixth upper insulating layer 102 to contact the second upper contact plug 97'. The third upper contact guard ring 105G can pass through the sixth upper insulating layer 102 to contact the second upper contact guard ring 97G. The third upper contact guard ring 105G can include the same material as the third upper contact plug 105 and is formed simultaneously with the third upper contact plug 105.

[0056] A common source line 118 can be disposed on the stacked structure ST. The common source line 118 can contact the channel pattern 164 of the channel structure 169. A seventh upper insulating layer 122 can be disposed on the sixth upper insulating layer 102, the stacked structure ST, the third upper contact plug 105, the third upper contact guard ring 105G, and the common source line 118. A fourth upper contact plug 125 and a fourth upper contact guard ring 125G can be disposed within the seventh upper insulating layer 122. The fourth upper contact plug 125 can pass through the seventh upper insulating layer 122 to contact the common source line 118 or the third upper contact plug 105. The fourth upper contact guard ring 125G can pass through the seventh upper insulating layer 122 to contact the third upper contact guard ring 105G. The fourth upper contact guard ring 125G can include the same material as the fourth upper contact plug 125 and is formed simultaneously with the fourth upper contact plug 125.

[0057] The second upper wire 129 and the second upper wire protection ring 129G can be disposed on the seventh upper insulating layer 122, the fourth upper contact plug 125, and the fourth upper contact protection ring 125G. The second upper wire 129 can contact the fourth upper contact plug 125. The second upper wire protection ring 129G can contact the fourth upper contact protection ring 125G. The second upper wire protection ring 129G can include the same material as the second upper wire 129 and is formed simultaneously with the second upper wire 129. The second upper wire protection ring 129G can have substantially the same thickness as the second upper wire 129.

[0058] In the embodiments, some or all of the second upper insulating layer 82, the third upper insulating layer 84, the fourth upper insulating layer 92, the fifth upper insulating layer 96, the sixth upper insulating layer 102, and the seventh upper insulating layer 122 may be referred to as upper insulating layers. Some or all of the first upper contact plug 89, the bit line 93, the first upper line 93', the bit contact plug 97, the second upper contact plug 97', the third upper contact plug 105, the fourth upper contact plug 125, and the second upper line 129 may be referred to as upper lines. Some or all of the first upper contact protection ring 89G, the first upper line protection ring 93G, the second upper contact protection ring 97G, the third upper contact protection ring 105G, the fourth upper contact protection ring 125G, and the second upper line protection ring 129G may be referred to as upper protection rings.

[0059] The channel structure 169 can be connected to the lower drain region 27 via bit contact plug 97, bit line 93, first upper contact plug 89, upper bonding pad 78, lower bonding pad 67, lower contact plug 56, and lower line 45. The stacked structure ST, multiple channel structures 169, and common source line 118 can constitute a cell array of flash memory. The second circuit structure CS2 can include non-volatile memory such as flash memory.

[0060] Figure 7 This is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure.

[0061] refer to Figure 7 The semiconductor device according to embodiments of this disclosure may include a first circuit structure CS1 and a second circuit structure CS2 bonded to the first circuit structure CS1. The first circuit structure CS1 may include a first active region AR1 and a first guard ring region GR1. The second circuit structure CS2 may include a second active region AR2 and a second guard ring region GR2.

[0062] The first circuit structure CS1 may include a first substrate 21, a component isolation layer 23, a lower source region 25, a lower drain region 27, a lower channel region 29, a lower gate insulating layer 32, a lower gate electrode 33, a gate capping layer 37, a gate spacer 39, a first lower insulating layer 42, a lower line 45, a lower line protection ring 45G, a second lower insulating layer 52, a lower contact plug 56, a lower contact protection ring 56G, a lower insulating bonding layer 62, and a lower bonding pad 67.

[0063] The second circuit structure CS2 may include an upper insulating bonding layer 72, an upper bonding pad 78, a second upper insulating layer 82, a third upper insulating layer 84, a first upper contact plug 89, a first upper contact protection ring 89G, a fourth upper insulating layer 92, a bit line 93, a first upper line 93′, a first upper line protection ring 93G, a fifth upper insulating layer 96, a bit contact plug 97, a second upper contact plug 97′, a second upper contact protection ring 97G, a sixth upper insulating layer 102, a stacked structure ST, a third upper contact plug 105, a third upper contact protection ring 105G, a common source line 118, a seventh upper insulating layer 122, a fourth upper contact plug 125, a fourth upper contact protection ring 125G, a second upper line 129, a second upper line protection ring 129G, and multiple channel structures 169. The stacked structure ST may include multiple alternately stacked molded layers 112 and multiple horizontal electrodes 115. In an embodiment, the first upper insulating layer may be omitted. Figure 1 74).

[0064] The upper insulating bonding layer 72 can completely fill the interior of the second protection ring region GR2 between the lower contact protection ring 56G and the first upper contact protection ring 89G. The upper insulating bonding layer 72 can completely cover the lower surface of the first upper contact protection ring 89G. In an embodiment, the lowermost surface of the first upper contact protection ring 89G can contact the uppermost surface of the upper insulating bonding layer 72.

[0065] According to embodiments of this disclosure, a lower bonding pad 67 may be disposed in a lower insulating bonding layer 62 in a first active region AR1, and the lower insulating bonding layer 62 may extend into a first guard ring region GR1. The lower insulating bonding layer 62 may completely cover the first guard ring region GR1. An upper bonding pad 78 may be disposed in an upper insulating bonding layer 72 in a second active region AR2, and the upper insulating bonding layer 72 may extend into a second guard ring region GR2. The upper insulating bonding layer 72 may completely cover the second guard ring region GR2. The upper insulating bonding layer 72 in the second guard ring region GR2 may be bonded to the lower insulating bonding layer 62 in the first guard ring region GR1. This can increase the coupling strength between the first circuit structure CS1 and the second circuit structure CS2.

[0066] Figures 8 to 20 This is a cross-sectional view illustrating a method for forming a semiconductor device according to an embodiment of the present disclosure. In the embodiment, Figures 8 to 20 It can be along Figures 2 to 5 The cross-sectional view taken from the sectional line II′.

[0067] refer to Figure 8A device isolation layer 23, a lower source region 25, a lower drain region 27, a lower channel region 29, a lower gate insulating layer 32, a lower gate electrode 33, a gate capping layer 37, a gate spacer 39, a first lower insulating layer 42, a lower line 45, and a lower line protection ring 45G can be formed on the first substrate 21.

[0068] The first substrate 21 may extend from the first active region AR1 to the first guard ring region GR1. The first substrate 21 may include a semiconductor substrate, such as a silicon wafer or a silicon-on-insulator (SOI) wafer. The first substrate 21 may include a III-V group semiconductor substrate, for example, a compound semiconductor substrate such as gallium arsenide (GaAs). The first substrate 21 may include monocrystalline silicon, polycrystalline silicon, amorphous silicon, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, or combinations thereof.

[0069] A device isolation layer 23 can be formed from the upper surface of the first substrate 21 to a predetermined depth using trench isolation technology. A lower source region 25 and a lower drain region 27 can be formed from the upper surface of the first substrate 21 to a predetermined depth using ion implantation technology. A lower channel region 29 can be confined between the lower source region 25 and the lower drain region 27 in the first substrate 21. The lower source region 25 and the lower drain region 27 may include impurities of a different conductivity type than the impurities in the lower channel region 29.

[0070] In one embodiment, the lower channel region 29 may include a semiconductor layer, such as single-crystal silicon with P-type impurities. The lower source region 25 and the lower drain region 27 may include semiconductor layers with N-type impurities. In another embodiment, the lower channel region 29 may include a semiconductor layer with N-type impurities, while the lower source region 25 and the lower drain region 27 may include semiconductor layers with P-type impurities.

[0071] A lower gate insulating layer 32 can be formed on the lower channel region 29. A lower gate electrode 33 can be formed on the lower gate insulating layer 32. The lower gate electrode 33 can be aligned with the lower channel region 29. The lower gate electrode 33 can be stacked with the lower channel region 29. A gate capping layer 37 can be formed on the lower gate electrode 33. The gate capping layer 37 can cover the lower gate electrode 33. Gate spacers 39 can be formed on the side surfaces of the gate capping layer 37 and the lower gate electrode 33. The first lower insulating layer 42 can cover the first substrate 21, the device isolation layer 23, the lower source region 25, the lower drain region 27, the lower channel region 29, the lower gate insulating layer 32, the lower gate electrode 33, the gate capping layer 37, and the gate spacers 39.

[0072] A lower line 45 and a lower line guard ring 45G may be formed in the first lower insulating layer 42. The lower line 45 and the lower line guard ring 45G may include a plurality of horizontal lines and a plurality of vertical lines. The lower line guard ring 45G may include the same material as the lower line 45 and may be formed simultaneously with the lower line 45. The lower line 45 may pass through the first lower insulating layer 42 to contact the lower source region 25 or the lower drain region 27. At least one lower line 45 may pass through the first lower insulating layer 42 and the gate capping layer 37 to contact the lower gate electrode 33. The lower line guard ring 45G may pass through the first lower insulating layer 42 to contact the first substrate 21.

[0073] The element isolation layer 23, lower gate insulating layer 32, gate capping layer 37, gate spacer 39, and first lower insulating layer 42 may include at least two selected from the group consisting of silicon (Si), oxygen (O), nitrogen (N), carbon (C), boron (B), phosphorus (P), and hydrogen (H). In embodiments, the lower gate insulating layer 32 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric, or a combination thereof. The element isolation layer 23, gate capping layer 37, gate spacer 39, and first lower insulating layer 42 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof. The lower gate electrode 33, lower line 45, and lower line guard ring 45G may include metal, metal nitride, metal oxide, metal silicide, polysilicon, conductive carbon, or a combination thereof.

[0074] refer to Figure 9 A second lower insulating layer 52 may be formed on the first lower insulating layer 42. The second lower insulating layer 52 may cover the lower conductor 45 and the lower conductor protection ring 45G. The second lower insulating layer 52 may include at least two selected from the group consisting of silicon (Si), oxygen (O), nitrogen (N), carbon (C), boron (B), phosphorus (P), and hydrogen (H). In embodiments, the second lower insulating layer 52 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof.

[0075] refer to Figure 10 A lower contact plug 56 and a lower contact guard ring 56G may be formed in the second lower insulating layer 52. The lower contact plug 56 may pass through the second lower insulating layer 52 to contact the lower wire 45. The lower contact guard ring 56G may pass through the second lower insulating layer 52 to contact the lower wire guard ring 45G. The lower contact guard ring 56G may comprise the same material as the lower contact plug 56 and may be formed simultaneously with the lower contact plug 56. The lower contact plug 56 and the lower contact guard ring 56G may comprise metal, metal nitride, metal oxide, metal silicide, polysilicon, conductive carbon, or combinations thereof.

[0076] The formation of the lower contact plug 56 and the lower contact guard ring 56G may include a thin film formation process and a planarization process. In an embodiment, a chemical mechanical polishing (CMP) process may be used to planarize the upper surfaces of the second lower insulating layer 52, the lower contact plug 56, and the lower contact guard ring 56G. The upper surfaces of the second lower insulating layer 52, the lower contact plug 56, and the lower contact guard ring 56G may be formed in the same plane or substantially the same plane.

[0077] refer to Figure 11 A lower insulating bonding layer 62 may be formed on the second lower insulating layer 52, the lower contact plug 56, and the lower contact guard ring 56G. A lower bonding pad 67 may be formed in the lower insulating bonding layer 62. The lower bonding pad 67 may pass through the lower insulating bonding layer 62 in the first active region AR1 to contact the lower contact plug 56.

[0078] In this embodiment, a chemical mechanical polishing (CMP) process can be used to planarize the upper surface of the lower insulating bonding layer 62 and the upper surface of the lower bonding pad 67. The upper surface of the lower insulating bonding layer 62 and the upper surface of the lower bonding pad 67 can be formed in the same plane or substantially the same plane. The lower insulating bonding layer 62 can completely cover the upper surface of the lower contact guard ring 56G. The lower insulating bonding layer 62 can completely cover the upper surface of the second lower insulating layer 52 and the upper surface of the lower contact guard ring 56G in the first guard ring region GR1.

[0079] The lower insulating bonding layer 62 may include at least two selected from the group consisting of silicon (Si), oxygen (O), nitrogen (N), carbon (C), boron (B), phosphorus (P), and hydrogen (H). In embodiments, the lower insulating bonding layer 62 may include silicon carbonitride (SiCN), silicon carbon oxynitride (SiOCN), silicon hydroxyl nitride (SiOHN), silicon carbon hydride nitride (SiCHN), silicon carbon oxynitride hydride (SiOCHN), or combinations thereof. The lower bonding pad 67 may include metal, metal nitride, metal oxide, metal silicide, polysilicon, conductive carbon, or combinations thereof. In embodiments, the lower bonding pad 67 may include a copper layer formed using an electroplating method.

[0080] refer to Figure 12A stacked structure ST, a sixth upper insulating layer 102, a third upper contact plug 105, a third upper contact guard ring 105G, multiple channel structures 169, a fifth upper insulating layer 96, a bit contact plug 97, a second upper contact plug 97′, a second upper contact guard ring 97G, a fourth upper insulating layer 92, a bit line 93, a first upper line 93′, and a first upper line guard ring 93G can be formed on the second substrate 121S. The second substrate 121S may include a semiconductor substrate that is the same as or similar to the first substrate 21. The second substrate 121S can extend from the second active region AR2 to the second guard ring region GR2.

[0081] A stacked structure ST, multiple channel structures 169, and a sixth upper insulating layer 102 can be formed on the second substrate 121S. The stacked structure ST may include multiple alternately stacked molded layers 112 and multiple horizontal electrodes 115. Each of the multiple channel structures 169 may extend vertically through the stacked structure ST and into the second substrate 121S. Figure 6 As shown, each of the multiple channel structures 169 may include an information storage pattern 157, a channel pattern 164, a core layer 166, and a drain pad 168. The information storage pattern 157 may include a tunnel layer 151, a charge trapping layer 153, and a barrier layer 155.

[0082] The plurality of molding layers 112 may include at least two selected from the group consisting of silicon (Si), oxygen (O), nitrogen (N), carbon (C), boron (B), phosphorus (P), and hydrogen (H). In an embodiment, the plurality of molding layers 112 may include silicon oxide. The plurality of horizontal electrodes 115 may include metal, metal nitride, metal oxide, metal silicide, polycrystalline silicon, conductive carbon, or combinations thereof. In an embodiment, the plurality of horizontal electrodes 115 may include tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof.

[0083] The channel pattern 164 may include a semiconductor layer such as a polysilicon layer. The core layer 166 may include an insulating layer, a conductive layer, or a combination thereof. In embodiments, the core layer 166 may include at least two selected from the group consisting of silicon (Si), oxygen (O), nitrogen (N), carbon (C), boron (B), phosphorus (P), and hydrogen (H). The core layer 166 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof. The drain pad 168 may include a semiconductor layer such as a polysilicon layer.

[0084] The sixth upper insulating layer 102 may cover the side surface of the stacked structure ST and extend to the second guard ring region GR2. The third upper contact plug 105 and the third upper contact guard ring 105G may extend vertically through the sixth upper insulating layer 102 to contact the second substrate 121S. The third upper contact guard ring 105G may comprise the same material as the third upper contact plug 105 and be formed simultaneously with the third upper contact plug 105.

[0085] A fifth upper insulating layer 96 may be formed on the stacked structure ST, the multiple channel structures 169, the sixth upper insulating layer 102, the third upper contact plug 105, and the third upper contact guard ring 105G. A position contact plug 97, a second upper contact plug 97', and a second upper contact guard ring 97G may be formed in the fifth upper insulating layer 96. The position contact plug 97, the second upper contact plug 97', and the second upper contact guard ring 97G may comprise the same material and may be formed simultaneously. The position contact plug 97 may pass through the fifth upper insulating layer 96 to connect to a corresponding one of the multiple channel structures 169. The second upper contact plug 97' may pass through the fifth upper insulating layer 96 to contact the third upper contact plug 105. The second upper contact guard ring 97G may pass through the fifth upper insulating layer 96 to contact the third upper contact guard ring 105G.

[0086] A fourth upper insulating layer 92 may be formed on the fifth upper insulating layer 96, the position contact plug 97, the second upper contact plug 97', and the second upper contact protection ring 97G. A bit line 93, a first upper line 93', and a first upper line protection ring 93G may be formed in the fourth upper insulating layer 92. The bit line 93, the first upper line 93', and the first upper line protection ring 93G may comprise the same material and be formed simultaneously. The bit line 93 may contact the position contact plug 97. The first upper line 93' may contact the second upper contact plug 97'. The first upper line protection ring 93G may contact the second upper contact protection ring 97G.

[0087] The fourth upper insulating layer 92, the fifth upper insulating layer 96, and the sixth upper insulating layer 102 may include at least two selected from the group consisting of silicon (Si), oxygen (O), nitrogen (N), carbon (C), boron (B), phosphorus (P), and hydrogen (H). In embodiments, the fourth upper insulating layer 92, the fifth upper insulating layer 96, and the sixth upper insulating layer 102 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof.

[0088] Bit line 93, first upper line 93', first upper line guard ring 93G, bit contact plug 97, second upper contact plug 97', second upper contact guard ring 97G, third upper contact plug 105, and third upper contact guard ring 105G may include metal, metal nitride, metal oxide, metal silicide, polysilicon, conductive carbon, or combinations thereof. In an embodiment, bit line 93, first upper line 93', first upper line guard ring 93G, bit contact plug 97, second upper contact plug 97', second upper contact guard ring 97G, third upper contact plug 105, and third upper contact guard ring 105G may include tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof.

[0089] refer to Figure 13 The third upper insulating layer 84 and the second upper insulating layer 82 can be sequentially stacked on the fourth upper insulating layer 92, the bit line 93, the first upper line 93', and the first upper line guard ring 93G. The third upper insulating layer 84 and the second upper insulating layer 82 can include at least two selected from the group consisting of silicon (Si), oxygen (O), nitrogen (N), carbon (C), boron (B), phosphorus (P), and hydrogen (H). In embodiments, the third upper insulating layer 84 can include SiN, SiCN, SiOCN, SiOHN, SiCHN, SiOCHN, or combinations thereof. The second upper insulating layer 82 can include SiO, SiOH, SiCH, SiCOH, or combinations thereof.

[0090] refer to Figure 14 A first upper contact plug 89 and a first upper contact guard ring 89G can be formed in the third upper insulating layer 84 and the second upper insulating layer 82. The first upper contact plug 89 can pass through the third upper insulating layer 84 and the second upper insulating layer 82 in the vertical direction to contact the bit line 93 or the first upper line 93'. The first upper contact guard ring 89G can pass through the third upper insulating layer 84 and the second upper insulating layer 82 in the vertical direction to contact the first upper line guard ring 93G. The upper surfaces of the second upper insulating layer 82, the first upper contact plug 89, and the first upper contact guard ring 89G can be planarized using a chemical mechanical polishing (CMP) process. The upper surfaces of the second upper insulating layer 82, the first upper contact plug 89, and the first upper contact guard ring 89G can be formed in the same plane or substantially the same plane.

[0091] The first upper contact protection ring 89G may comprise the same material as the first upper contact plug 89 and be formed simultaneously with the first upper contact plug 89. The first upper contact plug 89 and the first upper contact protection ring 89G may comprise metals, metal nitrides, metal oxides, metal silicides, polycrystalline silicon, conductive carbon, or combinations thereof. In embodiments, the first upper contact plug 89 and the first upper contact protection ring 89G may comprise copper (Cu), tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof.

[0092] refer to Figure 15 The first upper insulating layer 74 and the upper insulating bonding layer 72 can be sequentially stacked on the second upper insulating layer 82, the first upper contact plug 89 and the first upper contact protection ring 89G.

[0093] The first upper insulating layer 74 may comprise a material different from that of the upper insulating bonding layer 72. The first upper insulating layer 74 may comprise at least two selected from the group consisting of silicon (Si), oxygen (O), nitrogen (N), carbon (C), boron (B), phosphorus (P), and hydrogen (H). In embodiments, the first upper insulating layer 74 may comprise SiN, SiO, SiOH, SiCH, SiCOH, SiCN, SiOCN, SiOHN, SiCHN, SiOCHN, or combinations thereof.

[0094] The upper insulating bonding layer 72 may include at least two selected from the group consisting of silicon (Si), oxygen (O), nitrogen (N), carbon (C), boron (B), phosphorus (P), and hydrogen (H). In embodiments, the upper insulating bonding layer 72 may include SiCN, SiOCN, SiOHN, SiCHN, SiOCHN, or combinations thereof. The upper insulating bonding layer 72 may include the same material as the lower insulating bonding layer 62.

[0095] The first upper insulating layer 74 and the upper insulating bonding layer 72 can completely cover the upper surface of the first upper contact protection ring 89G. The first upper insulating layer 74 and the upper insulating bonding layer 72 can completely cover the upper surface of the second upper insulating layer 82 and the upper surface of the first upper contact protection ring 89G in the second protection ring region GR2. The first upper insulating layer 74 can contact the uppermost end of the first upper contact protection ring 89G. The first upper insulating layer 74 can be omitted.

[0096] refer to Figure 16An upper bonding pad 78 can be formed in the first upper insulating layer 74 and the upper insulating bonding layer 72. The upper bonding pad 78 can extend vertically through the upper insulating bonding layer 72 and the first upper insulating layer 74 to contact the first upper contact plug 89. A chemical mechanical polishing (CMP) process can be used to planarize the upper surfaces of the upper insulating bonding layer 72 and the upper surfaces of the upper bonding pad 78. The upper surfaces of the upper insulating bonding layer 72 and the upper surfaces of the upper bonding pad 78 can be formed in the same plane or substantially in the same plane.

[0097] The upper bonding pad 78 may include metal, metal nitride, metal oxide, metal silicide, polysilicon, conductive carbon, or combinations thereof. In an embodiment, the upper bonding pad 78 may include a copper layer formed using an electroplating method. The upper bonding pad 78 may include the same material as the lower bonding pad 67.

[0098] refer to Figure 17 The second circuit structure CS2 can be bonded to the first circuit structure CS1. The upper insulating bonding layer 72 and the upper bonding pad 78 can be bonded to the lower insulating bonding layer 62 and the lower bonding pad 67, facing each other.

[0099] refer to Figure 18 The upper insulating bonding layer 72 can be bonded to the lower insulating bonding layer 62, and the upper bonding pad 78 can be bonded to the lower bonding pad 67. An interface IF can be formed between the lower insulating bonding layer 62 and the upper insulating bonding layer 72, and between the lower bonding pad 67 and the upper bonding pad 78. The lower insulating bonding layer 62, the upper insulating bonding layer 72, and the first upper insulating layer 74 can completely fill the first guard ring region GR1 and the second guard ring region GR2 between the lower contact guard ring 56G and the first upper contact guard ring 89G. This can increase the coupling strength between the first circuit structure CS1 and the second circuit structure CS2.

[0100] refer to Figure 19 The stacked structure ST, the sixth upper insulating layer 102, the third upper contact plug 105, and the third upper contact guard ring 105G can be exposed by removing the second substrate 121S. The information storage pattern can be partially removed. Figure 6 157) to make the channel pattern ( Figure 6 164) is exposed. A common source line 118 can be formed on the stacked structure ST. The common source line 118 can be connected to the channel pattern ( Figure 6 (164) Contact. The common source line 118 may include a metal, metal nitride, metal oxide, metal silicide, polysilicon, conductive carbon, or a combination thereof. In an embodiment, the common source line 118 may include a semiconductor layer such as a polysilicon layer.

[0101] A seventh upper insulating layer 122 may be formed on the common source line 118, the sixth upper insulating layer 102, the third upper contact plug 105, and the third upper contact guard ring 105G. The seventh upper insulating layer 122 may include at least two selected from the group consisting of silicon (Si), oxygen (O), nitrogen (N), carbon (C), boron (B), phosphorus (P), and hydrogen (H). In embodiments, the seventh upper insulating layer 122 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof.

[0102] refer to Figure 20 A fourth upper contact plug 125 and a fourth upper contact guard ring 125G can be formed in the seventh upper insulating layer 122. The fourth upper contact guard ring 125G may comprise the same material as the fourth upper contact plug 125 and be formed simultaneously with the fourth upper contact plug 125. One of the fourth upper contact plugs selected from the fourth upper contact plugs 125 can contact the common source line 118. Another fourth upper contact plug selected from the fourth upper contact plugs 125 can contact the third upper contact plug 105. The fourth upper contact guard ring 125G can contact the third upper contact guard ring 105G.

[0103] The fourth upper contact plug 125 and the fourth upper contact protection ring 125G may comprise metal, metal nitride, metal oxide, metal silicide, polysilicon, conductive carbon, or combinations thereof. In embodiments, the fourth upper contact plug 125 and the fourth upper contact protection ring 125G may comprise copper (Cu), tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof.

[0104] Return to reference Figure 1 A second upper wire 129 and a second upper wire guard ring 129G may be formed on the seventh upper insulating layer 122. The second upper wire guard ring 129G may include the same material as the second upper wire 129 and be formed simultaneously with the second upper wire 129. The second upper wire 129 may contact the fourth upper contact plug 125. The second upper wire guard ring 129G may contact the fourth upper contact guard ring 125G. The second upper wire 129 and the second upper wire guard ring 129G may include metals, metal nitrides, metal oxides, metal silicides, polycrystalline silicon, conductive carbon, or combinations thereof. In embodiments, the second upper wire 129 and the second upper wire guard ring 129G may include copper (Cu), tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof.

[0105] The above embodiments are merely illustrative, and those skilled in the art should understand that various modifications can be made without departing from the scope of this disclosure. Therefore, the embodiments described herein are provided for illustrative purposes and should not limit the scope of this disclosure. Furthermore, these embodiments can be combined to form other embodiments.

Claims

1. A semiconductor device, comprising: A first circuit structure, wherein the first circuit structure has a first active region and a first guard ring region; as well as A second circuit structure is attached to the first circuit structure, and the second circuit structure has a second active region and a second guard ring region. The first circuit structure includes: Lower insulation layer; The lower wire is disposed in the lower insulating layer in the first active region; A lower protective ring, wherein the lower protective ring is disposed in the lower insulating layer in the first protective ring region; A lower insulating bonding layer, the lower insulating bonding layer being disposed on the lower insulating layer, the lower insulating bonding layer extending between the first active region and the first guard ring region; and A lower bonding pad is disposed in the lower insulating bonding layer in the first active region, and the lower bonding pad is connected to the lower line. The second circuit structure includes: An upper insulating bonding layer is disposed in the second active region and the second guard ring region, and the upper insulating bonding layer is bonded to the lower insulating bonding layer; An upper bonding pad is disposed in the upper insulating bonding layer in the second active region, and the upper bonding pad is bonded to the lower bonding pad; An upper insulating layer, the upper insulating layer being located on the upper insulating bonding layer; An upper line, wherein the upper line is disposed in the upper insulating layer in the second active region, and the upper line is connected to the upper bonding pad; and An upper protective ring is disposed in the upper insulating layer within the second protective ring region. The lower insulating bonding layer is disposed in the first protective ring region between the lower protective ring and the upper protective ring, and The upper insulating bonding layer is disposed in the second protective ring region between the lower protective ring and the upper protective ring.

2. The semiconductor device as claimed in claim 1, wherein, The lower insulating bonding layer completely fills the first protective ring region between the lower protective ring and the upper protective ring, and The upper insulating bonding layer completely fills the second protective ring region between the lower protective ring and the upper protective ring.

3. The semiconductor device as claimed in claim 1, wherein, The lowest surface of the lower insulating bonding layer is in contact with the highest surface of the lower protective ring, and the highest surface of the upper insulating bonding layer is in contact with the lowest surface of the upper protective ring.

4. The semiconductor device as claimed in claim 1, wherein, The lower insulating bonding layer completely covers the upper surface of the lower protective ring, and the upper insulating bonding layer completely covers the lower surface of the upper protective ring.

5. The semiconductor device as claimed in claim 1, wherein, The uppermost surface of the lower protective ring and the uppermost surface of the lower line form the same plane.

6. The semiconductor device of claim 1, wherein, The lowest surface of the upper protective ring and the lowest surface of the upper line form the same plane.

7. The semiconductor device of claim 1, wherein, The second circuit structure further includes: a first upper insulating layer, the first upper insulating layer being disposed between the upper insulating bonding layer and the upper insulating layer and having a different material from the upper insulating bonding layer; and The upper insulating bonding layer includes SiCN, SiOCN, SiOHN, SiCHN, SiOCHN, or combinations thereof.

8. The semiconductor device of claim 7, wherein, The first upper insulating layer completely fills the second protective ring region between the upper protective ring and the upper insulating bonding layer.

9. The semiconductor device of claim 7, wherein, The first upper insulating layer completely covers the lower surface of the upper protective ring.

10. The semiconductor device of claim 7, wherein, The upper bonding pad penetrates the upper insulating bonding layer and the first upper insulating layer to contact the upper line.

11. The semiconductor device of claim 1, wherein, The second circuit structure includes: A stacked structure located within the upper insulating layer; A channel structure that penetrates the stacked structure; and A common source line, wherein the common source line is disposed on the stacked structure and connected to the channel structure, and The channel structure is connected to the upper bonding pad via the upper line.

12. The semiconductor device of claim 11, wherein, The upper insulating layer includes a second upper insulating layer disposed between the upper insulating bonding layer and the stacked structure and extending into the second protective ring region. The upper line includes a bit line disposed in the second upper insulating layer and connected to the channel structure and the upper bonding pad. The upper protection ring includes the upper wire protection ring in the second upper insulation layer.

13. The semiconductor device of claim 12, wherein, The lowest end of the upper protection ring and the lowest end of the bit line form the same plane.

14. The semiconductor device of claim 12, wherein, The upper insulating layer includes a third upper insulating layer, which is disposed between the upper insulating bonding layer and the second upper insulating layer and extends into the second protective ring region. The upper line further includes an upper contact plug, which is disposed in the third upper insulating layer and contacts the bit line and the upper bonding pad. The upper protection ring further includes an upper contact protection ring, which is disposed in the third upper insulation layer and contacts the upper line protection ring.

15. The semiconductor device of claim 14, wherein, The lower surface of the upper contact protection ring and the lower surface of the upper contact plug form the same plane.

16. The semiconductor device of claim 1, wherein, The first circuit structure further includes: Substrate; and The lower transistor is located on the substrate. Wherein, the lower insulating layer covers the substrate and the lower transistor, and The lower transistor is connected to the lower bonding pad via the lower wire.

17. A semiconductor device, comprising: A first circuit structure, wherein the first circuit structure has a first active region and a first guard ring region; as well as A second circuit structure is coupled to the first circuit structure and has a second active region and a second guard ring region. The first circuit structure includes: Lower insulation layer; The lower wire is disposed in the lower insulating layer in the first active region; A lower protective ring, wherein the lower protective ring is disposed in the lower insulating layer in the first protective ring region; and A lower insulating bonding layer is disposed in the first active region and the first guard ring region, and is disposed on the lower insulating layer. The second circuit structure includes: An upper insulating bonding layer is disposed in the second active region and the second guard ring region, and is bonded to the lower insulating bonding layer; An upper insulating layer, the upper insulating layer being located on the upper insulating bonding layer; The upper line is disposed in the upper insulating layer in the second active region; and An upper protective ring is disposed in the upper insulating layer within the second protective ring region. Wherein, the lower insulating bonding layer extends into the first protective ring region between the lower protective ring and the upper protective ring, and The upper insulating bonding layer extends into the second protection ring region between the lower protection ring and the upper protection ring.

18. The semiconductor device of claim 17, wherein, The lower insulating bonding layer completely covers the upper surface of the lower protective ring, and the upper insulating bonding layer completely covers the lower surface of the upper protective ring.

19. A semiconductor device, comprising: A first circuit structure, wherein the first circuit structure has a first active region and a first guard ring region; as well as A second circuit structure is coupled to the first circuit structure and has a second active region and a second guard ring region. The first circuit structure includes: Substrate; A lower transistor, the lower transistor being located on the substrate; A lower insulating layer, the lower insulating layer being located on the substrate and the lower transistor; The lower wire is disposed in the lower insulating layer in the first active region; A lower protective ring, wherein the lower protective ring is disposed in the lower insulating layer in the first protective ring region; A lower insulating bonding layer, wherein the lower insulating bonding layer is disposed in the first active region and the first guard ring region, and is disposed on the lower insulating layer; and A lower bonding pad, wherein the lower bonding pad is disposed in the lower insulating bonding layer in the first active region and is connected to the lower line, The second circuit structure includes: An upper insulating bonding layer is disposed in the second active region and the second guard ring region, and is bonded to the lower insulating bonding layer; An upper bonding pad is disposed in the upper insulating bonding layer in the second active region and bonded to the lower bonding pad; An upper insulating layer, the upper insulating layer being located on the upper insulating bonding layer; An upper line is disposed in the upper insulating layer in the second active region and connected to the upper bonding pad; A stacked structure disposed in the upper insulating layer in the second active region; A channel structure that penetrates the stacked structure; A common source line, wherein the common source line is disposed on the stacked structure and connected to the channel structure; and An upper protective ring is disposed in the upper insulating layer within the second protective ring region. Wherein, the lower insulating bonding layer extends into the first protective ring region between the lower protective ring and the upper protective ring, and The upper insulating bonding layer extends into the second protective ring region between the lower protective ring and the upper protective ring.

20. The semiconductor device of claim 19, wherein, The lower insulating bonding layer completely covers the upper surface of the lower protective ring, and the upper insulating bonding layer completely covers the lower surface of the upper protective ring.

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