High voltage schottky diode and charge pump

Abstract

A diode includes a semiconductor substrate, an n-well formed in the semiconductor substrate, a p-well formed in the semiconductor substrate, the p-well being spaced apart from the n-well, a first isolation region formed in the n-well, a first electrode formed in direct contact with the n-well and formed of a metal material, a first heavily doped region formed in the n-well and having a dopant concentration greater than a dopant concentration of the n-well, a second electrode formed in direct contact with the first heavily doped region, a second isolation region formed in the semiconductor substrate and formed between the n-well and the p-well, a second heavily doped region formed in the p-well and having a dopant concentration greater than a dopant concentration of the p-well, and a third electrode formed in direct contact with the second heavily doped region.

Description

Technical Field

[0001] This disclosure relates to diodes, and more particularly to Schottky diodes. Background Technology

[0002] A diode is a two-terminal electronic component (with an anode and a cathode) that conducts primarily in one direction. While an ideal diode would have zero resistance in one direction and infinite resistance in the opposite direction, in practice, diodes typically have low resistance when current flows in one direction (anode to cathode) and higher resistance in the opposite direction (cathode to anode). For example, applying a positive voltage to the anode (relative to the voltage potential on the cathode) will result in relatively high electrical conduction with low resistance from anode to cathode, while having a relatively low forward bias voltage (i.e., the voltage drop across the diode). Applying a positive voltage to the cathode (relative to the voltage potential on the anode) will result in low electrical conduction with high resistance. The reverse bias voltage (the voltage drop across the diode) can reach the diode's breakdown voltage even with a very small current flowing through it. If the positive voltage on the cathode (relative to the positive voltage on the anode) exceeds the diode's breakdown voltage, then significant electrical conduction will occur from cathode to anode.

[0003] There are many types of diodes. One type is the Schottky diode, which is constructed using metal electrodes bonded to an N-type semiconductor. The metal serves as the anode, and the N-type semiconductor serves as the cathode, with the metal-semiconductor junction providing the desired electrical characteristics. Schottky diodes can have relatively fast switching speeds (i.e., rapid switching between on and off states), relatively low forward bias voltages, and relatively high reverse breakdown voltages (although not as high as many P / N junction diodes).

[0004] The performance of Schottky diodes needs to be improved, namely, lower forward voltage, lower reverse bias current leakage, and higher breakdown voltage. Summary of the Invention

[0005] The aforementioned problems and needs are addressed by a diode comprising: a semiconductor substrate; an n-well formed in the semiconductor substrate; a p-well formed in the semiconductor substrate, wherein the p-well is spaced apart from the n-well; a first isolation region formed in the n-well; a first electrode formed in direct contact with the n-well, wherein the first electrode is formed of a metallic material; a first heavily doped region formed in the n-well, wherein the first heavily doped region has a dopant concentration greater than that of the n-well; a second electrode formed in direct contact with the first heavily doped region; a second isolation region formed in the semiconductor substrate and between the n-well and the p-well; a second heavily doped region formed in the p-well, wherein the second heavily doped region has a dopant concentration greater than that of the p-well; and a third electrode formed in direct contact with the second heavily doped region.

[0006] A method for forming a diode on a semiconductor substrate, the method comprising: forming an n-well in the semiconductor substrate; forming a p-well in the semiconductor substrate, wherein the p-well is spaced apart from the n-well; forming a first isolation region in the n-well; forming a first electrode in direct contact with the n-well, wherein the first electrode is formed of a metallic material; forming a first heavily doped region in the n-well, wherein the first heavily doped region has a dopant concentration greater than that of the n-well; forming a second electrode in direct contact with the first heavily doped region; forming a second isolation region in the semiconductor substrate and between the n-well and the p-well; forming a second heavily doped region in the p-well, wherein the second heavily doped region has a dopant concentration greater than that of the p-well; and forming a third electrode in direct contact with the second heavily doped region.

[0007] A charge pump includes a semiconductor substrate and multiple pump stages, each pump stage including a diode and a capacitor. The diode includes: an n-well formed in the semiconductor substrate; a p-well formed in the semiconductor substrate, wherein the p-well is spaced apart from the n-well; a first isolation region formed in the n-well; a first electrode formed in direct contact with the n-well, wherein the first electrode is formed of a metallic material; a first heavily doped region formed in the n-well, wherein the first heavily doped region has a dopant concentration greater than that of the n-well; a second electrode formed in direct contact with the first heavily doped region; a second isolation region formed in the semiconductor substrate and between the n-well and the p-well; a second heavily doped region formed in the p-well, wherein the second heavily doped region has a dopant concentration greater than that of the p-well; and a third electrode formed in direct contact with the second heavily doped region. The capacitor has a first terminal and a second terminal electrically connected to a second electrode. For each pump stage, the first electrode is electrically connected to a circuit input or a second electrode of another pump stage, and the second electrode is electrically connected to a circuit output or a first electrode of another pump stage. A first clock signal line is electrically connected to the second terminals of a first group of multiple pump stages. A second clock signal line is electrically connected to the second terminals of a second group of multiple pump stages.

[0008] Other objects and features of this disclosure will become apparent from a review of the specification, claims and drawings. Attached Figure Description

[0009] Figure 1 This is a cross-sectional view of an example Schottky diode.

[0010] Figure 2A yes Figure 1 A top view of a Schottky diode.

[0011] Figure 2B The electrodes are omitted. Figure 2A A top view of a Schottky diode.

[0012] Figure 3 This is a cross-sectional view of a second example of a Schottky diode.

[0013] Figure 4 This is a schematic diagram of a multistage charge pump.

[0014] Figure 5 This is a schematic diagram of a multistage charge pump. Detailed Implementation

[0015] This disclosure involves Figure 1The Schottky diode 10 is shown. Diode 10 is formed on a semiconductor substrate 12 (e.g., silicon), which may be p-type doped. An n-well 14 is formed in the semiconductor substrate 12. The n-well 14 can be formed by introducing an n-type dopant (e.g., phosphorus, arsenic, or antimony) into this region of the semiconductor substrate 12. P-wells 16a and 16b are formed in the semiconductor substrate 12 such that the n-well 14 is located between and spaced from the p-wells 16a and 16b. The p-wells 16a and 16b can be formed by introducing more p-type dopant (e.g., boron, indium, aluminum, or gallium) into these regions of the semiconductor substrate 12 such that the p-type dopant concentration in the p-wells 16a and 16b is greater than the p-type dopant concentration of the surrounding p-type semiconductor substrate 12.

[0016] First isolation regions 20a, 20b and second isolation regions 22a, 22b are formed in the upper surface 12a of the semiconductor substrate 12. An isolation region is a region of the semiconductor substrate 12 in which semiconductor material is removed and replaced with an insulating material. For example, the first isolation regions 20a / b and the second isolation regions 22a / b can be shallow trench isolation (STI), a well-known and commonly used feature involving forming trenches in the upper surface of the substrate and then filling the trenches with an insulating material such as silicon oxide, silicon dioxide, or combinations thereof (collectively referred to herein as "oxides"). Figure 1 As shown, the first isolation regions 20a and 20b are completely formed within the n-well 14. The second isolation region 22a is formed between the n-well 14 and the p-well 16a. The second isolation region 22b is formed between the n-well 14 and the p-well 16b.

[0017] A first electrode 24 (i.e., the anode) is formed on the surface 12a of the semiconductor substrate 12, above the n-well 14, and between the first isolation regions 20a and 20b. The first electrode 24 is formed of a metallic material and is in direct contact with the n-well 14. A non-limiting example of the metallic material used for the first electrode 24 is a silicide, which is a combination of metal and silicon. The silicide can be formed by forming a metal layer on the upper surface 12a of the semiconductor substrate 12, followed by an annealing process that mixes the metal and silicon together. Non-limiting examples of silicides include nickel silicide (NiSi) and cobalt silicide (CoSi).

[0018] Second electrodes 26a and 26b (i.e., cathodes) are formed on the upper surface 12a of the semiconductor substrate 12, above the n-well 14. Second electrode 26a is disposed between the first isolation region 20a and the second isolation region 22a (i.e., the first isolation region 20a is disposed between the first electrode 24 and the second electrode 26a), and second electrode 26b is disposed between the first isolation region 20b and the second isolation region 22b (i.e., the first isolation region 20a is disposed between the first electrode 24 and the second electrode 26a). Second electrodes 26a and 26b may be made of the same material as the first electrode 24.

[0019] Heavily doped regions 28a and 28b (i.e., first heavily doped regions) are formed in the n-well 14 directly below the second electrodes 26a and 26b, respectively (i.e., heavily doped region 28a is located below the second electrode 26a and between the first isolation region 20a and the second isolation region 22a, and heavily doped region 28b is located below the second electrode 26b and between the first isolation region 20b and the second isolation region 22b). The heavily doped regions 28a and 28b can be N+ (i.e., the heavily doped regions 28a and 28b have an n-type dopant concentration greater than the n-type dopant concentration of the surrounding n-well 14).

[0020] Heavily doped regions 30a and 30b (i.e., second heavily doped regions) may be formed in the n-well 14 directly below the edge portion of the first electrode 24 and extend along the first isolation regions 20a and 20b. The heavily doped regions 30a and 30b may be P+ (i.e., the heavily doped regions 30a and 30b have a p-type dopant concentration greater than the n-type dopant concentration of the n-well 14). The first electrode 24 is in direct contact with the n-well 14 between the heavily doped regions 30a and 30b.

[0021] Third isolation regions 32a and 32b (having a composition similar to that of the first isolation region 20a / b and the second isolation region 22a / b) may be formed at least partially in p-wells 16a and 16b, respectively, wherein the third isolation region 32a is spaced apart from the second isolation region 22a, and the third isolation region 32b is spaced apart from the second isolation region 22b.

[0022] Third electrodes 34a and 34b (i.e., for connection to voltage source V) are formed on the upper surface 12a of semiconductor substrate 12 above p-wells 16a and 16b, respectively. Third electrode 34a is disposed between second isolation region 22a and third isolation region 32a, and third electrode 34b is disposed between second isolation region 22b and third isolation region 32b. Third electrodes 34a and 34b may be made of the same material as the first electrode 24.

[0023] Heavily doped regions 36a and 36b (i.e., third heavily doped regions) are formed in n-wells 16a and 16b directly below the third electrodes 34a and 34b, respectively (i.e., heavily doped region 36a is located below the third electrode 34a and between the second isolation region 22a and the third isolation region 32a, and heavily doped region 36b is located below the third electrode 34b and between the second isolation region 22b and the third isolation region 32b). Heavily doped regions 36a and 36b can be P+ (i.e., heavily doped regions 36a and 36b have a p-type dopant concentration greater than that of the surrounding p-wells 16a and 16b).

[0024] Figure 2A This is a top view of the upper surface 12a of the semiconductor substrate 12, wherein Figure 1 yes Figure 2A A sectional view along line AA. Figure 2B Is with Figure 2A The same top view is shown, except that the first electrode 24, second electrodes 26a and 26b, and third electrodes 34a and 34b are omitted. The first electrode 24 may have a rectangular shape. The first isolation regions 20a and 20b may be continuous first isolation regions 20 surrounding the first electrode 24 (i.e., when viewed from above the upper surface 12a). The second electrodes 26a and 26b may be continuous second electrodes 26 surrounding the first isolation region 20. The second isolation regions 22a and 22b may be continuous second isolation regions 22 surrounding the first isolation region 20. The third electrodes 34a and 34b may be continuous third electrodes 34 surrounding the second isolation region 22. Therefore, the heavily doped regions 28a and 28b can be continuous heavily doped regions 28 extending below the second electrode 26 and surrounding the first isolation region 20, the heavily doped regions 36a and 36b can be continuous heavily doped regions 36 extending below the third electrode 34 and surrounding the second isolation region 22, the heavily doped regions 30a and 30b can be continuous heavily doped regions 30 extending below the first electrode 24 and along the first isolation region 20, and the third isolation regions 32a and 32b can be continuous third isolation regions 32 surrounding the heavily doped regions 36.

[0025] The first electrode 24 (made of a metallic material) is in direct contact with a relatively lightly doped n-well 14 portion of the semiconductor substrate 12, thereby forming a metal-semiconductor junction with a Schottky barrier. This Schottky barrier is conductive in the forward bias direction (i.e., when a positive voltage is applied to the first electrode 24 relative to the n-well 14, current flows in the forward direction), with a barrier height of approximately 0.5 volts. The Schottky barrier is typically non-conductive (i.e., high resistance) in the reverse bias direction (i.e., when a positive voltage is applied to the n-well 14 relative to the first electrode 24). In contrast, the second electrodes 26a and 26b (also made of a metallic material) are in direct contact with heavily doped regions 28a and 28b of the semiconductor substrate 12. The high doping levels of the heavily doped regions 28a and 28b effectively change the work function of the n-type semiconductor to be closer to that of a metal silicide (which is fixed). The end result is that the metal-semiconductor junction at the second electrodes 26a and 26b is conductive in both directions, without a significant Schottky barrier to prevent current in either direction.

[0026] In operation, when a positive voltage is applied to the first electrode 24 (relative to the voltage applied to the second electrodes 26a, 26b), current flows in the forward direction from the first electrode 24 through the n-well 14 below the first isolation regions 20a, 20b to the second electrodes 26a, 26b with low resistance and a low forward bias voltage. As an example, the turn-on voltage (i.e., the voltage that allows current to flow in the forward direction) can be as low as about 0.5V. In contrast, when a positive voltage is applied to the second electrodes 26a, 26b (relative to the voltage applied to the first electrode 24), there is a high resistance that suppresses current in the opposite direction due to the Schottky barrier at the first electrode 24. As an example, the breakdown voltage (i.e., the voltage that allows current to flow in the opposite direction despite the high Schottky barrier) can be greater than 16V.

[0027] Similarly, during operation, a low voltage, ground voltage, or negative voltage V is applied to the third electrodes 34a, 34b to capture minority carriers leaking through the substrate 12, which are then conducted away through the third electrodes 34a, 34b. Effective minority carrier capture is achieved by spacing the p-wells 16a, 16b from the n-well 14 by a distance S. The distance S allows minority carriers to be captured from the semiconductor material of the semiconductor substrate 12 beneath the second isolation regions 22a, 22b. The third electrodes 34a, 34b (also made of metallic material) are in direct contact with the heavily doped regions 36a, 36b of the semiconductor substrate 12. The heavily doped regions 36a, 36b are used to change the work function of the p-type doped semiconductor material to be closer to that of metal silicides (which are fixed). The end result is that the metal-semiconductor junction at the third electrodes 34a, 34b is conductive in both directions without a significant Schottky barrier to prevent current in either direction.

[0028] Diode 10 offers several advantages. It can have a low forward voltage, for example, approximately 0.5V at room temperature. The reverse-bias breakdown voltage can exceed 9V to 10V, with very low leakage current below reverse-bias breakdown. The transition from heavily doped regions 28a, 28b to the n-well 14 between the first isolation regions 20a, 20b and the second isolation regions 22a, 22b results in low reverse saturation current leakage. Including heavily doped regions 30a, 30b below the first electrode 24 is optional, but has been found to reduce leakage current by up to four to six times at room temperature and by two to three times at high temperatures, while exhibiting a high ratio (e.g., >20) between the on-current (in the forward direction) and off-current (in the reverse direction) without measurable loss of anode capacitance. The spacing S between the n-well 14 and the p-wells 16a, 16b (separated by the semiconductor substrate material beneath the second isolation regions 22a, 22b) contributes to a high breakdown voltage. The diode 10, as a single unit, provides low reverse current leakage and rapid switching between forward bias (conduction on) and reverse bias (conduction off), and vice versa. This allows for a relatively small area occupied by the first electrode 24, resulting in low parasitic capacitance with little or no degradation of the forward conduction voltage.

[0029] Figure 3 Another example is shown, which is similar to Figure 1 For example, but below the second isolation regions 22a, 22b and between n-well 14 and p-wells 16a, 16b, n-wells 40a, 40b are added. n-wells 40a, 40b may have an n-type dopant concentration less than that of n-well 14 to provide a higher reverse breakdown voltage. It has been found that adding n-wells 40a, 40b increases the overall breakdown voltage.

[0030] Figure 4 An example application for diode 10 is illustrated. Specifically, a multi-stage charge pump 50 for boosting the input voltage can utilize multiple diodes 10 connected in series. The multi-stage charge pump 50 includes multiple pump stages PS1-PS1. n (where n is greater than or equal to 4). Each pump stage PS includes 10 diodes (as mentioned above). Figures 1 to 3 (The type described) and capacitor 52. Each diode 10 has an input terminal (i.e., its first electrode 24) and an output terminal (i.e., its second electrode 26). The circuit input of the multi-stage charge pump 50 is placed on the first electrode 24 of diode 101, wherein the second electrode 26 of diode 101 is electrically connected to the first electrode 24 of diode 102, and the second electrode 26 of diode 102 is electrically connected to the first electrode 24 of diode 103, and so on. Diode 10 nThe second electrode 26 provides the circuit output of the multi-stage charge pump 50. Therefore, for each pump stage PS, except for the first pump stage PS1 where the first electrode 24 is connected to the circuit input, the first electrode 24 is electrically connected to the second electrode 26 of the previous pump stage PS. Similarly, for each pump stage PS, except for the last pump stage PS where the second electrode 26 is connected to the circuit output... n In addition, the second electrode 26 is electrically connected to the first electrode 24 of the subsequent pump stage PS.

[0031] The capacitor 52 for each pump stage PS includes a first terminal electrically connected to the second electrode 26 of the corresponding diode 10 and a second terminal electrically connected to either the first clock signal line 54 or the second clock signal line 56. Specifically, for odd-numbered pump stages PS1...PS n-1 (That is, the first group in the pump stage PS), corresponding capacitors 521...52 n The second terminal of -1 is connected to the first clock signal line 54; for even-numbered pump stages PS2...PS n (That is, the second group in the pump stage PS), corresponding capacitors 522...52 n The second terminal is connected to the second clock signal line 56; wherein the odd-numbered pump stages PS1...PS n-1 (That is, the first group in pump stage PS) and even-numbered pump stages PS2...PS n (That is, the second group in the pump stage PS) is interleaved.

[0032] A clock signal source circuit 58 is connected to a first clock signal line 54 and a second clock signal line 56 to provide a first clock signal clk1 on the first clock signal line 54 and a second clock signal clk2 on the second clock signal line 56. The clock signal source circuit 58 can generate the first clock signal clk1 and the second clock signal clk2 on the chip, or it can receive the first clock signal clk1 and the second clock signal clk2 from an external source. The first clock signal clk1 is the inverse of the second clock signal (i.e., when the first clock signal clk1 is low, the second clock signal clk2 is high, and vice versa).

[0033] The multistage charge pump 50 offers numerous advantages. It operates using only two clock signals. Due to the fast response (i.e., switching time) of the Schottky diode 10, the clock signals can be rapid. The size of the multistage charge pump 50 can be significantly smaller than conventional pump designs, as can its power consumption. The pump efficiency is higher than conventional pump designs, allowing for the use of lower startup voltages. As a non-limiting example, a multistage charge pump 50 with twenty pump stages (i.e., n = 20) (using a first clock signal clk1 and a second clock signal clk2, each with a clock frequency of 10 ns and an input voltage of 1.6 V) can output 12 V with a power consumption of only 0.8 mA and occupy a total area of ​​0.03 square millimeters. As another non-limiting example, a multi-stage charge pump 50 with twenty pump stages (i.e., n=20) (using a first clock signal clk1 and a second clock signal clk2, each with a clock frequency of 5ns and an input voltage of 1.6V) can output a voltage of 12V with a power consumption of 1.08mA and occupy a total area of ​​0.016 square millimeters.

[0034] Figure 5 Another example of a multi-stage charge pump 50 is illustrated, except that the circuit output includes a load diode 10. L and load capacitor 52 L In addition, it and Figure 4 Same as shown. Load diode 10 L This can be the above about Figures 1 to 3 The type described (i.e., having the same elements as those described above, where, for clarity, the elements described above are...) Figure 1 , Figure 2A , Figure 2B and Figure 3 All components of the described diode 10 are load diodes 10. L The components, each of which can be individually referred to as the preceding "load", such as load n-well 14, first load isolation region 20, second load isolation region 22, first load electrode 24, second load electrode 26, etc. Diode 10 n The second electrode 26 is electrically connected to the load diode 10. L The first load electrode 24. Load capacitor 52. L Includes electrical connection to load diode 10 L The second load electrode 26 has a first load terminal and a second load terminal electrically connected to a voltage source such as ground. It includes a load diode 10. L and load capacitor 52 L The advantage of using it as part of the circuit output is that it provides a charge pump output to nodes with load capacitance.

[0035] It should be pointed out that, although Figure 2Aand Figure 2B A series of elements surrounding the first electrode 24 are shown (i.e., a series of first isolation regions 20 surrounding the first electrode 24, a series of second electrodes 26 surrounding the first isolation regions 20, a series of second isolation regions 22 surrounding the first isolation regions 20 and the second electrodes 26, a series of third electrodes 34 surrounding the second isolation regions 22, etc.), but these elements need not be continuous, so that each of these elements can be made into two or more such elements to form a single diode 10.

[0036] It should be understood that this disclosure is not limited to the examples above and illustrated herein, but covers any and all variations within the scope of any claim. For example, references to this disclosure or the invention or examples herein are not intended to limit the scope of any claim or claim terminology, but only to one or more features that may be covered by one or more claims. The examples of materials, processes, and values ​​described above are merely exemplary and should not be construed as limiting the claims. A single layer of material may be formed as multiple layers of such or similar materials, and vice versa. As used herein, the terms "form" and "formed" should include material deposition, material growth, or any other technique used to provide the disclosed or claimed material. Unless otherwise stated, the claims encompass the claims, and therefore "each" of a plurality of limited elements does not exclude the inclusion of additional such elements lacking limitation, unless expressly stated otherwise. Finally, it should be noted that references herein to circuits or modules of circuits that perform or are configured to perform operations refer to the physical structure of the circuit (i.e., the circuitry capabilities determined by its structure), and not to any method or actual use of the circuit.

Claims

1. A diode, the diode comprising: Semiconductor substrate; n-well, wherein the n-well is formed in the semiconductor substrate; p-well, the p-well being formed in the semiconductor substrate, wherein the p-well is connected to the... n-wells are spaced apart; A first isolation region is formed in the n-well; A first electrode is formed in direct contact with the n-well, wherein the first electrode is formed of a metallic material; A first doped region is formed in the n-well, wherein the first doped region has a dopant concentration greater than that of the n-well; The second electrode is formed in direct contact with the first heavily doped region; A second isolation region is formed in the semiconductor substrate and between the n-well and the p-well; A second doped region is formed in the p-well, wherein the second doped region has a dopant concentration greater than that of the p-well. and The third electrode is formed in direct contact with the second heavily doped region.

2. The diode according to claim 1, wherein the first heavily doped region comprises an n-type dopant.

3. The diode according to claim 1, wherein the second heavily doped region comprises a p-type dopant.

4. The diode according to claim 1, wherein the diode comprises: A third doped region is formed below and in direct contact with the first electrode, wherein the third doped region has a dopant concentration greater than that of the n-well.

5. The diode according to claim 4, wherein the third doped region comprises a p-type dopant.

6. The diode of claim 4, wherein the third heavily doped region extends along the first isolation region.

7. The diode according to claim 1, wherein: The first isolation region includes oxides; and The second isolation zone includes oxides.

8. The diode of claim 1, wherein the semiconductor substrate comprises a p-type dopant.

9. The diode according to claim 1, wherein: The first isolation region surrounds the first electrode; The second electrode surrounds the first isolation region; The second isolation region surrounds the second electrode; and The third electrode surrounds the second isolation region.

10. The diode according to claim 9, wherein: The first heavily doped region surrounds the first isolation region; and The second heavily doped region surrounds the second isolation region.

11. The diode according to claim 1, wherein the diode comprises: The second n-well is formed below the first isolation region and between the n-well and the p-well.

12. A method for forming a diode on a semiconductor substrate, the method comprising: An n-well is formed in the semiconductor substrate; A p-well is formed in the semiconductor substrate, wherein the p-well is spaced apart from the n-well; A first isolation region is formed in the n-well; A first electrode is formed in direct contact with the n-well, wherein the first electrode is formed of a metallic material; A first heavily doped region is formed in the n-well, wherein the first heavily doped region has a dopant concentration greater than that of the n-well; A second electrode is formed in direct contact with the first heavily doped region; A second isolation region is formed in the semiconductor substrate and between the n-well and the p-well; A second doped region is formed in the p-well, wherein the second doped region has a dopant concentration greater than that of the p-well; as well as The third electrode is formed in direct contact with the second heavily doped region.

13. The method of claim 12, wherein the first heavily doped region comprises an n-type dopant and the second heavily doped region comprises a p-type dopant.

14. The method according to claim 12, wherein the method comprises: A third doped region is formed below and in direct contact with the first electrode, wherein the third doped region has a dopant concentration greater than that of the n-well.

15. The method according to claim 12, wherein: The first isolation region surrounds the first electrode; The second electrode surrounds the first isolation region; The second isolation region surrounds the second electrode; and The third electrode surrounds the second isolation region.

16. The method of claim 15, wherein: The first heavily doped region surrounds the first isolation region; and The second heavily doped region surrounds the second isolation region.

17. The method according to claim 12, further comprising: A second n-well is formed below the first isolation zone and between the n-well and the p-well.

18. A charge pump, the charge pump comprising: Semiconductor substrate; Multiple pump stages, each of which includes: A diode, the diode comprising: n-well, wherein the n-well is formed in the semiconductor substrate; p-well, wherein the p-well is formed in the semiconductor substrate, and wherein the p-well is spaced apart from the n-well; A first isolation region is formed in the n-well; A first electrode is formed in direct contact with the n-well, wherein the first electrode is formed of a metallic material; A first doped region is formed in the n-well, wherein the first doped region has a dopant concentration greater than that of the n-well; The second electrode is formed in direct contact with the first heavily doped region; A second isolation region is formed in the semiconductor substrate and between the n-well and the p-well; A second doped region is formed in the p-well, wherein the second doped region has a dopant concentration greater than that of the p-well; and A third electrode is formed in direct contact with the second heavily doped region; and A capacitor having a first terminal and a second terminal electrically connected to the second electrode; For each pump stage in the pump stages: The first electrode is electrically connected to the circuit input or the second electrode of another pump stage in the pump stage, and The second electrode is electrically connected to the circuit output or the first electrode of another pump stage in the pump stage; A first clock signal line, the first clock signal line being electrically connected to the second terminal of a first group of the plurality of pump stages; and The second clock signal line is electrically connected to the second terminal of the second group of the plurality of pump stages.

19. The charge pump of claim 18, wherein the charge pump comprises: A clock signal source circuit is provided to provide a first clock signal to the first clock signal line and a second clock signal to the second clock signal line, wherein the first clock signal is the inverse of the second clock signal.

20. The charge pump of claim 18, wherein the first group of the plurality of pump stages is alternated with the second group of the plurality of pump stages.

21. The charge pump of claim 18, wherein the charge pump comprises: Load diode, the load diode comprising: A loaded n-well, wherein the loaded n-well is formed in the semiconductor substrate; A loaded p-well, wherein the loaded p-well is formed in the semiconductor substrate, and wherein the loaded p-well is spaced apart from the loaded n-well; A first load isolation region is formed in the load n-well; A first load electrode is formed in direct contact with the load n-well, wherein the first load electrode is formed of a metallic material; A first heavily doped region is formed in the n-well, wherein the first heavily doped region has a dopant concentration greater than that of the n-well. The second load electrode is formed in direct contact with the first heavily doped load region. A second load isolation region is formed in the semiconductor substrate and between the load n-well and the load p-well; A second heavily doped region is formed in the loaded p-well, wherein the second heavily doped region has a dopant concentration greater than that of the loaded p-well; and A third load electrode is formed in direct contact with the second heavily doped region; and A load capacitor having a first load terminal electrically connected to the second load electrode and a second load terminal electrically connected to a voltage source.

22. The charge pump of claim 21, wherein the voltage source is grounded.

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