Method of manufacturing silicon carbide power device and silicon carbide power device
By employing a double-layer epitaxial process in silicon carbide MOSFET devices to introduce nitrogen and boron doping to form deep-level recombination centers, the complexity of traditional processes is solved, and the on-resistance and leakage current are reduced, thereby improving the conductivity of the material and the performance of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- INVENTCHIP TECH CO LTD
- Filing Date
- 2026-03-19
- Publication Date
- 2026-06-23
AI Technical Summary
Existing technologies struggle to effectively reduce minority carrier lifetime when manufacturing silicon carbide MOSFET devices, leading to bipolar degradation effects, increased on-resistance and leakage current, and complex traditional processes that make it difficult to control defect depth distribution.
A double-layer epitaxial process is used to grow a first N-type epitaxial layer and a second N-type epitaxial layer on a silicon carbide substrate. Nitrogen doping and boron doping are introduced into the second N-type epitaxial layer to form deep-level recombination centers to regulate minority carrier lifetime. This simplifies the process and avoids high-temperature annealing and electron irradiation.
By controlling the minority carrier lifetime, the on-resistance and leakage current of the device are reduced, the conductivity of the material is improved, energy loss is reduced, and the process is simple and compatible with conventional SiC MOSFET processes.
Smart Images
Figure CN122269741A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductors, and more particularly to a method for manufacturing silicon carbide power devices. Background Technology
[0002] Silicon carbide (SiC) MOSFETs are a crucial component in realizing the green energy revolution. Planar SiC MOSFETs are currently one of the mainstream silicon carbide power devices, such as planar VDMOS (Vertical Double-diffused Metal-Oxide-Semiconductor). Their advantages include relatively simple device structure and manufacturing process, and mature reliability. SiC MOSFETs are suitable for applications requiring high power density, high efficiency, and high switching frequency. Optimizing the device's switching characteristics, especially improving the reverse recovery characteristics of the body diode, is critical.
[0003] To reduce switching losses caused by reverse recovery of the body diode, it is necessary to accelerate the recombination and removal of minority carriers (hereinafter referred to as "minority carriers") during the turn-off process. One effective method is to reduce the minority carrier lifetime. Furthermore, SiC bipolar devices exhibit a "bipolar degradation effect," meaning that when minority carrier injection exceeds a certain level, basal plane dislocations (BPDs) in the SiC substrate may convert into single-shockley stacking faults (1SSFs) in the epitaxial layer, causing a series of adverse effects such as increased Rdson, increased Vsd, and increased Idss leakage current in the SiC MOSFET. Therefore, it is necessary to reduce the minority carrier lifetime to suppress the occurrence of the bipolar degradation effect.
[0004] Traditional silicon-based bipolar devices typically employ methods such as electron irradiation and high-temperature annealing (>1800℃) to introduce minority carrier recombination centers and reduce minority carrier lifetime. These methods are relatively complex, requiring additional process steps or equipment, and it is difficult to control the depth distribution of defects. Summary of the Invention
[0005] In a first aspect, embodiments of this application provide a method for manufacturing a silicon carbide power device, the method comprising:
[0006] A first N-type epitaxial layer is grown on a silicon carbide substrate;
[0007] A second N-type epitaxial layer is grown on the first N-type epitaxial layer, the second N-type epitaxial layer containing both nitrogen doping and boron doping;
[0008] P-Well, N+ and P+ regions were implanted on the second N-type epitaxial layer, and then high-temperature activation annealing was performed.
[0009] The device is fabricated by forming a gate oxide layer, a polysilicon gate, an insulating dielectric layer, and a source metal.
[0010] Secondly, embodiments of this application provide silicon carbide power devices manufactured using the method described in the first aspect.
[0011] In this invention, in a SiC MOSFET device, boron ions (B) are introduced by simultaneously using nitrogen doping and boron doping in the second N-type epitaxial layer, thereby enabling the modulation of minority carrier lifetime. Boron ion doping introduces deep-level recombination centers (D-centers) in the silicon carbide bandgap, generating carbon vacancies in the adjacent lattice. D-centers and carbon vacancies are considered to be the main defect types limiting the minority carrier lifetime of silicon carbide, thus playing a role in modulating the minority carrier lifetime.
[0012] In this invention, boron ions are introduced through a double-layer epitaxy (a first N-type epitaxial layer and a second N-type epitaxial layer) to form minority carrier recombination centers. This method is fully compatible with conventional SiC MOSFET processes and is simple to implement. It avoids the complex processes of introducing minority carrier recombination centers through traditional methods such as electron irradiation and high-temperature annealing (>1800℃), thus reducing the difficulty of control.
[0013] In this invention, the N-type doping concentration of the second N-type epitaxial layer is greater than that of the first N-type epitaxial layer. A higher N-type doping concentration improves the conductivity of the material. In power devices, this highly doped region (i.e., the second N-type epitaxial layer) can act as a current spreading layer, allowing current to flow more smoothly from the source to the drain, reducing energy loss. Furthermore, in SiC MOSFETs, the doping concentration of the JFET region between the two P-well regions directly determines the trade-off between the device's voltage withstand capability and on-resistance. Therefore, increasing the N-type doping concentration of the second N-type epitaxial layer can reduce the on-resistance. Attached Figure Description
[0014] Figure 1 A flowchart illustrating a method for manufacturing a silicon carbide power device according to an embodiment of the present invention is shown;
[0015] Figures 2a to 2d A process diagram for manufacturing a silicon carbide power device according to an embodiment of the present invention is shown. Detailed Implementation
[0016] The following specific embodiments illustrate the implementation of the present invention. It should be noted that in this specification, similar reference numerals and letters denote similar items in the following drawings; therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.
[0017] The terms “first,” “second,” “third,” etc., are used only for distinguishing descriptions and do not indicate any order, nor should they be interpreted as indicating or implying relative importance.
[0018] Figure 1 A flowchart illustrating a method for manufacturing a silicon carbide power device according to an embodiment of the present invention is shown; Figures 2a to 2d A process diagram for manufacturing a silicon carbide power device according to an embodiment of the present invention is shown.
[0019] The following is combined with Figure 1 , Figures 2a to 2d The present invention describes in detail the method for manufacturing silicon carbide power devices.
[0020] In S11, a first N-type epitaxial layer is grown on a silicon carbide substrate. For example... Figure 2a As shown, a first N-type epitaxial layer 1 is grown on a silicon carbide substrate 10. In this embodiment, the first N-type epitaxial layer 1 is nitrogen-doped. It is understood that its doping concentration and thickness can be set according to the voltage rating requirements.
[0021] Understandably, the first N-type epitaxial layer 1 can also use other dopants without restriction.
[0022] In S12, a second N-type epitaxial layer is grown on the first N-type epitaxial layer, the second N-type epitaxial layer containing both nitrogen doping and boron doping.
[0023] like Figure 2b As shown, a second N-type epitaxial layer 2 is grown on the first N-type epitaxial layer 1. The second N-type epitaxial layer 2 contains both nitrogen doping and boron doping (Boron + Nitrogen-doped). The thickness of the second N-type epitaxial layer 2 is 1 to 2 micrometers.
[0024] In this invention, the N-type doping concentration of the second N-type epitaxial layer 2 is greater than that of the first N-type epitaxial layer. A higher N-type doping concentration can improve the conductivity of the material. In power devices, this highly doped region (i.e., the second N-type epitaxial layer 2) can act as a current spreading layer, allowing current to flow more smoothly from the source to the drain, reducing energy loss. Furthermore, in SiC MOSFETs, the JFET region between the two P-well regions (e.g., ...) Figure 2cThe doping concentration of the second N-type epitaxial layer (as shown) directly determines the trade-off between the device's voltage withstand and on-resistance. Therefore, increasing the N-type doping concentration of the second N-type epitaxial layer 2 can reduce the on-resistance.
[0025] In S13, P-Well, N+ and P+ regions are implanted on the second N-type epitaxial layer, and high-temperature activation annealing is performed.
[0026] like Figure 2c As shown, P-Well, N+, and P+ regions are implanted on the second N-type epitaxial layer 2. These are conventional implantations for planar VDMOS, followed by high-temperature activation annealing. It can be understood that the JFET region lies between the two P-well regions.
[0027] It is understandable that P-Well, N+, and P+ are all "doped regions" in silicon carbide power devices, used to construct the device structure.
[0028] As we can understand, the P-Well region is the P-well (also called a P-type well) region. In VDMOS, it is the P-type base region where the channel is located. Its main function is to form the channel of the MOS transistor and to bear the breakdown voltage and block reverse voltage. The N+ region represents the heavily doped N-type region, usually implanted / diffused with nitrogen (N), phosphorus (P), or arsenic (As). It has a very high concentration and strong conductivity. In VDMOS, N+ is equivalent to the source, the heavily doped region through which current flows. The P+ region represents the heavily doped P-type region, with a very high concentration, strong conductivity, and good ohmic contact. In VDMOS, P+ is equivalent to the ohmic contact region next to the source.
[0029] In S14, the gate oxide layer, polysilicon gate, insulating dielectric layer, and source metal are formed to complete the device fabrication.
[0030] like Figure 2d As shown, conventional planar VDMOS processes such as gate oxidation, polysilicon deposition, dielectric layer deposition, ohmic contact, and metallization are performed to form a gate oxide layer (not shown), a polysilicon gate (not shown), an insulating dielectric layer 3, and a source metal 4. This completes the fabrication of the silicon carbide power device 200.
[0031] Boron doping introduces deep recombination centers (D-centers) in the silicon carbide bandgap and generates carbon vacancies in the adjacent lattice, which can be used to regulate minority carrier lifetime.
[0032] This invention also provides a silicon carbide power device. For example... Figure 2d As shown, the silicon carbide power device 200 uses Figure 1 The silicon carbide power device is manufactured using the method shown.
[0033] In this invention, in a SiC MOSFET device, boron ions (B) are introduced by simultaneously using nitrogen doping and boron doping in the second N-type epitaxial layer, thereby enabling the modulation of minority carrier lifetime. Boron ion doping introduces deep-level recombination centers (D-centers) in the silicon carbide bandgap, generating carbon vacancies in the adjacent lattice. D-centers and carbon vacancies are considered to be the main defect types limiting the minority carrier lifetime of silicon carbide, thus playing a role in modulating the minority carrier lifetime.
[0034] In this invention, boron ions are introduced through a double-layer epitaxy (a first N-type epitaxial layer and a second N-type epitaxial layer) to form minority carrier recombination centers. This method is fully compatible with conventional SiC MOSFET processes and is simple to implement. It avoids the complex processes of introducing minority carrier recombination centers through traditional methods such as electron irradiation and high-temperature annealing (>1800℃), thus reducing the difficulty of control.
[0035] In this invention, the N-type doping concentration of the second N-type epitaxial layer is greater than that of the first N-type epitaxial layer. A higher N-type doping concentration improves the conductivity of the material. In power devices, this highly doped region (i.e., the second N-type epitaxial layer) can act as a current spreading layer, allowing current to flow more smoothly from the source to the drain, reducing energy loss. Furthermore, in SiC MOSFETs, the doping concentration of the JFET region between the two P-well regions directly determines the trade-off between the device's voltage withstand capability and on-resistance. Therefore, increasing the N-type doping concentration of the second N-type epitaxial layer can reduce the on-resistance.
[0036] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.
[0037] Similarly, it should be understood that, in order to simplify the invention and aid in understanding one or more of the various inventive aspects, features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof in the above description of exemplary embodiments of the invention. However, this disclosure should not be construed as reflecting an intention that the claimed invention requires more features than expressly recited in each claim. Rather, as reflected in the claims, inventive aspects lie in fewer than all features of the single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of the invention.
Claims
1. A method for manufacturing silicon carbide power devices, characterized in that, The method includes: A first N-type epitaxial layer is grown on a silicon carbide substrate; A second N-type epitaxial layer is grown on the first N-type epitaxial layer, the second N-type epitaxial layer containing both nitrogen doping and boron doping; P-Well, N+ and P+ regions were implanted on the second N-type epitaxial layer, and then high-temperature activation annealing was performed. The device is fabricated by forming a gate oxide layer, a polysilicon gate, an insulating dielectric layer, and a source metal.
2. The method according to claim 1, characterized in that, The first N-type epitaxial layer is nitrogen-doped, wherein the N-type doping concentration of the second N-type epitaxial layer is greater than that of the first N-type epitaxial layer.
3. The method according to claim 1, characterized in that, The thickness of the second N-type epitaxial layer is 1 to 2 micrometers.
4. The method according to claim 1, characterized in that, The boron doping introduces a deep-level recombination center (D-center) in the silicon carbide bandgap and generates carbon vacancies in the adjacent lattice, which is used to regulate minority carrier lifetime.
5. A silicon carbide power device, characterized in that, The silicon carbide power device is manufactured using the method according to any one of claims 1-4.