Method for producing a semiconductor structure

Abstract

The invention relates to a method for producing a semiconductor structure, comprising the following steps: - providing a support substrate (1) comprising: · a semiconductor support layer (2) made of a first material and having a first face (3) and a second face (4) opposite the first face (3); · a polycrystalline silicon carbide layer (5) arranged on the first face (3) of the semiconductor support layer (2); - treating (7) the free surface (6) of the polycrystalline silicon carbide layer (5) ;- transferring, by bonding, a layer (8) of gallium nitride onto the treated free surface (6) of the silicon carbide layer (5).

Description

DESCRIPTION TITLE: PROCESS FOR MANUFACTURING A SEMICONDUCTIVE STRUCTURE TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of semiconductor materials for microelectronic components. The invention relates more particularly to a method for manufacturing a semiconductor structure comprising gallium nitride (GaN). TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] Gallium nitride (GaN) is a particularly promising material, especially for the formation of high-power light-emitting diodes (LEDs) and high-frequency electronic devices, such as high-electron-mobility transistors (HEMTs) or other field-effect transistors (FETs).

[0003] Since gallium nitride is very difficult to find in the form of large, bulk substrates, it is usually formed by heteroepitaxy, that is, by epitaxy on a substrate made of a different material.

[0004] The choice of such a substrate takes into account, in particular, the difference in lattice parameters and the difference in coefficient of thermal expansion between the substrate material and the gallium nitride. Indeed, the greater these differences, the greater the risk of crystal defects, such as dislocations, forming in the gallium nitride, and the generation of significant mechanical stresses, which can cause excessive deformation.

[0005] Materials used for GaN heteroepitaxy include sapphire (Al2O3), silicon carbide (SiC) and silicon (Si).

[0006] Besides its smaller lattice parameter difference with gallium nitride compared to silicon or sapphire, silicon carbide is often preferred for high-power electronic applications because of its thermal conductivity, which is significantly higher than that of sapphire and silicon, and which allows Consequently, it is easier to dissipate the thermal energy generated during component operation. This makes it possible to deposit high-quality gallium nitride layers onto a silicon carbide substrate. However, silicon carbide also has some drawbacks: it is particularly expensive and is currently only available in substrates of limited size. SUMMARY OF THE INVENTION

[0007] The invention aims to provide a process for obtaining a gallium nitride layer in a less expensive way, including on larger substrates.

[0008] The invention thus relates to a method for manufacturing a semiconductor structure, comprising the following steps: - supply of a carrier block comprising: o a semiconductor carrier layer formed of a first material and comprising a first face and a second face opposite the first face; o a layer of polycrystalline silicon carbide disposed on the first face of the semiconductor carrier layer; - treatment of the free surface of the polycrystalline silicon carbide layer; - transfer by bonding of a layer of gallium nitride onto the treated free surface of the silicon carbide layer.

[0009] Thanks to the invention, the GaN layer is deposited on a carrier block forming a hybrid substrate comprising a thin, and therefore relatively inexpensive, polycrystalline silicon carbide layer with a low-cost carrier layer, for example, made of an inexpensive material other than silicon carbide, such as monocrystalline or polycrystalline silicon. This carrier block can be obtained by various approaches, which will be described in more detail later. The presence of the polycrystalline silicon carbide layer also allows for efficient bonding of the gallium nitride layer.

[0010] In addition to the characteristics mentioned in the preceding paragraphs, the manufacturing process according to the invention may exhibit a or several complementary characteristics from the following, considered individually or according to all technically possible combinations: According to a first embodiment of the invention, the step of supplying the carrier block comprises the following steps: supplying a substrate made of the first material forming the semiconductor carrier layer, said substrate having a first face and a second face opposite to the first face; deposition on the first face of said substrate of the polycrystalline silicon carbide layer; deposition on the second face of said substrate of another polycrystalline silicon carbide layer. According to the first embodiment, the process includes a step of removing the other silicon carbide layer after the step of transferring the gallium nitride layer by bonding. According to the first embodiment, the thickness of the polycrystalline silicon carbide layer is between 5 and 50 microns and preferably between 10 and 20 microns. According to a second embodiment of the invention, the step of supplying the carrier block comprises the following steps: supplying a temporary graphite substrate comprising a first face and a second face opposite the first face; deposition on the first face of the temporary substrate of the polycrystalline silicon carbide layer; bonding the semiconducting carrier layer to the free surface of the polycrystalline silicon carbide layer; removing the temporary substrate so as to leave a free surface of said layer; preferably, the removal is made with a stop on the polycrystalline silicon carbide layer. According to the second embodiment, the bonding of the semiconductor carrier layer to the free surface of the polycrystalline silicon carbide layer is achieved by first depositing a carbon-based bonding resin onto the free surface of the polycrystalline silicon carbide layer. According to the second embodiment, the thickness of the polycrystalline silicon carbide layer is between 50 and 250 microns and preferably between 100 and 200 microns. According to the second embodiment, the step of supplying a carrier block also includes a step of depositing on the second face of the temporary substrate a second layer of polycrystalline silicon carbide followed by cutting the temporary substrate along a plane parallel to the plane of the temporary substrate so as to remove the second layer of polycrystalline silicon carbide and part of the thickness of the temporary substrate. The first material is monocrystalline or polycrystalline silicon. The first material is chosen such that the semiconductor carrier layer has a resistivity between 1000 and 100,000 ohm·cm, and preferably between 10,000 and 100,000 ohm·cm. The polycrystalline silicon carbide layer has a resistivity greater than 1000 ohm·cm, and preferably greater than 10,000 ohm·cm, and again preferably greater than 100,000 ohm·cm. The transfer by bonding of the gallium nitride layer onto the treated free surface of the silicon carbide layer is carried out according to the following steps: provision of a donor substrate having at least one gallium nitride zone on the upper part of the donor substrate; formation, by ion implantation, of a localized embrittlement plane in the gallium nitride zone of the donor substrate. and separating the gallium nitride layer from the rest of the donor substrate; bonding the donor substrate to the treated free surface of the silicon carbide layer; detaching the donor substrate along the embrittlement plane in order to transfer the gallium nitride layer to the treated free surface of the silicon carbide layer. BRIEF DESCRIPTION OF THE FIGURES

[0011] Other features and advantages of the invention will become clear from the description given below, by way of example and not limitation, with reference to the accompanying figures, among which: Figures 1, 2 and 3 represent the general steps of the process according to the invention; Figure 4 illustrates an example of the transfer of a gallium nitride layer; Figures 4 to 8 illustrate the different stages of a first embodiment of the manufacturing process according to the invention; Figures 9 to 14 illustrate the different stages of a second embodiment of the manufacturing process according to the invention.

[0012] For clarity, identical or similar elements are identified by identical reference symbols across all figures. DETAILED DESCRIPTION

[0013] Figures 1, 2, and 3 illustrate the steps describing the general principle of the manufacturing process according to the invention. Each of these figures represents, in schematic cross-sectional view, the result of a step in the manufacturing process.

[0014] The process according to the invention includes a step 100 (figure 1) of supplying a carrier block 1 comprising: a semiconducting carrier layer 2 formed of a first material and comprising a first face 3 and a second face 4 opposite to the first face 3; a layer 5 of polycrystalline silicon carbide (p-SiC) disposed on the first face 3 of the carrier layer 2.

[0015] We will see in the rest of the description two examples of embodiments of the carrier block 1. Advantageously, the first material of the semiconductor carrier layer is monocrystalline or polycrystalline silicon.

[0016] The process according to the invention continues with a step 101 (Figure 2) of treating the free surface 6 of the p-SiC layer 5 in order to transfer a gallium nitride layer onto the free surface 6 by bonding. This surface treatment 7 aims to improve the surface roughness of the p-SiC layer 5. Conventional chemical etching and / or mechanical grinding and / or chemical polishing techniques can thus be implemented to achieve the desired surface roughness.

[0017] The process continues with a step 102 (Figure 3) of bonding a gallium-8 nitride layer onto the treated free surface 6 of the silicon carbide layer 5. The transfer employs molecular adhesion bonding via a bonding interface 9. Advantageously, and as illustrated in Figure 4, the transfer utilizes the SmartCut™ process. SmartCut™ technology applied to GaN enables the transfer of the gallium-8 nitride layer, taken from a GaN wafer, onto the carrier block 1. More specifically, the transfer step comprises the following steps: Introduction of light species into a donor substrate 10 in GaN to form a fragile buried plane 11, defining with the front face 12 of the donor substrate 10, the layer 8 of GaN. Assembly of the front face 12 of the donor substrate 10 onto the p-SiC layer 5, by molecular adhesion bonding, along the bonding interface 9. Separation along the buried fragile plane 11 to transfer the useful layer 8 of GaN.

[0018] Light species can be, for example, hydrogen and / or helium. As is well known from the prior art, molecular adhesion bonding does not require an adhesive material; bonds are established at the atomic scale between the surfaces being joined. Several types of molecular adhesion bonding exist. Molecular adhesion methods exist, which differ in particular by the conditions of temperature, pressure, atmosphere or pre-treatments prior to the contact of the surfaces. Examples include room temperature bonding with or without prior plasma activation of the surfaces to be joined, atomic diffusion bonding (ADB), surface-activated bonding (SAB), etc.

[0019] Separation along the buried fragile plane 11 is usually achieved by applying a heat treatment that induces the development of cavities and microcracks in the buried fragile plane 11, and pressurizing them with light gaseous compounds until a fracture propagates along said fragile plane 11. Alternatively or concurrently, mechanical stress can be applied to the bonded assembly, and in particular to the buried fragile plane 11, so as to propagate or mechanically assist the propagation of the fracture leading to separation. Following this separation, the structure is as shown in Figure 3.

[0020] It should be noted that the invention has been described in the case of a GaN donor substrate. The invention also applies to other types of substrates such as a GaN-on-Si substrate, a GaN-on-sapphire substrate, or a GaN-on-PSD pseudo-donor substrate, provided that a GaN region is located on the upper part of the substrate.

[0021] Figures 5 to 8 illustrate the different stages of a first embodiment of the manufacturing process according to the invention, enabling in particular the production of the carrier block described with reference to Figures 1 to 3.

[0022] Figure 5 shows a first step 200 of the process according to the invention, during which a polycrystalline or monocrystalline silicon substrate 20 is provided. This substrate 20 forms a first example of a semiconductor carrier layer 2 shown in Figures 1 to 3.

[0023] The process continues with a step 201 (Figure 6) of deposition on the front face 21 of the substrate 20 of a layer 22 of polycrystalline silicon carbide and on the rear face 23 of a second layer 24 of polycrystalline silicon carbide. It should be noted that the presence of this second layer 24 is optional, but it helps to prevent deformation of the carrier layer during manufacturing. The assembly formed by the substrate 20 and the layer 22 of polycrystalline silicon carbide constitutes a first example of the carrier block 1 of figures 1 to 3. The deposition of polycrystalline silicon can be carried out by any known technique, for example by chemical vapor deposition (CVD for Chemical Vapor Deposition according to English terminology).

[0024] According to this embodiment, thanks to the load-bearing function of the substrate 20, the polycrystalline silicon carbide layer 22 can be very thin; in other words, the thickness of layer 22 can be chosen to be as thin as possible for the GaN layer transfer described below. Here, the thickness of the polycrystalline silicon carbide layer 22 is between 5 and 50 microns, and preferably between 10 and 20 microns. Given the high cost of p-SiC, the advantage of using a very thin p-SiC layer is clear.

[0025] Alternatively, the thickness of the polycrystalline silicon carbide layer 22 can be thicker: in other words, the thickness of layer 22 can be between 50pm and 150pm, especially between 80 and 100pm.

[0026] As in Figure 2, the process according to this first embodiment continues with a step 202 (Figure 7) of treating the free surface 26 of the p-SiC layer 22 in order to transfer a gallium nitride layer onto the free surface 26 by bonding. This surface treatment 25 aims to improve the surface roughness of the p-SiC layer 22. Conventional techniques of chemical etching and / or mechanical grinding and / or chemical polishing can thus be implemented to achieve the desired surface roughness.

[0027] The process continues with a step 203 (Figure 8) of bonding a gallium nitride layer 27 onto the treated free surface 26 of the p-SiC layer 22. The transfer implements molecular adhesion bonding via a bonding interface 28. Advantageously, and as illustrated in Figure 4, the transfer utilizes the SmartCut™ process.

[0028] Figures 9 to 14 illustrate the different stages of a second embodiment of the manufacturing process according to the invention, enabling in particular the production of the carrier block described with reference to Figures 1 to 3.

[0029] Figure 9 shows a first step 300 of the process according to the invention during which a temporary graphite substrate 30 is provided.

[0030] The process continues with a step 301 (Figure 10) of deposition on the front face 31 of the temporary substrate 30 of a layer 32 of polycrystalline silicon carbide and on the rear face 33 of a second layer 34 of polycrystalline silicon carbide. The deposition of polycrystalline silicon carbide can be carried out by any known technique, for example by chemical vapor deposition (CVD) such as atmospheric pressure deposition (APCVD), low pressure deposition (LPCVD) or plasma-enhanced deposition (PECVD). Here, the thickness of the polycrystalline silicon carbide layer 32 on the front face 31 is between 50 and 250 microns and preferably between 100 and 200 microns. The same applies to the thickness of the second p-SiC layer 34.The p-SiC layers therefore remain relatively thin in order to limit the cost of this material.

[0031] The process continues with step 302 (Figure 11) of separating the temporary substrate 30 into two parts so as to retain only the substrate 30 and the p-SiC layer 32 deposited on its front face. The other part of the temporary substrate 30 and the p-SiC layer 34 can, for example, be used in the same way as described later in the process for the temporary substrate 30 and the p-SiC layer 32. This separation can be achieved, for example, by slicing with a diamond saw.

[0032] The process continues with a step 303 (Figure 12) of bonding a semiconductor carrier layer 39 to the free surface 34 of the polycrystalline silicon carbide layer 32. This semiconductor carrier layer 39 is preferably made of polycrystalline or monocrystalline silicon. The bonding step 303 is carried out by first depositing a bonding resin 35, for example carbon-based, onto the free surface 34 of the p-SiC layer 32. The advantage of this second embodiment is that it incorporates the semiconductor carrier layer 39 very early in the process.

[0033] The process according to this second embodiment then includes a step 304 (Figure 13) of removing the temporary graphite substrate 30 to form a carrier block including the semiconductor carrier layer 39 and the p-SiC layer 32. It is understood here that the thickness of the semiconductor carrier layer 39 must be higher than in the case of the first embodiment insofar as it does not rely on a substrate but on a load-bearing layer.

[0034] The assembly formed by the semiconductor carrier layer 39 and the polycrystalline silicon carbide layer 32 thus forms a second example of the carrier block 1 of figures 1 to 3. It should be noted that this carrier block is reversed in figure 13 so that the p-SiC layer 32 is above the carrier layer 39.

[0035] The step of removing the temporary substrate 30 can be carried out by known techniques such as mechanical dismantling by crack propagation in the temporary substrate 30, chemical etching of the temporary substrate 30 or dismantling by thermal damage of the temporary substrate 30.

[0036] As in Figure 2, the process according to this second embodiment continues with an unshown step of treating the free surface of the p-SiC layer 32 in order to transfer a gallium nitride layer onto the free surface by bonding. This surface treatment aims to improve the surface roughness of the p-SiC layer 32. Conventional techniques such as chemical etching and / or mechanical grinding and / or chemical polishing can thus be implemented to achieve the desired surface roughness.

[0037] The process according to the second embodiment continues with a step 305 (Figure 14) of transferring a gallium nitride layer 36 onto the treated free surface 37 of the p-SiC layer 32 by bonding. The transfer employs molecular adhesion bonding via a bonding interface 38. Advantageously, and as illustrated in Figure 4, the transfer utilizes the SmartCut™ process.

[0038] Depending on the type of application chosen and for all the described embodiments, the resistivity of the semiconductor carrier layer and the polycrystalline silicon carbide layer is adapted. Thus, for lateral applications (i.e., the current flows laterally through the GaN layer), a high-resistivity (HR) polycrystalline silicon layer is required at a minimum, or even a high-resistivity carrier layer if the latter is not removed. Advantageously, for lateral applications, the polycrystalline silicon carbide layer has a resistivity greater than 100 ohm·cm, advantageously greater than 1000 ohm·cm, and even more advantageously greater than 10,000 ohm·cm, and preferably greater than 100000 ohm.cm. Similarly, advantageously, for lateral applications, the semiconductor carrier layer has a resistivity between 1000 and 100000 ohm.cm and advantageously between 10000 and 100000 ohm.cm.

[0039] Conversely, for vertical applications (i.e., the current flows perpendicular to the plane of the layers), the polycrystalline silicon carbide layer must potentially ensure vertical electrical conduction. To guarantee this latter property of electrical conduction (low resistivity), the polycrystalline silicon carbide layer is advantageously doped with n-type or p-type doping, depending on the requirement.

[0040] According to all the embodiments described, following the transfer by bonding of the gallium nitride layer, the process according to the invention may include a step of fabricating one or more components (for example, one or more HEMT transistors or high electron mobility transistors) from the deposition of one or more III-N semiconductor layers grown on the transferred GaN layer. By way of example, the process according to the invention may include a step of deposition by epitaxy of a GaN layer directly onto the transferred GaN layer.

Claims

DEMANDS

1. A method for manufacturing a semiconductor structure, comprising the following steps: - supply of a carrier block (39, 32) comprising: o a semiconductor carrier layer (39) formed of a first material and comprising a first face and a second face opposite to the first face; o a layer (32) of polycrystalline silicon carbide disposed on the first face of the semiconductor carrier layer (39); - treatment of the free surface of the polycrystalline silicon carbide layer (32); - transfer (305) by bonding a layer (36) of gallium nitride onto the treated free surface (37) of the polycrystalline silicon carbide layer (32); the step of supplying the carrier block comprising the following steps: - supply (300) of a temporary graphite substrate (30) comprising a first face (31) and a second face (33) opposite the first face; - deposition (301) on the first face (31) of the temporary substrate (30) of the layer (32) in polycrystalline silicon carbide; - bonding (303) of the semiconductor carrier layer (39) onto the free surface (34) of the polycrystalline silicon carbide layer (32); - removal (304) of the temporary substrate (30) so as to leave a surface free of said layer.

2. A method according to the preceding claim characterized in that the bonding (303) of the semiconductor carrier layer (39) on the free surface of the polycrystalline silicon carbide layer (32) is achieved by the prior deposition on the free surface of the polycrystalline silicon carbide layer of a carbon-based bonding resin (35).

3. A method according to any one of the preceding claims characterized in that the thickness of the polycrystalline silicon carbide layer is between 50 and 250 microns and preferably between 100 and 200 microns.

4. A method according to any one of the preceding claims characterized in that the step of supplying a carrier block also includes a step of depositing (301) on the second face (33) of the temporary substrate (30) a second layer (34) of polycrystalline silicon carbide followed by cutting the temporary substrate along a plane parallel to the plane of the temporary substrate so as to remove the second layer (34) of polycrystalline silicon carbide and a part of the thickness of the temporary substrate.

5. A method according to any one of the preceding claims characterized in that the first material is monocrystalline or polycrystalline silicon.

6. A method according to any one of the preceding claims characterized in that the polycrystalline silicon carbide layer has a resistivity greater than 1000 ohm.cm, and preferably greater than 10000 ohm.cm, and even more preferably greater than 100000 ohm.cm.

7. A method according to any one of the preceding claims characterized in that the first material is chosen such that the semiconductor carrier layer has a resistivity between 1000 and 100000 ohm.cm and preferably between 10000 and 100000 ohm.cm.

8. A method according to any one of the preceding claims, characterized in that the transfer by bonding of the gallium nitride layer onto the treated free surface of the silicon carbide layer is carried out according to the following steps: - provision of a donor substrate (10) comprising at least one gallium nitride zone on the upper part of the donor substrate; - formation, by ion implantation, of a weakening plane (11) located in the gallium nitride zone of the donor substrate (10) and separating the gallium nitride layer (8) from the rest of the donor substrate (10); - bonding of the donor substrate (10) onto the treated free surface of the silicon carbide layer; - detachment of the donor substrate (10) along the embrittlement plane (11) in order to transfer the gallium nitride layer (8) onto the treated free surface of the silicon carbide layer.

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