High-voltage GaN-based double-channel super junction HEMT device and preparation method thereof

Abstract

The application provides a high-voltage GaN-based double-channel super-junction HEMT device and a preparation method thereof, and belongs to the technical field of semiconductors, and is used for solving the problem of the voltage resistance of a modulated GaN HEMT device. The high-voltage GaN-based double-channel super-junction HEMT device comprises a main body structure, a source structure, a drain structure and a gate structure. The main body structure comprises, from bottom to top, a substrate, a buffer layer, a back barrier layer, a channel layer, a barrier layer and a passivation layer. The barrier layer and the channel layer interface generate two-dimensional electron gas. The channel layer and the back barrier layer interface generate two-dimensional hole gas. The upper part of the source structure forms ohmic contact with the two-dimensional electron gas. The lower part of the source structure forms ohmic contact or Schottky contact with the two-dimensional hole gas. The drain structure forms ohmic contact with the two-dimensional electron gas. The gate structure is arranged between the source structure and the drain structure and is connected to the barrier layer. The voltage resistance level of the device can be improved without affecting the conduction characteristics of the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a high-voltage GaN-based dual-channel superjunction HEMT device and its fabrication method. Background Technology

[0002] GaN, as a wide bandgap semiconductor, boasts a wider bandgap, stronger material breakdown electric field, and higher electron saturation velocity compared to Si, resulting in GaN HEMT devices with higher switching speeds and output power. However, conventional electron-channel GaN HEMT devices fabricated by epitaxially layering AlGaN / GaN heterojunction materials on Si substrates exhibit a high electric field peak near the drain corner due to the depletion of channel electrons during breakdown voltage. This peak represents a high-risk point for leakage current and breakdown as hot electrons from the channel leak into the device surface and buffer layer. Simultaneously, most of the channel direction has not yet reached the critical breakdown electric field. Therefore, the non-uniformity of the channel electric field during breakdown voltage limits the full potential of GaN HEMT devices to withstand the material's electric field.

[0003] To prevent the drawback of premature breakdown in GaN HEMT devices, the paper J. Li, et al., "High breakdownvoltage GaN HFET with field plate" (IEEE Electron Lett.) introduces a metal field plate that is shorted to the gate and extends towards the drain. The field plate covers the surface of the passivation layer and attracts electric field lines instead of the gate electrode, effectively reducing the peak electric field at the gate corner and improving the device breakdown voltage. However, the field plate increases the gate capacitance by increasing the facing area, which is detrimental to the high-frequency characteristics of the device. The paper A. Nakajima et al., "GaN-Based SuperHeterojunction Field Effect Transistors Using the Polarization Junction Concept," uses a resistive field plate instead of a metal field plate. It utilizes the pGaN region on the device surface connected to the gate to form a double heterojunction structure. When the device is turned off, after the 2DEG and 2DHG are depleted together, the polarization charges at the double heterojunction interface compensate for each other. The main problems with this structure, besides increasing the device's gate capacitance, are that the lack of a hole extraction mechanism in the ohmic gate causes the surface pGaN to deplete and scatter the 2DEG in the channel when the device is turned on, thus worsening the device's specific on-resistance characteristics. Furthermore, the patterning and etching of the surface pGaN is also technologically challenging. Summary of the Invention

[0004] Therefore, the technical problem to be solved by the present invention is to provide a high-voltage GaN-based dual-channel superjunction HEMT device and its fabrication method, which can solve the problem of modulating the internal electric field of GaN HEMT device under off-state voltage without applying a metal field plate and surface superjunction.

[0005] In a first aspect, the present invention provides a high-voltage GaN-based dual-channel superjunction HEMT device, comprising: a body structure, a source structure, a drain structure, and a gate structure. The body structure includes, from bottom to top, a substrate, a buffer layer, a back barrier layer, a channel layer, a barrier layer, and a passivation layer. A two-dimensional electron gas is generated at the interface between the barrier layer and the channel layer. A two-dimensional hole gas is generated at the interface between the channel layer and the back barrier layer. The source structure is disposed at a first end of the body structure. The source structure penetrates the passivation layer, the barrier layer, and the channel layer from top to bottom, and extends into the back barrier layer. The upper part of the source structure forms an ohmic contact with the two-dimensional electron gas. The lower part of the source structure forms an ohmic contact or a Schottky contact with the two-dimensional hole gas. The drain structure is disposed at a second end of the body structure. The drain structure penetrates the passivation layer and the barrier layer from top to bottom, and extends into the channel layer. The drain structure forms an ohmic contact with the two-dimensional electron gas. The gate structure is disposed between the source structure and the drain structure. The gate structure extends from top to bottom through the passivation layer and connects to the barrier layer.

[0006] Optionally, the material of the trench layer is Al. x Ga 1-x N. The Al component x ranges from 0% to 90%. The barrier layer material is Al. y Ga 1-y N. The Al component y is 10–100%, and y > x. The back barrier layer is made of Al. z Ga 1-z N. Among them, the component z of Al is 10-100%, and z>x.

[0007] Optionally, the back barrier layer can be a single-layer, double-layer, or triple-layer structure. When the back barrier layer is a single-layer structure, the material of the back barrier layer is Al. z1 Ga 1-z1 N. Where z1 > x. When the back barrier layer is a double-layer structure, the back barrier layer consists of a first thin layer and a second thin layer from top to bottom. The material of the first thin layer is Al. z1 Ga 1-z1 N, the material of the second thin layer is Al z2 Ga 1- z2 N. Where z2>z1>x. When the back barrier layer has a three-layer structure, the back barrier layer consists of a first thin layer, a second thin layer, and a third thin layer from top to bottom. The material of the first thin layer is Al. z1 Ga 1-z1 N, the material of the second thin layer is Alz2 Ga 1-z2 N, the material of the third thin layer is Al z3 Ga 1-z3 N. Where z3>z2>z1>x.

[0008] Optionally, the source structure includes: a source aperture, a lower source, and an upper source. The source aperture penetrates the passivation layer, the barrier layer, and the channel layer sequentially from top to bottom, and penetrates at least part of the back barrier layer. The lower source is located below the source aperture. The lower source forms an ohmic contact or a Schottky contact with the two-dimensional hole gas. The upper source is located above the source aperture. The upper source forms an ohmic contact with the two-dimensional electron gas. The upper source and the lower source are shorted at the same potential.

[0009] Optionally, the drain structure includes a drain hole and a drain electrode. The drain hole penetrates the passivation layer and the barrier layer sequentially from top to bottom, and also penetrates part of the channel layer. The drain electrode is located in the drain hole. The drain electrode forms an ohmic contact with the two-dimensional electron gas.

[0010] Optionally, the gate structure includes a gate aperture and a gate electrode. The gate aperture penetrates the passivation layer and partially penetrates the barrier layer. The gate electrode is located within the gate aperture.

[0011] Optionally, the passivation layer may be made of at least one of silicon nitride, silicon dioxide, and aluminum oxide.

[0012] Optionally, the material of the buffer layer includes at least one of AlN, AlGaN, and GaN.

[0013] Alternatively, the substrate material may be one of Si, sapphire, SiC, and GaN.

[0014] Secondly, the present invention provides a method for fabricating a high-voltage GaN-based dual-channel superjunction HEMT device, comprising the following steps:

[0015] A buffer layer, a back barrier layer, a channel layer, a barrier layer, and a passivation layer are sequentially grown on the substrate.

[0016] Forming a source structure and extracting the device source potential;

[0017] A drain structure is formed, and the drain potential of the device is extracted;

[0018] A gate structure is formed, and the device gate potential is extracted.

[0019] Beneficial effects

[0020] The high-voltage GaN-based dual-channel superjunction HEMT device and its fabrication method provided by this invention reduce the electric field gradient in the channel direction, which is beneficial to the uniform flattening of the internal electric field when the device withstands voltage. It can effectively prevent the electric field peak on the side of the gate near the drain from being too high, and can improve the voltage withstand level of the device without affecting the conduction characteristics of the device. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of a high-voltage GaN-based dual-channel superjunction HEMT device according to an embodiment of the present invention;

[0022] Figure 2 A schematic diagram of the electric field distribution under breakdown voltage of a high-voltage GaN-based dual-channel superjunction HEMT device according to an embodiment of the present invention;

[0023] Figure 3 A schematic diagram of the structure of a high-voltage GaN-based dual-channel superjunction HEMT device according to another embodiment of the present invention;

[0024] Figure 4 A schematic diagram of the structure of a high-voltage GaN-based dual-channel superjunction HEMT device according to another embodiment of the present invention;

[0025] Figure 5 A flowchart illustrating a method for fabricating a high-voltage GaN-based dual-channel superjunction HEMT device according to an embodiment of the present invention;

[0026] Figure 6 A schematic diagram of the device obtained in step S1 of the fabrication method of a high-voltage GaN-based dual-channel superjunction HEMT device according to an embodiment of the present invention;

[0027] Figure 7 A schematic diagram of the device obtained in step S2 of the fabrication method of a high-voltage GaN-based dual-channel superjunction HEMT device according to an embodiment of the present invention;

[0028] Figure 8 A schematic diagram of the device obtained in step S3 of the fabrication method of a high-voltage GaN-based dual-channel superjunction HEMT device according to an embodiment of the present invention;

[0029] Figure 9 A schematic diagram of the device obtained in step S4 of the fabrication method of a high-voltage GaN-based dual-channel superjunction HEMT device according to an embodiment of the present invention.

[0030] The reference numerals in the attached figures are as follows:

[0031] 1. Substrate; 2. Buffer layer; 3. Back barrier layer; 4. Channel layer; 5. Barrier layer; 6. Passivation layer; 7. Source structure; 8. Drain structure; 9. Gate structure;

[0032] 01. Two-dimensional electron gas; 02. Two-dimensional cavitation gas;

[0033] 31. First thin layer; 32. Second thin layer; 33. Third thin layer;

[0034] 71. Source hole; 72. Lower source electrode; 73. Upper source electrode;

[0035] 81. Drain via; 82. Drain electrode;

[0036] 91. Gate hole; 92. Gate electrode. Detailed Implementation

[0037] In the description of this invention, it should be understood that the terms "longitudinal", "thickness", "upper", "lower", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0038] Furthermore, in the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0039] In this invention, unless otherwise explicitly specified and limited, the term "connection" can refer to an electrical connection, a direct connection, or an indirect connection via an intermediate medium, or a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0040] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0041] In one aspect, this embodiment provides a high-voltage GaN-based dual-channel superjunction HEMT device. Figure 1 This is a schematic diagram of a high-voltage GaN-based dual-channel superjunction HEMT device provided in this embodiment. Figure 2 This is a schematic diagram of the electric field distribution of a high-voltage GaN-based dual-channel superjunction HEMT device under high voltage conditions, as provided in this embodiment.

[0042] like Figure 1 and Figure 2As shown, the high-voltage GaN-based dual-channel superjunction HEMT device of this embodiment includes: a main structure, a source structure 7, a drain structure 8, and a gate structure 9. The main structure includes, from bottom to top, a substrate 1, a buffer layer 2, a back barrier layer 3, a channel layer 4, a barrier layer 5, and a passivation layer 6. A two-dimensional electron gas 01 is generated at the interface between the barrier layer 5 and the channel layer 4. A two-dimensional hole gas 02 is generated at the interface between the channel layer 4 and the back barrier layer 3. The source structure 7 is disposed at the first end of the main structure. The source structure 7 penetrates the passivation layer 6, the barrier layer 5, and the channel layer 4 from top to bottom, and extends into the back barrier layer 3. The upper part of the source structure 7 forms an ohmic contact with the two-dimensional electron gas 01. The lower part of the source structure 7 forms an ohmic contact or a Schottky contact with the two-dimensional hole gas 02. The drain structure 8 is disposed at the second end of the main structure. The drain structure 8 penetrates the passivation layer 6 and the barrier layer 5 from top to bottom, and extends into the channel layer 4. The drain structure 8 forms an ohmic contact with the two-dimensional electron gas 01. The gate structure 9 is disposed between the source structure 7 and the drain structure 8. The gate structure 9 extends from top to bottom through the passivation layer 6 and is connected to the barrier layer 5.

[0043] In the high-voltage GaN-based dual-channel superjunction HEMT device of this embodiment, the back barrier layer 3, the channel layer 4, and the barrier layer 5 form a double heterojunction structure. Two-dimensional electron gas (O1) and two-dimensional hole gas (O2) can be generated at the interfaces of barrier layer 5 and channel layer 4, and between channel layer 4 and back barrier layer 3, respectively. The upper part of the source structure 7 forms an ohmic contact with the two-dimensional electron gas (O1). The lower part of the source structure 7 forms an ohmic contact or a Schottky contact with the two-dimensional hole gas (O2). The drain structure 8 forms an ohmic contact with the two-dimensional electron gas (O1).

[0044] When the device is in the ON state and the gate structure 9 is on, the two-dimensional electron gas (2DEG) 01 conducts between the source structure 7 and the drain structure 8, meaning the device primarily relies on the high-mobility 2DEG 01 for conductivity. When the device is in the OFF state, the gate structure 9 is off, and the drain structure 8 withstands high voltage, the 2DEG 01 and 2DHG 02 at the upper and lower interfaces of the channel layer 4 are depleted, leaving behind fixed positive and negative charges of opposite polarity. That is, during breakdown voltage, electrons between the gate and drain of the 2DEG are extracted by the drain structure 8, and holes in the 2DHG channel are extracted by the lower part of the low-level source structure 7. A potential difference is formed between the depleted 2DEG channel and the depleted 2DHG channel, causing electric field lines to emanate from the fixed positive charges in the depleted 2DEG channel and point towards the fixed negative charges in the depleted 2DHG channel, thus establishing a longitudinal built-in electric field within the channel layer 4, forming a breakdown voltage effect similar to a superjunction. Figure 2As shown, the superposition of the longitudinal electric field and the channel electric field reduces the electric field gradient in the channel direction of the device, promotes the uniformity and flattening of the internal electric field when the device withstands voltage, effectively prevents the electric field peak on the side of the gate structure 9 near the drain structure 8 from being too high, and further improves the withstand voltage level of the device without affecting the conduction characteristics of the device.

[0045] In some embodiments, see Figure 1 The material of channel layer 4 is Al x Ga 1-x N. The Al component x ranges from 0% to 90%. The barrier layer 5 is made of Al. y Ga 1-y N. The Al component y is 10–100%, and y > x. The material of the back barrier layer 3 is Al. z Ga 1-z N. Among them, the component z of Al is 10-100%, and z>x.

[0046] In some examples, see Figure 1 The thickness of the channel layer 4 is 10nm-1000nm; the thickness of the barrier layer 5 is 1nm-50nm; and the thickness of the back barrier layer 3 is 1nm-600nm.

[0047] In this embodiment, the material of the barrier layer 5 is Al. y Ga 1-y N, the material of channel layer 4 is Al x Ga 1-x N, the material of the back barrier layer 3 is Al z Ga 1-z N, and y>x, z>x. Therefore, the back barrier layer 3, the channel layer 4, and the barrier layer 5 form a double heterojunction structure, and two-dimensional electron gas 01 and two-dimensional hole gas 02 are generated at the interface between the barrier layer 5 and the channel layer 4, and at the interface between the channel layer 4 and the back barrier layer 3, respectively.

[0048] Figure 3 This is a schematic diagram of another high-voltage GaN-based dual-channel superjunction HEMT device provided in this embodiment. Figure 4 This is a schematic diagram of another high-voltage GaN-based dual-channel superjunction HEMT device provided in this embodiment. In some embodiments, such as Figure 1 , Figure 3 , Figure 4 As shown, the back barrier layer 3 can be a single-layer, double-layer, or triple-layer structure. Figure 4 As shown, when the back barrier layer 3 is a single-layer structure, the material of the back barrier layer 3 is Al. z1 Ga 1-z1 N. Where z1 > x. For example... Figure 3As shown, when the back barrier layer 3 has a double-layer structure, it comprises a first thin layer 31 and a second thin layer 32 from top to bottom. The material of the first thin layer 31 is Al. z1 Ga 1-z1 N, the material of the second thin layer 32 is Al z2 Ga 1-z2 N. Where z2 > z1 > x. For example... Figure 1 As shown, when the back barrier layer 3 has a three-layer structure, it comprises, from top to bottom, a first thin layer 31, a second thin layer 32, and a third thin layer 33. The material of the first thin layer 31 is Al. z1 Ga 1-z1 N, the material of the second thin layer 32 is Al z2 Ga 1-z2 N, the material of the third thin layer 33 is Al z3 Ga 1-z3 N. Where z3>z2>z1>x.

[0049] In some examples, such as Figure 4 As shown, when the back barrier layer 3 is a single-layer structure, its thickness is 1nm-200nm. Figure 3 or Figure 1 As shown, when the back barrier layer 3 is a two-layer or three-layer structure, the thickness of each layer is 1nm-200nm.

[0050] In this embodiment, the back barrier layer 3 is a single-layer, double-layer, or triple-layer stacked structure. When the back barrier layer 3 is a double-layer or triple-layer structure, the Al component in each thin layer decreases gradually from bottom to top, which is beneficial to improving the uniformity of the Al component distribution in the back barrier layer 3 and avoiding the situation where the device performance is affected by the uneven Al component in the back barrier layer 3.

[0051] In some embodiments, such as Figure 1 As shown, the source structure 7 includes: a source hole 71, a lower source 72, and an upper source 73. The source hole 71 penetrates the passivation layer 6, the barrier layer 5, and the channel layer 4 sequentially from top to bottom, and also penetrates at least a portion of the back barrier layer 3. The lower source 72 is located below the source hole 71. The lower source 72 forms an ohmic contact or a Schottky contact with the two-dimensional hole gas 02. The upper source 73 is located above the source hole 71. The upper source 73 forms an ohmic contact with the two-dimensional electron gas 01. The upper source 73 and the lower source 72 are shorted at the same potential.

[0052] In some examples, such as Figure 1As shown, the source aperture 71 is located at the first end of the main structure, penetrating the passivation layer 6, barrier layer 5, channel layer 4, and back barrier layer 3 from top to bottom, and extending to the buffer layer 2. However, it should be noted that in other embodiments, the source aperture 71 may not completely penetrate the back barrier layer 3, as long as the lower source 72 can form an ohmic contact or a Schottky contact with the two-dimensional hole gas 02.

[0053] In this embodiment, as Figure 1 As shown, the lower source 72 is located below the source hole 71, corresponding to the lower part of the channel layer 4 and the back barrier layer 3 (or the upper part of the back barrier layer 3). The upper source 73 is located above the source hole 71, above the lower source 72. The position of the upper source 73 corresponds to the upper part of the passivation layer 6, the barrier layer 5, and the channel layer 4. The upper source 73 leads out the device source potential through the source hole 71.

[0054] In this embodiment, the lower source electrode 72 and the upper source electrode 73 are made of metal, or a multi-layer metal stack, or an alloy. Specifically, they include one or more combinations of metals Ti, Al, Ni, W, Pt, Pd, Au, and Ag. For example, the lower source electrode 72 and the upper source electrode 73 adopt a multi-layer metal stack structure; the lower source electrode 72 is composed of Ni and Au from bottom to top; the upper source electrode is composed of Ti, Al, Ni, and Au from bottom to top.

[0055] In some embodiments, such as Figure 1 As shown, the drain structure 8 includes a drain hole 81 and a drain electrode 82. The drain hole 81 penetrates the passivation layer 6 and the barrier layer 5 from top to bottom, and also penetrates part of the channel layer 4. The drain electrode 82 is located in the drain hole 81. The drain electrode 82 forms an ohmic contact with the two-dimensional electron gas 01.

[0056] In some examples, such as Figure 1 As shown, the drain hole 81 is located at the second end of the main structure, penetrating the passivation layer 6 and the barrier layer 5 from top to bottom, and extending to the upper part of the channel layer 4. It should be noted that to avoid contact between the drain electrode 82 and the two-dimensional hole gas 02, the drain hole 81 cannot penetrate to the bottom of the channel layer 4. After the drain electrode 82 fills the drain hole 81, it only forms an ohmic contact with the two-dimensional electron gas 01. The drain electrode 82 leads out the device drain potential through the drain hole 81.

[0057] In this embodiment, the drain electrode 82 is made of metal, a multilayer metal stack, or an alloy. Specifically, it includes one or more combinations of metals such as Ti, Al, Ni, W, Pt, Pd, Au, and Ag.

[0058] In some embodiments, such as Figure 1 As shown, the gate structure 9 includes a gate hole 91 and a gate electrode 92. The gate hole 91 penetrates the passivation layer 6 and partially penetrates the barrier layer 5. The gate electrode 92 is located in the gate hole 91.

[0059] In this embodiment, as Figure 1 As shown, the gate via 91 is located at the top of the main structure, between the source structure 7 and the drain structure 8. The gate via 91 is not connected to either the source structure 7 or the drain structure 8, and its position is biased towards the source structure 7. The gate via 91 penetrates the passivation layer 6 from top to bottom and partially penetrates the barrier layer 5. The gate electrode 92 is a conductive material disposed within the gate via 91. The gate electrode 92 leads out the device gate potential through the gate via 91.

[0060] In this embodiment, the gate electrode 92 is made of metal, or a multilayer metal stack, or an alloy. Specifically, it includes one or more combinations of metals such as Ti, Al, Ni, W, Pt, Pd, Au, and Ag.

[0061] The material of the passivation layer 6 includes at least one of silicon nitride, silicon dioxide, and aluminum oxide.

[0062] The material of the buffer layer 2 includes at least one of AlN, AlGaN, and GaN.

[0063] The substrate 1 is made of one of Si, sapphire, SiC and GaN.

[0064] The high-voltage GaN-based dual-channel superjunction HEMT device of this embodiment has been described above. When the high-voltage GaN-based dual-channel superjunction HEMT device of this embodiment is in the on state and the gate structure 9 is turned on, the 2DEG conducts between the source structure 7 and the drain structure 8, and the device mainly relies on the high-mobility 2DEG channel for conduction. In the off state, when the gate structure 9 is turned off and the drain structure 8 withstands high voltage, the two-dimensional electron gas 01 and the two-dimensional hole gas 02 at the upper and lower interfaces of the channel layer 4 are depleted, leaving fixed positive charges and fixed positive charges of opposite polarities. Electrons between the gate and drain of the 2DEG are extracted by the drain electrode 82, and the channel holes of the 2DHG are extracted by the low-level lower source electrode 72. A potential difference is formed between the depleted 2DEG and the depleted 2DHG, so that electric field lines are emitted from the fixed positive charges in the two depletion regions and point towards the fixed negative charges, thereby establishing a longitudinal built-in electric field in the channel layer 4, forming a voltage withstand effect similar to that of a superjunction. Figure 2 As shown, the superposition of the longitudinal electric field and the channel electric field reduces the electric field gradient in the channel direction of the device, promotes the uniformity and flattening of the internal electric field when the device withstands voltage, and can effectively prevent the electric field peak on the drain side of the gate structure 9 from being too high. Furthermore, it improves the withstand voltage level of GaN-based devices without affecting the conduction characteristics of the device.

[0065] Secondly, this embodiment provides a method for fabricating a high-voltage GaN-based dual-channel superjunction HEMT device. Figure 5This is a flowchart illustrating a method for fabricating a high-voltage GaN-based dual-channel superjunction HEMT device provided in this embodiment.

[0066] like Figure 5 As shown, the fabrication method of the high-voltage GaN-based dual-channel superjunction HEMT device in this embodiment includes the following steps:

[0067] S1. A buffer layer 2, a back barrier layer 3, a channel layer 4, a barrier layer 5, and a passivation layer 6 are sequentially grown on a substrate 1.

[0068] Specifically, Figure 6 This is a schematic diagram of the device obtained in step S1, i.e., the main structure. In this embodiment, the material of the buffer layer 2 includes AlN. When the back barrier layer 3 is a two-layer or three-layer structure, it is grown layer by layer, and the thickness of each layer is 1nm-200nm. The thickness of the channel layer 4 is 10nm-1000nm. The thickness of the barrier layer 5 is 1nm-50nm. The material of the passivation layer 6 includes one or more materials including silicon nitride, silicon dioxide, or aluminum oxide, and the passivation layer 6 covers the surface of the barrier layer 5.

[0069] S2. Form source structure 7 and bring out the device source potential;

[0070] Specifically, Figure 7 This is a schematic diagram of the device obtained in step S2. Step S2 includes: forming a source via 71 at the first end of the main structure. The source via 71 penetrates the passivation layer 6, the barrier layer 5, and the channel layer 4 from top to bottom, and penetrates at least part of the back barrier layer 3. A lower source 72 is placed in the lower part of the source via 71, corresponding to the lower part of the channel layer 4 and the upper part of the back barrier layer 3, so that the lower source 72 forms an ohmic contact or a Schottky contact with the 2DHG. An upper source 73 is placed in the upper part of the source via 71, corresponding to the upper part of the channel layer 4 and the barrier layer 5. The upper source 73 forms an ohmic contact with the 2DEG. The lower source 72 and the upper source 73 are always shorted at the same potential, and the upper source 73 leads out the device source potential through the source via 71.

[0071] S3. Form the drain structure 8 and bring out the device drain potential;

[0072] Specifically, Figure 8 This is a schematic diagram of the device obtained in step S3. Step S3 includes: forming a drain hole 81 at the second end of the main structure. The drain hole 81 penetrates from top to bottom through the passivation layer 6 and the barrier layer 5, and extends to the upper part of the channel layer 4. A drain electrode 82 is disposed in the drain hole 81. The drain electrode 82 forms an ohmic contact with the 2DEG. The drain electrode 82 leads out the device drain potential through the drain hole 81.

[0073] S4. Form gate structure 9 and bring out the device gate potential.

[0074] Specifically, Figure 9 This is a schematic diagram of the device obtained in step S4. Step S3 includes: forming a gate hole 91 at the top of the main structure. The gate hole 91 is located between the source structure 7 and the drain structure 8, and the gate hole 91 is not connected to either the source structure 7 or the drain structure 8. The gate hole 91 is positioned closer to the source structure 7. The gate hole 91 penetrates the passivation layer 6 from top to bottom and partially penetrates the barrier layer 5. A gate electrode 92 is disposed in the gate hole 91. The gate electrode 92 leads out the device gate potential through the gate hole 91.

[0075] It should be noted that the preparation processes involved in the above steps include deposition, photolithography, etching, and annealing, all of which are conventional processes and will not be elaborated here.

[0076] The fabrication method of this embodiment can be used to fabricate the high-voltage GaN-based dual-channel superjunction HEMT device described in the above embodiments, and therefore possesses all the beneficial effects of the above embodiments, which will not be repeated here.

[0077] It will be readily understood by those skilled in the art that the aforementioned advantageous methods can be freely combined and superimposed without conflict.

[0078] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention. The above are merely preferred embodiments of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the protection scope of the present invention.

Claims

1. A high-voltage GaN-based dual-channel superjunction HEMT device, characterized in that, include: The main structure includes, from bottom to top, a substrate, a buffer layer, a back barrier layer, a channel layer, a barrier layer, and a passivation layer; a two-dimensional electron gas is generated at the interface between the barrier layer and the channel layer; a two-dimensional hole gas is generated at the interface between the channel layer and the back barrier layer. A source structure is disposed at the first end of the main structure; the source structure passes through the passivation layer, the barrier layer, and the channel layer from top to bottom, and extends into the back barrier layer; the upper part of the source structure forms an ohmic contact with the two-dimensional electron gas; the lower part of the source structure forms an ohmic contact or a Schottky contact with the two-dimensional hole gas. A drain structure is disposed at the second end of the main structure; The drain structure extends from top to bottom through the passivation layer and the barrier layer, and extends into the channel layer. The drain structure forms an ohmic contact with the two-dimensional electron gas; A gate structure is disposed between the source structure and the drain structure; the gate structure extends from top to bottom through the passivation layer and is connected to the barrier layer.

2. The high-voltage GaN-based dual-channel superjunction HEMT device according to claim 1, characterized in that, The material of the channel layer is Al. x Ga 1-x N; Among them, the component x of Al ranges from 0% to 90%; The barrier layer is made of Al. y Ga 1-y N; wherein the component y of Al is 10-100%, and y > x; The material of the back barrier layer is Al. z Ga 1-z N; wherein the component z of Al is 10-100%, and z > x.

3. The high-voltage GaN-based dual-channel superjunction HEMT device according to claim 2, characterized in that, The back barrier layer can be a single-layer structure, a double-layer structure, or a triple-layer structure. When the back barrier layer is a single-layer structure, the material of the back barrier layer is Al. z1 Ga 1-z1 N; where z1 > x; When the back barrier layer is a double-layer structure, the back barrier layer comprises a first thin layer and a second thin layer from top to bottom; the material of the first thin layer is Al. z1 Ga 1-z1 N, the material of the second thin layer is Al z2 Ga 1-z2 N; where z2>z1>x; When the back barrier layer has a three-layer structure, the back barrier layer comprises, from top to bottom, a first thin layer, a second thin layer, and a third thin layer; the material of the first thin layer is Al. z1 Ga 1-z1 N, the material of the second thin layer is Al z2 Ga 1-z2 N, the material of the third thin layer is Al z3 Ga 1-z3 N; Among them, z3>z2>z1>x.

4. The high-voltage GaN-based dual-channel superjunction HEMT device according to claim 1, characterized in that, The source structure includes: The source aperture penetrates the passivation layer, the barrier layer and the channel layer from top to bottom, and penetrates at least a portion of the back barrier layer; The lower source electrode is located below the source electrode aperture; the lower source electrode forms an ohmic contact or a Schottky contact with the two-dimensional cavitation gas; The upper source electrode is located above the source electrode hole; the upper source electrode forms an ohmic contact with the two-dimensional electron gas; the upper source electrode and the lower source electrode are shorted at the same potential.

5. The high-voltage GaN-based dual-channel superjunction HEMT device according to claim 1, characterized in that, The drain structure includes: The drain hole penetrates the passivation layer and the barrier layer from top to bottom, and also penetrates part of the channel layer; A drain electrode is located in the drain hole; the drain electrode forms an ohmic contact with the two-dimensional electron gas.

6. The high-voltage GaN-based dual-channel superjunction HEMT device according to claim 1, characterized in that, The gate structure includes: A gate aperture penetrates the passivation layer and a portion of the barrier layer; The gate electrode is located in the gate hole.

7. The high-voltage GaN-based dual-channel superjunction HEMT device according to claim 1, characterized in that, The passivation layer is made of at least one of silicon nitride, silicon dioxide, and aluminum oxide.

8. The high-voltage GaN-based dual-channel superjunction HEMT device according to claim 1, characterized in that, The material of the buffer layer includes at least one of AlN, AlGaN, and GaN.

9. The high-voltage GaN-based dual-channel superjunction HEMT device according to claim 1, characterized in that, The substrate is made of one of the following materials: Si, sapphire, SiC, and GaN.

10. A method for fabricating a high-voltage GaN-based dual-channel superjunction HEMT device, characterized in that, The method includes the following steps: A buffer layer, a back barrier layer, a channel layer, a barrier layer, and a passivation layer are sequentially grown on the substrate. Forming a source structure and extracting the device source potential; A drain structure is formed, and the drain potential of the device is extracted; A gate structure is formed, and the device gate potential is extracted.

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