Solar cell and method of manufacturing the same, photovoltaic module, and photovoltaic system
By using high-temperature preparation of polar doped layers and etching slurry imaging processes, the problems of low preparation efficiency and large mask layer damage in existing technologies have been solved, achieving high-efficiency preparation and high photoelectric conversion efficiency of solar cells.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ZHEJIANG AIKO SOLAR ENERGY TECH CO LTD
- Filing Date
- 2026-03-27
- Publication Date
- 2026-06-23
AI Technical Summary
Existing technologies involve time-consuming processes for preparing doped layers with different polarities, resulting in poor solar cell fabrication efficiency. Laser etching of the mask layer causes significant damage to the doped layer, leading to low photoelectric conversion efficiency.
High temperature is used to prepare the polar doped layer, combined with an etching paste imaging process to avoid damage to the doped layer by laser etching. The first and second polar doped layers are prepared sequentially on the back side of the silicon substrate, and a metal layer is formed on the passivation layer for electrical connection.
It saves heat loss in the fabrication process, improves the fabrication efficiency of solar cells, reduces damage to the doped layer, and enhances photoelectric conversion efficiency.
Smart Images
Figure CN122269858A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of solar cell technology, and in particular to a solar cell and its preparation method, a photovoltaic module and a photovoltaic system. Background Technology
[0002] A solar cell is a semiconductor device that converts light energy into electrical energy using the photovoltaic effect. Solar energy is an inexhaustible and clean energy source, and has therefore received widespread attention.
[0003] Solar cells consist of doped layers with different polarities. Different doping conditions correspond to different polarities. Current technologies for preparing doped layers with different polarities have long processing times, resulting in poor solar cell fabrication efficiency. Furthermore, laser etching of the mask layer causes significant damage to the doped layers, leading to poor photoelectric conversion efficiency in the fabricated solar cells. Summary of the Invention
[0004] This application proposes a solar cell and its fabrication method, a photovoltaic module and a photovoltaic system, which are used to improve the fabrication efficiency of solar cells and reduce the damage of the etching mask layer to the doped layer.
[0005] To achieve the above objectives, this application adopts the following technical solution: In a first aspect, a method for fabricating a solar cell is provided, the method comprising: imaged the back side of a silicon substrate based on an etching paste to sequentially fabricate a first polar doped layer and a second polar doped layer on the back side of the silicon substrate; the fabrication temperature of the first polar doped layer and the maximum fabrication temperature of the second polar doped layer are both greater than or equal to 900°C; forming a passivation layer on the side of the first polar doped layer and the second polar doped layer away from the silicon substrate; forming a via in the area to be metallized on the passivation layer to expose the first polar doped layer and the second polar doped layer; forming a metal layer on the exposed first polar doped layer and the second polar doped layer, the metal layer being electrically connected to the first polar doped layer and the second polar doped layer.
[0006] Based on this scheme, the maximum preparation temperature of both the first polar doped layer and the second polar doped layer is greater than or equal to 900℃. In this way, the maximum preparation temperature of the second polar doped layer continuously activates the dopant corresponding to the first polar doped layer. The maximum preparation temperature of the second polar doped layer can assist in further doping of the first polar doped layer. On the one hand, it can save the heat loss of the process of preparing the first polar doped layer, resulting in overall energy saving and consumption reduction. On the other hand, it can comprehensively reduce the advance time and improve the preparation efficiency of solar cells. In addition, this application uses etching paste to image the back side of the silicon substrate, which can avoid the large thermal damage to the doped layer caused by laser etching mask layer, thus ensuring the photoelectric conversion efficiency of solar cells.
[0007] In conjunction with the first aspect, in some embodiments of the first aspect, the highest preparation temperature of the first polar doped layer is 900°C to 1050°C, and preferably, the highest preparation temperature of the first polar doped layer is 920°C to 1000°C.
[0008] In conjunction with the first aspect, in some embodiments of the first aspect, the highest preparation temperature of the second polar doped layer is 900°C to 1025°C, and preferably, the highest preparation temperature of the second polar doped layer is 900°C to 980°C.
[0009] In conjunction with the first aspect, in some embodiments of the first aspect, the duration of the highest preparation temperature of the first polar doped layer is 2 min to 40 min.
[0010] In conjunction with the first aspect, in some embodiments of the first aspect, the duration of the highest preparation temperature of the second polar doped layer is 0.5 min to 30 min.
[0011] In conjunction with the first aspect, in certain embodiments of the first aspect, imagery is performed on the back side of a silicon substrate based on an etching paste to sequentially fabricate a first polar doped layer and a second polar doped layer on the back side of the silicon substrate, comprising: fabricating a full-surface first tunneling layer and a first polar doped layer on the back side of the silicon substrate; removing the first tunneling layer and the first polar doped layer in a second polar region based on the etching paste, forming a first tunneling layer and a first polar doped layer retained in the first polar region; the second polar region and the first polar region are arranged alternately; and fabricating a second tunneling layer and a second polar doped layer in the second polar region.
[0012] In conjunction with the first aspect, in certain embodiments of the first aspect, removing the first tunneling layer and the first polar doped layer of the second polar region includes: forming a first mask layer on the side of the first polar doped layer opposite to the silicon substrate; forming an etching paste on the first mask layer of the second polar region, causing the etching paste to react with the first mask layer to remove the first mask layer of the second polar region; the etching paste contains one or more of hydrofluoric acid and nitric acid; removing the etching paste using an organic solvent; and removing the first tunneling layer and the first polar doped layer of the second polar region using an alkaline solution; the alkaline solution includes one or more of NaOH, KOH, NH4OH, and TMAH.
[0013] In conjunction with the first aspect, in certain embodiments of the first aspect, fabricating a second tunneling layer and a second polar doped layer in a second polar region includes: sequentially fabricating a second tunneling layer, a second polar doped layer, and a second mask layer on the entire back side of a silicon substrate; removing the second mask layer of the first polar region and a portion of the second polar region using an etching paste; the portion of the second polar region corresponds to the region to be formed as an isolation region; removing the second tunneling layer and the second polar doped layer of the first polar region and a portion of the second polar region using an alkaline solution; removing the first mask layer of the first polar region and the second mask layer of the second polar region using an etching paste, or removing the first mask layer of the first polar region and the second mask layer of the second polar region using a wet etching process.
[0014] In conjunction with the first aspect, in some embodiments of the first aspect, the silicon substrate includes a first diffusion-doped region and a second diffusion-doped region; the first diffusion-doped region corresponds to a first polar doped layer; the first diffusion-doped region corresponds to a second polar doped layer; The doping elements in the first diffusion doping region include one or more of Ga and B; the doping elements in the second diffusion doping region include one or more of P or As.
[0015] In conjunction with the first aspect, in some embodiments of the first aspect, the doping concentration of the doping element in the first diffusion doping region is less than the doping concentration of the doping element in the second diffusion doping region.
[0016] Secondly, the present invention provides a solar cell, which is made by the solar cell preparation method described above.
[0017] Thirdly, the present invention provides a photovoltaic module, which includes any of the possible solar cells described above.
[0018] Fourthly, the present invention provides a photovoltaic system, which includes the photovoltaic modules described above. Attached Figure Description
[0019] Figure 1 A schematic flowchart illustrating a method for fabricating a solar cell, provided as an embodiment of this application; Figure 2 A schematic flowchart illustrating another method for fabricating a solar cell provided in an embodiment of this application; Figure 3 A schematic diagram of the structure of a semi-finished solar cell provided for an embodiment of this application; Figure 4 A schematic diagram of the structure of another semi-finished solar cell provided for an embodiment of this application; Figure 5 A schematic flowchart illustrating another method for fabricating a solar cell provided in an embodiment of this application; Figure 6 A schematic flowchart illustrating another method for fabricating a solar cell provided in an embodiment of this application; Figure 7 A schematic diagram of the structure of another semi-finished solar cell provided for an embodiment of this application; Figure 8 A schematic diagram of the structure of another semi-finished solar cell provided for an embodiment of this application; Figure 9 A schematic diagram of the structure of another semi-finished solar cell provided for an embodiment of this application; Figure 10 This is a schematic diagram of the structure of another semi-finished solar cell provided for an embodiment of this application.
[0020] Explanation of reference numerals in the attached drawings: silicon substrate 10, first mask layer 11, first polar doped layer 12, first tunneling layer 13, second mask layer 14, second polar doped layer 15, second tunneling layer 16. Detailed Implementation
[0021] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. Examples of embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. Furthermore, it should be understood that the specific embodiments described herein are merely for explaining this application and are not intended to limit this application.
[0022] In the description of this application, it should be understood that the terms "length", "width", "upper", "lower", "top", "bottom", "lateral", "longitudinal", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0023] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0024] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0025] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.
[0026] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.
[0027] According to one aspect of this application, a method for preparing a solar cell is provided, such as... Figure 1 As shown, the method includes: S201. The back side of the silicon substrate 10 is imaged based on the etching paste to sequentially prepare a first polar doped layer 12 and a second polar doped layer 15 on the back side of the silicon substrate 10.
[0028] The highest preparation temperature of the first polar doped layer 12 and the highest preparation temperature of the second polar doped layer 15 are both greater than or equal to 900℃.
[0029] As one possible implementation, after forming the first polar doped layer 12 and the first mask layer 11 on the back side of the silicon substrate 10, an etching paste can be printed to image the back side of the silicon substrate 10, so that the first polar doped layer 12 and the second polar doped layer 15 can be sequentially prepared on the back side of the silicon substrate 10.
[0030] It should be noted that detailed instructions for this step can be found in subsequent sections, and will not be repeated here.
[0031] In some embodiments, the silicon substrate 10 may be placed in a deposition apparatus, and silane gas may be introduced into the deposition apparatus to deposit a doped polycrystalline silicon layer, and phosphorus diffusion or boron diffusion may be performed to sequentially prepare a first polar doped layer 12 and a second polar doped layer 15 on the back side of the silicon substrate 10.
[0032] In one example, the deposition equipment can be LPCVD or PECVD.
[0033] In some other embodiments, a tunneling layer may be formed on the back side of the silicon substrate 10, and a first polar doped layer 12 and a second polar doped layer 15 may be formed on the side of the tunneling layer opposite to the silicon substrate 10.
[0034] Specifically, the silicon substrate 10 can be wet-processed, and an oxide layer (such as silicon oxide) can be grown on the wet-processed silicon substrate 10 to prepare a tunneling layer on the silicon substrate 10.
[0035] For example, a tunneling layer can be prepared by reacting a silicon substrate 10 with oxygen or water vapor at a high temperature using a thermal oxidation method to generate silicon dioxide, thereby growing an oxide layer (such as silicon oxide) on the wet-processed silicon substrate 10.
[0036] For example, silicon oxide can be generated by decomposing a gas-phase precursor on the surface of the silicon substrate 10 to grow an oxide layer (such as silicon oxide) on the wet-processed silicon substrate 10, thus preparing a tunneling layer.
[0037] The wet processing can include a pretreatment stage and a main etching stage.
[0038] For example, organic matter, metallic impurities, and natural oxide layers on the surface of the silicon substrate 10 can be removed during the pretreatment stage, and the silicon substrate 10 can be etched during the main etching stage. It should be noted that the specific processes for removing organic matter, metallic impurities, and natural oxide layers from the surface of the silicon substrate 10, as well as the specific processes for etching the silicon substrate 10 during the main etching stage, can be referred to existing technologies and will not be elaborated here.
[0039] Understandably, by preparing a tunneling layer, interfacial recombination loss can be reduced, the open-circuit voltage and fill factor of the cell can be improved, thereby enhancing the photoelectric conversion efficiency of the cell.
[0040] In some embodiments, the solar cell is a back-contact cell. Since the P-region and N-region of the back-contact cell are both formed on the back side of the cell, corresponding tunneling layers are formed in the corresponding regions of the P-region and N-region respectively when the tunneling layer is prepared. Then, the corresponding doped layer, passivation layer and grid line structure are formed on it. Generally, the P-region and N-region are isolated by an isolation region to avoid direct contact between the two regions and cause a short circuit. The structure of the back-contact cell can refer to the prior art and will not be described in detail here.
[0041] The highest preparation temperature of the first polar doped layer 12 and the highest preparation temperature of the second polar doped layer 15 are both greater than or equal to 900℃.
[0042] Thus, the highest preparation temperature of the second polar doped layer 15 is relatively high. The high temperature of the doping reaction of the second polar doped layer 15 can be used to assist the doping reaction of the first polar doped layer 12, saving the doping time of the first polar doped layer 12 and improving the preparation efficiency of solar cells.
[0043] S202, a passivation layer is formed on the side of the first polar doped layer 12 and the second polar doped layer 15 away from the silicon substrate 10.
[0044] As one possible implementation, one or more of silicon nitride films, silicon nitride films, and aluminum nitride films can be deposited on the first polar doped layer 12 and the second polar doped layer 15 to form a passivation layer on the side of the first polar doped layer 12 and the second polar doped layer 15 away from the silicon substrate 10.
[0045] In some embodiments, an acidic solution such as HF can be used to remove the doped residual phosphosilicate glass (PSG) / borosilicate glass (BSG), and after removing the PSG / BSG, a passivation layer is formed on the side of the first polar doped layer 12 and the second polar doped layer 15 facing away from the silicon substrate 10.
[0046] S203. A via is formed in the region to be metallized on the passivation layer, exposing the first polar doped layer 12 and the second polar doped layer 15.
[0047] As one possible implementation, a via can be formed in the area to be metallized on the passivation layer by laser or etching, exposing the first polar doped layer 12 and the second polar doped layer 15.
[0048] In some embodiments, the highest preparation temperature of the first polar doped layer 12 is 900°C to 1050°C. For example, it can be any value between 900°C, 920°C, 940°C, 960°C, 980°C, 1000°C, 1025°C, 1050°C, or 900°C to 1050°C. Preferably, the highest preparation temperature of the first polar doped layer 12 is 920°C to 1000°C. For example, it can be any value between 920°C, 940°C, 960°C, 980°C, 1000°C, or 920°C to 1000°C, and is not limited herein.
[0049] This enables high activation and uniform diffusion of impurities, effectively reducing contact resistance and improving carrier collection efficiency. This temperature range also helps repair lattice defects, thereby enhancing the cell's open-circuit voltage and fill factor, and improving photoelectric conversion efficiency.
[0050] In some embodiments, the highest preparation temperature of the second polar doped layer 15 is 900°C to 1025°C. For example, it can be any value between 900°C, 920°C, 940°C, 960°C, 980°C, 1000°C, 1020°C, 1025°C, or 900°C to 1025°C. Preferably, the highest preparation temperature of the second polar doped layer 15 is 900°C to 980°C, for example, it can be any value between 900°C, 920°C, 940°C, 960°C, 980°C, or 900°C to 980°C, and is not limited herein.
[0051] This enables high activation and uniform diffusion of impurities, effectively reducing contact resistance and improving carrier collection efficiency. This temperature range also helps repair lattice defects, thereby enhancing the cell's open-circuit voltage and fill factor, and improving photoelectric conversion efficiency.
[0052] In some embodiments, the holding time of the highest fabrication temperature of the first polar doped layer 12 is 2 min to 40 min. For example, it can be any value between 2 min, 5 min, 10 min, 20 min, 30 min, 40 min, or 2 min to 40 min, and is not limited herein.
[0053] In addition, the fabrication process of the doped layer also includes processes such as vacuuming, tube insertion and removal, and temperature rise and fall. In this way, it can be avoided that the first polar doped layer 12 is not fully doped due to an excessively short fabrication time, and it can also be avoided that the first polar doped layer 12 is not fully doped due to an excessively long fabrication time, which would lead to the accumulation of impurities in the crystal lattice, forming high-concentration defect clusters, which become strong recombination centers and seriously reduce minority carrier lifetime.
[0054] In some embodiments, the holding time of the highest fabrication temperature of the second polar doped layer 15 is 0.5 min to 30 min. For example, it can be any value between 0.5 min, 5 min, 10 min, 20 min, 30 min or 0.5 min to 40 min, and is not limited herein.
[0055] In this way, the impurities in the second polar doped layer 15 can be fully activated and evenly distributed, and the first polar doped layer 12 can be further doped.
[0056] Among them, the first polar doped layer 12 and the second polar doped layer 15 are respectively P-doped layer and N-doped layer.
[0057] The P-doped layer and N-doped layer can be doped polycrystalline silicon layers. The N-doped layer is doped with an N-type element, specifically a group VA element of the periodic table, such as phosphorus. The P-doped layer is doped with a P-type element, specifically a group IIIA element of the periodic table, such as boron.
[0058] In some embodiments, a tunneling layer is further included between the silicon substrate 10 and the first polar doped layer 12, and between the silicon substrate 10 and the second polar doped layer 15.
[0059] In some embodiments, the solar cell is a back-contact solar cell, with the P-region and N-region located on the same surface of the silicon substrate 10. Specifically, both the P-region and N-region are located on the back side of the silicon substrate 10.
[0060] When both the P-region and the N-region are located on the back side of the silicon substrate 10, they are isolated from each other by an isolation region. A first polar doped layer 12 and a second polar doped layer 15 are alternately arranged on the back side of the silicon substrate 10; the tunneling layer may include a first tunneling layer 13 and a second tunneling layer 16. The second tunneling layer 16 may be a P-tunneling layer, and the first tunneling layer 13 may be an N-tunneling layer. One of the first polar doped layer 12 and the other of the second polar doped layer 15 is a P-doped layer, and the other is an N-doped layer.
[0061] For example, when both the P-region and the N-region are located on the back side of the silicon substrate 10, the second polar doped layer 15 can be a P-doped layer and the first polar doped layer 12 can be an N-doped layer; the second tunneling layer 16 can be a P-tunneling layer and the first tunneling layer 13 can be an N-tunneling layer. The P-region and the N-region are isolated by an isolation region.
[0062] S204. A metal layer is formed on the exposed first polar doped layer 12 and second polar doped layer 15.
[0063] The metal layer is electrically connected to the first polar doped layer 12 and the second polar doped layer 15.
[0064] As one possible implementation, a seed layer can be formed on the exposed first polar doped layer 12 and second polar doped layer 15, and metal can be deposited on the seed layer by an electroplating process to form a metal layer.
[0065] Specifically, the seed layer is a metal seed layer. At least one of the following processes can be used to form the seed layer on the exposed first polar doped layer 12 and second polar doped layer 15: PVD, ALD, screen printing, vapor deposition, sputtering, etc.
[0066] For example, PVD / ALD can be used to deposit metal seed layers such as Al, Co, Ta, W, and Ti.
[0067] Specifically, at least one of the following equipment can be used for electroplating: horizontal electroplating machine, vertical electroplating machine, and tank electroplating machine. The electroplating solution can be at least one of copper sulfate, copper plating additive, stannous sulfate, and tin plating additive.
[0068] Understandably, by depositing metal in the seed layer through electroplating to form a metal layer, the seed layer can reduce contact resistance, improve adhesion, and ensure long-term stable operation of the battery.
[0069] As another possible implementation, a metal layer can be formed on the exposed first polar doped layer 12 and second polar doped layer 15 by screen printing.
[0070] For example, a screen printing device can be provided with a target screen printing stencil. Printing material is laid on the target screen printing stencil. Further, a silicon substrate 10 with a passivated layer is placed on the screen printing device. The screen printing squeegee of the device holds the mesh lines perpendicularly and scrapes along the mesh line direction with a preset pressure, precisely printing through the cutout pattern area of the target screen printing stencil onto the silicon substrate 10 to form a gate pattern. Further, the printed gate pattern is sintered to form a metal layer on the exposed doped layer.
[0071] Based on this scheme, the preparation temperature of the first polar doped layer 12 and the maximum preparation temperature of the second polar doped layer 15 are both greater than or equal to 900℃. In this way, the maximum preparation temperature of the second polar doped layer 15 continuously activates the dopant corresponding to the first polar doped layer 12. The maximum preparation temperature of the second polar doped layer 15 can assist in further doping of the first polar doped layer 12. On the one hand, it can save the heat loss of the process of preparing the first polar doped layer 12, resulting in overall energy saving and consumption reduction. On the other hand, it can comprehensively reduce the advance time and improve the preparation efficiency of solar cells. In addition, this application uses etching paste to image the back side of the silicon substrate 10, which can avoid the laser etching mask layer from causing significant damage to the doped layer and ensure the photoelectric conversion efficiency of the solar cell.
[0072] When this method is applied to BC batteries, the structure described above can be a local P-region structure or an N-region structure of the battery cell, and is not limited here.
[0073] In some embodiments, such as Figure 2 As shown, in order to image the back side of the silicon substrate 10 based on the etching paste, and to sequentially fabricate the first polar doped layer 12 and the second polar doped layer 15 on the back side of the silicon substrate 10, step S201 of this application may include the following steps: S301. A first tunneling layer 13 and a first polar doped layer 12 are formed on the back side of the silicon substrate 10.
[0074] As one possible implementation, the silicon substrate 10 can be placed in a deposition apparatus and silane gas can be introduced into the deposition apparatus to deposit a doped polycrystalline silicon layer on the back side of the silicon substrate 10, and phosphorus diffusion or boron diffusion can be performed to form a first polar doped layer 12.
[0075] It should be noted that the preparation method of the first tunneling layer 13 can be referred to the description in S201, and will not be repeated here.
[0076] In one example, a schematic diagram showing the fabrication of a full-surface first tunneling layer 13 and a first polar doped layer 12 on the back side of a silicon substrate 10 can be shown as follows: Figure 3 As shown.
[0077] S302, the first tunneling layer 13 and the first polar doped layer 12 in the second polar region are removed based on the etching paste, forming the first tunneling layer 13 and the first polar doped layer 12 retained in the first polar region.
[0078] The second polar region and the first polar region are arranged alternately.
[0079] As one possible implementation, after forming the first mask layer 11 on the side of the first polar doped layer 12 away from the silicon substrate 10, the first mask layer 11 of the second polar region can be removed based on the etching paste, and the first tunneling layer 13 and the first polar doped layer 12 of the second polar region can be removed using an alkaline solution, forming the first tunneling layer 13 and the first polar doped layer 12 retained in the first polar region.
[0080] It should be noted that the mask can be a single-layer or multi-layer film such as phosphosilicate glass, borosilicate glass, or silicon nitride, or a photoresist. When the mask is a photoresist, a coating process can be used to coat the entire surface of the first polar doped layer 12 with a wet film or photoresist. Then, an exposure machine or laser is used to remove the first mask layer 11 in the second polar region, exposing the first polar doped layer 12 in the second polar region. An alkaline solution is then used to remove the first polar doped layer 12 in the second polar region, forming the first polar doped layer 12 retained in the first polar region. The coating process includes at least one of spraying, roller coating, and spin coating. Alternatively, a printing process can be used directly to form a patterned mask.
[0081] In one example, a schematic diagram showing the formation of a first tunneling layer 13 and a first polar doped layer 12 remaining in the first polar region after removing the first polar doped layer 12 based on an etching paste can be shown as follows: Figure 4 As shown. S303, a second tunneling layer 16 and a second polar doped layer 15 are prepared in the second polar region.
[0082] As one possible implementation, the second tunneling layer 16, the second polar doped layer 15, and the second mask layer 14 can be fabricated on the entire back side of the silicon substrate 10, and the second mask layer 14, the first mask layer 11, and the second polar doped layer 15 in the first polar region can be removed to fabricate the second polar doped layer 15 in the second polar region.
[0083] The second mask layer 14 is disposed on the side of the second polar doped layer 15 away from the silicon substrate 10. The second mask layer 14 is made of the same material as the first mask layer 11, and the removal methods of the second mask layer 14 and the first mask layer 11 are the same. Please refer to the above description, which will not be repeated here.
[0084] In some embodiments, after forming vias in the region to be metallized on the passivation layer to expose the first polar doped layer 12 and the second polar doped layer 15, the passivation layer can be activated by sintering or photoinjection. For example, a laser device can be provided to irradiate the silicon substrate 10, and the passivation layer is partially sintered in the laser-irradiated area to activate the passivation layer by sintering.
[0085] Understandably, activating the passivation layer through sintering or light injection can effectively reduce the surface recombination rate, improve photoelectric conversion efficiency, and enhance the long-term stability of the battery.
[0086] In some embodiments, such as Figure 5 As shown, in order to remove the first polar doped layer 12 in the second polar region, S302 may include the following steps: S401, a first mask layer 11 is formed on the side of the first polar doped layer 12 away from the silicon substrate 10.
[0087] The first mask layer 11 is made of silicon oxide.
[0088] As one possible implementation, silicon oxide can be grown on the side of the first polar doped layer 12 away from the silicon substrate 10 by atomic layer deposition to form the first mask layer 11.
[0089] In some embodiments, a single-layer or multi-layer film such as phosphosilicate glass, borosilicate glass, or silicon nitride may be formed on the side of the first polar doped layer 12 away from the silicon substrate 10 to form the first mask layer 11.
[0090] In some other embodiments, the material for preparing the first mask layer 11 can be photoresist, which can be coated onto the surface of the first polar doped layer 12 using a coating process to form the first mask layer 11.
[0091] Photolithography can be either positive or negative photoresist.
[0092] S402, An etching paste is formed on the first mask layer 11 in the second polarity region, and the etching paste reacts with the first mask layer 11 to remove the first mask layer 11 in the second polarity region.
[0093] The etching slurry contains one or more of hydrofluoric acid and nitric acid.
[0094] As one possible implementation, an etching paste can be formed on the first mask layer 11 in the second polar region by means of coating or other methods, so that the etching paste reacts with the first mask layer 11 to remove the first mask layer 11 in the second polar region.
[0095] Specifically, after forming an etching paste on the first mask layer 11 in the second polar region, an oven is used to bake the material, causing the etching paste to react with the first mask layer 11, thereby removing the first mask layer 11 in the second polar region.
[0096] In some embodiments, the material for preparing the first mask layer 11 is a positive photoresist. After exposure, the positive photoresist in the first polar region is exposed, and the first mask layer 11 in the unexposed second polar region is soluble in the developing solution. After exposure, development removes the positive photoresist in the second polar region, and finally drying removes the first mask layer 11 in the second polar region.
[0097] In some other embodiments, the material for preparing the first mask layer 11 is a negative photoresist. After the photoresist in the second polar region is exposed, the exposed negative photoresist in the second polar region is soluble in the developer. After exposure, the negative photoresist in the second polar region is removed by development, and finally dried to remove the first mask layer 11 in the second polar region.
[0098] S403. Use organic solvents to remove the etching paste.
[0099] The organic solvents include one or more of ethanol, acetone, and ethyl acetate.
[0100] For example, a cleaning tank containing organic solvents can be provided, and the silicon substrate 10 is placed in the cleaning tank to remove the etching paste using the organic solvents in the cleaning tank.
[0101] Alternatively, a spraying device can be provided, which can spray organic solvents onto the silicon substrate 10 to remove the etching paste.
[0102] S404. Use an alkaline solution to remove the first tunneling layer 13 and the first polar doped layer 12 in the second polar region.
[0103] Specifically, a cleaning tank containing an alkaline solution can be provided, and the silicon substrate 10 is placed in the cleaning tank to remove the first polar doped layer 12 of the second polar region using the alkaline solution in the cleaning tank.
[0104] Alternatively, a spraying device can be provided that can spray an alkaline solution onto the silicon substrate 10 to remove the first polar doped layer 12 of the second polar region using the alkaline solution.
[0105] Specifically, the cleaning spray equipment may include multiple spray nozzles, with multiple sprays evenly distributed in the spray chamber. The spray chamber also includes conveyor rollers, which can convey the silicon substrate 10 within the spray chamber to achieve better etching results.
[0106] In some embodiments, such as Figure 6 As shown, in order to prepare the second polar doped layer 15 in the second polar region, S303 may include the following steps: S501, the second tunneling layer 16, the second polar doped layer 15, and the second mask layer 14 are sequentially prepared on the entire back side of the silicon substrate 10.
[0107] The second mask layer 14 is disposed on the side of the second polar doped layer 15 away from the silicon substrate 10.
[0108] As one possible implementation, the diffusion types of the first polar doped layer 12 and the second polar doped layer 15 are different; When the first polar doped layer 12 is phosphorus diffusion, the silicon substrate 10 can be placed in a deposition apparatus and silane gas can be introduced into the deposition apparatus to deposit a doped polycrystalline silicon layer on the entire back side of the silicon substrate 10 and perform boron diffusion to form the second polar doped layer 15.
[0109] When the first polar doped layer 12 is boron diffusion, the silicon substrate 10 can be placed in a deposition apparatus and silane gas can be introduced into the deposition apparatus to deposit a doped polycrystalline silicon layer on the entire back side of the silicon substrate 10 and perform phosphorus diffusion to form the second polar doped layer 15.
[0110] It should be noted that before the second polar doped layer 15 and the second mask layer 14 are fabricated on the entire back side of the silicon substrate 10, since the first polar region includes the first polar doped layer 12 and the first mask layer 11, and the first polar region includes the silicon substrate 10, after the second polar doped layer 15 and the second mask layer 14 are fabricated on the entire back side of the silicon substrate 10, the first polar region sequentially includes the first polar doped layer 12, the first mask layer 11, the second doped layer and the second mask layer 14, and the second polar region sequentially includes the second polar doped layer 15 and the second mask layer 14.
[0111] In one example, a schematic diagram showing the sequential fabrication of the second tunneling layer 16, the second polar doped layer 15, and the second mask layer 14 on the entire back surface of the silicon substrate 10 can be shown as follows: Figure 7 As shown.
[0112] S502, Use etching paste to remove the second mask layer 14 of the first polarity region and part of the second polarity region.
[0113] Among them, some of the second polarity regions correspond to the areas where isolation zones are to be formed.
[0114] In one possible implementation, an etching slurry can be applied to a second mask layer 14 in the first polar region and a portion of the second polar region, so that the etching slurry reacts with the second mask layer 14 in the first polar region and a portion of the second polar region to remove the second mask layer 14 in the first polar region and a portion of the second polar region.
[0115] In one example, a schematic diagram of the second mask layer 14 after removing the first polarity region and part of the second polarity region using an etching paste can be shown as follows: Figure 8 As shown.
[0116] S503, using an alkaline solution to remove the second tunneling layer 16 and the second polar doped layer 15 from the first polar region and part of the second polar region.
[0117] The removal method can be found in the specific description of S404, and will not be repeated here.
[0118] In one example, a schematic diagram showing the removal of the second tunneling layer 16 and the second polar doped layer 15 from the first polar region and part of the second polar region using an alkaline solution is shown below. Figure 9 As shown.
[0119] S504. Use an etching paste to remove the first mask layer 11 of the first polar region and the second mask layer 14 of the second polar region, or use a wet etching process to remove the first mask layer 11 of the first polar region and the second mask layer 14 of the second polar region.
[0120] As one possible implementation method, in conjunction with the above... Figure 9 The etching slurry can be applied to the second mask layer 14 of the first polar region and part of the second polar region, so that the etching slurry reacts with the second mask layer 14 of the first polar region and part of the second polar region, thereby removing the second mask layer 14 of the first polar region and part of the second polar region.
[0121] In one example, a schematic diagram after removing the first mask layer 11 of the first polarity region and the second mask layer 14 of the second polarity region can be shown as follows: Figure 10 As shown.
[0122] In some embodiments, in forming such Figure 10 After the structure shown, texturing can be performed on the isolation areas of the front and back sides of the silicon substrate 10.
[0123] As one possible implementation, a texturing material can be used to texturize the isolation regions on the front and back sides of the silicon substrate 10.
[0124] The texturing material includes an alkaline texturing solution and additives; the alkaline texturing solution is at least one of NaOH, KOH, NH4OH, and TMAH; the additives include at least one of surfactants, dispersants, emulsifiers, nucleating agents, and protective agents. In some embodiments, the texturing solution may also be formed by mixing other components, which is not limited herein.
[0125] In some embodiments, the silicon substrate 10 includes a first diffusion-doped region and a second diffusion-doped region; the first diffusion-doped region corresponds to the first polar doped layer 12; and the second diffusion-doped region corresponds to the second polar doped layer 15. The doping elements in the first diffusion doping region include one or more of Ga and B; the doping elements in the second diffusion doping region include one or more of P or As.
[0126] The doping concentration of the doping element in the first diffusion doping region is less than that in the second diffusion doping region.
[0127] In one example, the thickness of the diffusion-doped region can be 50 nm. That is, the depth of the diffusion doping is 50 nm.
[0128] In this way, by using concentration differentiation design, the electrical characteristics of different functional areas can be adjusted independently, thereby improving the overall performance of the device.
[0129] It is understood that in such embodiments, the photovoltaic module corresponding to the solar cell may also include a metal frame, a backsheet, photovoltaic glass, and an encapsulating film. The encapsulating film can be filled between the front and back of the solar cell, as well as between the photovoltaic glass and adjacent cells. As a filler, it can be a transparent colloid with good light transmittance and aging resistance. For example, the encapsulating film can be EVA film or POE film, and the specific choice can be made according to the actual situation, without limitation.
[0130] Photovoltaic glass can be applied to the encapsulating film on the front of solar cells. This photovoltaic glass can be ultra-clear glass, characterized by high light transmittance, high transparency, and superior physical, mechanical, and optical properties. For example, ultra-clear glass can achieve a light transmittance of over 92%, protecting the solar cells while minimizing impact on their efficiency. Simultaneously, the encapsulating film bonds the photovoltaic glass and the solar cells together, providing sealing, insulation, and waterproofing / moisture protection for the solar cells.
[0131] The backsheet is attached to the encapsulant film on the back of the solar cell. It protects and supports the solar cell, providing reliable insulation, water resistance, and aging resistance. Multiple backsheet options are available, typically including tempered glass, acrylic glass, and aluminum alloy TPT composite encapsulant film, with specific choices depending on the specific circumstances. The backsheet, solar cell, encapsulant film, and photovoltaic glass can be mounted on a metal frame. The metal frame serves as the main external support structure for the entire photovoltaic module, providing stable support and installation. For example, the photovoltaic module can be installed at the desired location using the metal frame.
[0132] The photovoltaic system of this application embodiment includes the photovoltaic module described above.
[0133] In this embodiment, the photovoltaic system can be applied in photovoltaic power plants, such as ground-mounted power plants, rooftop power plants, and floating power plants. It can also be applied to equipment or devices that utilize solar energy to generate electricity, such as user solar power supplies, solar streetlights, solar cars, and solar buildings. Of course, it is understood that the application scenarios of the photovoltaic system are not limited to these; that is, the photovoltaic system can be applied in all fields that require solar energy to generate electricity. Taking a photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a combiner box, and an inverter. The photovoltaic array may be an array combination of multiple photovoltaic modules; for example, multiple photovoltaic modules can form multiple photovoltaic arrays. The photovoltaic array is connected to the combiner box, which can collect the current generated by the photovoltaic array. The collected current flows through the inverter and is converted into AC power required by the mains power grid before being connected to the mains power grid to achieve solar power supply.
[0134] In the description of this specification, the references to terms such as "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0135] Furthermore, the above are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A method for preparing a solar cell, characterized in that, The method includes: The back side of the silicon substrate is imaged using an etching paste to sequentially fabricate a first polar doped layer and a second polar doped layer on the back side of the silicon substrate; the maximum fabrication temperature of the first polar doped layer and the maximum fabrication temperature of the second polar doped layer are both greater than or equal to 900°C. A passivation layer is formed on the side of the first polar doped layer and the second polar doped layer that is away from the silicon substrate; A via is formed in the area to be metallized on the passivation layer to expose the first polar doped layer and the second polar doped layer; A metal layer is formed on the exposed first polar doped layer and second polar doped layer, the metal layer being electrically connected to the first polar doped layer and second polar doped layer.
2. The preparation method according to claim 1, characterized in that, The highest preparation temperature of the first polar doped layer is 900℃~1050℃, preferably 920℃~1000℃.
3. The preparation method according to claim 1, characterized in that, The maximum preparation temperature of the second polar doped layer is 900℃~1025℃, preferably 900℃~980℃.
4. The preparation method according to claim 1, characterized in that, The maximum preparation temperature of the first polar doped layer is maintained for 2 min to 40 min.
5. The preparation method according to claim 1, characterized in that, The maximum preparation temperature of the second polar doped layer is maintained for 0.5 min to 30 min.
6. The preparation method according to claim 1, characterized in that, The method of imagerizing the back side of a silicon substrate using an etching paste to sequentially fabricate a first polar doped layer and a second polar doped layer on the back side of the silicon substrate includes: A first tunneling layer and a first polar doped layer are fabricated on the entire back surface of the silicon substrate; The first tunneling layer and the first polar doped layer in the second polar region are removed to form the first tunneling layer and the first polar doped layer retained in the first polar region; the second polar region and the first polar region are arranged alternately. A second tunneling layer and a second polar doped layer are prepared in the second polar region.
7. The preparation method according to claim 6, characterized in that, Removing the first tunneling layer and the first polar doped layer from the second polar region includes: A first mask layer is formed on the side of the first polar doped layer that is away from the silicon substrate; The etching slurry is formed on the first mask layer in the second polarity region, and the etching slurry reacts with the first mask layer to remove the first mask layer in the second polarity region; the etching slurry contains one or more of hydrofluoric acid and nitric acid; The etching slurry was removed using an organic solvent; The first tunneling layer and the first polar doped layer in the second polar region are removed using an alkaline solution; the alkaline solution includes one or more of NaOH, KOH, NH4OH, and TMAH.
8. The preparation method according to claim 6, characterized in that, The fabrication of the second tunneling layer and the second polar doped layer in the second polar region includes: The second tunneling layer, the second polar doped layer, and the second mask layer are sequentially fabricated on the entire back side of the silicon substrate. The second mask layer is removed using an etching paste to remove the first polarity region and a portion of the second polarity region; the portion of the second polarity region corresponds to the region where the isolation area is to be formed. The second tunneling layer and the second polar doped layer of the first polar region and the portion of the second polar region are removed using an alkaline solution. The first mask layer of the first polar region and the second mask layer of the second polar region are removed using the etching slurry, or the first mask layer of the first polar region and the second mask layer of the second polar region are removed using a wet etching process.
9. The preparation method according to claim 1, characterized in that, The silicon substrate includes a first diffusion-doped region and a second diffusion-doped region; the first diffusion-doped region corresponds to the first polar doped layer; the second diffusion-doped region corresponds to the second polar doped layer; The doping elements of the first diffusion doping region include one or more of Ga and B; the doping elements of the second diffusion doping region include one or more of P or As.
10. The preparation method according to claim 9, characterized in that, The doping concentration of the doping element in the first diffusion doping region is less than that in the second diffusion doping region.
11. A solar cell, characterized in that, The solar cell is manufactured using the preparation method described in any one of claims 1-10.
12. A photovoltaic module, characterized in that, Including the solar cell as described in claim 11.
13. A photovoltaic system, characterized in that, Including the photovoltaic module as described in claim 12.