A back contact cell and a method of manufacturing the same

Abstract

The application provides a back contact cell and a preparation method thereof. A polysilicon layer is arranged on one side of a bearing substrate, and interdigital staggered P-type and N-type doped regions are arranged on the side away from the substrate. The P-type doped region has a concentration of 2-3*10 19 cm ‑3 , and a width of 400-440μm. The N-type doped region has a concentration of 5-6*10 20 cm ‑3 , and a width of 330-370μm. A fine grid structure of an electrode layer is arranged on the doped region, and a single line or a multi-line interval design is adopted according to the relationship between the length of the fine grid electrode and a preset threshold value of 3-5mm. The precisely matched P / N region parameters can efficiently separate and directionally transport photo-generated carriers, reduce the recombination loss, balance the electron and hole transport, the differentiated fine grid is suitable for different path requirements, reduces the long-distance conduction loss, and controls the electrode coverage ratio. The overall design improves the carrier collection efficiency, reduces the series resistance, optimizes the photoelectric conversion performance, is suitable for the mature semiconductor preparation process, and has good mass production feasibility.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, specifically to a back contact cell and its fabrication method. Background Technology

[0002] Back-contact solar cells, by integrating the PN junction and metal electrodes on the back of the cell, completely eliminate optical losses caused by light shading from the front electrodes, significantly improving light absorption efficiency and photoelectric conversion potential. This has made them a core research and industrialization direction for high-efficiency crystalline silicon photovoltaic cells. Among these, the back-contact cell structure, which uses a polycrystalline silicon layer as the functional carrier and features interdigitated P-type and N-type doped regions, has become the mainstream technology for high-efficiency back-contact solar cells due to its excellent interface passivation effect and carrier transport characteristics.

[0003] In related technologies, back-contact batteries suffer from low efficiency in separating and transporting photogenerated carriers, high recombination losses, and a tendency to become unbalanced during transport. Summary of the Invention

[0004] The purpose of this application is to provide a back contact battery and its preparation method, so as to solve the technical problems of low photogenerated carrier separation and transport efficiency, large recombination loss and easy imbalance in the transport process of back contact batteries in related technologies.

[0005] In a first aspect, this application provides a back contact battery, comprising: Supporting substrate; A polycrystalline silicon layer is disposed on one side of the supporting substrate. The side of the polycrystalline silicon layer facing away from the supporting substrate includes P-type doped regions and N-type doped regions, which are arranged in an interdigitated pattern. The doping concentration of the P-type doped regions ranges from 2 × 10⁻⁶. 19 cm -3 -3×10 19 cm -3 The width of the P-type doped region ranges from 400 μm to 440 μm, and the doping concentration of the N-type doped region ranges from 5 × 10⁻⁶. 20 cm -3 -6×10 20 cm -3 The width of the N-type doped region ranges from 330 μm to 370 μm; An electrode layer comprising multiple fine gate structures disposed on the P-type doped region and the N-type doped region, each fine gate structure comprising at least one fine gate electrode. When the length of the fine gate electrode is greater than a preset threshold, the number of fine gate electrodes in one fine gate structure is at least two, and the at least two fine gate electrodes are spaced apart. When the length of the fine gate electrode is less than the preset threshold, the number of fine gate electrodes in one fine gate structure is one. The preset threshold ranges from 3 mm to 5 mm.

[0006] In the back-contact battery provided in this application, a polycrystalline silicon layer is disposed on one side of a supporting substrate. The side of the polycrystalline silicon layer away from the supporting substrate includes P-type doped regions and N-type doped regions, which are arranged in an interdigitated pattern. The doping concentration of the P-type doped regions ranges from 2 × 10⁻⁶. 19 cm -3 -3×10 19 cm -3 The width of the P-type doped region ranges from 400 μm to 440 μm, and the doping concentration of the N-type doped region ranges from 5 × 10⁻⁶. 20 cm -3 -6×10 20 cm -3 The width of the N-type doped region ranges from 330 μm to 370 μm. The electrode layer includes multiple fine gate structures disposed on the P-type and N-type doped regions. Each fine gate structure includes at least one fine gate electrode. When the length of the fine gate electrode is greater than a preset threshold, there are at least two fine gate electrodes in one fine gate structure, and these at least two fine gate electrodes are spaced apart. When the length of the fine gate electrode is less than the preset threshold, there is only one fine gate electrode in one fine gate structure. The preset threshold ranges from 3 mm to 5 mm. The combination of the P-type and N-type doped regions with precisely defined doping concentrations and width ranges enables efficient and rapid separation and directional transport of photogenerated carriers, effectively reducing recombination losses during carrier conduction and ensuring the overall balance of electron and hole transport processes. Furthermore, based on a differentiated fine-grid structure with a preset threshold of 3mm-5mm, it can be specifically matched to the carrier collection requirements of different transport paths: multiple spaced fine-grid electrodes are used in the long-path region to significantly shorten the transport distance of carriers to the electrode and reduce recombination losses over long distances; a single-line fine-grid electrode is used in the short-path region to reduce electrode coverage and contact losses while ensuring carrier collection capability. The overall design of the back-contact battery significantly improves carrier collection efficiency, reduces the internal series resistance of the battery, and ultimately achieves comprehensive optimization of photoelectric conversion performance. At the same time, the structural parameters are compatible with mature semiconductor fabrication processes, possessing good mass production feasibility.

[0007] The width of the P-type doped region is positively correlated with its doping concentration. When the doping concentration of the P-type doped region is 2 × 10⁻⁶, the width of the P-type doped region is positively correlated with its doping concentration. 19 cm -3 -2.5×10 19 cm -3 When the width of the P-type doped region ranges from 400 μm to 420 μm, and the doping concentration of the P-type doped region ranges from 2.5 × 10⁻⁶, the width of the P-type doped region ranges from 400 μm to 420 μm. 19 cm -3 -3.0×10 19 cm -3 At that time, the width of the P-type doped region ranges from 420 μm to 440 μm.

[0008] The width of the N-type doped region is negatively correlated with its doping concentration. Specifically, when the doping concentration of the N-type doped region is in the range of 5.0 × 10⁻⁶... 20 cm -3 -5.5×10 20 cm -3 When the width of the N-type doped region ranges from 350 μm to 370 μm, and the doping concentration of the N-type doped region ranges from 5.5 × 10⁻⁶, the width of the N-type doped region ranges from 350 μm to 370 μm. 20 cm -3 -6×10 20 cm -3 At that time, the width of the N-type doped region ranges from 330μm to 350μm.

[0009] The preset threshold is positively correlated with the doping concentration of the P-type doped region. When the doping concentration of the P-type doped region is in the range of 2 × 10⁻⁶, the threshold value is positively correlated with the doping concentration of the P-type doped region. 19 cm -3 -2.5×10 19 cm -3 When the preset threshold ranges from 3.0 mm to 4.0 mm, and the doping concentration of the P-type doped region ranges from 2.5 × 10⁻⁶, the threshold value is within the range of 3.0 mm to 4.0 mm. 19 cm -3 -3.0×10 19 cm -3 When the preset threshold is in the range of 4.0mm-5.0mm.

[0010] The preset threshold is negatively correlated with the width of the P-type doped region. When the width of the P-type doped region is 400μm-420μm, the preset threshold is 4.0mm-5.0mm. When the width of the P-type doped region is 420μm-440μm, the preset threshold is 3.0mm-4.0mm.

[0011] The linewidth of the fine gate electrode ranges from 13μm to 17μm, and the line spacing between adjacent fine gate electrodes within the same fine gate structure ranges from 55μm to 65μm.

[0012] The polysilicon layer further includes an isolation region on the side opposite to the supporting substrate. The isolation region is located between the P-type doped region and the N-type doped region, and the width of the isolation region ranges from 55μm to 65μm.

[0013] The electrode layer includes multiple bus structures, which are disposed on the P-type doped region and the N-type doped region. Each of the two ends of a bus structure is connected to a fine gate structure, and the overlap length between the fine gate structure and the bus structure is 15μm-25μm.

[0014] Secondly, this application provides a method for preparing a back contact battery, the method comprising: A support substrate is provided, and the polycrystalline silicon layer is deposited on the support substrate; P-type doped regions and N-type doped regions are formed on the polycrystalline silicon layer; The electrode layer is printed on the polysilicon layer, wherein the electrode layer includes a plurality of fine gate structures, the fine gate structures are disposed on the P-type doped region and the N-type doped region, and the fine gate structure includes at least one fine gate electrode. When the length of the fine gate electrode is greater than a preset threshold, the number of fine gate electrodes in one fine gate structure is at least two, and the at least two fine gate electrodes are spaced apart. When the length of the fine gate electrode is less than the preset threshold, the number of fine gate electrodes in one fine gate structure is one. The preset threshold ranges from 3 mm to 5 mm. After the electrode layer is pre-baked and sintered, it is encapsulated to form a back contact battery.

[0015] Among them, P-type doped regions and N-type doped regions are formed on the polycrystalline silicon layer, including: A glass layer is provided on the polycrystalline silicon layer, and the glass layer is laser-etched according to the width range of the P-type doped region and the N-type doped region, wherein the width range of the P-type doped region is 400μm-440μm and the width range of the N-type doped region is 330μm-370μm. Boron diffusion is performed according to the doping concentration range of the P-type doped region, wherein the doping concentration range of the P-type doped region is 2 × 10⁻⁶. 19 cm -3 -3×10 19 cm -3The flow rate of boron trichloride ranges from 2 sccm to 4 sccm, the ambient temperature ranges from 890℃ to 910℃, and the boron diffusion time ranges from 28 min to 32 min. Phosphorus diffusion is performed according to the doping concentration range of the N-type doped region, wherein the doping concentration range of the N-type doped region is 5 × 10⁻⁶. 20 cm -3 -6×10 20 cm -3 The flow rate of phosphorus oxychloride ranges from 6 sccm to 9 sccm, the ambient temperature ranges from 840℃ to 860℃, and the phosphorus diffusion time ranges from 22 min to 26 min. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the fine grid structure distribution of a back contact battery provided in an embodiment of this application; Figure 2 This is a schematic diagram of the cross-sectional structure of a back contact battery for the P-type doped region provided in an embodiment of this application; Figure 3 This is a schematic diagram of the cross-sectional structure of the N-type doped region of a back contact battery provided in an embodiment of this application; Figure 4 This is a schematic diagram of a busbar structure and a fine grid structure provided in an embodiment of this application; Figure 5 This is a flowchart of a back contact battery manufacturing method provided in the embodiments of this application; Figure 6 This is a flowchart of step S200 in a back contact battery preparation method provided in this application.

[0018] Label Explanation: The back contact cell 100, the carrier substrate 10, the polycrystalline silicon layer 20, the P-type doped region 21, the isolation region 22, the N-type doped region 23, the fine grid structure 31, the fine grid electrode 311, the bus structure 40, and the tunneling oxide layer 50. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0021] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0022] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joint" shall be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0023] Back-contact solar cells, by integrating the PN junction and metal electrodes on the back of the cell, completely eliminate optical losses caused by light shading from the front electrodes, significantly improving light absorption efficiency and photoelectric conversion potential. This has made them a core research and industrialization direction for high-efficiency crystalline silicon photovoltaic cells. Among these, the back-contact cell structure, which uses a polycrystalline silicon layer as the functional carrier and features interdigitated P-type and N-type doped regions, has become the mainstream technology for high-efficiency back-contact solar cells due to its excellent interface passivation effect and carrier transport characteristics.

[0024] In related technologies, back-contact batteries suffer from low photogenerated carrier separation and transport efficiency, high recombination losses, and a tendency to become unbalanced in the transport process. Specifically, firstly, existing technologies all employ fixed P / N region widths and uniform doping concentrations, failing to consider the differences in electron and hole mobility. This easily leads to problems such as high hole transport resistance in the P region and increased electron recombination probability in the N region, resulting in a carrier collection efficiency of only 91.2%. Secondly, the P / N region width is not optimized in conjunction with the doping concentration, making it impossible to adapt to the target doping range. Even with increased P region doping concentration, the improvement in hole transport efficiency is limited, hindering the release of the battery's performance potential. Thirdly, TBC batteries lack reasonable path thresholds in the long-path region. The fixed structure causes holes to reach the electrode much faster than electrons, resulting in a recombination probability of 1.85% and a series resistance as high as 22.8 mΩ, significantly exacerbating losses. Fourth, the existing narrow linewidth printing process has poor adaptability and cannot stably produce fine grids below 15μm. Furthermore, it does not match the width variation of the P / N region, resulting in a printing yield of only 96.5%. The contact resistance between the fine grid and the P region is too high, ultimately leading to the inability of the overall performance and mass production stability of the battery to meet the development needs of high-efficiency photovoltaic cells.

[0025] Please refer to Figures 1 to 4 , Figure 1 This is a schematic diagram of the fine grid structure distribution of a back contact battery according to an embodiment of this application. Figure 2 This is a schematic cross-sectional view of the P-type doped region of a back-contact battery according to an embodiment of this application. Figure 3 This is a schematic cross-sectional view of the N-type doped region of a back-contact battery according to an embodiment of this application. Figure 4 This is a schematic diagram of a busbar structure and a fine grid structure provided in an embodiment of this application.

[0026] This application provides a back contact battery 100 to solve the technical problems of low photogenerated carrier separation and transport efficiency, large recombination loss, and easy imbalance in the transport process in related technologies.

[0027] The back contact battery 100 includes a carrier substrate 10, a polycrystalline silicon layer 20, and an electrode layer. The polycrystalline silicon layer 20 is disposed on one side of the carrier substrate 10. The side of the polycrystalline silicon layer 20 facing away from the carrier substrate 10 includes P-type doped regions 21 and N-type doped regions 23, which are arranged in an interdigitated pattern. The doping concentration of the P-type doped regions 21 ranges from 2 × 10⁻⁶. 19 cm -3 -3×10 19 cm -3 The width of the P-type doped region 21 ranges from 400 μm to 440 μm, and the doping concentration of the N-type doped region 23 ranges from 5 × 10⁻⁶. 20 cm -3 -6×1020 cm -3 The width of the N-type doped region 23 ranges from 330 μm to 370 μm. The electrode layer includes a plurality of fine gate structures 31, which are disposed on the P-type doped region 21 and the N-type doped region 23. Each fine gate structure 31 includes at least one fine gate electrode 311. When the length of the fine gate electrode 311 is greater than a preset threshold, there are at least two fine gate electrodes 311 in one fine gate structure 31, and the at least two fine gate electrodes 311 are spaced apart. When the length of the fine gate electrode 311 is less than the preset threshold, there is only one fine gate electrode 311 in one fine gate structure 31. The preset threshold ranges from 3 mm to 5 mm.

[0028] It should be noted that the differentiated design of the fine grid structure 31 can be provided on the same back contact battery 100 or on back contact batteries 100 with different designs. In other words, in this embodiment, due to the process differences in the edge regions, the fine grid structure 31 in the middle region of the back contact battery 100 includes one fine grid electrode 311, and the fine grid structure 31 in the edge regions includes two fine grid electrodes 311. In other embodiments, the back contact battery 100 may also include one or two fine grid electrodes 311 in its overall fine grid structure 31 due to different designs of the number of main grids. All of the above are embodiments of this application and should not be construed as limiting this application.

[0029] The back contact battery 100 includes a support substrate 10, a polycrystalline silicon layer 20, and an electrode layer. The support substrate 10 generates photogenerated carriers, the polycrystalline silicon layer 20 realizes the separation and directional transport of carriers, and the electrode layer completes the efficient collection and external export of carriers, thereby realizing the basic functions of the back contact battery 100.

[0030] The supporting substrate 10 is the core support and carrier generation unit of the back contact battery 100. Specifically, the supporting substrate 10 serves as the generation region for photogenerated carriers (electron-hole pairs), providing the foundation for the photoelectric conversion of the battery. At the same time, the supporting substrate 10 provides physical support for the polycrystalline silicon layer 20 and the electrode layer of the entire back contact battery 100, and is the basic substrate of the back contact battery 100.

[0031] The electrical properties of the silicon material in the supporting substrate 10 directly determine the generation efficiency, lifetime, and transport capacity of photogenerated carriers. Optionally, in this embodiment, the supporting substrate 10 is an n-type single-crystal silicon wafer, and the thickness of the supporting substrate 10 is 135 μm and the resistivity is 5 Ω. cm, carrier lifetime ≥2.05ms.

[0032] The polycrystalline silicon layer 20 is the core functional layer of the back contact battery 100. The polycrystalline silicon layer 20 is disposed on the back side of the support substrate 10. In this embodiment, the polycrystalline silicon layer 20 is prepared by low-pressure chemical vapor deposition (LPCVD). Optionally, the thickness of the polycrystalline silicon layer 20 is 300 nm.

[0033] The polycrystalline silicon layer 20 is divided into two regions, P-type doped region 21 and N-type doped region 23, on the side opposite to the supporting substrate 10, which simultaneously has the dual functions of surface passivation and carrier transport.

[0034] The P-type doped region 21 and the N-type doped region 23 are arranged in an interdigitated pattern. This arrangement maximizes the contact area between the P-type doped region 21 and the N-type doped region 23, improves the carrier separation efficiency, and shortens the carrier transport path.

[0035] The P-type doped region 21 can capture and transport photogenerated holes, and directionally conduct the holes to the electrode layer; the N-type doped region 23 can capture and transport photogenerated electrons, and directionally conduct the electrons to the electrode layer.

[0036] In related technologies, the back contact battery 100 adopts a design with a fixed P / N region width and uniform doping concentration, without considering the difference in carrier mobility between the P and N regions (electron mobility ≥ 1400 cm⁻¹). 2 / (V s), hole mobility ≥450cm 2 / (V Actual tests show that when the P-region doping concentration is below 2×10⁻⁶, 19 cm -3 The N-region doping concentration is higher than 5 × 10⁻⁶. 20 cm -3 When the widths of the P-region and N-region are fixed (e.g., 380 μm for the P-region and 320 μm for the N-region), the hole transport resistance in the P-region increases, the electron recombination probability in the N-region increases, and the overall carrier collection efficiency is low.

[0037] Understandably, for the p-type doped region 21, the hole mobility is low (≥450 cm⁻¹). 2 / (V The transport resistance is high, requiring adjustments to the concentration to increase mobility and adjustments to the width to expand the transport region to offset this disadvantage. Specifically, the doping concentration range of the P-type doped region 21 is 2 × 10⁻⁶. 19 cm -3 -3×10 19 cm -3The width of the P-type doped region 21 ranges from 400 μm to 440 μm. The width of the P-type doped region 21 is the lateral width of the interdigitated arrangement, that is, the dimension perpendicular to the extension direction of the fine gate electrode 311.

[0038] The lower limit of the doping concentration of the P-type doped region 21 is 2 × 10⁻⁶. 19 cm -3 This ensures that the P-type doped region 21 has sufficient acceptor impurities (boron atoms) to form a stable hole conduction channel, preventing insufficient hole carrier concentration due to low concentration and conduction interruption during transport. Simultaneously, it ensures that the contact barrier between the doped region and the polysilicon layer 20 is sufficiently low, allowing holes to smoothly enter the P-type doped region 21 from the substrate 10, reducing interfacial transport resistance. The upper limit of the doping concentration of the P-type doped region 21 is 3 × 10⁻⁶. 19 cm -3 To avoid exacerbating lattice distortion due to excessive doping concentration, too many boron atoms will destroy the integrity of the silicon lattice, forming a large number of recombination centers, causing holes to collide and recombine with lattice defects during transport. At the same time, excessively high concentration will make the resistivity of the P-type doped region 21 too low, resulting in an excessively strong ohmic contact with the electrode layer, which will increase the series resistance.

[0039] The doping concentration range of the P-type doped region 21 is 2 × 10⁻⁶. 19 cm -3 -3×10 19 cm -3 This approach ensures an effective increase in hole mobility without causing significant lattice distortion, representing the optimal balance between mobility and recombination loss. Optionally, the doping concentration of the p-type doped region 21 can be 2 × 10⁻⁶. 19 cm -3 or 2.1×10 19 cm -3 or 2.2×10 19 cm -3 or 2.3×10 19 cm -3 or 2.4×10 19 cm -3 or 2.5×10 19 cm -3 or 2.6×10 19 cm -3 or 2.7×10 19 cm -3 or 2.8×10 19 cm -3 or 2.9×10 19 cm -3 or 3×10 19 cm-3 or at 2×10 19 cm -3 -3×10 19 cm -3 Other values ​​within this range are not limited in this application.

[0040] The lower limit of the width of the P-type doped region 21 is 400 μm, providing sufficient carrier capture area to accommodate the photogenerated carrier generation of the large-size back contact cell 100. This avoids insufficient hole capture due to excessively narrow width, preventing a large number of photogenerated holes from being captured by the P-type doped region 21 and ultimately resulting in recombination losses in the silicon substrate. Simultaneously, it ensures sufficient contact length between the fine gate electrode 311 and the P-type doped region 21, reducing the contact resistance between the electrode and the doped region. The upper limit of the width of the P-type doped region 21 is 440 μm, preventing excessively wide widths from causing excessively long hole transport paths. Increased transport distance within the width of the P-type doped region 21 leads to a higher recombination probability. Furthermore, an excessively wide P-type doped region 21 would compress the arrangement space of the N-type doped region 23, resulting in an overall P / N region imbalance in the back contact cell 100 and a mismatch in electron and hole collection efficiency.

[0041] The width of the P-type doped region 21 ranges from 400 μm to 440 μm, ensuring sufficient capture area while controlling the transport path of holes within the doped region within a reasonable range. Optionally, the width of the P-type doped region 21 can be 400 μm, 405 μm, 410 μm, 415 μm, 420 μm, 425 μm, 430 μm, 435 μm, 440 μm, or other values ​​within the range of 400 μm to 440 μm; this application does not impose any limitations on this.

[0042] Understandably, for the N-type doped region 23, the electron mobility is high (≥1400 cm⁻¹). 2 / (V The N-type doped region 23 has low transport resistance, and increasing the concentration can reduce the recombination probability, while reducing the width can improve space utilization. Specifically, the doping concentration range of the N-type doped region 23 is 5 × 10⁻⁶. 20 cm -3 -6×10 20 cm -3 The width of the N-type doped region 23 ranges from 330 μm to 370 μm. The width of the N-type doped region 23 is the lateral width of the interdigitated arrangement, that is, the dimension perpendicular to the extension direction of the fine gate electrode 311.

[0043] The lower limit of doping in the N-type doped region 23 is 5 × 10⁻⁶. 20 cm -3This ensures that the N-type doped region 23 has sufficient donor impurities (phosphorus atoms) to form a high-density, low-resistance electronic conduction channel, allowing photogenerated electrons to be rapidly injected from the silicon substrate and directionally conducted to the electrode layer. Simultaneously, the high concentration significantly reduces the intrinsic and interfacial recombination probabilities of the N-type doped region 23. The upper limit of the doping concentration of the N-type doped region 23 is 6 × 10⁻⁶. 20 cm -3 To avoid phosphorus atom clusters and slight lattice distortions caused by high concentrations, if the concentration exceeds 6 × 10⁻⁶... 20 cm -3 Excessive phosphorus atoms will form clusters in the silicon lattice, becoming electron recombination centers, which will reduce transport efficiency. At the same time, excessively high concentrations will cause abnormal contact barriers between the N-type doped region 23 and the polycrystalline silicon layer 20, increasing the carrier interface transport resistance.

[0044] The doping concentration range of the N-type doped region 23 is 5 × 10⁻⁶. 20 cm -3 -6×10 20 cm -3 This concentration range represents the optimal balance between electron recombination loss and conductive channel density. Optionally, the doping concentration of the N-type doped region 23 can be 5 × 10⁻⁶. 20 cm -3 or 5.1×10 20 cm -3 5.2×10 20 cm -3 or 5.3×10 20 cm -3 or 5.4×10 20 cm -3 or 5.5×10 20 cm -3 or 5.6×10 20 cm -3 or 5.7×10 20 cm -3 or 5.8×10 20 cm -3 or 5.9×10 20 cm -3 or 6×10 20 cm -3 or in 5×10 20 cm -3 -6×10 20 cm -3 Other values ​​within this range are not limited in this application.

[0045] The lower limit of the width of the N-type doped region 23 is 330 μm to ensure that the N-type doped region 23 has sufficient electron capture area to accommodate the amount of photogenerated electrons generated by the large-size back contact battery 100. This avoids insufficient electron capture due to excessive width, preventing some photogenerated electrons from being captured by the N-type doped region 23 and recombinating in the carrier substrate 10. At the same time, it ensures that the fine grid electrode 311 and the N-type doped region 23 have sufficient contact area, reducing the contact resistance between the electrode and the doped region. The upper limit of the width of the N-type doped region 23 is 370 μm to avoid excessive width leading to a longer lateral electron transport path. Even with high electron mobility, an excessively long transport path will still slightly increase the recombination probability. Furthermore, an excessively wide N-type doped region 23 will squeeze the arrangement space of the P-type doped region 21, resulting in insufficient width of the P-type doped region 21, a significant decrease in hole transport efficiency, and ultimately, an imbalance in the overall carrier collection of the battery.

[0046] The width of the N-type doped region 23 ranges from 330 μm to 370 μm. This width range controls the maximum lateral transport distance of electrons within the N-type doped region 23 to within 200 μm. The time for electrons to reach the fine gate electrode 311 is extremely short, and recombination loss is negligible. Simultaneously, a reasonable width is reserved for the P-type doped region 21 to ensure the requirements for hole transport. Optionally, the width of the N-type doped region 23 can be 330 μm, 335 μm, 340 μm, 345 μm, 350 μm, 355 μm, 360 μm, 365 μm, 370 μm, or other values ​​within the range of 330 μm to 370 μm. This application does not impose any limitations on this.

[0047] The electrode layer is disposed on the surface of the P-type doped region 21 and the N-type doped region 23 of the polycrystalline silicon layer 20, and is in direct contact with the doped regions. The electrode layer can capture directionally transported charge carriers from the P-type doped region 21 and the N-type doped region 23, and guide the charge carriers to the circuit system outside the back contact cell 100.

[0048] It should be noted that in this embodiment, the electrode layer does not include the main grid electrode, that is, the back contact battery 100 is an OBB design, eliminating the main grid electrode of a traditional battery and consisting only of multiple independent fine grid structures 31, which reduces the amount of silver paste used and avoids light-shielding loss from the main grid. Optionally, in other embodiments, the electrode layer may also include the main grid electrode. All of the above are embodiments of this application, and this application does not limit them.

[0049] The electrode layer is composed of a plurality of fine gate structures 31, each fine gate structure 31 being an independent electrode unit, and each fine gate structure 31 including at least one fine gate electrode 311.

[0050] When the length of the fine gate electrode 311 is greater than a preset threshold, the number of fine gate electrodes 311 in one fine gate structure 31 is at least two, and the at least two fine gate electrodes 311 are spaced apart, that is, at least two fine gate electrodes 311 are arranged in parallel with intervals. The use of two fine gate electrodes 311 in one fine gate structure 31 in this application is for illustrative purposes only and should not be construed as a limitation of this application. With two fine gate electrodes 311 in one fine gate structure 31, the dual-line fine gate is equivalent to adding a carrier collection node in a long path, splitting the original long transport path into multiple short paths, significantly shortening the actual transport distance of the carriers, and reducing recombination losses during transport.

[0051] When the length of the fine gate electrode 311 is less than a preset threshold, only one fine gate electrode 311 (single-line fine gate) is set in a single fine gate structure 31. The carrier transport distance in this region is short and the recombination probability is low. A single-line fine gate can achieve a carrier collection efficiency of more than 99%, without the need for additional encryption, thus avoiding the ineffective consumption of silver paste.

[0052] The recombination probability of charge carriers is positively correlated with the transport path length. The longer the path, the higher the probability of charge carriers colliding and recombinating with the lattice and impurities during transport. By dividing the long / short path regions by a preset threshold, the long path region is encrypted with a double-line fine grid to shorten the actual transport distance of charge carriers, while the short path region is encrypted with a single-line fine grid. This controls the amount of silver paste used while ensuring collection efficiency, achieving the dual optimization of performance and cost.

[0053] In the back contact battery 100 provided in this application, the polycrystalline silicon layer 20 is disposed on one side of the supporting substrate 10. The side of the polycrystalline silicon layer 20 away from the supporting substrate 10 includes a P-type doped region 21 and an N-type doped region 23. The P-type doped region 21 and the N-type doped region 23 are arranged in an interdigitated staggered pattern. The doping concentration range of the P-type doped region 21 is 2 × 10⁻⁶. 19 cm -3 -3×10 19 cm -3 The width of the P-type doped region 21 ranges from 400 μm to 440 μm, and the doping concentration of the N-type doped region 23 ranges from 5 × 10⁻⁶. 20 cm -3 -6×10 20 cm -3The width of the N-type doped region 23 ranges from 330 μm to 370 μm. The electrode layer includes multiple fine gate structures 31 disposed on the P-type doped region 21 and the N-type doped region 23. Each fine gate structure 31 includes at least one fine gate electrode 311. When the length of the fine gate electrode 311 is greater than a preset threshold, there are at least two fine gate electrodes 311 in one fine gate structure 31, and these at least two fine gate electrodes 311 are spaced apart. When the length of the fine gate electrode 311 is less than the preset threshold, there is only one fine gate electrode 311 in one fine gate structure 31. The preset threshold ranges from 3 mm to 5 mm. The P-type doped region 21 and the N-type doped region 23, combined with precisely defined doping concentrations and width ranges, can efficiently achieve rapid separation and directional transport of photogenerated carriers, effectively reducing recombination losses during carrier conduction and ensuring the overall balance of electron and hole transport processes. Furthermore, the differentiated fine grid structure 31 based on a preset threshold of 3mm-5mm can be specifically matched to the carrier collection requirements of different transport paths: in long path regions, multiple spaced fine grid electrodes 311 are used, significantly shortening the transport distance of carriers to the electrodes and reducing recombination losses over long distances; in short path regions, a single fine grid electrode 311 is used, ensuring carrier collection capability while reducing electrode coverage and contact losses. The overall design of the back contact battery 100 significantly improves carrier collection efficiency, reduces internal series resistance, and ultimately achieves comprehensive optimization of photoelectric conversion performance. Simultaneously, the structural parameters are compatible with mature semiconductor fabrication processes, possessing good mass production feasibility.

[0054] In one embodiment, the back contact battery 100 further includes a tunneling oxide layer 50, which is disposed between the polycrystalline silicon layer 20 and the carrier substrate 10. The tunneling oxide layer 50 and the polycrystalline silicon layer 20 form a passivation stack, which can effectively passivate the dangling bonds on the back of the silicon wafer, reduce the carrier recombination rate on the surface of the carrier substrate 10, and significantly improve the effective lifetime of the carriers.

[0055] Optionally, in this embodiment, the tunneling oxide layer 50 is prepared by a thermal oxidation process, and the thickness of the tunneling oxide layer 50 is 1.5 nm.

[0056] Furthermore, in one embodiment, an isolation region 22 is provided between the P-type doped region 21 and the N-type doped region 23. The isolation region 22 can prevent carrier recombination caused by direct contact between the P-type doped region 21 and the N-type doped region 23. The isolation region 22 is an insulating layer and has no carrier transport capability.

[0057] The width of the isolation region 22 is in the range of 55μm-65μm. Optionally, the width of the isolation region 22 can be 55μm, 56μm, 57μm, 58μm, 59μm, 60μm, 61μm, 62μm, 63μm, 64μm, 65μm, or other values ​​within the range of 55μm-65μm. This application does not limit this value.

[0058] In one embodiment, the width of the P-type doped region 21 is positively correlated with the doping concentration of the P-type doped region 21, wherein the doping concentration range of the P-type doped region 21 is 2 × 10⁻⁶. 19 cm -3 -2.5×10 19 cm -3 When the width of the P-type doped region 21 is in the range of 400 μm-420 μm, and the doping concentration of the P-type doped region 21 is in the range of 2.5 × 10⁻⁶, the width of the P-type doped region 21 is in the range of 400 μm-420 μm. 19 cm -3 -3.0×10 19 cm -3 At that time, the width of the P-type doped region 21 ranges from 420μm to 440μm.

[0059] The doping concentration of the P-type doped region 21 directly determines the hole transport capability: the higher the boron doping concentration, the higher the hole carrier concentration, the stronger the mobility, and the lower the transport resistance of the P-type doped region 21, enabling it to support a longer hole transport path; conversely, at low concentrations, the hole transport capability is limited, and the transport path length must be controlled, otherwise recombination loss will occur before the holes reach the electrode. The width of the P-type doped region 21 directly determines the hole capture amount and transport path: the larger the width, the larger the photogenerated hole capture area of ​​the P-type doped region 21, and the more carriers can be collected, but the longer the hole transport path from the edge of the doped region to the electrode, and the higher the requirements for hole transport capability.

[0060] Traditional fixed-parameter designs have an inherent performance contradiction: with a fixed width, the hole transport capacity is insufficient at low concentrations, and a wide width will lead to excessively long transport paths and a sharp increase in recombination losses; at high concentrations, the hole transport capacity is abundant, and a narrow width will lead to insufficient carrier capture and parameter redundancy.

[0061] The width of the P-type doped region 21 in this application is positively correlated with the doping concentration of the P-type doped region 21. This positive correlation design achieves a precise fit between the two: the low doping concentration of the P-type doped region 21 matches the narrow width, strictly controlling the hole transport path length and avoiding recombination caused by excessive transport resistance; the high doping concentration of the P-type doped region 21 matches the wide width, using the enhanced transport capacity to completely cover the longer transport path, with no wasted capacity.

[0062] In one embodiment, the width of the N-type doped region 23 is negatively correlated with the doping concentration of the N-type doped region 23, wherein the doping concentration of the N-type doped region 23 is in the range of 5.0 × 10⁻⁶. 20 cm -3 -5.5×10 20 cm -3 When the width of the N-type doped region 23 is in the range of 350 μm-370 μm, and the doping concentration of the N-type doped region 23 is in the range of 5.5 × 10⁻⁶, the width of the N-type doped region 23 is in the range of 350 μm-370 μm. 20 cm -3 -6×10 20 cm -3 At that time, the width of the N-type doped region 23 ranges from 330μm to 350μm.

[0063] The doping concentration of the N-type doped region 23 directly determines the low-loss electron transport capability: the higher the phosphorus doping concentration, the higher the electron carrier concentration and the denser the conductive channel of the N-type doped region 23, resulting in a stronger ability to suppress electron recombination. Even within a narrower width, complete capture and efficient transport of photogenerated electrons can be achieved. The width of the N-type doped region 23 directly determines the electron capture amount and the battery space allocation: a larger width results in a larger electron capture area, but it occupies more arrangement space on the back side of the battery, compressing the width of the P-type doped region 21 and lengthening the lateral electron transport path, causing unnecessary slight recombination losses.

[0064] The width of the N-type doped region 23 in this application is negatively correlated with the doping concentration of the N-type doped region 23. A wide width is matched with a low doping concentration, and the sufficient capture area is used to make up for the insufficient conductivity margin at medium and low concentrations, so as to avoid incomplete electron capture. A narrow width is matched with a high doping concentration, and the strong transport and anti-recombination ability brought by the dense conductive channel completely replaces the area gain of the wide width. There is no loss of electron collection efficiency and the redundant transport loss brought by the wide width is avoided.

[0065] The core function of the p-type doped region 21 is to capture and transport photogenerated holes, and the hole mobility (≥450 cm⁻¹) is crucial. 2 / (V S) constitutes only 1 / 3 of electrons, making it a critical weakness in battery carrier collection. The doping concentration range of the p-type doped region 21 is 2 × 10⁻⁶. 19 cm -3 -3×10 19 cm -3The width of the P-type doped region 21 ranges from 400 μm to 440 μm. Combined with a positive correlation matching rule, its essence is to precisely align the hole transport capacity (determined by the doping concentration) with the transport requirement (determined by the width), completely avoiding parameter mismatch losses. The core function of the N-type doped region 23 is to capture and transport photogenerated electrons, which themselves possess extremely high mobility (≥450 cm⁻¹). 2 / (V s), is a natural advantage for carrier transport. The doping concentration range of the N-type doped region 23 is 5 × 10 20 cm -3 -6×10 20 cm -3 The width of the N-type doped region 23 ranges from 330μm to 370μm. Combined with the negative correlation matching rule, the essence is to precisely coordinate the low-loss electron transport capability with the space utilization rate of the back side of the battery, so as to achieve optimal space allocation without sacrificing electron collection efficiency.

[0066] Understandably, the P-type doped region 21 and the N-type doped region 23 arranged in an interdigitated pattern on the back contact battery 100 have a fixed total width, which naturally leads to competition for space. The N-type doped region 23 narrows its width at high concentration, which just provides sufficient space for the P-type doped region 21 to widen its width at high concentration. The two are perfectly matched and do not squeeze each other, which solves the problem of unbalanced P / N region space distribution in traditional designs from the root.

[0067] Understandably, the positive correlation design of the P-type doped region 21 makes up for the shortcomings of hole transport, while the negative correlation design of the N-type doped region 23 stabilizes the advantages of electron transport. Ultimately, the transport efficiency of electrons and holes and their arrival time at the electrode are completely aligned, reducing the difference in collection efficiency between the two and solving the problems of carrier accumulation and high recombination loss caused by the fast electron transport and slow hole transport in traditional designs.

[0068] In one embodiment, the preset threshold is positively correlated with the doping concentration of the P-type doped region 21, and the doping concentration of the P-type doped region 21 is in the range of 2 × 10⁻⁶. 19 cm -3 -2.5×10 19 cm -3 When the preset threshold ranges from 3.0 mm to 4.0 mm, and the doping concentration of the P-type doped region 21 ranges from 2.5 × 10⁻⁶, the threshold value is within the range of 3.0 mm to 4.0 mm. 19 cm -3 -3.0×10 19 cm -3 When the preset threshold is in the range of 4.0mm-5.0mm.

[0069] Understandably, the preset threshold is the encryption threshold of the fine gate structure 31. When the length of the fine gate electrode 311 exceeds this threshold, the recombination probability of long-distance carrier transport will increase significantly, requiring the use of double-line spaced fine gate encryption to split the long path into multiple short paths to reduce losses; when it is below this threshold, the single-line fine gate electrode 311 can achieve efficient collection without additional encryption.

[0070] Understandably, the boron doping concentration of the P-type doped region 21 directly determines the hole carrier concentration, mobility, and transport resistance. The higher the doping concentration of the P-type doped region 21, the stronger the hole mobility and the better the anti-recombination ability over long distances. Without significant losses, it can withstand a longer maximum effective transport path, eliminating the need for premature gate densification. The preset threshold can be increased synchronously, and the two naturally form a positive correlation.

[0071] In one embodiment, the preset threshold is negatively correlated with the width of the P-type doped region 21. When the width of the P-type doped region 21 is 400μm-420μm, the preset threshold is 4.0mm-5.0mm. When the width of the P-type doped region 21 is 420μm-440μm, the preset threshold is 3.0mm-4.0mm.

[0072] Understandably, the wider the P-type doped region 21, the longer the lateral hole transport distance, the higher the amount of lossless path already occupied, and the shorter the tolerable length of the fine gate electrode 311. This requires a lower preset threshold and earlier initiation of dual-line fine gate densification, avoiding recombination loss due to exceeding the total path limit. Conversely, the narrower the P-type doped region 21, the shorter the lateral hole transport distance, the lower the amount of lossless path already occupied, and the longer the tolerable length of the longitudinal fine gate electrode 311. This allows for a higher preset threshold, delaying dual-line fine gate densification and reducing silver paste usage without performance loss.

[0073] In one embodiment, the linewidth of the fine gate electrode 311 ranges from 13 μm to 17 μm.

[0074] 13μm is the minimum critical linewidth for steel plate screen printing in photovoltaic mass production lines, which can stably achieve continuous, unbroken grids and uniform linewidth. If the linewidth of the fine grid electrode 311 is less than 13μm, three major problems will occur: First, the printing process yield will drop sharply, as narrow linewidths are prone to insufficient silver paste transfer, broken grids, and jagged edges; second, conductivity will deteriorate, as excessively narrow linewidths will cause the sheet resistance of the fine grid to soar, and the series resistance loss of charge carriers conducting along the longitudinal direction of the fine grid will increase significantly, offsetting the performance gains brought by double-line densification; third, structural defects will occur after sintering, as silver paste with excessively narrow linewidths will have insufficient density after sintering, easily leading to porosity and high resistance problems, and the contact resistance between the fine grid and the doped region will also increase significantly.

[0075] 17μm is the maximum critical linewidth to ensure conductivity without bottlenecks and additional recombination losses. If the linewidth of the fine gate electrode 311 exceeds 17μm, two major problems will arise: First, the cost of silver paste will become uncontrollable. For every 1μm increase in linewidth, the amount of silver paste used per cell increases by about 1.5%. A linewidth greater than 17μm will completely offset the silver paste saving advantage brought by the differentiated fine gate design. Second, surface recombination losses will increase. An excessively wide linewidth will excessively occupy the surface area of ​​the P / N doped region, squeeze the proportion of the intrinsic passivation region, and increase the probability of carrier surface recombination. At the same time, the silver paste spread of an excessively wide linewidth is prone to cross the isolation region 22, causing a short circuit risk in the P / N region.

[0076] The linewidth of the fine gate electrode 311 ranges from 13μm to 17μm, with 15μm being the optimal golden linewidth, achieving a printing yield of ≥98.5% and a contact resistance between the fine gate and the doped region of ≤7.3mΩ. cm 2 This also achieves the silver paste saving effect of narrow linewidth. Optionally, the linewidth of the fine gate electrode 311 can be 13μm, 14μm, 15μm, 16μm, 17μm, or other values ​​within the range of 13μm-17μm, and this application does not limit it.

[0077] In one embodiment, when the fine gate structure 31 includes a plurality of fine gate electrodes 311, the line spacing between adjacent fine gate electrodes 311 within the same fine gate structure 31 ranges from 55μm to 65μm.

[0078] 55μm is the minimum critical spacing required for two parallel fine gate electrodes 311 to stably achieve silver paste spreading and adhesion in mass production screen printing. If the spacing is less than 55μm, the natural spreading of silver paste during printing will directly cause the two fine gate electrodes 311 to stick together and short-circuit, completely losing the design significance of dual-line densification and current shunting. At the same time, it will cause a large number of pattern defects and a significant decrease in mass production yield. In addition, an excessively narrow spacing will cause the current to converge on the two fine gate electrodes 311, resulting in excessively high local current density and additional series resistance loss.

[0079] 65 μm is the maximum critical spacing for matching the hole diffusion length and achieving loss reduction through dual-line densification. In this scheme, the hole diffusion length of the P-type doped region 21 is approximately 100 μm. The maximum transport distance for carriers to be effectively collected needs to be controlled within half of the diffusion length (≤50 μm). The maximum transport distance for carriers in the middle region of the two fine gates corresponding to a 65 μm spacing is only 32.5 μm, which is well within the effective collection range. If the spacing exceeds 65 μm, the transport distance for carriers in the middle region exceeds the safe range, and recombination occurs before reaching the fine gate. The loss reduction effect of dual-line densification is completely ineffective, and there is no significant difference in performance compared to the single-line fine gate electrode 311.

[0080] The line spacing between adjacent fine gate electrodes 311 within the same fine gate structure 31 ranges from 55μm to 65μm. 60μm within this range is considered the optimal spacing, completely avoiding the risk of short circuits due to printing adhesion and controlling the maximum carrier transport distance to within 30μm. This shortens the transport distance compared to a single-line fine gate electrode 311, reducing the probability of carrier recombination in long-path regions and maximizing the encryption effect. Optionally, the line spacing between adjacent fine gate electrodes 311 within the same fine gate structure 31 can be 55μm, 56μm, 57μm, 58μm, 59μm, 60μm, 61μm, 62μm, 63μm, 64μm, 65μm, or other values ​​within the 55μm-65μm range; this application does not impose any limitations on this.

[0081] In one embodiment, the electrode layer includes a plurality of bus structures 40 disposed on the P-type doped region 21 and the N-type doped region 23, and each end of a bus structure 40 is connected to a fine gate structure 31, wherein the overlap length between the fine gate structure 31 and the bus structure 40 is in the range of 15μm-25μm.

[0082] In this embodiment, the bus structure 40 is a bus pad. The bus structure 40 serves as the core component for the carrier bus of the electrode layer. It is located on the surface of the P-type doped region 21 and the N-type doped region 23. Each of the bus pads is connected to the fine gate structure 31 at both ends, and is a key hub for connecting and dispersing the fine gate electrodes 311.

[0083] The fine grid structure 31 consists of dispersed parallel lines, which can only capture and initially conduct local carriers on the surface of the doped region. The busbar structure 40 connects multiple fine grid structures 31, and then concentrates and directionally discharges the carriers collected by each fine grid structure 31. This avoids the increase in series resistance caused by the dispersion of carrier transmission in the dispersed structures, and greatly improves the overall conductivity of the electrode layer. It is the core structure of the electrode layer of the back contact battery 100 from local capture to overall discharge.

[0084] The busbar structure 40 is only located on the surface of the P-type doped region 21 and the N-type doped region 23, and does not cross the isolation region 22 between the P-type doped region 21 and the N-type doped region 23. It is fully adapted to the arrangement characteristics of the interdigitated P / N doped regions, and structurally avoids the risk of P / N short circuit caused by crossing regions, thus ensuring the basic function of carrier separation in the battery.

[0085] The overlap length of the fine grid structure 31 and the busbar structure 40 ranges from 15μm to 25μm. The overlap length of the fine grid structure 31 and the busbar structure 40 refers to the overlapping size of their contact and connection areas.

[0086] The lower limit of the overlap length between the fine gate structure 31 and the busbar structure 40 is 15 μm. 15 μm is the minimum overlap length to achieve effective low-resistance contact between the fine gate structure 31 and the busbar structure 40. If the overlap length is less than 15 μm, it is easy to cause an increase in contact resistance. If the overlap length is too short, the actual conductive contact area between the two will be insufficient. The contact resistance when the charge carriers are conducted from the fine gate structure 31 to the busbar structure 40 will increase sharply, and even contact breaks may occur, resulting in interruption of charge carrier transmission and directly reducing the overall collection efficiency of the electrode layer.

[0087] The upper limit of the overlap length of the fine gate structure 31 and the bus structure 40 is 25 μm. 25 μm is the maximum overlap length that avoids silver paste waste and carrier recombination loss while ensuring conductivity stability. If the overlap length exceeds 25 μm, the amount of silver paste used in the overlap area of ​​the bus structure 40 and the fine gate structure 31 will increase synchronously for every 1 μm increase in the overlap length. An overlap length of more than 25 μm does not provide any conductivity gain and only causes ineffective consumption of silver paste, thus offsetting the cost control advantage brought by the differentiated fine gate design.

[0088] The overlap length between the fine gate structure 31 and the bus structure 40 ranges from 15μm to 25μm, with 20μm being the optimal golden overlap length, ensuring that the contact resistance between the fine gate structure 31 and the bus structure 40 is ≤7.3mΩ. cm 2 This design achieves lossless carrier conduction, keeps the amount of silver paste within an optimal range, occupies only a very small surface area in the doped region, and has no additional recombination losses. Optionally, the overlap length of the fine gate structure 31 and the bus structure 40 can be 15μm, 16μm, 17μm, 18μm, 19μm, 20μm, 21μm, 22μm, 23μm, 24μm, 25μm, or other values ​​within the range of 15μm-25μm. This application does not impose any limitations on this.

[0089] Please refer to the above as well. Figure 5 , Figure 5 This is a flowchart of a back contact battery preparation method provided in the embodiments of this application.

[0090] This application also provides a method for preparing a back contact battery 100. The preparation method is used to prepare the back contact battery 100. The preparation method includes steps S100, S200, S300 and S400. The detailed description of steps S100, S200, S300 and S400 is as follows.

[0091] S100: Provide a support substrate 10 and deposit the polysilicon layer 20 on the support substrate 10.

[0092] After providing the support substrate 10, the surface of the support substrate 10 is treated. The side of the support substrate 10 facing the light is texturized and an anti-reflection film is prepared. Texturing forms a pyramid-shaped micro / nano structure, increasing the number of light reflections and improving light absorption efficiency. The anti-reflection film is generally made of materials such as SiNx and Al2O3 to reduce the surface reflectivity of light. The side of the support substrate 10 that is attached to the polycrystalline silicon layer 20 is double-sided polished to ensure surface flatness, ensure tight adhesion with the subsequent polycrystalline silicon layer 20, and reduce interlayer contact resistance.

[0093] The formation of a tunneling oxide layer 50 on the support substrate 10 before depositing the polysilicon layer 20 on the support substrate 10, and then forming the polysilicon layer 20 on the tunneling oxide layer 50, should not be construed as a limitation of this application.

[0094] S200: A P-type doped region 21 and an N-type doped region 23 are formed on the polysilicon layer 20.

[0095] S300: The electrode layer is printed on the polysilicon layer 20, wherein the electrode layer includes a plurality of fine gate structures 31, the fine gate structures 31 are disposed on the P-type doped region 21 and the N-type doped region 23, the fine gate structure 31 includes at least one fine gate electrode 311, when the length of the fine gate electrode 311 is greater than a preset threshold, the number of fine gate electrodes 311 in one fine gate structure 31 is at least two, and the at least two fine gate electrodes 311 are spaced apart, when the length of the fine gate electrode 311 is less than the preset threshold, the number of fine gate electrodes 311 in one fine gate structure 31 is one, the preset threshold range is 3mm-5mm.

[0096] In this embodiment, the electrode layer is made of high-resolution conductive silver paste with a silver content of 7.2 wt% and a polyurethane resin as the binder phase. It has high conductivity, high adhesion and high printing resolution, which can realize the precise molding of narrow linewidth fine gates. In addition, it has low contact resistance with the P / N doped region of the polycrystalline silicon layer 20, ensuring efficient conduction of charge carriers.

[0097] Furthermore, in this embodiment, a steel plate screen with a measured linewidth of 11μm is used for screen printing. Unlike traditional PI screens, the steel plate screen has higher printing resolution and better wear resistance, and can stably prepare narrow linewidth fine grids of about 15μm with a printing yield of ≥98.5%. The printing process parameters are precisely controlled as follows: printing pressure 45N-50N, printing speed 450mm / s-500mm / s, squeegee angle 60°, and demolding distance 0.3mm, to ensure the linewidth uniformity, edge flatness, and adhesion to the doped area of ​​the fine grid.

[0098] S400: After pre-baking and sintering the electrode layer, it is encapsulated to form a back contact battery 100.

[0099] The printed electrode layer needs to undergo pre-baking and sintering to form a dense conductive electrode. The pre-baking temperature is 120℃, and the holding time is 60 minutes to remove organic solvents from the paste. The sintering parameters are: heating rate 15℃ / s, peak temperature 680℃~700℃, holding time 15 seconds, and cooling rate 5℃ / s. After sintering, the density of the fine grid structure 31 is ≥95%, and the contact resistance with the polycrystalline silicon layer 20 is ≤7.3mΩ. cm², ensuring conductivity and adhesion.

[0100] Encapsulation is performed by: interconnecting with 0.3mm copper solder strips (contact density 3.5 points / mm), laminating at 150℃ and 0.15MPa for 20 minutes to achieve encapsulation.

[0101] In the fabrication method provided in this application, a support substrate 10 is provided, and a polycrystalline silicon layer 20 is deposited on the support substrate 10. A P-type doped region 21 and an N-type doped region 23 are formed on the polycrystalline silicon layer 20. An electrode layer is printed on the polycrystalline silicon layer 20. The electrode layer includes a plurality of fine gate structures 31. The fine gate structures 31 are disposed on the P-type doped region 21 and the N-type doped region 23. Each fine gate structure 31 includes at least one fine gate electrode 311. When the length of the fine gate electrode 311 is greater than a preset threshold, the number of fine gate electrodes 311 in one fine gate structure 31 is at least two, and the at least two fine gate electrodes 311 are spaced apart. When the length of the fine gate electrode 311 is less than the preset threshold, the number of fine gate electrodes 311 in one fine gate structure 31 is one. The preset threshold ranges from 3 mm to 5 mm. After pre-baking and sintering the electrode layer, it is encapsulated to form a back contact battery 100. Based on the differentiated fine gate structure 31 with a preset threshold of 3mm-5mm, it can be specifically matched to the carrier collection requirements of different transport paths: in the long path region, multiple spaced fine gate electrodes 311 are used to significantly shorten the transport distance of carriers to the electrode and reduce the recombination loss of long-distance conduction; in the short path region, a single fine gate electrode 311 is used to reduce the electrode coverage ratio and contact loss while ensuring the carrier collection capability.

[0102] Please refer to the above as well. Figure 6 , Figure 6 This is a flowchart of step S200 in a back contact battery preparation method provided in this application.

[0103] In one embodiment, step S200, which forms the P-type doped region 21 and the N-type doped region 23 on the polysilicon layer 20, includes steps S210, S220 and S230. A detailed description of steps S210, S220 and S230 is as follows.

[0104] S210: A glass layer is provided on the polycrystalline silicon layer 20, and the glass layer is laser-etched according to the width range of the P-type doped region 21 and the N-type doped region 23, wherein the width range of the P-type doped region 21 is 400μm-440μm, and the width range of the N-type doped region 23 is 330μm-370μm.

[0105] A glass layer is fabricated on the polycrystalline silicon layer 20, serving as a masking template for doping. The glass layer is etched away using a laser at corresponding positions, with the width of the P-type doped region 21 being 400μm-440μm and the width of the N-type doped region 23 being 330μm-370μm, exposing the areas to be doped. The un-etched glass layer remains as a mask, preventing impurities from entering during subsequent diffusion, ultimately forming interdigitated P-type doped regions 21 and N-type doped regions 23, precisely controlling the width of both regions.

[0106] S220: Boron diffusion is performed according to the doping concentration range of the P-type doped region 21, wherein the doping concentration range of the P-type doped region 21 is 2 × 10⁻⁶. 19 cm -3 -3×10 19 cm -3 The flow rate of boron trichloride ranges from 2 sccm to 4 sccm, the ambient temperature ranges from 890℃ to 910℃, and the boron diffusion time ranges from 28 min to 32 min.

[0107] The P-type regions exposed by laser engraving are then subjected to boron (B) diffusion to form the hole-conducting P-type doped region 21. The flow rate of boron trichloride ranges from 2 sccm to 4 sccm, the ambient temperature ranges from 890℃ to 910℃, and the diffusion time ranges from 28 min to 32 min. Using these parameters, the concentration of the P-type doped region 21 is stably controlled at 2 × 10⁻⁶. 19 cm -3 -3×10 19 cm -3 This meets the concentration requirements for hole transport.

[0108] Optionally, the flow rate of boron trichloride can be 2 sccm, or 2.2 sccm, or 2.5 sccm, or 2.7 sccm, or 2.9 sccm, or 3.0 sccm, or 3.1 sccm, or 3.5 sccm, or 3.6 sccm, or 3.8 sccm, or 4 sccm, or other values ​​within the range of 2 sccm to 4 sccm; this application does not limit this. The ambient temperature can be 890℃, or 892℃, or 895℃, or 898℃, or 900℃, or 901℃, or 904℃, or 905℃, or 906℃, or 909℃, or 910℃, or other temperatures within the range of 890℃ to 910℃; this application does not limit this. The boron diffusion time can be 28 min, or 29 min, or 30 min, or 31 min, or 32 min, or other times within the range of 28 min to 32 min; this application does not limit this.

[0109] It should be noted that after boron diffusion, the doping concentration can be confirmed by SIMS testing (error ≤ ±5%) before annealing.

[0110] S230: Phosphorus diffusion is performed according to the doping concentration range of the N-type doped region 23, wherein the doping concentration range of the N-type doped region 23 is 5 × 10⁻⁶. 20 cm -3 -6×10 20 cm -3 The flow rate of phosphorus oxychloride ranges from 6 sccm to 9 sccm, the ambient temperature ranges from 840℃ to 860℃, and the phosphorus diffusion time ranges from 22 min to 26 min.

[0111] Phosphorus (P) diffusion was performed on the N-type regions exposed by laser engraving to form electronically conductive N-type doped regions. The phosphorus oxychloride flow rate ranged from 6 sccm to 9 sccm, the ambient temperature ranged from 840℃ to 860℃, and the diffusion time ranged from 22 min to 26 min. Using these parameters, the concentration of the N-type doped region 23 was stably controlled at 5 × 10⁻⁶. 20 cm -3 -6×10 20 cm -3 It meets the high concentration requirements for electron transport.

[0112] Optionally, the flow rate of phosphorus oxychloride can be 6 sccm, or 6.2 sccm, or 6.5 sccm, or 6.7 sccm, or 7 sccm, or 7.3 sccm, or 7.5 sccm, or 7.8 sccm, or 8 sccm, or 8.2 sccm, or 8.5 sccm, or 8.9 sccm, or 9 sccm, or other values ​​within the range of 6 sccm to 9 sccm. This application does not limit this. The ambient temperature can be 840℃, or 842℃, or 845℃, or 847℃, or 850℃, or 851℃, or 853℃, or 855℃, or 858℃, or 859℃, or 860℃, or other temperatures within the range of 840℃ to 860℃. This application does not limit this. The phosphorus diffusion time can be 22 min, 23 min, 24 min, 25 min, 26 min, or other times within the range of 22 min to 26 min, and this application does not limit it.

[0113] It should be noted that after phosphorus diffusion, the doping concentration can also be confirmed by SIMS testing (error ≤ ±5%) before annealing.

[0114] The following embodiments are provided to illustrate the structure and fabrication effect of the back contact battery described in this application, and should not be construed as limiting this application.

[0115] Experimental research design ideas With P-region doping concentration (2×10) 19 cm -3 2.5×10 19 cm -3 3×10 19 cm -3 P-region width (400μm, 420μm, 440μm), N-region doping concentration (5.0×10⁻⁶) 20 cm -3 5.5×10 20 cm -3 6×10 20 cm -3 The widths of the N region (330μm, 350μm, 370μm) are used as P / N region variable combinations, and the fine grid path thresholds L (3.0mm, 3.5mm, 4.0mm, 4.5mm, 5.0mm, 5.5mm) are used to form 3×3×3×3×6=486 theoretical combinations. Several key combinations (covering the intersection points of the gradients of each variable) are selected for physical experiments, and all combination data are completed by SentaurusTCAD simulation.

[0116] Core objective: Define the range of L where carrier collection efficiency is ≥99.5% under different P / N region parameters; A five-dimensional adaptation model of "P-region concentration - P-region width - N-region concentration - N-region width - L" is established to ensure maximum carrier collection. Experimental raw materials and equipment: Silicon wafer: 135μm thick n-type monocrystalline silicon wafer (resistivity 5Ω) cm, carrier lifetime 2.05ms, size 210mm×210mm). Paste: 7.2 wt% high-resolution conductive silver paste (BC special paste), polyurethane resin binder phase; Mesh: Steel plate mesh, actual wire width 11µm; Core equipment: BC production line mass production equipment, four-probe resistance meter (RM3000, accuracy ±0.01mΩ), secondary ion mass spectrometer (SIMS, model: IMS-6f, accuracy ±1×10⁻⁶). 17 cm -3 ), electronic balance (ME204E, accuracy ±0.1mg).

[0117] Experimental and comparative parameter design

[0118] Control group:

[0119] Experimental procedures (process parameters are the same for all groups, only the variables differ) Silicon wafer pretreatment: Double-sided polishing and texturing on the front side are both carried out in-situ processes; the back passivation layer is prepared by thermal oxidation to form a 1.5nm tunneling oxide layer; and a 300nm polycrystalline silicon layer is deposited by LPCVD.

[0120] Preparation of doped regions (core variable control steps): Laser engraving of etched glass layer (PSG / BSG): The engraving pattern is designed according to the width of each P / N zone group, and the width of the isolation zone is uniformly 60μm; Boron diffusion in the P-region: Adjust the Bcl3 source flux (2-4 sccm), temperature (890-910℃), and time (28-32 min) according to the target doping concentration. Confirm the doping concentration by SIMS testing (error ≤ ±5%), and then anneal. N-region phosphorus diffusion: Adjust the POCl3 source flow rate (6-9 sccm), temperature (840-860℃), and time (22-26 min) according to the target doping concentration. Confirm the doping concentration by SIMS test (error ≤ ±5%), and then anneal. Fine grid pattern preparation: Printing parameters: 11µm steel stencil, printing pressure 50N, printing speed 500mm / s, squeegee angle 60°, demolding distance 0.3mm; differentiated layout is implemented according to each group L, and single-line fine grids (line width 15.0±2μm, spacing 1.0mm) are printed in the remaining areas, with the overlap length between the fine grids and the P / N busbar area being 20±0.5μm.

[0121] Electrode forming and packaging: Pre-baking: 120℃, 60min; Sintering: heating rate 15℃ / s, peak temperature of 690℃ for 15s, cooling rate 5℃ / s; Encapsulation: 0.3mm copper solder strip interconnect (contact density 3.5 points / mm), lamination at 150℃ and 0.15MPa for 20 minutes; Sample testing: 30 samples per group, testing key indicators such as carrier collection efficiency, series resistance, and PCE, and taking the average value.

[0122] Experimental test results (average value of 30 samples)

[0123] Experimental conclusions 1. Three-variable fit law for maximizing carrier collection By fitting experimental data, the optimal L and effective L range under different P / N region parameters were determined, and the core principle was: The concentration in region P increased (2×10) 19 cm -3 -3×10 19 cm -3 ): Hole mobility is improved, and the optimal L is shifted by 0.5-1.0 mm over a wider range (e.g., 2×10). 19 cm -3 The optimal value is L=3.5. 19 cm -3 -4.0mm, 3×10 19 cm -3 The optimal value is L = 4.5mm - 5.0mm. The width of the P region increases (400-440μm): the hole transport path becomes longer, and the optimal L is adjusted by 0.3-0.5mm to the narrower region (e.g., the optimal L=3.5mm-4.5mm when it is 400μm, and the optimal L=3.0mm-4.0mm when it is 440μm). The concentration in the N region increased (5×10) 20 cm -3 -6×10 20 cm -3 ): Electron mobility is stable, and the optimal L does not shift significantly (maintaining 3.5-4.5 mm). The increased width of the N region (330-370μm) has a small impact on the electron transport path, and the optimal L is only slightly adjusted by ±0.2mm.

[0124] 2. Effective parameter range for maximizing carrier collection Overall effective L range: 3.5mm-4.5mm (carrier collection efficiency ≥99.8% for more than 90% of P / N region parameter combinations within this range); Optimal parameter combination: P region 2.5×10 19 cm -3 / 420μm, N region 5.5×10 20 cm -3 With a diameter of 350 μm and an aperture of L=4.0 mm, the carrier collection efficiency reaches 100.2%, the PCE is 27.5%, and the series resistance is 16.6 mΩ. Critical condition: When L deviates from the optimal value by ±0.5 mm, the carrier collection efficiency decreases by 0.3-0.5 percentage points, and the PCE decreases by 0.2-0.3 percentage points.

[0125] 3. Performance-cost balance Within the effective parameter range, the silver paste dosage was 117.2-119.5 mg / tablet, a reduction of 6.6-8.3% compared to Comparative Example 1, and a reduction of 11.6-13.3% compared to the fully encrypted solution (Comparative Example 4); printing yield was ≥98.5%, and contact resistance was ≤7.3 mΩ. cm² achieves the dual goals of "maximizing collection efficiency and optimizing cost".

[0126] Beneficial effects of the technical solution of the present invention 1. Significantly improved carrier collection efficiency: Through three-variable collaborative optimization, the carrier collection efficiency reaches up to 100.2%, which is 9.87% higher than the existing technology (91.2%); the series resistance is reduced to a minimum of 16.6mΩ, a reduction of 27.19%; and the recombination probability in long-path regions is reduced to 0.62%, a reduction of 66.49%, completely solving the problem of carrier transport imbalance.

[0127] 2. Breakthrough in overall battery performance: Under optimal parameter combination, PCE reaches 27.5%, an improvement of 1.5 percentage points compared to existing technologies; VOC reaches 747.5mV; and JSC reaches 43.2mA / cm². 2 The fill factor reached 83.9%, breaking through the performance bottleneck.

[0128] 3. Significant cost and process advantages: Silver paste usage is reduced by 6.6-8.3% compared to existing technologies, and the cost per watt of silver paste is reduced by 3.6-4.5 cents; the printing yield of steel screen printing is ≥98.5%, and the contact resistance is ≤7.3mΩ. cm 2 To meet mass production needs.

[0129] Highly adaptable: The three-variable synergistic scheme covers 2×10 of the P region. 19 cm -3 -3×10 19 cm -3 N zone 5×10 20 cm -3 -6×10 20 cm -3 The concentration range and the width range of the P region (400μm-440μm) and N region (330μm-370μm) can be flexibly adjusted according to different silicon wafer substrates, and are compatible with large-size TBC cells of 210mm and above.

[0130] In this application, the terms "embodiment" and "implementation" mean that a specific feature, structure, or characteristic described in connection with an embodiment can be included in at least one embodiment of this application. The appearance of these phrases in various locations throughout the specification does not necessarily refer to the same embodiment, nor are they independent or alternative embodiments mutually exclusive with other embodiments. Those skilled in the art will understand, explicitly and implicitly, that the embodiments described in this application can be combined with other embodiments. Furthermore, it should be understood that the features, structures, or characteristics described in the various embodiments of this application can be arbitrarily combined to form another embodiment that does not depart from the spirit and scope of the technical solution of this application, provided there is no contradiction between them.

[0131] The above description represents some embodiments of this application. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this application, and these improvements and modifications are also considered to be within the scope of protection of this application.

Claims

1. A back-contact battery, characterized in that, include: Supporting substrate; A polycrystalline silicon layer is disposed on one side of the supporting substrate. The side of the polycrystalline silicon layer facing away from the supporting substrate includes P-type doped regions and N-type doped regions, which are arranged in an interdigitated pattern. The doping concentration of the P-type doped regions ranges from 2 × 10⁻⁶. 19 cm -3 -3×10 19 cm -3 The width of the P-type doped region ranges from 400 μm to 440 μm, and the doping concentration of the N-type doped region ranges from 5 × 10⁻⁶. 20 cm -3 -6×10 20 cm -3 The width of the N-type doped region ranges from 330 μm to 370 μm; An electrode layer comprising multiple fine gate structures disposed on the P-type doped region and the N-type doped region, each fine gate structure comprising at least one fine gate electrode. When the length of the fine gate electrode is greater than a preset threshold, the number of fine gate electrodes in one fine gate structure is at least two, and the at least two fine gate electrodes are spaced apart. When the length of the fine gate electrode is less than the preset threshold, the number of fine gate electrodes in one fine gate structure is one. The preset threshold ranges from 3 mm to 5 mm.

2. The back contact battery according to claim 1, characterized in that, The width of the P-type doped region is positively correlated with the doping concentration of the P-type doped region. When the doping concentration of the P-type doped region is 2 × 10⁻⁶, the width of the P-type doped region is positively correlated with the doping concentration of the P-type doped region. 19 cm -3 -2.5×10 19 cm -3 When the width of the P-type doped region ranges from 400 μm to 420 μm, and the doping concentration of the P-type doped region ranges from 2.5 × 10⁻⁶, the width of the P-type doped region ranges from 400 μm to 420 μm. 19 cm -3 -3.0×10 19 cm -3 At that time, the width of the P-type doped region ranges from 420 μm to 440 μm.

3. The back contact battery according to claim 1, characterized in that, The width of the N-type doped region is negatively correlated with the doping concentration of the N-type doped region. When the doping concentration of the N-type doped region is in the range of 5.0 × 10⁻⁶, the width of the N-type doped region is negatively correlated with the doping concentration of the N-type doped region. 20 cm -3 -5.5×10 20 cm -3 When the width of the N-type doped region ranges from 350 μm to 370 μm, and the doping concentration of the N-type doped region ranges from 5.5 × 10⁻⁶, the width of the N-type doped region ranges from 350 μm to 370 μm. 20 cm -3 -6×10 20 cm -3 At that time, the width of the N-type doped region ranges from 330μm to 350μm.

4. The back contact battery according to claim 1, characterized in that, The preset threshold is positively correlated with the doping concentration of the P-type doped region. When the doping concentration of the P-type doped region is in the range of 2 × 10⁻⁶, the threshold value is positively correlated with the doping concentration of the P-type doped region. 19 cm -3 -2.5×10 19 cm -3 When the preset threshold ranges from 3.0 mm to 4.0 mm, and the doping concentration of the P-type doped region ranges from 2.5 × 10⁻⁶, the threshold value is within the range of 3.0 mm to 4.0 mm. 19 cm -3 -3.0×10 19 cm -3 When the preset threshold is in the range of 4.0mm-5.0mm.

5. The back contact battery according to claim 1, characterized in that, The preset threshold is negatively correlated with the width of the P-type doped region. When the width of the P-type doped region is 400μm-420μm, the preset threshold is 4.0mm-5.0mm. When the width of the P-type doped region is 420μm-440μm, the preset threshold is 3.0mm-4.0mm.

6. The back contact battery according to claim 1, characterized in that, The linewidth of the fine gate electrode ranges from 13μm to 17μm, and the line spacing between adjacent fine gate electrodes within the same fine gate structure ranges from 55μm to 65μm.

7. The back contact battery according to claim 1, characterized in that, The polysilicon layer also includes an isolation region on the side opposite to the supporting substrate. The isolation region is located between the P-type doped region and the N-type doped region, and the width of the isolation region ranges from 55μm to 65μm.

8. The back contact battery according to claim 1, characterized in that, The electrode layer includes multiple bus structures, which are disposed on the P-type doped region and the N-type doped region. Each of the two ends of a bus structure is connected to a fine gate structure. The overlap length between the fine gate structure and the bus structure is in the range of 15μm-25μm.

9. A method for preparing a back contact battery, characterized in that, The method for preparing the back contact battery according to any one of claims 1-8 comprises: A support substrate is provided, and the polycrystalline silicon layer is deposited on the support substrate; P-type doped regions and N-type doped regions are formed on the polycrystalline silicon layer; The electrode layer is printed on the polysilicon layer, wherein the electrode layer includes a plurality of fine gate structures, the fine gate structures are disposed on the P-type doped region and the N-type doped region, and the fine gate structure includes at least one fine gate electrode. When the length of the fine gate electrode is greater than a preset threshold, the number of fine gate electrodes in one fine gate structure is at least two, and the at least two fine gate electrodes are spaced apart. When the length of the fine gate electrode is less than the preset threshold, the number of fine gate electrodes in one fine gate structure is one. The preset threshold ranges from 3 mm to 5 mm. After the electrode layer is pre-baked and sintered, it is encapsulated to form a back contact battery.

10. The preparation method according to claim 9, characterized in that, Forming P-type doped regions and N-type doped regions on the polysilicon layer includes: A glass layer is provided on the polycrystalline silicon layer, and the glass layer is laser-etched according to the width range of the P-type doped region and the N-type doped region, wherein the width range of the P-type doped region is 400μm-440μm and the width range of the N-type doped region is 330μm-370μm. Boron diffusion is performed according to the doping concentration range of the P-type doped region, wherein the doping concentration range of the P-type doped region is 2 × 10⁻⁶. 19 cm -3 -3×10 19 cm -3 The flow rate of boron trichloride ranges from 2 sccm to 4 sccm, the ambient temperature ranges from 890℃ to 910℃, and the boron diffusion time ranges from 28 min to 32 min. Phosphorus diffusion is performed according to the doping concentration range of the N-type doped region, wherein the doping concentration range of the N-type doped region is 5 × 10⁻⁶. 20 cm -3 -6×10 20 cm -3 The flow rate of phosphorus oxychloride ranges from 6 sccm to 9 sccm, the ambient temperature ranges from 840℃ to 860℃, and the phosphorus diffusion time ranges from 22 min to 26 min.

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