Light emitting diode chip and method of manufacturing the same
By employing a mesa trench and a distributed Bragg reflector layer design in the light-emitting diode chip, the bump electrode contacts the second semiconductor layer, solving the problem of excessive thickness and achieving improved brightness and thinner design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BOE HUACAN OPTOELECTRONICS (GUANGDONG) CO LTD
- Filing Date
- 2026-03-12
- Publication Date
- 2026-06-23
AI Technical Summary
The relatively large thickness of light-emitting diode chips makes them unsuitable for thinner and lighter designs.
An epitaxial layer design is adopted, including mesa trenches and distributed Bragg reflector layers. Bump electrodes penetrate the primary electrode and contact the second semiconductor layer to form an overlapping structure to achieve electrical connection and reflector function.
It improves the brightness of the LED chip and effectively reduces its thickness, which is beneficial for thinner and lighter designs.
Smart Images
Figure CN122269893A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a light-emitting diode chip and its fabrication method. Background Technology
[0002] A light-emitting diode (LED) chip is a semiconductor device that can convert electrical energy into light energy.
[0003] In related technologies, the epitaxial layer of a light-emitting diode (LED) chip has an N-type primary electrode and a P-type primary electrode on one side. The N-type primary electrode is electrically connected to the N-type semiconductor layer of the epitaxial layer, and the P-type primary electrode is electrically connected to the P-type semiconductor layer of the epitaxial layer. Furthermore, a bump electrode is provided on the P-type primary electrode for bonding with a driver chip.
[0004] However, since the bump electrode is set on the P-type primary electrode, the LED chip is relatively thick, which is not conducive to the design of thinner and lighter chips. Summary of the Invention
[0005] This disclosure provides a light-emitting diode (LED) chip and its fabrication method, which facilitates the thinner and lighter design of LED electrodes. The technical solution is as follows: On one hand, embodiments of this disclosure provide a light-emitting diode chip, including: an epitaxial layer, a bump electrode, and a primary electrode; The epitaxial layer includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially. The first semiconductor layer is of a first conductivity type, and the second semiconductor layer is of a second conductivity type, which is different from the first conductivity type. The epitaxial layer has mesa trenches that extend from the second semiconductor layer to the first semiconductor layer. The primary electrode covers the first semiconductor layer, the sidewall of the mesa trench, and the second semiconductor layer, and the primary electrode is in contact with the first semiconductor layer. The primary electrode has a first hole. One end of the bump electrode penetrates through the first hole to contact the second semiconductor layer.
[0006] In one implementation of this disclosure, in the epitaxial growth direction, the orthographic projection of the bump electrode onto the plane where the epitaxial layer is located partially coincides with the orthographic projection of the primary electrode onto the plane where the epitaxial layer is located.
[0007] In one implementation of this disclosure, the light-emitting diode chip further includes a distributed Bragg reflector layer; The distributed Bragg reflector layer is located between the primary electrode and the epitaxial layer, and the distributed Bragg reflector layer covers the sidewalls of the second semiconductor layer and the mesa trench. The distributed Bragg reflector layer has a second hole, which is connected to the first hole. One end of the bump electrode passes through the first hole and the second hole in sequence to contact the second semiconductor layer.
[0008] In one implementation of this disclosure, the light-emitting diode chip further includes a passivation layer; The passivation layer covers the primary electrode.
[0009] In one implementation of this disclosure, the passivation layer covers the wall of the first hole, such that the passivation layer is located between the bump electrode and the primary electrode.
[0010] In one implementation of this disclosure, the end of the bump electrode facing away from the epitaxial layer has a bonding notch.
[0011] On the other hand, embodiments of this disclosure provide a method for fabricating a light-emitting diode chip, comprising: An epitaxial layer is prepared, the epitaxial layer comprising a first semiconductor layer, an active layer and a second semiconductor layer stacked sequentially, wherein the first semiconductor layer is of a first conductivity type and the second semiconductor layer is of a second conductivity type, and the second conductivity type is different from the first conductivity type; The epitaxial layer is etched to obtain a mesa trench, the mesa trench extending from the second semiconductor layer to the first semiconductor layer; A primary electrode is prepared, which covers the first semiconductor layer, the sidewall of the mesa trench, and the second semiconductor layer, and the primary electrode is in contact with the first semiconductor layer. The primary electrode is etched to form a first hole on the primary electrode; A bump electrode is prepared, one end of which penetrates through the first hole to contact the second semiconductor layer.
[0012] In one implementation of this disclosure, before fabricating the primary electrode, the following steps are included: A distributed Bragg reflector layer is prepared, which covers the second semiconductor layer and the sidewall of the mesa trench; The distributed Bragg reflector layer is etched to form a second hole in the distributed Bragg reflector layer, the second hole being connected to the first hole.
[0013] In one implementation of this disclosure, after etching the primary electrode, the process includes: A passivation layer is prepared, which covers the primary electrode and the wall of the first hole; The passivation layer is etched to expose the first hole.
[0014] In one implementation of this disclosure, after fabricating the bump electrode, the process includes: The bump electrode is etched to form a bonding notch at one end of the bump electrode facing away from the epitaxial layer.
[0015] The beneficial effects of the technical solutions provided in this disclosure include at least the following: The light-emitting diode (LED) chip provided in this embodiment includes an epitaxial layer comprising a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially. The first and second semiconductor layers have different conductivity types, enabling the active layer to emit light under their combined action. The epitaxial layer has a mesa trench extending from the second semiconductor layer to the first semiconductor layer, such that the sidewalls of the mesa trench extend sequentially through the second semiconductor layer, the active layer, and the first semiconductor layer along the epitaxial growth direction. The bottom of the mesa trench is located at the first semiconductor layer, thereby exposing the side of the first semiconductor layer facing the second semiconductor layer. The LED chip also includes a bump electrode and a primary electrode. The primary electrode covers the first semiconductor layer, the sidewalls of the mesa trench, and the second semiconductor layer, acting as a reflective layer to achieve sufficient reflection of light from the epitaxial layer, thereby improving the brightness of the LED chip. Furthermore, the primary electrode contacts the first semiconductor layer, achieving an electrical connection between them. One end of the bump electrode penetrates through a first hole in the primary electrode to contact the second semiconductor layer, thereby achieving an electrical connection between them. Since the bump electrode directly penetrates the primary electrode and contacts the second semiconductor layer, the thickness of the LED chip is effectively reduced, which is beneficial for achieving a thinner and lighter LED chip design.
[0016] In other words, by completely covering the first semiconductor layer, the second semiconductor layer, and the sidewalls of the mesa trench with the primary electrode, the primary electrode can reflect the light generated by the epitaxial layer, thus improving the brightness of the LED chip. Furthermore, the bump electrode penetrates the primary electrode and directly contacts the second semiconductor layer, effectively reducing the thickness of the LED chip and facilitating a thinner and lighter design. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a schematic diagram of the structure of the light-emitting diode chip provided in the embodiments of this disclosure; Figure 2 This is a flowchart illustrating a method for fabricating a light-emitting diode chip according to an embodiment of this disclosure; Figure 3 This is a flowchart of another method for fabricating a light-emitting diode chip provided in this embodiment.
[0019] Icon labels: 10. Epitaxial layer; 110, First semiconductor layer; 120, Active layer; 130, Second semiconductor layer; 140, Mesa trench; 20. Primary electrode; 210. First hole; 30. Bump electrode; 310. Bonding notch; 40. Distributed Bragg reflector layer; 410. Second hole; 50. Passivation layer; 60. Substrate. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.
[0021] ADB (Adaptive Driving Beam) is a new type of vehicle lighting system that has been widely used in automobiles, especially in new energy vehicles.
[0022] In related technologies, the main light-emitting device of ADB (Advanced Driver Assistance) vehicle lights is a light-emitting diode (LED) chip. One side of the epitaxial layer of the LED chip has an N-type primary electrode and a P-type primary electrode. The N-type primary electrode is electrically connected to the N-type semiconductor layer of the epitaxial layer, and the P-type primary electrode is electrically connected to the P-type semiconductor layer of the epitaxial layer. Furthermore, a bump electrode is provided on the P-type primary electrode for bonding with the driver chip.
[0023] However, since the bump electrode is set on the P-type primary electrode, the LED chip is relatively thick, which is not conducive to the design of thinner and lighter chips.
[0024] To address the aforementioned technical problems, this disclosure provides a light-emitting diode chip. Figure 1 See the schematic diagram of the structure of this light-emitting diode chip. Figure 1In this embodiment, the light-emitting diode chip includes an epitaxial layer 10, a bump electrode 30, and a primary electrode 20. The epitaxial layer 10 includes a first semiconductor layer 110, an active layer 120, and a second semiconductor layer 130 stacked sequentially. The first semiconductor layer 110 has a first conductivity type, and the second semiconductor layer 130 has a second conductivity type, which is different from the first conductivity type. The epitaxial layer 10 has a mesa trench 140 extending from the second semiconductor layer 130 to the first semiconductor layer 110. The primary electrode 20 covers the first semiconductor layer 110, the sidewall of the mesa trench 140, and the second semiconductor layer 130, and is in contact with the first semiconductor layer 110. The primary electrode 20 has a first hole 210. One end of the bump electrode 30 penetrates the first hole 210 to contact the second semiconductor layer 130.
[0025] The light-emitting diode chip provided in this embodiment includes an epitaxial layer 10, wherein the epitaxial layer 10 includes a first semiconductor layer 110, an active layer 120, and a second semiconductor layer 130 stacked sequentially. The first semiconductor layer 110 and the second semiconductor layer 130 have different conductivity types, enabling the active layer 120 to emit light under the combined action. The epitaxial layer 10 has a mesa trench 140, which extends from the second semiconductor layer 130 to the first semiconductor layer 110, such that the sidewalls of the mesa trench 140 extend sequentially through the second semiconductor layer 130, the active layer 120, and the first semiconductor layer 110 along the epitaxial growth direction. The bottom of the mesa trench 140 is located at the first semiconductor layer 110, thereby exposing the side of the first semiconductor layer 110 facing the second semiconductor layer 130. The light-emitting diode (LED) chip also includes a bump electrode 30 and a primary electrode 20. The primary electrode 20 covers the first semiconductor layer 110, the sidewalls of the mesa trench 140, and the second semiconductor layer 130, acting as a reflective layer to ensure sufficient reflection of the epitaxial layer 10, thereby improving the brightness of the LED chip. Furthermore, the primary electrode 20 contacts the first semiconductor layer 110, achieving an electrical connection between them. One end of the bump electrode 30 penetrates through the first hole 210 on the primary electrode 20 to contact the second semiconductor layer 130, thus achieving an electrical connection between them. Because the bump electrode 30 directly penetrates the primary electrode 20 and contacts the second semiconductor layer 130, the thickness of the LED chip is effectively reduced, facilitating a thinner and lighter design for the LED chip.
[0026] In other words, by completely covering the first semiconductor layer 110, the second semiconductor layer 130, and the sidewalls of the mesa trench 140 with the primary electrode 20, the primary electrode 20 can reflect the light generated by the epitaxial layer 10, thereby improving the brightness of the LED chip. Furthermore, the bump electrode 30 penetrates the primary electrode 20 and directly contacts the second semiconductor layer 130, effectively reducing the thickness of the LED chip and facilitating a thinner and lighter design for the LED chip.
[0027] In this embodiment, the first semiconductor layer 110 is an N-type GaN layer, the active layer 120 is a quantum well layer, and the second semiconductor layer 130 is a P-type GaN layer.
[0028] Of course, in other embodiments, the first semiconductor layer 110 may be a P-type GaN layer, the active layer 120 may be a quantum well layer, and the second semiconductor layer 130 may be an N-type GaN layer. This disclosure does not limit this.
[0029] See also Figure 1 In this embodiment, in the epitaxial growth direction, the orthogonal projection of the bump electrode 30 on the plane where the epitaxial layer 10 is located partially coincides with the orthogonal projection of the primary electrode 20 on the plane where the epitaxial layer 10 is located.
[0030] In the above implementation, the primary electrode 20 extends as far as possible below the bump electrode 30 in its lateral area, so that the projection of the bump electrode 30 coincides with the projection of the primary electrode 20, thereby maximizing the coverage of the primary electrode 20 on the epitaxial layer 10. The greater the coverage of the primary electrode 20, the higher its efficiency in recovering stray light, thus further enhancing the brightness of the light-emitting diode chip.
[0031] Furthermore, the overlapping structure formed by overlapping the bump electrode 30 and the primary electrode 20 can provide a more stable bottom support for the bump electrode 30 and provide better mechanical strength during packaging.
[0032] For example, the area of the region where the orthographic projection of the bump electrode 30 and the primary electrode 20 overlaps accounts for more than 50% of the total projected area of the bump electrode 30.
[0033] This design ensures that the primary electrode 20 serves as a reflective layer beneath the main current injection area of the bump electrode 30, eliminating dead zones of optical loss. Furthermore, since the primary electrode 20 provides a larger support area for the bump electrode 30, it can effectively buffer the stress during bonding, preventing the underlying epitaxial layer 10 from cracking due to stress concentration.
[0034] In this embodiment, the light-emitting diode chip further includes a distributed Bragg reflector layer 40. The distributed Bragg reflector layer 40 is located between the primary electrode 20 and the epitaxial layer 10, and covers the sidewalls of the second semiconductor layer 130 and the mesa trench 140. The distributed Bragg reflector layer 40 has a second hole 410, which is connected to a first hole 210. One end of the bump electrode 30 passes through the first hole 210 and the second hole 410 in sequence to contact the second semiconductor layer 130.
[0035] In the above implementation, the distributed Bragg reflector layer 40 can electrically isolate the primary electrode 20 covering the sidewall of the mesa trench 140 and the second semiconductor layer 130 from the sidewall of the second semiconductor layer 130 and the active layer 120, preventing short circuits, thereby ensuring that the primary electrode 20 can wrap the chip over a large area without conducting electricity.
[0036] Furthermore, the distributed Bragg reflector layer 40 is optimized for specific wavelengths and can work with the primary electrode 20 to form an omnidirectional reflector (ODR). Compared to a simple primary electrode 20 metal reflector layer, it has a higher reflectivity and reduces the light absorption loss of the primary electrode 20, thereby further improving the brightness of the light-emitting diode chip.
[0037] For example, the distributed Bragg reflector layer 40 is composed of stacked dielectric thin films with alternating high and low refractive indices, and the material combination includes SiO2 / TiO2, SiO2 / Nb2O5 or SiO2 / Ta2O5.
[0038] For example, the diameter of the second hole 410 is less than or equal to the diameter of the first hole 210.
[0039] In the above implementation, the second hole 410 is designed to be smaller than or equal to the first hole 210, which can form a stepped or overlapping opening edge, which is beneficial for the subsequent climbing coverage of the passivation layer 50 and the bump electrode 30, and avoids the occurrence of faults or stress concentration points at the edge of the hole.
[0040] In this embodiment, the light-emitting diode chip further includes a passivation layer 50, which covers the primary electrode 20.
[0041] In the above implementation, the passivation layer 50 is used to protect the primary electrode 20.
[0042] For example, the passivation layer 50 is SiN x Materials such as SiO2 or Al2O3.
[0043] In this embodiment, the passivation layer 50 covers the hole wall of the first hole 210, such that the passivation layer 50 is located between the bump electrode 30 and the primary electrode 20.
[0044] In the above implementation, the passivation layer 50 covers the sidewalls of the primary electrode 20 and the first hole 210, so that the passivation layer 50 is located between the bump electrode 30 and the primary electrode 20, forming a robust insulating barrier. This eliminates the risk of a sidewall short circuit between the bump electrode 30 and the primary electrode 20, which have opposite potentials, at the hole, greatly improving the reliability of the chip. Furthermore, the passivation layer 50 covering the primary electrode 20 protects the internal primary electrode 20 from corrosion by external moisture, thereby enhancing the device's moisture and corrosion resistance.
[0045] In this embodiment, the bump electrode 30 has a bonding notch 310 at one end facing away from the epitaxial layer 10.
[0046] In the above implementation, the bonding notch 310 can increase the surface area and roughness of the top of the bump electrode 30, thereby enhancing the mechanical interlocking force when bonding with the driver chip.
[0047] Furthermore, the bonding notch 310 can also serve as an overflow channel for excess solder, preventing solder from overflowing to the side during the extrusion process and causing short circuits in adjacent LED chips, thereby improving the stability of subsequent packaging processes.
[0048] Figure 2 A flowchart illustrating a method for fabricating a light-emitting diode chip according to an embodiment of this disclosure is provided. (See attached flowchart.) Figure 2 In this embodiment, the preparation method includes: Step 201: Prepare an epitaxial layer 10. The epitaxial layer 10 includes a first semiconductor layer 110, an active layer 120, and a second semiconductor layer 130 stacked sequentially. The first semiconductor layer 110 is of a first conductivity type, and the second semiconductor layer 130 is of a second conductivity type, and the second conductivity type is different from the first conductivity type.
[0049] Step 202: Etch epitaxial layer 10 to obtain mesa trench 140, which extends from second semiconductor layer 130 to first semiconductor layer 110.
[0050] Step 203: Prepare a primary electrode 20, which covers the first semiconductor layer 110, the sidewall of the mesa trench 140, and the second semiconductor layer 130, and the primary electrode 20 is in contact with the first semiconductor layer 110.
[0051] Step 204: Etch the primary electrode 20 to form the first hole 210 on the primary electrode 20; Step 205: Prepare a bump electrode 30, one end of which penetrates the first hole 210 to contact the second semiconductor layer 130.
[0052] Figure 3For a flowchart of another method for fabricating a light-emitting diode chip provided in this disclosure embodiment, please refer to [link to flowchart]. Figure 3 In this embodiment, the preparation method includes: Step 301: Provide a substrate 60.
[0053] For example, substrate 60 is a sapphire substrate, a silicon substrate, or other light-emitting diode chip substrate material.
[0054] Step 302: Prepare epitaxial layer 10.
[0055] For example, a first semiconductor layer 110, an active layer 120, and a second semiconductor layer 130 are grown sequentially using metal-organic chemical vapor deposition (MOCVD).
[0056] For example, the first semiconductor layer 110 is an N-type GaN layer, the active layer 120 is a quantum well layer, and the second semiconductor layer 130 is a P-type GaN layer.
[0057] Step 303: Etch epitaxial layer 10 to obtain mesa trench 140, which extends from second semiconductor layer 130 to first semiconductor layer 110.
[0058] In step 303, the mesa trench 140 is etched by photolithography using inductively coupled plasma (ICP) etching.
[0059] Step 304: Prepare the distributed Bragg reflector layer 40.
[0060] A distributed Bragg reflector layer 40 covers the sidewalls of the second semiconductor layer 130 and the mesa trench 140.
[0061] Step 305: Etch the distributed Bragg reflector layer 40 to form a second hole 410 on the distributed Bragg reflector layer 40.
[0062] For example, the second hole 410 is obtained by photolithography using the ICP process.
[0063] Step 306: Prepare a primary electrode 20, which covers the first semiconductor layer 110, the sidewall of the mesa trench 140, and the second semiconductor layer 130, and the primary electrode 20 is in contact with the first semiconductor layer 110.
[0064] Step 307: Etch the primary electrode 20 to form a first hole 210 on the primary electrode 20, the first hole 210 being connected to the second hole 410.
[0065] For example, the first hole 210 is obtained by photolithography using the ICP process.
[0066] Step 308: Prepare a passivation layer 50, which covers the primary electrode 20 and the hole wall of the first hole 210.
[0067] Step 309: Etch the passivation layer 50 to expose the first hole 210.
[0068] For example, the passivation layer 50 is etched by photolithography using an ICP process, so that the first hole 210 beneath the passivation layer 50 is exposed.
[0069] Step 3010: Prepare a bump electrode 30, one end of which penetrates the first hole 210 to contact the second semiconductor layer 130.
[0070] Step 3011: Etch the bump electrode 30 to form a bonding notch 310 at one end of the bump electrode 30 facing away from the epitaxial layer 10.
[0071] The light-emitting diode chip prepared by the method provided in this embodiment includes an epitaxial layer 10, wherein the epitaxial layer 10 includes a first semiconductor layer 110, an active layer 120, and a second semiconductor layer 130 stacked sequentially. The first semiconductor layer 110 and the second semiconductor layer 130 have different conductivity types, enabling the active layer 120 to emit light under the combined action. The epitaxial layer 10 has a mesa trench 140, which extends from the second semiconductor layer 130 to the first semiconductor layer 110, such that the sidewalls of the mesa trench 140 extend sequentially through the second semiconductor layer 130, the active layer 120, and the first semiconductor layer 110 along the epitaxial growth direction. The bottom of the mesa trench 140 is located at the first semiconductor layer 110, thereby exposing the side of the first semiconductor layer 110 facing the second semiconductor layer 130. The light-emitting diode (LED) chip also includes a bump electrode 30 and a primary electrode 20. The primary electrode 20 covers the first semiconductor layer 110, the sidewalls of the mesa trench 140, and the second semiconductor layer 130, acting as a reflective layer to ensure sufficient reflection of the epitaxial layer 10, thereby improving the brightness of the LED chip. Furthermore, the primary electrode 20 contacts the first semiconductor layer 110, achieving an electrical connection between them. One end of the bump electrode 30 penetrates through the first hole 210 on the primary electrode 20 to contact the second semiconductor layer 130, thus achieving an electrical connection between them. Because the bump electrode 30 directly penetrates the primary electrode 20 and contacts the second semiconductor layer 130, the thickness of the LED chip is effectively reduced, facilitating a thinner and lighter design for the LED chip.
[0072] In other words, by completely covering the first semiconductor layer 110, the second semiconductor layer 130, and the sidewalls of the mesa trench 140 with the primary electrode 20, the primary electrode 20 can reflect the light generated by the epitaxial layer 10, thereby improving the brightness of the LED chip. Furthermore, the bump electrode 30 penetrates the primary electrode 20 and directly contacts the second semiconductor layer 130, effectively reducing the thickness of the LED chip and facilitating a thinner and lighter design for the LED chip.
[0073] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.
[0074] The above is not intended to limit this disclosure in any way. Although this disclosure has been disclosed above through embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this disclosure. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this disclosure without departing from the content of the technical solution of this disclosure shall still fall within the scope of the technical solution of this disclosure.
Claims
1. A light-emitting diode chip, characterized in that, include: Epitaxial layer (10), bump electrode (30) and primary electrode (20); The epitaxial layer (10) includes a first semiconductor layer (110), an active layer (120), and a second semiconductor layer (130) stacked sequentially. The first semiconductor layer (110) is of a first conductivity type, and the second semiconductor layer (130) is of a second conductivity type, and the second conductivity type is different from the first conductivity type. The epitaxial layer (10) has a mesa trench (140), which extends from the second semiconductor layer (130) to the first semiconductor layer (110). The primary electrode (20) covers the first semiconductor layer (110), the sidewall of the mesa trench (140), and the second semiconductor layer (130), and the primary electrode (20) is in contact with the first semiconductor layer (110). The primary electrode (20) has a first hole (210). One end of the bump electrode (30) penetrates through the first hole (210) to contact the second semiconductor layer (130).
2. The light-emitting diode chip according to claim 1, characterized in that, In the epitaxial growth direction, the orthographic projection of the bump electrode (30) on the plane where the epitaxial layer (10) is located coincides with the orthographic projection of the primary electrode (20) on the plane where the epitaxial layer (10) is located.
3. The light-emitting diode chip according to claim 1, characterized in that, The light-emitting diode chip also includes a distributed Bragg reflector layer (40). The distributed Bragg reflector layer (40) is located between the primary electrode (20) and the epitaxial layer (10), and the distributed Bragg reflector layer (40) covers the sidewalls of the second semiconductor layer (130) and the mesa trench (140). The distributed Bragg reflector layer (40) has a second hole (410) that is connected to the first hole (210). One end of the bump electrode (30) passes through the first hole (210) and the second hole (410) in sequence to contact the second semiconductor layer (130).
4. The light-emitting diode chip according to claim 1, characterized in that, The light-emitting diode chip also includes a passivation layer (50). The passivation layer (50) covers the primary electrode (20).
5. The light-emitting diode chip according to claim 4, characterized in that, The passivation layer (50) covers the hole wall of the first hole (210) such that the passivation layer (50) is located between the bump electrode (30) and the primary electrode (20).
6. The light-emitting diode chip according to claim 1, characterized in that, The bump electrode (30) has a bonding notch (310) at one end facing away from the epitaxial layer (10).
7. A method for fabricating a light-emitting diode chip, characterized in that, include: An epitaxial layer (10) is prepared, the epitaxial layer (10) comprising a first semiconductor layer (110), an active layer (120), and a second semiconductor layer (130) stacked sequentially, the first semiconductor layer (110) being of a first conductivity type, the second semiconductor layer (130) being of a second conductivity type, and the second conductivity type being different from the first conductivity type; The epitaxial layer (10) is etched to obtain a mesa trench (140) that extends from the second semiconductor layer (130) to the first semiconductor layer (110). A primary electrode (20) is prepared, which covers the first semiconductor layer (110), the sidewall of the mesa trench (140), and the second semiconductor layer (130), and the primary electrode (20) is in contact with the first semiconductor layer (110); The primary electrode (20) is etched to form a first hole (210) on the primary electrode (20); A bump electrode (30) is prepared, one end of which penetrates through the first hole (210) to contact the second semiconductor layer (130).
8. The preparation method according to claim 7, characterized in that, Before fabricating the primary electrode (20), the following steps are included: A distributed Bragg reflector layer (40) is prepared, which covers the sidewalls of the second semiconductor layer (130) and the mesa trench (140); The distributed Bragg reflector layer (40) is etched to form a second hole (410) on the distributed Bragg reflector layer (40), the second hole (410) being connected to the first hole (210).
9. The preparation method according to claim 7, characterized in that, After etching the primary electrode (20), the process includes: A passivation layer (50) is prepared, which covers the primary electrode (20) and the passivation layer (50) covers the hole wall of the first hole (210); The passivation layer (50) is etched to expose the first hole (210).
10. The preparation method according to claim 7, characterized in that, After fabricating the bump electrode (30), the following steps are included: The bump electrode (30) is etched to form a bonding notch (310) at one end of the bump electrode (30) facing away from the epitaxial layer (10).