Semiconductor structure and method of forming the same

Abstract

The application relates to a semiconductor structure and a forming method thereof. The semiconductor structure comprises: a substrate comprising a first main surface and a second main surface oppositely distributed along a first direction, the substrate having a first conductive type; a well region located in the substrate, and the well region having a second conductive type, the first conductive type and the second conductive type being opposite conductive types; an epitaxial layer covering the first main surface of the substrate, the epitaxial layer having the first conductive type; and a conductive lead-out assembly comprising a plurality of conductive lead-out structures spaced apart along a second direction, each conductive lead-out structure penetrating the epitaxial layer at least along the first direction and being electrically connected with the well region, and the conductive lead-out structure being used for transmitting a bias current to the well region. The application reduces the interference of the magnetic field generated by the current flowing through the metal interconnection line on the signal in the well region, and makes the manufacturing process of the semiconductor structure compatible with the BCD process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] In integrated circuits, especially in complex system chips that require the integration of sensing, analog signal processing, digital logic and power output functions, the BCD (Bipolar-CMOS-DMOS) process has become the mainstream technology platform for manufacturing high-performance and high-reliability chips due to its advantage of being able to integrate bipolar transistors, CMOS devices and DMOS power devices simultaneously.

[0003] In semiconductor structures such as sensors, the active region is located vertically near the metal interconnect layer at the back of the chip. When current flows through the metal interconnect, a magnetic field is generated around it. This magnetic field can easily interfere with the signal in the active region, affecting the stability of the semiconductor structure's performance. Taking a magnetic sensor (such as a Hall effect sensor) as an example, a traditional magnetic sensor defines the sensing area as the active region of the substrate, with the surface of the sensing area flush with the surface of the substrate. The contact electrode of the magnetic sensor is located at the top of the sensing area. Subsequently, a back metal interconnect is formed above the substrate. When current flows through the back metal interconnect, the magnetic field generated around the current in the back metal interconnect interferes with the detection signal at the contact electrode, thus affecting the accuracy and reliability of the magnetic sensor measurement. To reduce this interference, a large piece of metal is usually placed above the substrate to shield the magnetic field interference. The placement of a large shielding metal not only increases the overall structural complexity of the magnetic sensor and reduces its manufacturing efficiency, but also occupies the area above the substrate, thereby reducing the area available for wiring and reducing the internal space utilization of the magnetic sensor. In addition, the current manufacturing process of sensor devices has poor compatibility with BCD technology.

[0004] Therefore, how to improve the performance stability of semiconductor structures while avoiding the occupation of internal space by large shielding metals, improving the internal space utilization of semiconductor structures, and ensuring that the manufacturing process of semiconductor structures is compatible with BCD processes, thereby ensuring the manufacturing yield and efficiency of semiconductor structures and expanding the manufacturing and application fields of semiconductor structures, are the technical problems that urgently need to be solved. Summary of the Invention

[0005] This invention provides a semiconductor structure and its formation method, which improves the performance of sensor devices while avoiding the occupation of internal space by large shielding metals, thereby increasing the internal space utilization of the sensor device and making the manufacturing process of the sensor device compatible with BCD process, thus ensuring the manufacturing yield and efficiency of the sensor device and expanding the manufacturing and application fields of the sensor device.

[0006] According to some embodiments, the present invention provides a semiconductor structure comprising: The substrate includes a first main surface and a second main surface that are oppositely distributed along a first direction, and the substrate has a first conductivity type; A well region is located within the substrate, and the well region has a second conductivity type, wherein the first conductivity type and the second conductivity type are opposite conductivity types; An epitaxial layer is applied to the first main surface of the substrate, and the epitaxial layer has the first conductivity type; A conductive lead-out assembly includes a plurality of conductive lead-out structures spaced apart along a second direction, each of the conductive lead-out structures penetrating the epitaxial layer at least along a first direction and electrically connected to the well region, the conductive lead-out structures being used to transmit bias current to the well region, the second direction being parallel to the first main surface of the substrate.

[0007] In some embodiments, the conductive lead-out structure includes: A conductive connecting post extends along the first direction and is electrically connected to the well region. A contact electrode is provided, covering the end of the conductive connection post facing away from the well region.

[0008] In some embodiments, the surface of the well region facing away from the second main surface is flush with the first main surface of the substrate; or, The surface of the well region facing away from the second main surface is lower than the first main surface of the substrate.

[0009] In some embodiments, the well region includes a body region and a plurality of buried regions located within the body region and independent of each other. The plurality of buried regions are electrically connected to the plurality of conductive lead-out structures in a one-to-one correspondence. The surface of the body region away from the second main surface of the substrate and the surface of the buried regions away from the second main surface of the substrate are flush with the first main surface of the substrate. The conductive connecting post includes a conductive lead-out area electrically connected to the burial area, and the conductive lead-out area has the second conductivity type.

[0010] In some embodiments, the conductive lead-out region includes: The lower lead-out area is located within the epitaxial layer and is electrically connected to the buried area. The upper lead-out area is located above the lower lead-out area. One end of the upper lead-out area is electrically connected to the lower lead-out area, and the other end is electrically connected to the contact electrode.

[0011] In some embodiments, the surface of the well region facing away from the second main surface is lower than the first main surface of the substrate; The conductive lead-out component also includes multiple trenches that penetrate the epitaxial layer and extend to the well region, with multiple conductive connecting posts filling the multiple trenches one by one.

[0012] According to other embodiments, the present invention also provides a method for forming a semiconductor structure, comprising the following steps: A substrate is provided, the substrate including a first main surface and a second main surface that are oppositely distributed along a first direction, the substrate having a first conductivity type; A well region is formed within the substrate, the well region having a second conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types; An epitaxial layer is formed covering the first main surface of the substrate, the epitaxial layer having the first conductivity type; A conductive lead assembly is formed comprising a plurality of conductive lead structures spaced apart along a second direction, each of the conductive lead structures penetrating the epitaxial layer at least along the first direction and electrically connected to the well region, the conductive lead structure being used to transmit bias current to the well region, the second direction being parallel to the first main surface of the substrate.

[0013] In some embodiments, the specific steps of forming a well region within the substrate include: A second type of doped ions are implanted into the substrate from the first main surface of the substrate to form a bulk region; The second type of doped ions are implanted into the substrate from the first main surface of the substrate to form a plurality of buried regions in the body region. The concentration of the second type of doped ions in the buried regions is higher than the concentration of the second type of doped ions in the body region. The surface of the body region away from the second main surface of the substrate and the surface of the buried regions away from the second main surface of the substrate are flush with the first main surface of the substrate to form the well region including the buried regions and the body region.

[0014] In some embodiments, the specific steps of forming a conductive lead assembly including a plurality of conductive lead structures spaced apart along a second direction include: A plurality of conductive connection pillars are formed at least within the epitaxial layer, the plurality of conductive connection pillars are spaced apart along the second direction, and the plurality of conductive connection pillars are all electrically connected to the well region. Multiple contact electrodes are formed that are electrically connected to the multiple conductive connecting posts in a one-to-one manner. The conductive connecting posts and the contact electrodes electrically connected to them together constitute the conductive lead-out structure.

[0015] In some embodiments, the specific steps of forming at least a plurality of conductive connection pillars located within the epitaxial layer, wherein the plurality of conductive connection pillars are spaced apart along the second direction, and wherein each of the plurality of conductive connection pillars is electrically connected to the well region by contact include: The second type of doped ions are injected into the epitaxial layer to form a plurality of conductive lead-out regions that are electrically connected to the plurality of buried regions one by one, and the conductive lead-out regions are used as the conductive connection pillars.

[0016] The semiconductor structure and its formation method provided by this invention, by placing a well region within a substrate below an epitaxial layer and electrically connecting the well region through a conductive lead-out component that at least penetrates the epitaxial layer, wherein the conductive lead-out structure in the conductive lead-out component is used to transmit bias current to the well region, thereby increasing the distance between the well region and the metal interconnects formed in subsequent processes and located above the substrate, reducing the interference of the magnetic field generated by the current flowing through the metal interconnects on the well region detection signal, and improving the accuracy and reliability of the semiconductor structure detection. Furthermore, this invention eliminates the need for large shielding metal, thus avoiding the occupation of internal space by large shielding metal, improving the space utilization of the semiconductor structure, and ensuring the manufacturing yield and efficiency of the semiconductor structure. In addition, the semiconductor structure formation method provided by this invention is compatible with BCD (Bipolar-CMOS-DMOS) technology, thereby expanding its application areas and ensuring the manufacturing yield and efficiency of the semiconductor structure. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a semiconductor structure in a specific embodiment of the present invention; Figure 2 This is a diagram showing the relative positional relationship between a trap region and a conductive lead-out component in a specific embodiment of the present invention. Figure 3 This is a schematic diagram of another semiconductor structure in a specific embodiment of the present invention; Figure 4 This is a diagram showing the relative positional relationship between another well region and the conductive lead-out component in a specific embodiment of the present invention; Figure 5 This is a flowchart of a method for forming a semiconductor structure according to a specific embodiment of the present invention; Figure 6This is a schematic diagram of a structure after a well region is formed in the substrate in a specific embodiment of the present invention; Figure 7 This is a schematic diagram of the structure after an epitaxial layer is formed on the substrate in a specific embodiment of the present invention; Figure 8 This is another structural schematic diagram after a well region is formed in the substrate according to a specific embodiment of the present invention; Figure 9 This is another structural schematic diagram of the present invention after the epitaxial layer is formed on the substrate; Figure 10 This is a schematic diagram of the structure after multiple trenches have been formed according to a specific embodiment of the present invention; Figure 11 This is a schematic diagram of the structure after the initial filling layer is formed in the trench according to a specific embodiment of the present invention.

[0019] Explanation of reference numerals in the attached figures 10 substrates 11 epitaxial layers 12-well region 121 body area 122 Burial Area 13 conductive connecting posts 131 Lower Layer Lead-out Area 132 Upper Layer Lead-out Area 14 Contact Electrodes C1 First bias current lead-out structure C2 First Sensing Voltage Lead-out Structure C3 Second Bias Current Lead-out Structure C4 Second Sensing Voltage Lead-out Structure C5 Third Bias Current Lead-in Structure 100 trench 110 Initial Fill Layer Detailed Implementation The specific embodiments of the semiconductor structure and its formation method provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0020] This specific embodiment provides a semiconductor structure. Figure 1 This is a schematic diagram of a semiconductor structure according to a specific embodiment of the present invention. For example... Figure 1 As shown, the semiconductor structure includes: Substrate 10 includes a first main surface and a second main surface that are relatively distributed along a first direction D1, and substrate 10 has a first conductivity type; Well region 12 is located within the substrate 10, and well region 12 has a second conductivity type, wherein the first conductivity type and the second conductivity type are opposite conductivity types; An epitaxial layer 11 covers the first main surface of the substrate 10, and the epitaxial layer 11 has the first conductivity type; The conductive lead-out assembly includes a plurality of conductive lead-out structures spaced apart along a second direction D2. Each of the conductive lead-out structures penetrates the epitaxial layer 11 at least along the first direction D1 and is electrically connected to the well region 12. The conductive lead-out structure is used to transmit a bias current to the well region 12. The second direction D2 is parallel to the first main surface of the substrate 10.

[0021] Specifically, the substrate 10 may be, but is not limited to, a silicon substrate. This specific embodiment uses a silicon substrate as an example for illustration. The substrate 10 includes a first main surface and a second main surface opposite to the first main surface along the first direction D1. The substrate 10 has a first conductivity type, for example, the substrate 10 is a P-type substrate. The well region 12 is located within the substrate 10, and the well region 12 has a second conductivity type, for example, the well region 12 is an N-type well region. The epitaxial layer 11 is formed on the first main surface of the substrate 10 by an epitaxial growth process, and the epitaxial layer covers the first main surface of the substrate 10. The conductive lead-out component is located above the well region 12. The conductive lead-out component includes a plurality of conductive lead-out structures spaced apart along the second direction D2. The conductive lead-out structures penetrate the epitaxial layer 11 at least along the first direction D1 and are electrically connected to the well region 12, thereby enabling the transmission of the bias current signal to the well region 12 through the conductive lead-out structures. In one example, if the semiconductor structure is a sensor, then after the bias current is transmitted to the well region 12, the well region 12 will generate a sensing voltage, and the conductive lead-out structure is also used to detect the sensing voltage generated in the well region 12. For example, the semiconductor structure can be a magnetic sensor such as a Hall sensor, and correspondingly, the well region 12 is a Hall well region, and the sensing voltage is a Hall voltage.

[0022] This specific embodiment, by placing the well region 12 within the substrate 10 and forming the epitaxial layer 11 on the substrate 10, increases the distance between the well region 12 and the metal interconnects formed in subsequent processes and located above the substrate. This reduces the interference of the magnetic field generated by the current flowing through the metal interconnects on the signal within the well region, improving the accuracy and reliability of the semiconductor structure detection. Furthermore, this specific embodiment, by providing a conductive lead-out component electrically connected to the well region above the well region, and the conductive lead-out component comprising multiple independently spaced conductive lead-out structures, allows the bias current signal to be transmitted to the well region through multiple conductive lead-out structures, ensuring stable operation of the semiconductor structure. For example, if the semiconductor structure is a sensor, the conductive lead-out structures in the conductive lead-out component are also used to acquire the sensing voltage (e.g., Hall voltage) generated within the well region 12, thereby enabling the detection of external environmental parameters (e.g., detection of external magnetic fields (including external magnetic field strength and direction)). That is, this specific embodiment does not change the detection method of the sensor, is compatible with the design of traditional sensor devices, and facilitates mass production. In addition, this specific embodiment does not require the setting of a large shielding metal, thereby avoiding the occupation of internal space of the semiconductor structure by a large shielding metal, improving the space utilization rate inside the semiconductor structure, and ensuring the manufacturing yield and manufacturing efficiency of the semiconductor structure.

[0023] In one example, if the semiconductor structure is a sensor, then three of the plurality of conductive leads serve as three bias current leads, and the other two of the plurality of conductive leads serve as two sensing voltage leads. The bias current lead-out structure and the sensing voltage lead-out structure are arranged alternately along the second direction D2.

[0024] For example, such as Figure 1As shown, the semiconductor structure is a five-contact vertical Hall device. The conductive lead-out assembly includes five conductive lead-out structures arranged sequentially at intervals along the second direction D2, with the first conductive lead-out structure serving as the first bias current lead-out structure C1, the second conductive lead-out structure serving as the first sensing voltage lead-out structure C2, the third conductive lead-out structure serving as the second bias current lead-out structure C3, the fourth conductive lead-out structure serving as the second sensing voltage lead-out structure C4, and the fifth conductive lead-out structure serving as the third bias current lead-out structure C5. In one example, when the semiconductor structure is a Hall sensor, when the Hall sensor detects an external magnetic field, the second bias current lead-out structure C3 is used to input a bias current signal, and the first bias current lead-out structure C1 and the third bias current lead-out structure C5 are used to output the bias current signal, thereby forming a [structure] in the well region 12. Figure 1 The solid arrow in the diagram indicates the current flow path. Under the influence of an external magnetic field, the charge carriers in the well region 12 are deflected by the Lorentz force, thereby generating a potential difference between the first sensing voltage lead-out structure C2 and the second sensing voltage lead-out structure C4, i.e., generating a sensing voltage. By measuring the magnitude and polarity of the sensing voltage, the strength and direction of the external magnetic field can be obtained.

[0025] In some embodiments, the conductive lead-out structure includes: A conductive connecting post 13 extends along the first direction D1, and the conductive connecting post 13 is electrically connected to the well region 12. Contact electrode 14 covers the end of the conductive connection post 13 that is away from the well region 12.

[0026] Specifically, the conductive lead-out structure includes the conductive connecting post 13 and the contact electrode 14. The conductive connecting post 13 is electrically connected to the well region 12 and the contact electrode 14 at opposite ends along the first direction D1, respectively. In one example, the conductive connecting post 13 is inserted into the well region 12 to increase the contact area between the conductive connecting post 13 and the well region 12, thereby reducing contact resistance. The size of the contact electrode 14 (e.g., the area of ​​the bottom surface of the contact electrode 14 facing the well region 12) is larger than the size of the conductive connecting post 13 (e.g., the area of ​​the top surface of the conductive connecting post 13 facing the contact electrode 14), thus ensuring a stable connection between the contact electrode 14 and the conductive connecting post 13, and also increasing the window for electrical connection between the contact electrode 14 and other subsequent electrical structures.

[0027] In some embodiments, the surface of the well region 12 facing away from the second main surface is flush with the first main surface of the substrate 10; or, The surface of the well region 12 facing away from the second main surface is lower than the first main surface of the substrate 10.

[0028] Figure 2 This is a diagram showing the relative positions of a well region and a conductive lead-out component in a specific embodiment of the present invention. In some embodiments, such as... Figure 1 and Figure 2 As shown, the well region 12 includes a body region 121 and a plurality of buried regions 122 located within the body region 121 and independent of each other. The plurality of buried regions 122 are electrically connected to the plurality of conductive lead-out structures one by one. The surface of the body region 121 facing away from the second main surface of the substrate 10 and the surface of the buried regions 122 facing away from the second main surface of the substrate 10 are flush with the first main surface of the substrate 10. The conductive connecting post 13 includes a conductive lead-out area electrically connected to the burial area 122, and the conductive lead-out area has the second conductivity type.

[0029] In some embodiments, the plurality of buried regions 122 are of the same size, and the projected area of ​​the conductive lead-out region on the first main surface of the substrate 10 is smaller than the projected area of ​​the buried region 122 on the first main surface of the substrate 10.

[0030] In some embodiments, the conductive lead-out region includes: The lower lead-out area 131 is located within the epitaxial layer 11 and is electrically connected to the buried area 122. The upper lead-out area 132 is located above the lower lead-out area 131. One end of the upper lead-out area 132 is electrically connected to the lower lead-out area 131, and the other end is electrically connected to the contact electrode 14.

[0031] For example, such as Figure 1 and Figure 2As shown, the well region 12 includes the body region 121 and a plurality of buried regions 122 located within the body region 121 and independent of each other. Both the body region 121 and the buried regions 122 have the second conductivity type. For example, both the body region 121 and the buried regions 122 are N-type doped regions, and the concentration of doped ions in the buried regions 122 is greater than the concentration of doped ions in the body region 121, so as to reduce the contact resistance between the conductive lead-out structure and the well region 12. The conductive connection post 13 includes a conductive lead-out region electrically connected to the buried region 122. The conductive lead-out region includes a lower lead-out region 131 (e.g., a deep well region) electrically connected to the buried region 122 and an upper lead-out region 132 (e.g., a lightly doped region) located above the lower lead-out region 131. The conductive lead-out region has the second conductivity type, meaning both the lower lead-out region 131 and the upper lead-out region 132 have the second conductivity type (e.g., both are N-type well regions), and the doping concentration of the lower lead-out region 131 is lower than that of the upper lead-out region 132. In one example, the contact electrode 14 is also formed by high-concentration ion doping; for example, the contact electrode 14 is also a heavily N-type doped region. In this specific embodiment, the conductive lead-out region is formed by implanting dopant ions into the epitaxial layer 11, thereby eliminating the need for deep silicon etching, which helps to further simplify the manufacturing process of the semiconductor structure and improve the manufacturing efficiency of the semiconductor structure. Meanwhile, since the conductive lead-out region is formed by ion implantation, by making the top surface of the well region 12 flush with the first main surface of the substrate 10, the ion implantation energy can be reduced, thus avoiding damage to the epitaxial layer 11 or the substrate 10 due to excessive implantation energy.

[0032] The conductive lead-out area includes the lower lead-out area 131 and the upper lead-out area 132 covering the surface of the lower lead-out area 131. This can both lead out signals in the well region 12 or transmit bias signals to the well region 12, while avoiding the problem of excessively high lead-out resistance of the conductive connection structure caused by direct lead-out through the deep well region, and facilitate compatibility with surface layer device processes.

[0033] Figure 3 This is a schematic diagram of another semiconductor structure in a specific embodiment of the present invention. Figure 4 This is a diagram showing the relative positions of another well region and a conductive lead-out component in a specific embodiment of the present invention. Figure 4 The solid arrows in the diagram represent the flow paths of the bias current signal within the well region 12 when the semiconductor structure detects an external magnetic field. In other embodiments, such as... Figure 3 and Figure 4 As shown, the surface of the well region 12 facing away from the second main surface is lower than the first main surface of the substrate 10; The conductive lead-out component also includes a plurality of trenches that penetrate the epitaxial layer 11 and extend to the well region 12, and a plurality of conductive connecting posts 13 are filled in the plurality of trenches.

[0034] In some embodiments, the conductive connecting post 13 is made of doped polycrystalline silicon.

[0035] For example, such as Figure 3 and Figure 4 As shown, the well region 12 is buried inside the substrate 10, meaning the top surface of the well region 12 (i.e., the surface of the well region 12 facing the epitaxial layer 11) is lower than the first main surface of the substrate 10. This further increases the distance between the well region 12 and the metal interconnects formed in subsequent processes and located above the substrate 10, further reducing the interference of the magnetic field generated by the current flowing through the metal interconnects on the signals (e.g., detection signals) within the well region 12, thereby further improving the accuracy and reliability of the semiconductor structure detection. The conductive lead-out component also includes multiple trenches penetrating the epitaxial layer 11 and extending to the well region 12. Multiple conductive connection pillars 13 are filled in the multiple trenches, and the material of the conductive connection pillars 13 is doped polysilicon. That is, the conductive connection pillars 13 are formed by filling the trenches with doped polysilicon, thereby helping to reduce the loss of the bias current and the sensing voltage during transmission, and further improving the performance of the semiconductor structure.

[0036] This specific embodiment also provides a method for forming a semiconductor structure. Figure 5 This is a flowchart illustrating the method for forming a semiconductor structure according to a specific embodiment of the present invention. A schematic diagram of the semiconductor structure formed in this specific embodiment can be found in [reference needed]. Figures 1-4 .like Figures 1-5 As shown, the method for forming the semiconductor structure includes the following steps: Step S51, a substrate 10 is provided, the substrate 10 including a first main surface and a second main surface that are relatively distributed along a first direction D1, and the substrate 10 having a first conductivity type; Step S52: A well region 12 is formed in the substrate 10, the well region 12 having a second conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types; Step S53: Form an epitaxial layer 11 covering the first main surface of the substrate 10, the epitaxial layer 11 having the first conductivity type; Step S54: Form a conductive lead assembly including a plurality of conductive lead structures spaced apart along a second direction D2. Each of the conductive lead structures penetrates the epitaxial layer 11 at least along the first direction D1 and is electrically connected to the well region 12. The conductive lead structure is used to transmit bias current to the well region 12. The second direction D2 is parallel to the first main surface of the substrate 10.

[0037] Figure 6 This is a schematic diagram of a structure after a well region is formed in the substrate according to a specific embodiment of the present invention. In some embodiments, the specific steps of forming the well region 12 in the substrate 10 include: Second type doped ions are implanted into the substrate 10 from the first main surface of the substrate 10 to form a body region 121; Second type doped ions are implanted into the substrate 10 from the first main surface of the substrate 10, forming a plurality of buried regions 122 in the body region 121. The concentration of second type doped ions in the buried regions 122 is higher than the concentration of second type doped ions in the body region 121. The surface of the body region 121 facing away from the second main surface of the substrate 10 and the surface of the buried regions 122 facing away from the second main surface of the substrate 10 are flush with the first main surface of the substrate 10 to form the well region 12 including the buried regions 122 and the body region 121.

[0038] For example, the substrate 10 is a P-type substrate. An active region is defined in the substrate 10, and N-type implantation is performed on the active region from the first main surface of the substrate 10 to form an N-type doped region, which serves as the body region 121. Next, multiple buried regions (e.g., five buried regions) are defined within the active region, and N-type implantation is again performed on the buried regions from the first main surface of the substrate 10 to form multiple buried regions spaced apart along the second direction D2, such as... Figure 6 As shown.

[0039] In some embodiments, the specific steps of forming a conductive lead assembly including a plurality of conductive lead structures spaced apart along the second direction D2 include: A plurality of conductive connection pillars 13 are formed at least within the epitaxial layer 11. The plurality of conductive connection pillars 13 are arranged at intervals along the second direction D2, and the plurality of conductive connection pillars 13 are all electrically connected to the well region 12. Multiple contact electrodes 14 are formed that are electrically connected to each of the multiple conductive connecting posts 13 in a one-to-one manner. The conductive connecting posts 13 and the contact electrodes 14 electrically connected to them together constitute a conductive lead-out structure.

[0040] In some embodiments, the specific steps of forming a plurality of conductive connection posts 13 located at least within the epitaxial layer 11, wherein the plurality of conductive connection posts 13 are spaced apart along the second direction D2, and wherein the plurality of conductive connection posts 13 are all electrically connected to the well region 12 include: The second type of doped ions are injected into the epitaxial layer 11 to form a plurality of conductive lead-out regions that are electrically connected to the plurality of buried regions 122 in a one-to-one manner, and the conductive lead-out regions are used as the conductive connection pillars 13.

[0041] Figure 7 This is a schematic diagram of a structure after an epitaxial layer has been formed on a substrate in a specific embodiment of the present invention. For example, after forming such... Figure 6 Following the well region 12 shown, a P-type epitaxial layer 11 is grown on the first main surface of the substrate 10 using an epitaxial growth process, as shown below. Figure 7 As shown. Next, the second type of doped ions are implanted into the epitaxial layer 11 to form a plurality of conductive lead-out regions electrically connected to the plurality of buried regions 122. The conductive lead-out regions include a lower lead-out region 131 electrically connected to the buried region 122 and an upper lead-out region 132 located above the lower lead-out region 131. The conductive lead-out regions have the second conductivity type, that is, both the lower lead-out region 131 and the upper lead-out region 132 have the second conductivity type (e.g., both are N-type well regions). Afterwards, the second doped ions are implanted into the epitaxial layer 11 again to form the contact electrode 14 located above the upper lead-out region 132, as shown. Figure 1 and Figure 2 As shown.

[0042] Figure 8 This is another structural schematic diagram after the formation of a well region within the substrate, according to a specific embodiment of the present invention. In some other embodiments, the specific steps for forming the well region 12 within the substrate 10 include: Second type doped ions are implanted into the substrate 10 from the first main surface of the substrate 10 to form the well region 12, wherein the surface of the well region 12 facing away from the second main surface is lower than the first main surface of the substrate 10.

[0043] Figure 9 This is another structural schematic diagram after the epitaxial layer is formed on the substrate according to a specific embodiment of the present invention. Figure 10 This is a schematic diagram of the structure after multiple trenches have been formed according to a specific embodiment of the present invention. Figure 11 This is a schematic diagram of the structure after the initial filling layer is formed in the trench according to a specific embodiment of the present invention. In some embodiments, such as Figure 9 , Figure 10 and Figure 11As shown, the specific steps for forming a conductive lead assembly comprising multiple conductive lead structures spaced at intervals along the second direction D2 include: The epitaxial layer 11 and a portion of the substrate 10 are etched to form a plurality of trenches 100 that penetrate the epitaxial layer 11 along the first direction D1 and extend to the well region 12; A plurality of conductive lead-out structures are formed, each corresponding to one of the plurality of trenches 100.

[0044] In some embodiments, the specific steps of forming a plurality of conductive lead-out structures that correspond one-to-one with filling the plurality of trenches 100 include: A polycrystalline silicon material including the second type of doped ions is deposited in the trench 100 to form an initial filling layer 110; The second type of doped ions are injected into the initial filling layer 110 to form a contact electrode 14, and the remaining initial filling layer 110 below the contact electrode 14 serves as a conductive connection post 13.

[0045] For example, the substrate 10 is a P-type substrate, an active region is defined in the substrate 10, and N-type implantation is performed from the first main surface of the substrate 10 into the active region to form an N-type well region 12. The top surface of the well region 12 is lower than the first main surface of the substrate 10. Figure 8 As shown. Next, an epitaxial layer 11 of type P is grown on the first main surface of the substrate 10 using an epitaxial growth process, as shown. Figure 9 As shown. Then, a deep silicon etching process is used to etch the epitaxial layer 11 and a portion of the substrate 10, forming a plurality of trenches 100 extending along the first direction D1 through the epitaxial layer 11 and extending to the well region 12. The bottom of the trenches 100 exposes the well region 12, as shown. Figure 10 As shown. Next, N-type heavily doped polycrystalline silicon material is deposited into the trench 100, forming an initial fill layer 110 within the trench 100 that is electrically connected to the well region 12. Second-type dopant ions are implanted into the initial fill layer 110 to form the contact electrode 14, with the remaining portion of the initial fill layer 110 below the contact electrode 14 serving as the conductive connection pillar 13. Subsequently, a metal material is deposited on the surface of the epitaxial layer 11 facing away from the substrate 10. The top surface of the contact electrode 14 reacts with the metal material to form a metal silicide, thereby reducing the contact resistance between the contact electrode 14 and subsequent electronic devices.

[0046] In some embodiments, three of the plurality of conductive lead-out structures serve as three bias current lead-out structures, and the other two of the plurality of conductive lead-out structures serve as two sensing voltage lead-out structures. The bias current lead-out structure and the sensing voltage lead-out structure are arranged alternately along the second direction D2.

[0047] The semiconductor structure and its formation method provided in this specific embodiment, by placing a well region within a substrate below the epitaxial layer and electrically connecting the well region through a conductive lead-out component that at least penetrates the epitaxial layer, wherein the conductive lead-out structure in the conductive lead-out component is used to transmit bias current to the well region, thereby increasing the distance between the well region and the metal interconnects formed in subsequent processes and located above the substrate, reducing the interference of the magnetic field generated by the current flowing through the metal interconnects on the signals within the well region, and improving the stability, accuracy, and reliability of the semiconductor structure performance. Furthermore, this specific embodiment eliminates the need for a large shielding metal, thereby avoiding the occupation of internal space by a large shielding metal, improving the space utilization within the semiconductor structure, and ensuring the manufacturing yield and efficiency of the semiconductor structure.

[0048] Furthermore, BCD (Bipolar-CMOS-DMOS) technology is a manufacturing process that integrates bipolar transistors (Bipolar), CMOS (Complementary Metal-Oxide-Semiconductor) devices, and DMOS (Double-Diffused Metal-Oxide-Semiconductor) power devices onto a single chip. The core flow of the BCD process includes substrate pretreatment, buried layer implantation, epitaxial growth, well implantation (e.g., deep N-well, N-well / P-well), source / drain implantation, and metallization. The semiconductor structure formation method provided in this specific embodiment aligns with the core flow of the BCD process without adding any special process steps. Simultaneously, the core of the BCD process is the integration of Bipolar transistors, CMOS, and DMOS devices onto the same chip. The semiconductor structure formed in this specific embodiment will not interfere with the working mechanisms of Bipolar transistors, CMOS, and DMOS; on the contrary, it can achieve synergistic adaptation with them. For these reasons, the semiconductor structure formation method provided in this specific embodiment is compatible with the BCD process, thereby helping to improve the manufacturing yield and productivity of semiconductor structures and expand their application areas.

[0049] It should be noted that the terms "comprising" and "having," and their variations, used in this invention document are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context; it should be understood that such use of data can be interchanged where appropriate. The term "one or more" depends at least in part on the context and can be used to describe features, structures, or characteristics in a singular sense, or in a plural sense to describe combinations of features, structures, or characteristics. The term "based on" can be understood as not necessarily intended to express an exclusive set of factors, but can instead, also at least in part on the context, allow for the presence of other factors that are not necessarily explicitly described. Furthermore, embodiments and features in embodiments of this invention can be combined with each other without conflict. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this invention. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar / identical parts between embodiments can be referred to mutually.

[0050] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a first main surface and a second main surface that are oppositely distributed along a first direction, and the substrate has a first conductivity type; A well region is located within the substrate, and the well region has a second conductivity type, wherein the first conductivity type and the second conductivity type are opposite conductivity types; An epitaxial layer is applied to the first main surface of the substrate, and the epitaxial layer has the first conductivity type; A conductive lead-out assembly includes a plurality of conductive lead-out structures spaced apart along a second direction, each of the conductive lead-out structures penetrating the epitaxial layer at least along a first direction and electrically connected to the well region, the conductive lead-out structures being used to transmit bias current to the well region, the second direction being parallel to the first main surface of the substrate.

2. The semiconductor structure according to claim 1, characterized in that, The conductive lead-out structure includes: A conductive connecting post extends along the first direction and is electrically connected to the well region. A contact electrode is provided, covering the end of the conductive connection post facing away from the well region.

3. The semiconductor structure according to claim 2, characterized in that, The surface of the well region facing away from the second main surface is flush with the first main surface of the substrate; or, The surface of the well region facing away from the second main surface is lower than the first main surface of the substrate.

4. The semiconductor structure according to claim 2, characterized in that, The well region includes a body region and multiple independent buried regions located within the body region. The multiple buried regions are electrically connected to the multiple conductive lead-out structures in a one-to-one correspondence. The surface of the body region away from the second main surface of the substrate and the surface of the buried regions away from the second main surface of the substrate are flush with the first main surface of the substrate. The conductive connecting post includes a conductive lead-out area electrically connected to the burial area, and the conductive lead-out area has the second conductivity type.

5. The semiconductor structure according to claim 4, characterized in that, The conductive lead-out area includes: The lower lead-out area is located within the epitaxial layer and is electrically connected to the buried area. The upper lead-out area is located above the lower lead-out area. One end of the upper lead-out area is electrically connected to the lower lead-out area, and the other end is electrically connected to the contact electrode.

6. The semiconductor structure according to claim 2, characterized in that, The surface of the well region facing away from the second main surface is lower than the first main surface of the substrate; The conductive lead-out component also includes multiple trenches that penetrate the epitaxial layer and extend to the well region, with multiple conductive connecting posts filling the multiple trenches one by one.

7. A method for forming a semiconductor structure, characterized in that, Includes the following steps: A substrate is provided, the substrate including a first main surface and a second main surface that are oppositely distributed along a first direction, the substrate having a first conductivity type; A well region is formed within the substrate, the well region having a second conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types; An epitaxial layer is formed covering the first main surface of the substrate, the epitaxial layer having the first conductivity type; A conductive lead assembly is formed comprising a plurality of conductive lead structures spaced apart along a second direction, each of the conductive lead structures penetrating the epitaxial layer at least along the first direction and electrically connected to the well region, the conductive lead structure being used to transmit bias current to the well region, the second direction being parallel to the first main surface of the substrate.

8. The method for forming a semiconductor structure according to claim 7, characterized in that, The specific steps for forming a well region within the substrate include: A second type of doped ions are implanted into the substrate from the first main surface of the substrate to form a bulk region; The second type of doped ions are implanted into the substrate from the first main surface of the substrate to form a plurality of buried regions in the body region. The concentration of the second type of doped ions in the buried regions is higher than the concentration of the second type of doped ions in the body region. The surface of the body region away from the second main surface of the substrate and the surface of the buried regions away from the second main surface of the substrate are flush with the first main surface of the substrate to form the well region including the buried regions and the body region.

9. The method for forming a semiconductor structure according to claim 8, characterized in that, The specific steps for forming a conductive lead assembly comprising a plurality of conductive lead structures spaced apart along a second direction include: A plurality of conductive connection pillars are formed at least within the epitaxial layer, the plurality of conductive connection pillars are spaced apart along the second direction, and the plurality of conductive connection pillars are all electrically connected to the well region. Multiple contact electrodes are formed that are electrically connected to the multiple conductive connecting posts in a one-to-one manner. The conductive connecting posts and the contact electrodes electrically connected to them together constitute the conductive lead-out structure.

10. The method for forming a semiconductor structure according to claim 9, characterized in that, The specific steps of forming at least a plurality of conductive connection pillars located within the epitaxial layer, wherein the plurality of conductive connection pillars are spaced apart along the second direction, and wherein each of the plurality of conductive connection pillars is electrically connected to the well region in contact include: The second type of doped ions are injected into the epitaxial layer to form a plurality of conductive lead-out regions that are electrically connected to the plurality of buried regions one by one, and the conductive lead-out regions are used as the conductive connection pillars.

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