Wafer cleaning method

Abstract

This application provides a wafer cleaning method, belonging to the field of semiconductor technology. The wafer cleaning method includes: providing a wafer, the wafer including a first region and a second region; forming a plurality of piezoelectric structures on the first region of the wafer, the piezoelectric structures including sequentially stacked electric field shielding layers and piezoelectric layers; performing a semiconductor manufacturing process to form a semiconductor structure on the second region, after forming the semiconductor structure, the surface of the wafer has carbon-containing organic matter; performing a two-fluid cleaning process on the surface of the wafer, the piezoelectric structures causing the generation of oxide groups during the two-fluid cleaning process, and using the oxide groups to remove the carbon-containing organic matter on the surface of the wafer. This application can efficiently and safely remove carbon-containing organic matter from wafers.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a wafer cleaning method. Background Technology

[0002] With the continuous development of semiconductor technology, the feature size of semiconductor devices is getting smaller and smaller, and the requirements for contaminants in semiconductor manufacturing processes are also getting higher and higher. Insufficient cleaning can lead to contaminant residues, which can seriously affect the performance of devices and production yield.

[0003] Organic contaminants are common pollutants in semiconductor manufacturing processes, primarily consisting of carbon-containing organic residues, including etching byproducts, polishing slurry residues, and photoresist residues. To improve the cleaning effect on carbon-containing organic residues, highly oxidizing organic cleaning solutions are typically used. For example, carboxylic acid (a mixture of sulfuric acid and hydrogen peroxide) is a common wet cleaning method that removes organic matter through oxidation.

[0004] In some scenarios (such as residual photoresist layers after ion implantation), the cleaning effect of the aforementioned highly oxidizing organic solutions is still difficult to guarantee, for example... Figure 1 As shown, after cleaning, carbon-containing organic matter 11 still partially remains on wafer 10. Figure 2 This is an enlarged schematic diagram of residual carbon-containing organic matter 11 on the wafer. Moreover, in some scenarios, highly oxidizing organic solutions may also corrode other semiconductor structures (such as copper processes, metal gate processes, etc.), affecting yield and creating reliability risks (unsafety). Summary of the Invention

[0005] In view of this, this application aims to provide a wafer cleaning method for efficiently and safely removing carbon-containing organic matter from wafers.

[0006] The wafer cleaning method provided in this application includes: A wafer is provided, the wafer including a first region and a second region, and a plurality of piezoelectric structures are formed on the first region of the wafer, the piezoelectric structures including an electric field shielding layer and a piezoelectric layer stacked sequentially; A semiconductor manufacturing process is performed to form a semiconductor structure on the second region, and after the semiconductor structure is formed, the surface of the wafer has carbon-containing organic matter. The surface of the wafer is subjected to a two-fluid cleaning process, in which the piezoelectric structure causes the generation of oxide groups during the two-fluid cleaning process, and the oxide groups are used to remove carbon-containing organic matter on the surface of the wafer.

[0007] Optionally, multiple piezoelectric structures protrude from the surface of the first region and are arranged in an array.

[0008] Optionally, the plurality of piezoelectric structures are arranged in a nanowire array structure, and the extension direction of the piezoelectric structures is the same as the extension direction of the gate structure of the wafer.

[0009] Optionally, the fluid in the two-fluid cleaning process includes an oxidizing etchant and an inert gas. The piezoelectric structure excites a polarized electric field under the action of the inert gas. The polarized electric field causes the etchant to generate the oxide groups, thereby removing at least a portion of the carbon-containing organic matter.

[0010] Optionally, the oxidizing etchant includes at least one of sulfuric acid, nitric acid, hydrogen peroxide, and ozone water; the oxidizing group is formed by the combination of a hole with molecules and / or groups in the etchant.

[0011] Optionally, the first area is a non-device area, and the second area is a device area.

[0012] Optionally, the piezoelectric structure further includes a protective layer that covers the sidewalls of the electric field shielding layer, the surface of the piezoelectric layer, and the sidewalls.

[0013] Optionally, the piezoelectric layer includes at least one of lithium tantalate, barium titanate, and zinc oxide; The material of the electric field shielding layer and / or the protective layer includes silicon oxide.

[0014] Optionally, the semiconductor manufacturing process includes heavily doped source / drain ion implantation, the semiconductor structure includes source / drain contact regions, and the carbon-containing organic material includes photoresist or photoresist residue after heavily doped source / drain ion implantation.

[0015] Optionally, the semiconductor manufacturing process includes at least one of patterning, etching, planarization, and ion implantation. The patterning process includes photolithography, and the corresponding carbon-containing organic material includes photoresist or photoresist residue; and / or, The etching process includes a dry etching process, and the corresponding carbon-containing organic matter includes polymers or polymer residues after dry etching; and / or, The planarization process includes a grinding process, and the corresponding carbonaceous organic matter includes grinding slurry or grinding slurry residue; and / or, The ion implantation process uses a photoresist layer as a mask, and the corresponding carbon-containing organic material includes photoresist that has been hardened after ion implantation or photoresist residue.

[0016] In summary, the unexpected effect of this application is that: a piezoelectric structure is formed in the first region of the wafer, and a piezoelectric layer is provided in the piezoelectric structure. During the two-fluid cleaning process, the piezoelectric layer generates a polarized electric field in the first region under the action of the two-fluid cleaning fluid. This polarized electric field causes the particles in the two fluid to generate electron-hole pairs and promotes the generation of more active and numerous oxide groups in the two-fluid cleaning fluid. These oxide groups are used to improve the removal ability of carbon-containing organic matter, thereby efficiently removing carbon-containing organic matter. Moreover, in the above-mentioned two-fluid cleaning process, the polarized electric field is formed in the first region, that is, the location of the polarized electric field is far away from the second region, which can reduce the impact on the semiconductor structure of the second region. This can avoid the impact of oxygen free radicals with strong oxidizing ability on the semiconductor structure of the device region in common dry etching (dry cleaning), and some oxide groups diffused into the second region can also improve the removal ability of carbon-containing organic matter in the second region. On the other hand, compared to the ultra-high oxidation capacity of oxygen free radicals in dry etching, two-fluid cleaning is essentially a wet process. By increasing the number and activity of oxide groups in two-fluid cleaning through polarized electric fields, carbon-containing organic matter can be removed in a gentler and safer manner, thus improving the safety of removing carbon-containing organic matter. Attached Figure Description

[0017] Figure 1 This is a schematic diagram showing the distribution of residual carbon-containing organic matter on a wafer.

[0018] Figure 2 This is an enlarged schematic diagram of a carbon-containing organic compound.

[0019] Figure 3 This is a flowchart of a wafer cleaning method provided in an embodiment of this application.

[0020] Figure 4 This is a schematic diagram showing the sequential formation of a shielding material and a piezoelectric material on a wafer, according to an embodiment of this application.

[0021] Figure 5 This is a schematic diagram illustrating the graphical formation of an electric field shielding layer and a piezoelectric layer (stacked structure) according to an embodiment of this application.

[0022] Figure 6 This is a top view of a wafer-on-a-chip stacked structure provided in an embodiment of this application.

[0023] Figure 7 This is a schematic diagram of the formation of a protective layer and a piezoelectric structure provided in an embodiment of this application.

[0024] Figure 8 This is a schematic diagram of forming a gate material and a first patterned photoresist layer on a wafer, as provided in an embodiment of this application.

[0025] Figure 9Schematic diagram of forming a gate structure and removing a first patterned photoresist layer provided by an embodiment of the present application.

[0026] Figure 10 Schematic diagram of forming a second patterned photoresist layer and performing a lightly doped ion implantation provided by an embodiment of the present application.

[0027] Figure 11 Schematic diagram of removing a second patterned photoresist layer and forming a sidewall structure provided by an embodiment of the present application.

[0028] Figure 12 Schematic diagram of forming a third patterned photoresist layer and performing a heavily doped ion implantation provided by an embodiment of the present application.

[0029] Figure 13 Schematic diagram of performing a two-fluid cleaning process to remove the photoresist layer provided by an embodiment of the present application.

[0030] In the accompanying drawings: Figures 1 to 2 where: 10 - wafer; 11 - carbon-containing organic matter.

[0031] Figures 4 to 13 where: 100 - wafer; 101 - trench isolation structure; A1 - first region; A2 - second region; 201a - shielding material; 203a - piezoelectric material; 201 - electric field shielding layer; 203 - piezoelectric layer; 205 - stacked structure; 207 - protective layer; 210 - piezoelectric structure; 301 - gate material; 303 - first patterned photoresist layer; 305 - gate structure; 307 - second patterned photoresist layer; 309 - lightly doped structure; 311 - sidewall structure; 313 - third patterned photoresist layer; 315 - heavily doped contact region. Detailed embodiments

[0032] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present application.

[0033] The present application provides a wafer cleaning method. Figure 3 Flow chart of the wafer cleaning method provided by an embodiment of the present application. As Figure 3 shown, the wafer cleaning method provided by an embodiment of the present application includes: S100: Provide a wafer, the wafer including a first region and a second region, on which a plurality of piezoelectric structures are formed, the piezoelectric structures including an electric field shielding layer, a piezoelectric layer and a protective layer stacked sequentially; S200: Perform a semiconductor manufacturing process to form a semiconductor structure on the second region, wherein after the semiconductor structure is formed, the surface of the wafer has a carbon-containing organic material. S300: Perform a two-fluid cleaning process on the surface of the wafer, wherein the piezoelectric structure causes oxide groups to be generated during the two-fluid cleaning process, and the oxide groups are used to remove carbon-containing organic matter on the surface of the wafer.

[0034] Figures 4-13 This is a schematic diagram of the structure corresponding to the relevant steps of a wafer cleaning method provided in an embodiment of this application. Next, we will combine... Figures 4-13 The wafer cleaning method provided in this application is described in detail.

[0035] First, such as Figures 4-7 As shown, in step S100, a wafer 100 is provided. The wafer 100 includes a first region A1 and a second region A2. A plurality of piezoelectric structures 210 are formed on the first region A1 of the wafer 100. The piezoelectric structure 210 includes an electric field shielding layer 201 and a piezoelectric layer 203 stacked sequentially.

[0036] The material of wafer 100 can be silicon (Si), germanium (Ge), silicon-germanium (GeSi), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), silicon carbide (SiC), gallium nitride (GaN), indium phosphide (InP), zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc., or it can be an organic semiconductor material or other semiconductor materials known in the art. The surface of wafer 100 may also have functional structures, such as isolation structures, active regions, etc. Among them, the first region A1 can be a non-device region, such as a dicing region, and the second region A2 can be a device region used to form a semiconductor structure.

[0037] In such Figure 4 In one example, wafer 100 has a trench isolation structure 101 and an active region (not shown), and is in a process state where a gate structure and a source / drain structure are to be formed. The main processes to be performed include photolithography, etching, and ion implantation. In other examples, wafer 100 may also be in a process state where other semiconductor structures are to be formed, and the main processes to be performed include any one or more of polishing, photolithography, etching, and ion implantation.

[0038] like Figure 4As shown, the steps for forming the piezoelectric structure 210 include: sequentially forming a shielding material 201a and a piezoelectric material 203a on the surface of the wafer 100 (first region A1 and second region A2). The shielding material 201a forms an electric field shielding layer 201 to shield (or isolate) the influence of the polarized electric field generated by the piezoelectric layer 203 on the wafer 100, preventing carrier migration in the wafer 100, weakening the polarized electric field generated in the piezoelectric material 203a, and even interfering with or affecting the electrical performance of the device region. The material of the shielding material 201a may include, but is not limited to, insulating materials such as silicon oxide and silicon nitride. The piezoelectric material 203a forms the piezoelectric layer 203 to excite a polarized electric field under high-speed ion action (impact). The material of the piezoelectric material 203a may be any suitable material with a piezoelectric effect, such as lithium tantalate, barium titanate, and zinc oxide.

[0039] like Figure 5 As shown, the shielding material 201a and the piezoelectric material 203a are patterned, and the piezoelectric material 203a and the shielding material 201a in the second region A2 and a portion of the piezoelectric material 203a and the shielding material 201a in the first region A1 are removed. The remaining shielding material 201a on the first region A1 is used as the electric field shielding layer 201, and the remaining piezoelectric material 203a is used as the piezoelectric layer 203. The surface of the wafer 100 in the second region A2 and a portion of the surface of the wafer 100 in the first region A1 are exposed. In this process, a mask (e.g., a patterned photoresist layer) can be used to sequentially etch (e.g., wet etching) the piezoelectric material 203a and the shielding material 201a to achieve patterning, so that multiple piezoelectric layers 203 are stacked on multiple electric field shielding layers 201. Each stacked electric field shielding layer 201 and piezoelectric layer 203 can be a stacked structure 205. These stacked structures 205 are all located in the first region A1 and protrude from the surface of the first region A1, and can be arranged in an array in the planar direction.

[0040] In one example, multiple stacked structures 205 protrude from the surface of the first region A1 and are arranged in an array. Furthermore, the multiple piezoelectric structures 210 can be arranged as a nanowire array structure, so that the multiple piezoelectric layers 203 in the multiple stacked structures 205 have a high specific surface area, which is beneficial to improving the efficiency of exciting the polarization electric field.

[0041] Figure 6 This is a top view schematic diagram of a stacked structure 205 provided in one embodiment of this application. In one example, as... Figure 6As shown, the extension direction of the stacked structure 205 can be the same as the extension direction of the gate structure 305 (dashed box) formed on the subsequent wafer 100, and it has the same or similar size and spacing as the subsequently formed gate structure 305 (i.e., the same or similar layout design). For example, in the planar direction (the direction of the wafer 100 surface), the length and width of the stacked structure 205 are the same or similar to the length and width of the subsequently formed gate structure 305, and the spacing between the stacked structures 205 is the same or similar to the spacing between the subsequently formed gate structures 305. In other words, a portion of the layout pattern used to form the gate structure is used as the layout pattern for forming the stacked structure 205 in the first region A1, for patterning the shielding material 201a and the piezoelectric material 203a; or, the layout pattern originally used to form the gate structure in the non-device region is used for patterning the shielding material 201a and the piezoelectric material 203a, thereby simplifying the setup.

[0042] like Figure 7 As shown, a protective layer 207 is also formed to cover the outer walls of the electric field shielding layer 201 and the piezoelectric layer 203, and the stacked structure 205 covered with the protective layer 207 serves as the piezoelectric structure 210. The protective layer 207 protects the stacked structure 205 and prevents the piezoelectric layer 203 from being damaged by liquids or gases in subsequent processes. Therefore, the protective layer 207 can also conformally cover the outer walls of the stacked structure 205, including the surface and sidewalls of the piezoelectric layer 203. In one example, the material of the protective layer 207 can be an insulating material that can effectively transmit the polarized electric field; for example, the protective layer 207 is silicon oxide, and the thickness of the silicon oxide is relatively thin (less than the thickness of the electric field shielding layer 201). In some examples, it is also feasible for the protective layer 207 to also cover the surface of the second region A2.

[0043] Next, as Figures 8-11 As shown, step S200 is performed to execute a semiconductor manufacturing process to form a semiconductor structure on the second region A2. After the semiconductor structure is formed, the surface of the wafer 100 has carbon-containing organic matter.

[0044] In some embodiments, the semiconductor structure formed on the second region A2 may include a gate structure 305 and a source / drain structure, and the carbon-containing organic matter on the surface of the wafer 100 may be photoresist after ion implantation or photoresist residue.

[0045] Specifically, such as Figures 8-9 As shown, a gate structure 305 (which can be a real gate structure or a pseudo-gate structure) is formed on the second region A2. The steps for forming the gate structure 305 may include, for example, as follows: Figure 8As shown, a gate material 301 (the material of which includes, for example, polysilicon) is formed to cover the first region A1 and the second region A2, and a first patterned photoresist layer 303 is formed on the gate material 301. The first patterned photoresist layer 303 is located above the second region A2 and is used to define the pattern of the gate structure 305.

[0046] like Figure 9 As shown, a dry etching process is performed to remove a portion of the gate material 301 in the first region A1 and the second region A2, using the remaining gate material 301 in the second region A2 as the gate structure 305, and removing the first patterned photoresist layer 303. In one example, an ashing process and / or a wet process can be used to remove the first patterned photoresist layer 303.

[0047] like Figures 10-12 As shown, a source / drain structure is formed in the active regions on both sides of the gate structure 305. This source / drain structure may include a lightly doped structure 309 and a heavily doped contact region 315. The steps for forming the source / drain structure may include, for example, as follows: Figure 10 As shown, a second patterned photoresist layer 307 is formed on the surface of wafer 100. The second patterned photoresist layer 307 has an opening in the second region A2, exposing the gate structure 305 and the active regions (source and drain regions) on both sides. Lightly doped ion implantation is performed to form a lightly doped structure 309 in the active regions on both sides of the gate structure 305.

[0048] like Figure 11 As shown, the second patterned photoresist layer 307 is removed, forming a sidewall structure 311 located on the sidewall of the gate structure 305. In one example, since the impact of lightly doped ion implantation on the photoresist layer is relatively small, an ashing process and / or a wet process can be used to remove the second patterned photoresist layer 307 (reducing the probability of residual carbon-containing organic matter after removal), simplifying the process. In other examples, after removing the second patterned photoresist layer 307 using the aforementioned ashing process and / or wet process, a two-fluid cleaning process can be performed on the surface of the wafer 100 to remove residual carbon-containing organic matter (residue from ion implantation), ensuring no residual carbon-containing organic matter while also considering cost. In still other examples, a two-fluid cleaning process can be performed directly on the wafer 100 to remove the second patterned photoresist layer 307 (containing carbon-containing organic matter), avoiding the generation of residual carbon-containing organic matter.

[0049] Furthermore, in some embodiments, when performing a lightly doped ion implantation process to form a lightly doped structure 309, a patterned photoresist layer may not be formed, thus saving the aforementioned step of removing the second patterned photoresist layer 307.

[0050] like Figure 12As shown, a third patterned photoresist layer 313 is formed on the surface of wafer 100. The third patterned photoresist layer 313 has an opening in the second region A2 to expose the gate structure 305, the sidewall structure 311, and the active regions on both sides. A heavily doped source / drain ion implantation process is performed to form a heavily doped contact region 315 in the active region (i.e., the lightly doped structure 309) on the side of the sidewall structure 311 away from the gate structure 305. It is understandable that because the implantation dose of the heavily doped source / drain ion implantation process is much larger, 1 to 3 orders of magnitude larger than that of the lightly doped ion implantation process, and the implantation time is much longer than that of the lightly doped ion implantation process, the third patterned photoresist layer 313 undergoes significant hardening (even forming a hardened layer) during the heavily doped source / drain ion implantation process, which is very unfavorable for removal and cleaning.

[0051] Next, as Figure 13 As shown, in step S300, a two-fluid cleaning process is performed on the surface of wafer 100. The piezoelectric structure 210 causes oxide groups to be generated during the two-fluid cleaning process, and the oxide groups are used to remove carbon-containing organic matter on the surface of wafer 100.

[0052] In some embodiments, before performing the two-fluid cleaning process, a dry process (e.g., ashing) and / or a wet process can be used to remove some of the carbon-containing organic matter (i.e., the third patterned photoresist layer 313) to expose the surface of the wafer 100, where there are residual carbon-containing organic matter (e.g., photoresist residue). Then, the surface of the wafer 100 is subjected to a two-fluid cleaning process to remove the residual carbon-containing organic matter (photoresist residue), achieving complete removal of the carbon-containing organic matter while considering cost. Furthermore, the presence of the two-fluid cleaning process can correspondingly reduce the processing intensity or time of the dry and / or wet processes, thereby helping to reduce the adverse effects of the corresponding processes on the device.

[0053] In some other embodiments of this application, a two-fluid cleaning process can also be performed directly on the surface of the wafer 100, that is, a two-fluid cleaning process can be performed on the third patterned photoresist layer 313 (containing carbon organic matter) to remove the carbon organic matter and avoid the generation of carbon organic matter residue. The specific method can refer to the aforementioned method of removing carbon organic matter residue by using two-fluid cleaning process.

[0054] In the two-fluid cleaning process, the two fluids are an oxidizing etchant (cleaning agent) and an inert gas. During the two-fluid cleaning process, the high-speed moving inert gas acts (impacts) on the piezoelectric structure 210, providing kinetic energy to excite the piezoelectric structure 210 to generate a polarized electric field. This polarized electric field causes particles in the two fluids to generate electron-hole pairs. These electron-hole pairs combine with particles in the fluid (molecules and / or groups in the etchant), promoting the etchant to generate more active and numerous oxide groups, thereby improving its ability to remove carbon-containing organic matter. The oxide groups generated by the polarized electric field have high reactivity and extremely short diffusion length, thus exhibiting surface localization (regionality). Moreover, the polarized electric field is formed near the piezoelectric structure 210 in the first region A1 (i.e., the non-device region), thus avoiding the influence of oxygen free radicals with strong oxidizing capabilities on the semiconductor structure of the device region in common dry etching (dry cleaning). Understandably, region A1, being a non-device region, is significantly affected by ion implantation due to the large area of ​​the photoresist layer. It is also heavily influenced by residual carbonaceous organic matter. The oxide groups generated by the polarized electric field directly act on region A1, directly enhancing its ability to remove carbonaceous organic matter. Similarly, the small number of oxide groups diffusing into region A2 also contribute to improving its removal capacity. Furthermore, compared to the extremely high oxidation capacity (indiscriminately high activity) of oxygen free radicals in dry etching, two-fluid cleaning is essentially a wet process. By increasing the number and activity of oxide groups in two-fluid cleaning through a polarized electric field, carbonaceous organic matter can be removed in a gentler and safer manner.

[0055] In some examples, the carbonaceous organic matter may include photoresist or photoresist residue; the oxidizing etchant may include any one or a mixture of deionized water, such as sulfuric acid, nitric acid, hydrogen peroxide, or ozone water; the inert gas may include nitrogen and / or argon; and the oxidizing group may be a product of the combination of a hole with water, hydroxyl groups, hydrogen peroxide, or ozone molecules in the etchant. In other examples of this application, other corresponding oxidizing etchants may be selected depending on the type of carbonaceous organic matter for the two-fluid cleaning process.

[0056] It should be noted that the semiconductor manufacturing process used in the wafer cleaning method provided in this application is not limited to the specific embodiments described above. Semiconductor manufacturing processes in which the wafer cleaning method of this application can be applied may include patterning process, etching process, deposition process, planarization process and ion implantation process.

[0057] In one example, the patterning process for applying the wafer cleaning method of this application includes a photolithography process, and the corresponding carbon-containing organic matter includes photoresist or photoresist residue.

[0058] In one example, the etching process for applying the wafer cleaning method of this application includes a dry etching process, and the corresponding carbon-containing organic matter includes polymers or polymer residues after dry etching.

[0059] In one example, the planarization process of the wafer cleaning method of this application includes a polishing process, and the corresponding carbon-containing organic matter includes polishing slurry or polishing slurry residue.

[0060] In one example, the ion implantation process using the wafer cleaning method of this application uses a photoresist layer as a mask, and the corresponding carbon-containing organic matter includes photoresist that has been hardened after ion implantation or photoresist residue.

[0061] In summary, this application provides a wafer cleaning method, which includes: providing a wafer, the wafer including a first region and a second region; forming a plurality of piezoelectric structures on the first region of the wafer, the piezoelectric structures including an electric field shielding layer and a piezoelectric layer stacked sequentially; performing a semiconductor manufacturing process to form a semiconductor structure on the second region, after forming the semiconductor structure, the surface of the wafer has carbon-containing organic matter; performing a two-fluid cleaning process on the surface of the wafer, the piezoelectric structures causing the generation of oxide groups during the two-fluid cleaning process, and using the oxide groups to remove the carbon-containing organic matter on the surface of the wafer. An unexpected effect of this application is that: the piezoelectric structure formed in the first region of the wafer, with a piezoelectric layer in the piezoelectric structure, generates a polarized electric field in the first region under the action of the two-fluid cleaning fluid during the two-fluid cleaning process. This polarized electric field causes particles in the two fluid to generate electron-hole pairs, and promotes the generation of more active and numerous oxide groups in the two-fluid cleaning fluid. These oxide groups enhance the removal capacity of carbon-containing organic matter, thereby efficiently removing the carbon-containing organic matter. Furthermore, in the aforementioned two-fluid cleaning process, the polarized electric field is formed in the first region, meaning the location of the polarized electric field is far from the second region. This reduces the impact on the semiconductor structure of the second region, thus avoiding the influence of highly oxidizing oxygen free radicals, which are common in dry etching (dry cleaning), on the semiconductor structure of the device region. The partial diffusion of oxide groups into the second region also enhances the removal capacity of carbon-containing organic matter in the second region. On the other hand, compared to the extremely high oxidizing power of oxygen free radicals in dry etching, two-fluid cleaning is essentially a wet process. By increasing the number and activity of oxide groups in two-fluid cleaning through the polarized electric field, carbon-containing organic matter can be removed in a gentler and safer manner, thus improving the safety of carbon-containing organic matter removal.

[0062] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0063] It should also be noted that although preferred embodiments have been disclosed above, these embodiments are not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application, or modify them into equivalent embodiments, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application, without departing from the content of the technical solutions of this application, shall still fall within the scope of protection of the technical solutions of this application.

[0064] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0065] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and is not intended to limit the scope of this application. It must be noted that the singular forms “a” and “an” as used herein include plural bases unless the context clearly indicates the opposite. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood as having the definition of logical “or”, not logical “exclusive OR”, unless the context clearly indicates the opposite. Furthermore, implementations of the methods and / or devices in the embodiments of this application may include performing selected tasks manually, automatically, or in combination.

Claims

1. A wafer cleaning method, characterized in that, include: A wafer is provided, the wafer including a first region and a second region, and a plurality of piezoelectric structures are formed on the first region of the wafer, the piezoelectric structures including an electric field shielding layer and a piezoelectric layer stacked sequentially; A semiconductor manufacturing process is performed to form a semiconductor structure on the second region, and after the semiconductor structure is formed, the surface of the wafer has carbon-containing organic matter. The surface of the wafer is subjected to a two-fluid cleaning process, in which the piezoelectric structure causes the generation of oxide groups during the two-fluid cleaning process, and the oxide groups are used to remove carbon-containing organic matter on the surface of the wafer.

2. The wafer cleaning method according to claim 1, characterized in that, Multiple piezoelectric structures protrude from the surface of the first region and are arranged in an array.

3. The wafer cleaning method according to claim 2, characterized in that, The piezoelectric structures are arranged in a nanowire array structure, and the extension direction of the piezoelectric structures is the same as the extension direction of the gate structure of the wafer.

4. The wafer cleaning method according to claim 1, characterized in that, The fluid used in the two-fluid cleaning process includes an oxidizing etchant and an inert gas. The piezoelectric structure is excited by the inert gas to generate a polarized electric field, which causes the etchant to produce the oxide groups in order to remove at least a portion of the carbon-containing organic matter.

5. The wafer cleaning method according to claim 4, characterized in that, The oxidizing etchant includes at least one of sulfuric acid, nitric acid, hydrogen peroxide, and ozone water; the oxidizing group is formed by the combination of a hole with molecules and / or groups in the etchant.

6. The wafer cleaning method according to claim 1, characterized in that, The first area is a non-device area, and the second area is a device area.

7. The wafer cleaning method according to claim 1, characterized in that, The piezoelectric structure further includes a protective layer that covers the sidewalls of the electric field shielding layer, the surface of the piezoelectric layer, and the sidewalls.

8. The wafer cleaning method according to claim 7, characterized in that, The piezoelectric layer includes at least one of lithium tantalate, barium titanate, and zinc oxide; The material of the electric field shielding layer and / or the protective layer includes silicon oxide.

9. The wafer cleaning method according to any one of claims 1 to 8, characterized in that, The semiconductor manufacturing process includes heavily doped source / drain ion implantation, the semiconductor structure includes source / drain contact regions, and the carbon-containing organic material includes photoresist or photoresist residue after heavily doped source / drain ion implantation.

10. The wafer cleaning method according to any one of claims 1 to 8, characterized in that, The semiconductor manufacturing process includes at least one of patterning, etching, planarization, and ion implantation. The patterning process includes photolithography, and the corresponding carbon-containing organic material includes photoresist or photoresist residue; and / or, The etching process includes a dry etching process, and the corresponding carbon-containing organic matter includes polymers or polymer residues after dry etching; and / or, The planarization process includes a grinding process, and the corresponding carbonaceous organic matter includes grinding slurry or grinding slurry residue; and / or, The ion implantation process uses a photoresist layer as a mask, and the corresponding carbon-containing organic material includes photoresist that has been hardened after ion implantation or photoresist residue.

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