Packaging unit and method for manufacturing a packaging unit, package

Abstract

The application relates to the technical field of packaging structures, and particularly provides a packaging unit, a preparation method thereof and a packaging body. The packaging unit comprises unit core boards and a medium buffer part. The number of the unit core boards is at least two, and the unit core boards are stacked along a first direction. Any unit core board has a conductive path penetrating through opposite surfaces of the unit core board in the first direction, and adjacent unit core boards in the first direction are connected through the conductive path. The medium buffer part comprises a first medium layer and a second medium layer. The first medium layer is arranged between two adjacent unit core boards and is in contact with opposite surfaces of the two adjacent unit core boards. The unit core boards and the first medium layer are alternately stacked along the first direction and form a stacked body. The second medium layer at least wraps an outer side of the stacked body in the first direction. In the first direction, at least part of the orthographic projection of the conductive path on the unit core board is located outside the orthographic projection of the second medium layer on the unit core board. The application provides a packaging unit with a high processing yield.

Description

Technical Field

[0001] This application belongs to the field of packaging structure technology, and more specifically, relates to a packaging unit and its preparation method and packaging body. Background Technology

[0002] As electronic devices move towards miniaturization and high-density integration, traditional chip packaging units are cut from packaging master molds. However, in related technologies, packaging master molds that have undergone layer-addition processing are prone to cracking during cutting, which in turn affects the processing yield and reliability of the final packaged units.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] This application provides a packaging unit and its preparation method, as well as a packaging body, to improve the processing yield and reliability of the packaging unit to at least a certain extent.

[0005] To achieve the above objectives, the technical solution adopted in this application is as follows: In a first aspect, this application provides a packaging unit, including a unit core board and a dielectric buffer portion. The number of unit core boards is at least two and they are stacked along a first direction. Each unit core board has a conductive path penetrating its two opposing surfaces in the first direction. Adjacent unit core boards in the first direction are connected through the conductive path. The dielectric buffer portion includes a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed between two adjacent unit core boards and contacts the opposing surfaces of the adjacent unit core boards. The unit core boards and the first dielectric layer are alternately stacked along the first direction to jointly form a stacked body. The second dielectric layer at least covers the outer surface of the stacked body in the first direction. In the first direction, at least a portion of the orthographic projection of the conductive path onto the unit core board is located outside the orthographic projection of the second dielectric layer onto the unit core board.

[0006] In the packaging unit provided in this application embodiment, by filling the space between adjacent different unit core boards, the warpage of the unit core boards can be improved, the overall stress of the packaging unit can be reduced, and the processing yield and reliability of the prepared packaging unit can be improved. In addition, the second dielectric layer that wraps the unit core board and the first dielectric layer can further provide better protection for the side of the unit core board in the first direction, thereby reducing the possibility of cracks and defects in the unit core board during production, handling and use by buffering external force when external force is applied to the unit core board, and further improving the reliability of the packaging unit.

[0007] Optionally, the unit core board further includes a unit core substrate, the unit core substrate having a first surface and a second surface opposite to each other in the first direction, and the unit core substrate further having a through hole penetrating the first surface and the second surface; The conductive path includes a first conductive element and a second conductive element. The first conductive element is disposed on the unit core substrate through the through hole and covers part of the first surface and part of the second surface in the first direction. The second conductive element is connected to the first conductive element and is located on the side of the first conductive element facing away from the unit core substrate. Two adjacent unit core substrates are bonded together through the second conductive element.

[0008] Optionally, the second conductive elements on different unit core boards are bonded together by interatomic bonding forces.

[0009] Optionally, in the first direction, the orthographic projection of all the conductive paths on the unit core board lies within the orthographic projection outer contour of the first dielectric layer on the unit core board.

[0010] Optionally, the first conductive element and the second conductive element are made of the same material; And / or, the first dielectric layer is in contact with the surfaces of the first conductive element and the second conductive element; And / or, in the first direction, the thickness of the unit core substrate is less than or equal to 300 μm.

[0011] In a second aspect, this application provides a method for fabricating a packaging unit, comprising: At least two unit core boards are obtained, each of the unit core boards having a conductive path extending through its two opposite surfaces, and at least one of the two opposite surfaces of the unit core board is provided with a sacrificial layer, wherein the conductive path is partially exposed relative to the sacrificial layer. Align the different unit core boards along the first direction so that the ends of the conductive paths on the different unit core boards come into contact with each other, and the sacrificial layers on the different unit core boards come into contact with each other; The conductive paths that are in contact are bonded to fix different unit core boards through the conductive paths. At the same time or after the bonding process, the sacrificial layer is removed to form a gap between adjacent unit core boards. A dielectric material is filled outside the unit core board to form a dielectric buffer part. The dielectric buffer part includes a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed between two adjacent unit core boards and is in contact with the opposite surface of the adjacent unit core boards. The unit core boards and the first dielectric layer are alternately stacked along a first direction to form a stacked body. The second dielectric layer at least covers the outer side of the stacked body in the first direction. In the first direction, at least a portion of the orthographic projection of the conductive path onto the unit core board is located outside the orthographic projection of the second dielectric layer onto the unit core board.

[0012] In the packaging unit fabrication method provided in this application embodiment, by performing subsequent bonding processing on the unit core board obtained after cutting, the problems that are prone to occur during the cutting process of the organic and glass hybrid structure after the layering process can be effectively avoided, thereby helping to improve the problems of low processing yield and poor reliability of the packaging unit. In addition, the above-mentioned fabrication process also sets a sacrificial layer between the unit core boards. This sacrificial layer can provide certain support during the bonding process of the unit core board, thereby helping to reduce the difficulty of the bonding process and improve the bonding yield. In addition, the above-mentioned bonding process is used to bond multiple conductive paths at the same time, which has high processing efficiency and reduces the area to be bonded, thereby reducing the process difficulty and the potential risk of defects. The dielectric buffer part prepared after bonding not only avoids the possibility of stress caused by thermal expansion during the bonding process acting on the unit core board, reducing the requirements for dielectric materials, but also provides better wrapping and protection for the unit core board, thereby improving the reliability of the prepared packaging unit in subsequent processing, handling and use.

[0013] Optionally, the step of obtaining at least two unit core boards, each of which has a conductive path penetrating its two opposing surfaces, and at least one of the opposing surfaces of the unit core board being provided with a sacrificial layer, wherein the conductive path is partially exposed relative to the sacrificial layer, includes: Obtain a glass master plate, which has a preset cutting groove; The glass master plate is processed to obtain at least two unit core plates. Each unit core plate has a conductive path that penetrates its two opposing surfaces in the first direction, and a sacrificial layer is provided on at least one of the two opposing surfaces. The conductive path is partially exposed relative to the sacrificial layer. The processing includes: Conductive pathways are formed on the glass master plate, penetrating its two opposing surfaces. The number of conductive pathways is at least two and they are arranged at intervals from the cutting path. A sacrificial layer is formed on at least one of the two opposing surfaces of the glass master plate, and the conductive pathways are partially exposed relative to the sacrificial layer. The glass master plate, on which the conductive path and the sacrificial layer are formed, is cut along the cutting path to obtain the unit core plate; Alternatively, the process may include: The glass master plate is cut along the cutting path to obtain at least two unit core substrates. The unit core substrates have a first surface and a second surface opposite to each other in the first direction, and are also provided with through holes penetrating the first surface and the second surface. The conductive path penetrating the through hole is prepared on the unit core substrate, and a sacrificial layer covering at least one of the first surface and the second surface is formed to obtain the unit core board.

[0014] Optionally, the step of forming conductive pathways penetrating both opposing surfaces of the glass master, wherein the number of conductive pathways is at least two and they are spaced apart from the cutting paths, and forming a sacrificial layer on at least one of the opposing surfaces of the glass master, wherein the conductive pathways are partially exposed relative to the sacrificial layer, includes: A first conductive element is prepared on the glass master plate, the glass master plate is provided with the through hole, and the first conductive element covers the inner wall of the through hole and the two side portions of the surface of the glass master plate in the first direction; A sacrificial material layer is prepared on at least one of the two opposing surfaces of the glass master, the sacrificial material layer having a first opening through which a portion of the surface of the first conductive element is exposed relative to the sacrificial material layer; A second conductive material component connected to the first conductive component is prepared within the first opening; The sacrificial material layer and the second conductive material are planarized to form the sacrificial layer and the second conductive element, which together with the first conductive element constitute the conductive path.

[0015] Optionally, the bonding process includes a direct bonding process to directly bond the contacting conductive pathways and form atomic bonds between the ends of the contacting conductive pathways.

[0016] Optionally, the bonding process further includes annealing after the direct bonding process to form cross-interface grains between the ends of the contacting conductive pathways.

[0017] Optionally, the step of removing the sacrificial layer to form a gap between adjacent unit core boards during or after the bonding process includes: removing the sacrificial layer after the bonding process; or, the sacrificial layer decomposes during the bonding process, so that the removal of the sacrificial layer is performed synchronously with the bonding process.

[0018] Optionally, the medium material includes organic materials, and the coefficient of thermal expansion of the medium material is less than or equal to a preset coefficient of thermal expansion, and the Young's modulus of the medium material is less than or equal to a preset modulus; And / or, the step of filling the outer surface of the unit core board with dielectric material to form a dielectric buffer portion includes: A medium material is filled outside the unit core board to form an enclosure, and the enclosure at least covers the outer side of the stacked body in the first direction; The package is planarized so that the two ends of the conductive path in the first direction are exposed relative to the medium buffer.

[0019] In a third aspect, this application also provides a package, including a chip and a packaging unit, wherein the packaging unit has a bump on one side in the first direction, and the chip is connected to the packaging unit through the bump; the packaging unit is any of the packaging units described above, or is prepared by any of the packaging units described above.

[0020] The beneficial effects of the packaging unit, its preparation method, and the package provided in this application are as follows: Compared with related technologies, the packaging unit provided in this application can buffer and improve the warpage of the unit core board by filling the first dielectric layer between adjacent unit core boards and help reduce the overall stress of the packaging unit; the second dielectric layer that wraps the unit core board provides better protection to the outer periphery of the unit core board, thereby effectively buffering the external force acting on the unit core board, reducing the possibility of cracks and defects in the unit core board during production, handling, and use, and further improving the reliability of the packaging unit. When fabricating the encapsulation unit, an independent unit core board can be prepared by first splitting the relevant mother board. This avoids the problem that the encapsulation unit may be defective if it is cut and split after the addition of layers. At the same time, the sacrificial layer used in the fabrication can play a good supporting role in the bonding process and can be removed to leave space for filling the dielectric material. This method can avoid the possibility that the dielectric material will generate stress on the glass core board due to thermal expansion during the bonding process. It also reduces the performance requirements of the dielectric material. The dielectric material can provide better encapsulation and protection for the unit core board, thereby improving the reliability of the fabricated encapsulation unit in subsequent processing, handling and use.

[0021] The package provided in this application includes the package unit or the package unit prepared by any of the above-described package units or preparation methods. Therefore, the package has the beneficial effects of at least one or more of the above-described package units and their preparation methods. The specific effects are as described above and will not be repeated here. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application, and therefore should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the packaging unit provided in the embodiments of this application; Figure 2 for Figure 1 Top view; Figure 3 A flowchart illustrating the fabrication method of the packaging unit provided in this application embodiment; Figures 4A-4J A schematic diagram illustrating the fabrication process of the packaging unit provided in this application embodiment; Figure 5 This is a schematic diagram of the structure of a packaging unit provided in another embodiment of this application; Figure 6 This is a schematic diagram of the package structure provided in an embodiment of this application.

[0024] The following are the labeling elements in the figure: 10. Packaging unit; 1. Unit core board; 11. Conductive path; 111. First conductive element; 112. Second conductive element; 112'. Second conductive material element; 12. Unit core substrate; 1201. First surface; 1202. Second surface; 1203. Through hole; 101. Cutting channel; 1'. Glass core board; 1''. Glass master plate; 2. Dielectric buffer; 21. First dielectric layer; 22. Second dielectric layer; 2'. Encapsulation body; 3. Sacrificial layer; 301. First opening; 3'. Sacrificial material layer; 4. Protective layer; 401. Second opening; 5. Bump; 6. Solder ball; 20. Chip; 30. Circuit board; 100. Package body. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0026] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0027] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that, unless otherwise specified, different features in the embodiments of this application can be combined with each other.

[0028] For ease of understanding, the X direction (i.e., the first direction) is shown in the attached figure. The first direction can be considered as the thickness direction of the packaging unit or a direction parallel to the thickness direction of the packaging unit. The plane that is orthogonal to the first direction is a plane parallel to the surface of the packaging unit.

[0029] For certain elements, terms such as "above" or "over" are sometimes used when describing the position of an element located in the Z direction, and "below" or "under" are used when describing the position of an element located in the opposite direction. Furthermore, when using terms such as "above," "over," "below," "under," or "relative" to define the positional relationship between two elements, this includes not only the state where the two elements are directly adjacent, but also the state where the two elements are separated by a gap or other elements. Moreover, "above," "over," or "on top" of the first feature relative to the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "under," or "beneath" of the first feature relative to the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature. Furthermore, the terms "first," "second," and "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature specified as "first" or "second" can explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise expressly and specifically defined.

[0030] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0031] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between components; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0032] The term "layer" as used herein can refer to a portion of material comprising a material of a certain thickness. A layer may extend along an entire underlying or overlying structure, or may have a smaller extent than the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or non-homogeneous continuous structure, with a thickness less than the thickness of that continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure, or between any pairs of transverse planes at the top and bottom surfaces. A layer may extend laterally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers located on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (forming contacts, interconnects, and / or vias therein) and one or more dielectric layers.

[0033] Glass cores have become an important substrate material in advanced packaging due to their excellent electrical properties (low dielectric loss, high insulation), thermal stability (thermal expansion coefficient matching silicon), and potential for large-size, low-cost manufacturing. In 3D integration applications, multiple glass cores are typically stacked and bonded using vertical interconnect structures to achieve interlayer electrical connections and mechanical fixation.

[0034] In related technologies, glass core sheets can be stacked and fixed using processes such as hybrid bonding, and then cut to obtain individual encapsulation units. However, during the stacking of multilayer glass core sheets, due to the inherent properties of the glass material, stress accumulates within the encapsulation master formed after stacking. This stress extends towards the edges of the encapsulation master, causing defects such as cracks, delamination, or fractures (i.e., SeWaRe defects) to occur in the area near the cutting path during subsequent cutting. These defects can extend into the encapsulation master as it is cut, causing larger and more noticeable defects, ultimately resulting in low processing yield and reliability of the manufactured encapsulation units.

[0035] Based on this, embodiments of this application provide a packaging unit 10 and its preparation method, and a package 100, so as to improve the processing yield and reliability of the packaging unit 10 to at least a certain extent.

[0036] Please see Figure 1 This application provides a packaging unit 10, which is a plate-shaped structure with a certain thickness in a first direction, and can be electrically connected to external electronic components such as chip 20 and circuit board 30 as an independent structure.

[0037] Specifically, the encapsulation unit 10 includes a unit core board 1 and a dielectric buffer section 2. The number of unit core boards 1 is at least two and they are stacked along a first direction. Each unit core board 1 has a conductive path 11 that runs through its two opposing surfaces in the first direction. Adjacent unit core boards 1 in the first direction are connected through the conductive path 11. Figure 1 The packaging unit 10 shown has three unit core boards 1. Each unit core board 1 includes a glass unit core substrate 12 and a conductive path 11 made of conductive material disposed on the unit core substrate 12. The conductive path 11 is used to realize the electrical connection between the two surfaces of the unit core board 1 itself and to provide interconnection nodes for subsequent interlayer stacking. Two adjacent unit core boards 1 can be connected through their respective conductive paths 11 to realize the conduction of electrical signals. Of course, in other similar embodiments, the number of unit core boards 1 can be adaptively adjusted according to the design. For example, the number of unit core boards 1 can be set to two, four or even more. The dielectric buffer 2 encloses the unit core board 1 while ensuring that the conductive path 11 is partially exposed relative to the dielectric buffer 2 so that the conductive path 11 can be electrically connected to external electronic devices.

[0038] Figure 1 The conductive paths 11 on different unit core boards 1 can be constructed in the same or different ways. The actual structure of the conductive paths 11 can be adaptively adjusted according to the design. In this embodiment, it is only necessary to ensure that when different unit core boards 1 are aligned along the first direction, adjacent unit core boards 1 can achieve normal circuit conduction through their respective conductive paths 11.

[0039] Please see Figure 1 In order to cover and protect the conductive path 11 and the unit substrate, the packaging unit 10 also includes a dielectric buffer section 2.

[0040] The dielectric buffer section 2 includes a first dielectric layer 21 and a second dielectric layer 22. The first dielectric layer 21 and the second dielectric layer 22 are connected and together constitute an insulating structure that can wrap the other areas of the unit core board 1 except for the conductive path 11. Figure 1Taking the structure shown as an example, the first dielectric layer 21 is disposed between two adjacent unit core boards 1 and contacts the opposing surfaces of the adjacent unit core boards 1. The first dielectric layer 21 can surround and wrap a portion of the conductive path 11 located between the two adjacent unit core boards 1, and the first dielectric layer 21 and the unit core boards 1 are alternately stacked along the first direction to form a stack. The second dielectric layer 22 at least wraps the outer surface of the stack in the first direction. At this time, the first dielectric layer 21 can effectively protect the conductive path 11 located at least between the two adjacent unit core boards 1. The second dielectric layer 22 wraps the stack, and exposes at least a portion of the conductive path 11 in the first direction. At this time, the second dielectric layer 22 can provide better protection for the unit core boards 1 by wrapping and covering them.

[0041] It should be noted that the outer surface of the stack includes its top and bottom surfaces in the first direction, as well as the outer peripheral side surface connecting the top and bottom surfaces. The second dielectric layer 22 at least entirely includes the outer peripheral side surface of the stack, while also covering a portion of the top and bottom surfaces of the stack. At this time, in the first direction, at least a portion of the orthographic projection of the conductive path 11 on the unit core plate 1 is located outside the orthographic projection of the second dielectric layer 22 on the unit core plate 1, meaning that at least a portion of the surface of the conductive path 11 in the first direction can be exposed relative to the second dielectric layer 22, and the orthographic projection of the conductive path 11 on the unit core plate 1 is located within the outer contour of the orthographic projection of the first dielectric layer 21 on the unit core plate 1.

[0042] In the packaging unit 10 provided in this application embodiment, by filling the space between adjacent different unit core boards 1 with a first dielectric layer 21, the warpage of the unit core board 1 can be improved, the overall stress of the packaging unit 10 can be reduced, and the processing yield and reliability of the prepared packaging unit 10 can be improved. In addition, the second dielectric layer 22 that wraps the unit core board 1 and the first dielectric layer 21 can further provide better protection for the side of the unit core board 1 in the first direction, so that when external force is applied to the unit core board 1, the possibility of cracks and defects in the unit core board 1 during production, handling and use can be reduced by buffering external force impact, and the reliability of the packaging unit 10 can be further improved.

[0043] Specifically, the dielectric buffer section 2 is made of a dielectric material. Dielectric materials include organic materials such as organic resins, polyimide (PI), ABF (Ajinomoto Build-up Film), and other suitable organic polymers. Choosing these organic materials balances the basic properties required for the dielectric layer, such as insulation and molding, while also simplifying the processing of organic materials and adapting to the fabrication needs of various structures.

[0044] In terms of specific selection criteria for dielectric materials, materials with low coefficient of thermal expansion (CTE) and low Young's modulus are mainly chosen. A lower CTE means that the dielectric material expands or contracts less during temperature changes, effectively reducing thermal stress caused by differences in thermal expansion between the dielectric layer and adjacent core panels 1, thus avoiding defects such as interlayer warping, cracking, and delamination. A lower Young's modulus indicates lower material stiffness and better flexibility, reducing stress concentration in the dielectric layer under stress and mitigating stress from external mechanical impacts (such as during cutting), thereby preventing cracks in the core panel 1 during subsequent use and processing.

[0045] The structure of the aforementioned unit core board 1 will be described in detail below.

[0046] Please see Figure 1 In addition to the conductive path 11, the unit core board 1 also includes a unit core substrate 12. The unit core substrate 12 is a plate-shaped structure made of glass material and having a certain thickness in a first direction. The unit core substrate 12 has a first surface 1201 and a second surface 1202 opposite to each other in the first direction, and is also provided with a through hole 1203 penetrating the first surface 1201 and the second surface 1202. The conductive path 11 is disposed on the unit core substrate 12 through the aforementioned through hole 1203, penetrating the first surface 1201 and the second surface 1202, and covering part of the first surface 1201 and part of the second surface 1202.

[0047] Specifically, the conductive path 11 includes a first conductive element 111 and a second conductive element 112. The first conductive element 111 is disposed on the unit core substrate 12 through a through hole 1203 and covers part of the first surface 1201 and part of the second surface 1202 in a first direction. The second conductive element 112 is connected to the first conductive element 111 and is located on the side of the first conductive element 111 that is away from the unit core substrate 1.

[0048] Two adjacent unit core boards 1 in the first direction are bonded together by the second conductive element 112, and the circuit remains conductive.

[0049] To ensure the conductivity of the conductive path 11, the first conductive element 111 and the second conductive element 112 are made of the same material. For example, aluminum, germanium, copper, tin, nickel, gold, or other metal materials suitable for bonding. In this embodiment, both the first conductive element 111 and the second conductive element 112 are made of copper.

[0050] It should be noted that the first conductive element 111 can be a solid columnar structure, in which case the first conductive element 111 can completely fill the through hole 1203 and protrude relative to the through hole 1203; or, the first conductive element 111 can also be a partially recessed columnar structure, or even a hollow columnar structure that runs through the first direction. This embodiment does not limit it.

[0051] Of course, it should be noted that before the first conductive element 111 and the second conductive element 112 are prepared by electroplating, a seed layer needs to be prepared on the corresponding surface, which will not be elaborated here.

[0052] Please see Figure 1 In the first direction, the first conductive element 111 protrudes from at least one of the first surface 1201 and the second surface 1202 of the unit core substrate 12 on the unit core substrate 12. The second conductive element 112 is connected to the end of the first conductive element 111 facing away from the unit core substrate 12 in the first direction and protrudes from the unit core substrate 12 in the first direction. At this time, two adjacent unit core boards 1 can be connected through the second conductive element 112 to realize circuit conduction.

[0053] Under the action of the first conductive element 111 and the second conductive element 112, there is a certain gap between the surfaces of two adjacent unit core substrates 12 arranged in the first direction. This gap can be used to accommodate the first dielectric layer 21 in the dielectric buffer section 2.

[0054] In the first direction, the maximum size of the aforementioned gap is affected by the size of the conductive path 11, especially the size of the second conductive element 112. That is, the thickness of the first dielectric layer 21 filling the aforementioned gap depends on the size of the conductive path 11, especially the size of the second conductive element 112 in the first direction.

[0055] When determining the dimensions of the first dielectric layer 21 in the first direction, the dimensions of the conductive path 11 can be adjusted and determined according to the design requirements first. Then, based on the determined dimensions of the conductive path 11 and the dimensions of the unit core substrate 12, the final dimensions of the first dielectric layer 21 can be determined. The first dielectric layer 21 is in contact with the lateral surfaces of the first conductive element 111 and the second conductive element 112 in the first direction.

[0056] In some embodiments, the thickness of the unit core substrate 12 in the first direction is less than or equal to 300 μm. The thickness of the unit core substrate 12 is positively correlated with the cutting stress.

[0057] The unit core substrate 12 can be obtained by cutting the unit core plate 1, etc. The unit core plate 1 is provided with a cutting groove 101, and the required unit core substrate 12 can be obtained by cutting along the cutting groove 101. In the first direction, the thickness of the unit core substrate 12 is consistent with the thickness of the unit core plate 1.

[0058] Under the same cutting process conditions, the greater the thickness of the unit core board 1, the greater the stress generated during the cutting process, and the more likely the cut area is to develop defects such as micro-cracks, chipping, and breakage. Conversely, the smaller the thickness of the unit core board 1, the lower the cutting stress, the higher the cutting stability, and the lower the defect rate.

[0059] Since the thickness of the unit core substrate 12 in the first direction is consistent with the thickness of the unit core plate 1 in the first direction, by controlling the thickness of the unit core plate 1 to be relatively small, the stress on the unit core plate 1 during cutting can be alleviated to a certain extent. By controlling the stress within a certain range, the yield of the cut unit core substrate 12 can be improved. In addition, when the thickness of the unit core substrate 12 is relatively small, the possibility of forming a solid first conductive element 111 can be effectively increased when the first conductive element 111 is prepared by electroplating. Compared with a hollow structure, a solid conductive structure has better electrical and thermal conductivity, as well as better mechanical strength and reliability. When the thickness of the unit core substrate 12 is relatively small, it helps to form a reasonable depth-to-width ratio of the through hole 1203, thereby improving the morphology of the formed first conductive element 111.

[0060] Specifically, in the first direction, the thickness of the unit core substrate 12 is greater than or equal to 100 μm. When the thickness of the unit core substrate 12 is too small, its processing is difficult and it is easily damaged during the fabrication process.

[0061] In actual selection, the thickness of the unit core substrate 12 in the first direction can be set to any value among 100μm, 150μm, 200μm, 250μm and 300μm, or any two values.

[0062] Specifically, two adjacent unit core plates 1 in the first direction can be bonded together by a second conductive element 112. At this time, the second conductive elements 112 on different unit core plates 1 are bonded together by interatomic bonding forces.

[0063] The above-mentioned bonding connections can be achieved using a direct bonding process.

[0064] Specifically, after the second conductive element 112 in two adjacent unit core boards 1 is pre-pressed and bonded under high temperature and high pressure, it is then subjected to low temperature annealing treatment, which allows the atoms at the connection end interface to diffuse into each other and bond together through interatomic bonding force. At this time, the two can be bonded together at the connection interface through cross-interface grain growth.

[0065] For example, when both the first conductive element 111 and the second conductive element 112 are made of copper metal, copper atoms at the end interfaces of the conductive paths 11 located on different unit core plates 1 diffuse into each other.

[0066] Compared to other processes, direct bonding eliminates the need for solder or adhesives, avoiding the introduction of dissimilar materials. This process ensures bonding accuracy and reliability while also eliminating the risks of intermetallic compound formation and organic material aging, significantly improving the long-term reliability and electrical and thermal conductivity of interconnects.

[0067] It should also be noted that, compared to hybrid bonding, the above bonding process avoids bonding to the unit core substrate 12, thereby significantly reducing the bonding area, and simultaneously reducing the difficulty of the bonding process and the potential risks of defects that may occur during hybrid bonding. Please refer to... Figure 2 The circular structure formed by dashed lines in the figure is used to indicate the bonding position.

[0068] The portion of the first conductive element 111 protruding relative to the unit core substrate 12 in the above-mentioned conductive path 11 and the second conductive element 112 connected thereto can cooperate with the first dielectric layer 21 to form a redistribution layer (RDL), thereby realizing circuit conduction between different unit core boards 1.

[0069] It should be noted that the distribution and structure of the first conductive element 111 and the second conductive element 112 can be adapted to actual needs, and this embodiment does not limit them. In the specific manufacturing process, the spacing between any two adjacent unit core plates 1 in the first direction can be consistent or different, and this embodiment does not limit them, so it will not be elaborated here.

[0070] It is understood that the encapsulation unit 10 provided in this application embodiment can buffer and improve the warping of the unit core board 1 by filling the first dielectric layer 21 between adjacent unit core boards 1, and help reduce the overall stress of the encapsulation unit 10; by wrapping the unit core board 1 with the second dielectric layer 22, it provides better protection for the outer periphery of the unit core board 1, thereby effectively buffering the external force acting on the unit core board 1, reducing the possibility of cracks and defects in the unit core board 1 during production, handling and use, and further improving the reliability of the encapsulation unit 10.

[0071] Based on the same inventive concept, in a second aspect, embodiments of this application also provide a method for preparing the packaging unit 10. Please refer to [link to relevant documentation]. Figure 3 .

[0072] Specifically, the preparation method includes: Step S1: Obtain at least two unit core boards 1. Each unit core board 1 has a conductive path 11 that penetrates its two opposite surfaces. At least one of the two opposite surfaces of each unit core board 1 is provided with a sacrificial layer 3. The conductive path 11 is partially exposed relative to the sacrificial layer 3. Step S2: Align the different unit core boards 1 along the first direction so that the ends of the conductive paths 11 on the different unit core boards 1 are in contact with each other, and the sacrificial layers 3 on the different unit core boards 1 are in contact with each other. Step S3: Bond the contacting conductive paths 11 to fix different unit core boards 1 through the conductive paths 11. At the same time or after the bonding process, remove the sacrificial layer 3 to form a gap between adjacent unit core boards 1. Step S4: Fill the outer surface of the unit core board 1 with dielectric material to form a dielectric buffer part 2. The dielectric buffer part 2 includes a first dielectric layer 21 and a second dielectric layer 22. The first dielectric layer 21 is disposed between two adjacent unit core boards 1 and is in contact with the opposite surface of the adjacent unit core boards 1. The unit core boards 1 and the first dielectric layer 21 are alternately stacked along the first direction to form a stacked body. The second dielectric layer 22 at least covers the outer surface of the stacked body in the first direction. In the first direction, at least a portion of the orthographic projection of the conductive path 11 on the unit core board 1 is located outside the orthographic projection of the second dielectric layer 22 on the unit core board 1.

[0073] In the packaging unit 10 preparation method provided in this application embodiment, by performing subsequent bonding processing on the unit core board 1 obtained after cutting, the problems that are prone to occur during the cutting process of the organic and glass hybrid structure after the layering process can be effectively avoided, thereby helping to improve the problems of low processing yield and poor reliability of the packaging unit 10. In addition, the above preparation process also sets a sacrificial layer 3 between the unit core boards 1. The sacrificial layer 3 can provide a certain support during the bonding process of the unit core board 1, thereby helping to reduce the difficulty of the bonding process and improve the bonding yield. In addition, the above bonding process is used to bond multiple conductive paths 11 at the same time, which has high processing efficiency and reduces the area that needs to be bonded, thereby reducing the difficulty of the process and the possible risk of defects. The dielectric buffer part 2 prepared after bonding not only avoids the possibility of stress caused by thermal expansion during the bonding process acting on the unit core board 1, reducing the requirements for dielectric materials, but also provides better wrapping and protection for the unit core board 1, thereby improving the reliability of the prepared packaging unit 10 in subsequent processing, handling and use.

[0074] In the above-described fabrication process, firstly, at least two unit core boards 1 to be stacked are required. Each unit core board 1 has a conductive path 11 penetrating its two opposing surfaces. This conductive path 11 is used to achieve electrical connection between the two surfaces of the unit core board 1 itself and to provide interconnection nodes for subsequent interlayer stacking. Simultaneously, each unit core board 1 has a sacrificial layer 3 on at least one surface used for connection. The sacrificial layer 3 can be used to provide support for the relatively brittle unit core board 1 during subsequent bonding. The sacrificial layer 3 is not a structure ultimately formed on the packaging unit 10; it is removed during the fabrication of the packaging unit 10, forming a gap of a predetermined thickness between adjacent unit core boards 1. At least a portion of the dielectric material fills this gap, forming a first dielectric layer 21. The remaining dielectric material encapsulates the first dielectric layer 21 and the unit core board 1, forming a second dielectric layer 22. The first dielectric layer 21 and the second dielectric layer 22 together constitute the aforementioned dielectric buffer portion 2.

[0075] Specifically, step S1 includes: Step S11: Obtain glass master plate 1'', which has a preset cutting path 101; Step S12: Process the glass master plate 1'' to obtain at least two unit core plates 1. Each unit core plate 1 has a conductive path 11 that runs through its two opposing surfaces in a first direction, and a sacrificial layer 3 is provided on at least one of the two opposing surfaces, with the conductive path 11 partially exposed relative to the sacrificial layer 3.

[0076] The glass master plate 1'' refers to a plate-like structure made of glass material, on which through holes for the conductive path 11 of the component can be formed. The cutting groove 101 pre-set on the glass master plate 1'' can divide the opposing first surface 1201 and second surface 1202 on the glass master plate 1'' into corresponding different regions. Any complete conductive path 11 can be formed in a certain region divided by the cutting groove 101, and at least some regions have independent and complete conductive paths 11.

[0077] In step S12, according to processing requirements, the glass master plate 1'' can be first set with corresponding conductive paths 11 and sacrificial layers 3, and then cut along the preset cutting path 101 to obtain a unit core plate 1 that meets the requirements; or, the glass master plate 1'' can be cut along the preset cutting path 101 to obtain a unit core substrate 12, and then corresponding conductive paths 11 and sacrificial layers 3 can be set on the unit core substrate 12 to obtain a unit core plate 1 that meets the requirements. This embodiment does not limit the above processing sequence.

[0078] Please see Figures 4A-4E Taking the structure shown in the attached figure as an example, the specific processing steps in step S12 will be explained as follows: Specifically, the processing steps in step S12 include: Step S121: A conductive path 11 is formed on the glass master plate 1'' through its two opposing surfaces. The number of conductive paths 11 is at least two and they are arranged at intervals with the cutting path 101. A sacrificial layer 3 is formed on at least one of the two opposing surfaces of the glass master plate 1'', and the conductive path 11 is partially exposed relative to the sacrificial layer 3. Step S122: Cut the glass master plate 1'' with conductive path 11 and sacrificial layer 3 along the cutting path 101 to obtain unit core plate 1.

[0079] Step S121 includes: Step S1211: Prepare a first conductive element 111 on the glass master plate 1''. The glass master plate 1'' has a through hole 1203. The first conductive element 111 covers the inner wall of the through hole 1203 and the surface of both sides of the glass master plate 1'' in the first direction. Step S1212: Prepare a sacrificial material layer 3' on at least one of the two opposing surfaces of the glass master plate 1''. The sacrificial material layer 3' has a first opening 301, and a portion of the surface of the first conductive element 111 is exposed relative to the sacrificial material layer 3' through the first opening 301. Step S1213: Prepare a second conductive material part 112' connected to the first conductive part 111 within the first opening 301; Step S1214: Planarize the sacrificial material layer 3' and the second conductive material component 112' to form the sacrificial layer 3 and the second conductive component 112, which together with the first conductive component 111, constitute the conductive path 11.

[0080] The process of step S121 above will be explained in detail below: In step S121, the glass master plate 1'' is a plate-like structure with a certain thickness. This glass master plate 1'' has a first surface 1201 and a second surface 1202 opposite to each other in a first direction, and also has a pre-set through-hole 1203 penetrating the first surface 1201 and the second surface 1202. The dotted line in the figure represents the pre-set cutting path 101 on it. In step S1211, a first conductive element 111 can be prepared in the through-hole 1203 and on the first surface 1201 and the second surface 1202 by sputtering, electroplating, or other methods (a seed layer needs to be prepared beforehand; this process has been disclosed in related technologies and will not be described in detail here). The first conductive element 111 can be a solid columnar structure that completely fills the through-hole 1203, or a columnar structure that only fills part of the through-hole 1203 and has internal depressions or hollow areas. Please refer to [link to relevant documentation]. Figure 4ADuring preparation, the morphology and actual structure of the first conductive element 111 can be adaptively adjusted by controlling the preparation process of the first conductive element 111 or by adjusting the thickness of the glass master plate 1'' in the first direction, according to the actual design and processing technology.

[0081] It is important to note that the first conductive element 111 prepared in step S1211 is arranged at a distance from the cutting path 101 pre-set on the glass master plate 1''. In the first direction, the orthographic projection of the first conductive element 111 on the glass master plate 1'' and the orthographic projection of the cutting path 101 on the glass master plate 1'' are arranged at a distance to ensure that the first conductive element 111 does not pass through the pre-set cutting path 101, and that the pre-set cutting path 101 will not damage the circuit of the first conductive element 111 after subsequent cutting. The cutting path 101 is not an actual structure formed on the glass master plate 1''. The cutting path 101 is a set position for cutting the glass master plate 1'', and can be regarded as a baseline for subsequent cutting of the glass master plate 1''. Its specific position can be adjusted according to design needs.

[0082] After the fabrication of the first conductive element 111 is completed, step S1212 can be performed to prepare a sacrificial material layer 3' on at least one of the first surface 1201 and the second surface 1202 of the glass master plate 1''. The sacrificial material layer 3' has a first opening 301, through which a portion of the surface of the first conductive element 111 is exposed relative to the sacrificial material layer 3'. Figure 4B Taking the structure shown as an example, both the first surface 1201 and the second surface 1202 of the glass master plate 1'' are provided with sacrificial material layers 3'. At this time, both sides of the glass master plate 1'' in the first direction can be used to stack other glass master plates 1''. Of course, it is also possible to set the glass master plate 1'' to have sacrificial material layers 3' only on the first surface 1201, in which case only the first surface 1201 of the glass master plate 1'' is used to cooperate with other adjacent glass master plates 1''; or, only the second surface 1202 is provided with sacrificial material layers 3', in which case only the second surface 1202 of the glass master plate 1'' is used to cooperate with other adjacent glass master plates 1''.

[0083] It should be noted that the sacrificial material layer 3' can be made of photosensitive materials, etc., so that a first opening 301 that exposes part of the surface of the conductive path 11 can be formed through patterning processes such as exposure and development. For example, the photosensitive material used in the sacrificial material layer 3' can include organic materials such as photosensitive dry film and photosensitive adhesive. The above materials can form the first opening 301 by photolithography, and have no corrosive effect on the glass master 1'' and the metal constituting the first conductive element 111. Alternatively, the sacrificial material layer 3' can be made of other non-photosensitive materials. In this case, the material constituting the sacrificial material layer 3' can be removed by a specific solution or by laser ablation.

[0084] After the sacrificial material layer 3' is prepared, step S1213 can be performed to prepare a second conductive material element 112' connected to the first conductive element 111 within the first opening 301 using electroplating, chemical plating, or other processes. Please refer to [link to relevant documentation]. Figure 4C The prepared second conductive material component 112' is usually slightly higher than the surface of the sacrificial material layer 3', or the uniformity of the second conductive material component 112' in different regions of the sacrificial material layer 3' is relatively poor, manifested as the height of the second conductive material component 112' corresponding to different regions of the sacrificial material layer 3' not being completely consistent. To solve this problem and ensure the smooth progress of the subsequent bonding process, step S1214 needs to be performed to planarize the sacrificial material layer 3' and the second conductive material component 112', so that the end of the finally prepared second conductive component 112 in the first direction is located on the same plane perpendicular to the first direction (the accuracy can reach the nanometer level). At this time, the first conductive component 111 and the second conductive component 112 are connected and together form a conductive path 11. Step S121 is completed, and a glass core plate 1' with a pre-set cutting channel 101 is prepared. Please refer to [link to relevant documentation]. Figure 4D .

[0085] Compared to the glass master plate 1'', the glass core plate 1' refers to a glass plate structure that has been processed to form corresponding conductive paths 11. That is, the glass core plate 1' is composed of the glass master plate 1'' and the conductive paths 11 formed thereon.

[0086] It should be noted that, in the case of Figure 4C The structure shown is oriented towards Figure 4DDuring the fabrication of the structure shown, a chemical-mechanical planarization (CMP) process can be used to planarize the sacrificial material layer 3' and the second conductive material component 112'. In this process, both the sacrificial material layer 3' and the second conductive material component 112' are thinned to a certain extent. After planarization, a second conductive component 112 meeting the design requirements, and a sacrificial layer 3 distributed around the second conductive component 112, are obtained. At this point, the first conductive component 111 and the second conductive component 112 constitute a complete conductive path 11. On a plane perpendicular to the first direction, multiple unit core boards 1 to be separated are arranged in an array on the glass core board 1'. Any two adjacent unit core boards 1 are connected by a preset cutting area, and the unit core boards 1 and the preset cutting areas are spaced apart. The edge of the preset cutting area coincides with the cutting path 101. After cutting the glass core board 1' along the cutting path 101, multiple independent unit core boards 1 and cutting waste composed of the aforementioned preset cutting areas are obtained.

[0087] On a plane perpendicular to the first direction, the conductive path 11 and the cutting path 101 are arranged at intervals to ensure that any unit core board 1 obtained after cutting has an independent and complete conductive path 11, and the cutting will not damage the circuit integrity and functionality on the unit core board 1.

[0088] After step S121 is completed, step S122 needs to be performed to obtain the required unit core board 1 by cutting the glass core board 1'. Please refer to [link to relevant documentation]. Figure 4E .

[0089] The glass core board 1' is a structure with multiple independent unit core boards 1 arranged in an array. After cutting, multiple independent unit core boards 1 can be obtained.

[0090] Alternatively, in other similar embodiments, the processing steps in step S12 may also include: Step S1201: Cut the glass master plate 1'' along the cutting channel 101 to obtain at least two unit core substrates 12. The unit core substrate 12 has a first surface 1201 and a second surface 1202 opposite to each other in a first direction, and is also provided with a through hole 1203 penetrating the first surface 1201 and the second surface 1202. Step S1202: A conductive path 11 with a through hole 1203 is formed on the unit core substrate 12, and a sacrificial layer 3 covering at least one of the first surface 1201 and the second surface 1202 is formed to obtain the unit core board 1.

[0091] The unit core substrate 12 prepared in step S1201 refers to a sheet-like glass structure obtained by directly cutting the glass master plate 1'' mentioned above, on which through holes for forming conductive paths 11 are formed. After step S1202, conductive paths 11 are formed on the unit core substrate 12, and it finally constitutes the unit core plate 1.

[0092] The specific steps of step S1202 are basically the same as those of steps S1211 to S1214 described above. The difference is that step S1202 is applied to the unit core substrate 12 obtained after cutting, while steps S1211 to S1214 are applied to the uncut glass master plate 1'' with the preset cutting groove 101. For the specific operation steps of step S1202, please refer to the previous text, which will not be repeated here.

[0093] Each unit core board 1 includes a unit core substrate 12 made of glass material and conductive paths 11 formed on the unit core substrate 12. The unit core board 1 can be used as an independent interconnect structure and directly applied in the subsequent step S2 for processing and fabricating the packaging unit 10.

[0094] After step S1 is completed, proceed to step S2.

[0095] In step S2, at least two unit core boards 1 to be bonded need to be aligned along the first direction (i.e., the vertical stacking direction). At this time, the second surface 1202 of the unit core board 1 located above in the first direction is exactly opposite to the first surface 1201 of the unit core board 1 located below it, and the ends of the conductive paths 11 on the two unit core boards 1 (i.e., the surfaces of the second conductive elements 112) are in contact. The sacrificial layers 3 on the multiple unit core boards 1 also remain in contact to provide a certain support for the area of ​​the unit core substrate 12 located above in the first direction where there are no conductive paths 11. Please refer to [link to relevant documentation]. Figure 4F .

[0096] In step S3, the conductive paths 11 in contact are bonded.

[0097] In this embodiment, the bonding process employs a direct bonding process. This direct bonding process eliminates the need for solder or adhesive, avoiding the introduction of heterogeneous materials, thereby eliminating the risk of intermetallic compound formation and organic material aging, and significantly improving the long-term reliability and electrical and thermal conductivity of the interconnect.

[0098] The ends of the second conductive element 112 prepared in step S1 have nanoscale flatness and cleanliness. Taking the second conductive element 112 as being made of copper metal material as an example, the direct bonding process (Cu-Cu Bonding) can directly bond the conductive paths 11 in contact with each other and form atomic bonds between the ends of the conductive paths 11 in contact with each other.

[0099] Specifically, the bonding process may also include annealing after the direct bonding process to form cross-interface grains between the ends of the conductive pathways 11 in contact.

[0100] For example, a direct bonding process can be used to pre-compress the conductive path 11 at room temperature or under high temperature and high pressure. Then, after low temperature annealing, the copper atoms at the end interfaces of the two conductive paths 11 diffuse into each other and form interatomic bonding forces.

[0101] During the bonding process, the presence of the sacrificial layer 3 effectively supports the non-bonded areas of the two unit core plates 1, preventing the unit core plates 1 from cracking or developing cracks due to bonding forces or local pressure. The uniform thickness of the sacrificial layer 3 ensures the parallelism and spacing consistency between the upper and lower unit core plates 1, further improving the bonding yield.

[0102] In step S3, the sacrificial layer 3 can be removed after the bonding process is completed, or it can be gradually decomposed during the bonding process, so that the removal of the sacrificial layer 3 is carried out simultaneously with the bonding process.

[0103] Please see Figure 4F and Figure 4G The sacrificial layer 3 in the diagram is removed after the bonding process is completed. That is, the sacrificial layer 3 removal step is performed after the bonding is completed.

[0104] For example, when the material constituting the sacrificial layer 3 is a photosensitive material, it can be dissolved and removed using a corresponding solution. Alternatively, when the material of the sacrificial layer 3 includes polyimide, a dry ashing process can be used to remove the sacrificial layer 3 by ashing with oxygen plasma or the like.

[0105] The above process also utilizes the sacrificial layer 3 to assist direct bonding, thereby effectively supporting the adjacent unit core substrate 12 and reducing the risk of cracking of the unit core substrate 12 during the bonding process.

[0106] In other similar embodiments, the bonding process and the removal of the sacrificial layer 3 are performed in the same process step.

[0107] Specifically, after the ends of the conductive paths 11 of two adjacent unit core boards 1 come into contact, the sacrificial layer 3 can decompose based on the bonding conditions while the bonding process is being performed. For example, when the bonding process is carried out in a high-temperature and high-pressure environment, the material constituting the sacrificial layer 3 is a pyrolytic polymer (such as a specific type of polypropylene carbonate) whose thermal decomposition temperature matches the direct bonding annealing temperature. When the temperature is adjusted to the point where the pre-compression bonding of the conductive paths 11 is completed and the annealing process begins, the material constituting the sacrificial layer 3 begins to thermally decompose at this temperature (e.g., 250-300°C), generating gaseous small molecule products that volatilize. During this process, the ends of the conductive paths 11 undergo copper atom diffusion under high temperature and pressure, forming atomic bonds; simultaneously, the sacrificial layer 3 gradually decomposes and disappears. When the bonding process is completed, the sacrificial layer 3 is also almost completely removed, directly forming a void between the unit core boards 1.

[0108] Specifically, the sacrificial layer 3 only begins to decompose after the pre-compression bonding is completed, thus providing better support for the unit core substrate 12 during the bonding process, especially in the early stages of the bonding process.

[0109] Since the removal and bonding of sacrificial layer 3 are completed simultaneously, a separate removal step is eliminated, simplifying the process and improving production efficiency. Furthermore, because sacrificial layer 3 does not generate liquid intermediates during decomposition, potential structural contamination or residue issues are avoided, making it particularly suitable for encapsulation scenarios with extremely high cleanliness requirements.

[0110] Two sacrificial layers 3 located between two adjacent unit core substrates 12 are bonded together. After the sacrificial layer 3 is removed, a gap with a certain height in the first direction will be formed in the aforementioned space. Please refer to [link to relevant documentation]. Figure 4G .

[0111] The thickness of the gap is determined by the thickness of the second conductive element 112, and can be precisely controlled by adjusting the dimensions of the second conductive element 112 in the first direction.

[0112] Finally, step S4 is performed to fill the outer part of the unit core plate 1 with dielectric material to form the dielectric buffer section 2.

[0113] The dielectric material filling the gaps contacts the opposing surfaces of the adjacent unit core plate 1 to form a first dielectric layer 21; the dielectric material filling the outer surface of the stack formed by the first dielectric layer 21 and the unit core plate 1 forms a second dielectric layer 22, and the conductive path 11 can be exposed relative to the second dielectric layer 22.

[0114] In step S4, the dielectric material can be injected into the space between adjacent unit core plates 1 under negative pressure, and preferentially fill the space to form a first dielectric layer 21; excess dielectric material can flow out of the unit core plate 1 through the space and finally form a second dielectric layer 22 that wraps around the unit core plate 1. The first dielectric layer 21 and the second dielectric layer 22 together constitute the dielectric buffer section 2.

[0115] As mentioned above, the medium material is an organic material, and the coefficient of thermal expansion of the medium material is less than or equal to the preset coefficient of thermal expansion, and the Young's modulus of the medium material is less than or equal to the preset modulus.

[0116] In the first direction, the size of the dielectric layer depends on the total size of the conductive path 11 on the two adjacent unit core plates 1 relative to the protrusion of the glass master plate 1''.

[0117] For example, the dielectric material is set to a low-modulus material, specifically a modified epoxy resin, whose elastic modulus (e.g., <5 GPa) is significantly lower than that of the glass master plate 1'' (approximately 70 GPa). After the dielectric layer completely fills the voids, the conductive path 11 can be embedded within it in the first direction, providing insulation protection and mechanical reinforcement. Due to the low-modulus characteristics of the dielectric layer, it can effectively absorb and buffer the thermal expansion mismatch stress caused by temperature changes between the unit core plates 1, as well as the stress caused by external mechanical impacts, improving the overall stress state of the finally prepared encapsulation unit 10 and reducing the probability of cracking in the encapsulation unit 10 during subsequent handling or use, thereby improving the fabrication reliability and processing yield of the encapsulation unit 10.

[0118] Considering that the dielectric material filling the stacked body may directly wrap around and cover the conductive path 11, thereby affecting the normal circuit conduction between the packaging unit 10 and other external electronic devices, the above step S4 includes: Step S41: Fill the outer surface of the unit core board 1 with a dielectric material to form an enclosure 2'. Please refer to [link / reference]. Figure 4H The enclosure 2' at least encloses the outer surface of the stacked body in the first direction; Step S42: Flatten the package 2' so that both ends of the conductive path 11 in the first direction are exposed relative to the dielectric buffer portion 2. Please refer to [link to relevant documentation]. Figure 4I .

[0119] It should be noted that the planarization process used here can be the same as the planarization process used in step S1, or it can be a different process, as long as the second dielectric layer 22 that meets the requirements can be obtained in the end.

[0120] Specifically, the planarization process used in step S42 can be a grinding process, which can ultimately produce a surface with micron-level precision and ensure that the conductive path 11 is exposed relative to the dielectric buffer portion 2 in the first direction.

[0121] In completing the above process, further protection is also required for the packaging unit 10.

[0122] In some embodiments, the preparation method further includes step S5: preparing a protective layer 4 on both sides of the dielectric buffer portion 2 in a first direction, wherein the protective layer 4 is provided with a second opening 401, and a portion of the conductive path 11 surface is exposed relative to the second opening 401.

[0123] Please see Figure 4J The protective layer 4 is made of materials such as solder resist and ink, and can be used to protect the parts of the conductive path 11 that do not need to contact electrical connection structures such as solder balls 6 or bumps 5, so as to prevent the conductive path 11 from being damaged or short-circuited by environmental corrosion. At the same time, the coverage of the protective layer 4 does not affect the contact between the conductive path 11 and structures such as solder balls 6 or bumps 5. The surface of the conductive path 11 exposed relative to the protective layer 4 can be used to connect the bumps 5 or solder balls 6, so as to achieve circuit conduction and mechanical fixation with structures such as chip 20.

[0124] Please refer to the structure of the packaging unit 10 with the above-mentioned bumps 5 or solder balls 6. Figure 5 .

[0125] It is understood that the method for preparing the encapsulation unit 10 provided in this application embodiment can be used to prepare an independent unit core board 1 by first performing a splitting process (i.e., cutting process) on the relevant mother board. This avoids the problem that the encapsulation unit 10 may be defective if it is split after the layering process. At the same time, the sacrificial layer 3 used in the preparation can play a good supporting role in the bonding process and can be removed to leave space for filling the dielectric material. This method can avoid the possibility that the dielectric material will expand thermally and generate stress on the glass core board 1' due to the bonding process. It also reduces the performance requirements of the dielectric material. The dielectric material can provide better wrapping and protection for the unit core board 1, thereby improving the reliability of the prepared encapsulation unit 10 in subsequent processing, handling and use.

[0126] Based on the same inventive concept, in a third aspect, embodiments of this application also provide a package 100, please refer to [link to relevant documentation]. Figure 6 .

[0127] The package 100 includes a package unit 10, which is the package unit 10 described in any of the above claims, or is prepared by the preparation method of the package unit 10 described in any of the above claims.

[0128] Specifically, the package 100 also includes a chip 20 and / or a circuit board 30 (e.g., a PCB). See also... Figure 6 The package 100 has a bump 5 on one side for connecting the chip 20 in the first direction, and a solder ball 6 on the other side for connecting the circuit board 30. The chip 20 is connected to the package 100 through the bump 5, and the circuit board 30 is connected to the package 100 through the solder ball 6. At this time, the chip 20 and the circuit board 30 can maintain circuit conduction through the conductive path 11 in the package 100.

[0129] The structures of the aforementioned bump 5 and solder ball 6 can be the same or different. In this embodiment, both are set to be spherical or similar spherical structures, which can be made of tin-silver alloy.

[0130] Specifically, the bumps 5 and solder balls 6 can be manufactured through processes such as ball planting, printing, or electroplating.

[0131] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0132] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A packaging unit, characterized in that, include: The unit core board has at least two units stacked along a first direction, each unit core board having a conductive path penetrating its two opposing surfaces in the first direction, and adjacent unit core boards in the first direction being connected through the conductive path. The dielectric buffer section includes a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed between two adjacent unit core boards and contacts the opposing surfaces of the adjacent unit core boards. The unit core boards and the first dielectric layer are alternately stacked along the first direction to form a stacked body. The second dielectric layer at least covers the outer surface of the stacked body in the first direction. In the first direction, at least a portion of the orthographic projection of the conductive path onto the unit core board is located outside the orthographic projection of the second dielectric layer onto the unit core board.

2. The packaging unit according to claim 1, characterized in that, The unit core board further includes a unit core substrate, the unit core substrate having a first surface and a second surface opposite to each other in the first direction, and the unit core substrate also having a through hole penetrating the first surface and the second surface; The conductive path includes a first conductive element and a second conductive element. The first conductive element is disposed on the unit core substrate through the through hole and covers part of the first surface and part of the second surface in the first direction. The second conductive element is connected to the first conductive element and is located on the side of the first conductive element facing away from the unit core substrate. Two adjacent unit core substrates are bonded together through the second conductive element. Preferably, the second conductive elements on different unit core boards are bonded together by interatomic bonding forces; Preferably, in the first direction, the orthographic projection of all the conductive paths on the unit core board is located within the outer contour of the orthographic projection of the first dielectric layer on the unit core board.

3. The packaging unit according to claim 2, characterized in that, The first conductive component and the second conductive component are made of the same material; And / or, the first dielectric layer is in contact with the surfaces of the first conductive element and the second conductive element; And / or, in the first direction, the thickness of the unit core substrate is less than or equal to 300 μm.

4. A method for fabricating a packaging unit, characterized in that, include: At least two unit core boards are obtained, each of the unit core boards having a conductive path extending through its two opposite surfaces, and at least one of the two opposite surfaces of the unit core board is provided with a sacrificial layer, wherein the conductive path is partially exposed relative to the sacrificial layer. Align the different unit core boards along the first direction so that the ends of the conductive paths on the different unit core boards come into contact with each other, and the sacrificial layers on the different unit core boards come into contact with each other; The conductive paths that are in contact are bonded to fix different unit core boards through the conductive paths. At the same time or after the bonding process, the sacrificial layer is removed to form a gap between adjacent unit core boards. A dielectric material is filled outside the unit core board to form a dielectric buffer part. The dielectric buffer part includes a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed between two adjacent unit core boards and is in contact with the opposite surface of the adjacent unit core boards. The unit core boards and the first dielectric layer are alternately stacked along a first direction to form a stacked body. The second dielectric layer at least covers the outer side of the stacked body in the first direction. In the first direction, at least a portion of the orthographic projection of the conductive path onto the unit core board is located outside the orthographic projection of the second dielectric layer onto the unit core board.

5. The method for preparing the packaging unit according to claim 4, characterized in that, The step of obtaining at least two unit core boards, each of which has a conductive path penetrating its two opposing surfaces, and at least one of the opposing surfaces of the unit core board having a sacrificial layer, wherein the conductive path is partially exposed relative to the sacrificial layer, includes: Obtain a glass master plate, which has a preset cutting groove; The glass master plate is processed to obtain at least two unit core plates. Each unit core plate has a conductive path that penetrates its two opposing surfaces in the first direction, and a sacrificial layer is provided on at least one of the two opposing surfaces. The conductive path is partially exposed relative to the sacrificial layer. The processing includes: Conductive pathways are formed on the glass master plate, penetrating its two opposing surfaces. The number of conductive pathways is at least two and they are arranged at intervals from the cutting path. A sacrificial layer is formed on at least one of the two opposing surfaces of the glass master plate, and the conductive pathways are partially exposed relative to the sacrificial layer. The glass master plate, on which the conductive path and the sacrificial layer are formed, is cut along the cutting path to obtain the unit core plate; Alternatively, the process may include: The glass master plate is cut along the cutting path to obtain at least two unit core substrates. The unit core substrates have a first surface and a second surface opposite to each other in the first direction, and are also provided with through holes penetrating the first surface and the second surface. The conductive path penetrating the through hole is prepared on the unit core substrate, and a sacrificial layer covering at least one of the first surface and the second surface is formed to obtain the unit core board.

6. The method for preparing the packaging unit according to claim 5, characterized in that, The step of forming conductive pathways penetrating both opposing surfaces of the glass master, wherein the number of conductive pathways is at least two and they are spaced apart from the cutting paths, and forming a sacrificial layer on at least one of the opposing surfaces of the glass master, wherein the conductive pathways are partially exposed relative to the sacrificial layer, includes: A first conductive element is prepared on the glass master plate, the glass master plate is provided with the through hole, and the first conductive element covers the inner wall of the through hole and the two side portions of the surface of the glass master plate in the first direction; A sacrificial material layer is prepared on at least one of the two opposing surfaces of the glass master, the sacrificial material layer having a first opening through which a portion of the surface of the first conductive element is exposed relative to the sacrificial material layer; A second conductive material component connected to the first conductive component is prepared within the first opening; The sacrificial material layer and the second conductive material are planarized to form the sacrificial layer and the second conductive element, which together with the first conductive element constitute the conductive path.

7. The method for preparing the packaging unit according to claim 4, characterized in that, The bonding process includes a direct bonding process to directly bond the contacting conductive pathways and form atomic bonds between the ends of the contacting conductive pathways. Preferably, the bonding process further includes annealing after the direct bonding process to form cross-interface grains between the ends of the contacting conductive pathways.

8. The method for preparing the packaging unit according to claim 4, characterized in that, The step of removing the sacrificial layer to form a gap between adjacent unit core boards during or after the bonding process includes: removing the sacrificial layer after the bonding process; or, decomposing the sacrificial layer during the bonding process so that the removal of the sacrificial layer is performed synchronously with the bonding process.

9. The method for preparing the packaging unit according to claim 4, characterized in that, The medium material includes organic materials, and the coefficient of thermal expansion of the medium material is less than or equal to a preset coefficient of thermal expansion, and the Young's modulus of the medium material is less than or equal to a preset modulus; And / or, the step of filling the outer surface of the unit core board with dielectric material to form a dielectric buffer portion includes: A medium material is filled outside the unit core board to form an enclosure, and the enclosure at least covers the outer side of the stacked body in the first direction; The package is planarized so that the two ends of the conductive path in the first direction are exposed relative to the medium buffer.

10. A package, characterized in that, The device includes a chip and a packaging unit. The packaging unit has a bump on one side in the first direction, and the chip is connected to the packaging unit through the bump. The packaging unit is the packaging unit according to any one of claims 1-3, or is prepared by the preparation method of the packaging unit according to any one of claims 4-9.

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