Method of forming a semiconductor structure
By forming a pre-buried layer on the first side of the substrate and performing element precipitation and blocking treatment, the problem of the diffusion resistivity distribution curve being difficult to approach the substrate is solved, thus improving the performance of semiconductor devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SMIC ORIENTAL INTEGRATED CIRCUIT MANUFACTURING CO LTD
- Filing Date
- 2024-12-19
- Publication Date
- 2026-06-26
AI Technical Summary
In existing technologies, the diffusion resistivity distribution curve is difficult to approach the substrate region, which affects the performance of semiconductor devices.
By forming a pre-embedded layer on the first side of the substrate and performing element precipitation and element blocking treatments on the substrate, the probability of element escape and neutralization is reduced, thereby making the diffusion resistivity distribution curve closer to the substrate region.
This increases the resistivity of the working area of the semiconductor device, expands the working area, and improves the performance of the semiconductor device.
Smart Images
Figure CN122279759A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology
[0002] In semiconductor manufacturing, to improve the quality of silicon wafers, a layer of intrinsic silicon with higher purity is usually grown on the silicon wafer through epitaxy (EPI). During epitaxial growth, doping gas is introduced to precisely control the resistivity required by the device. Therefore, it is widely used in bipolar transistor devices, discrete devices, transient voltage suppressors and superjunction devices.
[0003] Controlling the spreading resistance profile (SRP) curve is particularly important during epitaxial growth, as it directly affects the device performance.
[0004] However, the diffusion resistivity distribution curve is currently difficult to control, and how to make the diffusion resistivity distribution curve closer to the substrate has become an urgent problem to be solved. Summary of the Invention
[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure that enables the diffusion resistivity distribution curve to be close to the substrate region.
[0006] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate having a first doped ion, the substrate including a first surface and a second surface opposite to the first surface; forming a buried layer on the first surface of the substrate, the buried layer having a second doped ion, wherein the first doped ion and the second doped ion are inversely related; after forming the buried layer, pre-treating the substrate, the pre-treating including one or both of element precipitation treatment on the first surface and element blocking treatment on the second surface; and after pre-treating the substrate, forming an epitaxial layer covering the first surface of the substrate.
[0007] Optionally, the step of performing element blocking treatment on the second surface includes: forming a diffusion barrier layer covering the second surface of the substrate.
[0008] Optionally, after forming the epitaxial layer covering the first side of the substrate, the method further includes: removing the diffusion barrier layer covering the second side of the substrate.
[0009] Optionally, in the step of forming a diffusion barrier layer covering the second side of the substrate, a diffusion barrier layer covering the first side and the second side of the substrate is formed; before forming the epitaxial layer covering the first side of the substrate, the step further includes: removing the diffusion barrier layer on the first side to expose the first side of the substrate, and retaining the diffusion barrier layer on the second side of the substrate.
[0010] Optionally, the preprocessing includes sequentially performing element blocking processing on the second surface and element precipitation processing on the first surface; wherein, after removing the diffusion blocking layer of the first surface, the first surface is subjected to element precipitation processing.
[0011] Optionally, the step of performing element precipitation treatment on the first surface includes: performing one or more heat treatments on the substrate to remove elements diffused from the first surface, wherein the heat treatment includes: heating the substrate from a first preset temperature to a second preset temperature; after heating the substrate, maintaining the second preset temperature and performing a first baking treatment on the substrate; wherein, when the number of heat treatments is multiple, the step of performing element precipitation treatment on the first surface further includes: cooling the substrate between two adjacent heat treatments, from the second preset temperature of the previous heat treatment to the first preset temperature of the next heat treatment.
[0012] Optionally, the temperature rise corresponding to the heating process is less than or equal to 500 degrees Celsius.
[0013] Optionally, the cooling process corresponds to a cooling range of less than or equal to 500 degrees Celsius.
[0014] Optionally, the gas used in the first baking process may include a gas containing hydrogen.
[0015] Optionally, in the first baking process, the gas containing hydrogen includes hydrogen gas.
[0016] Optionally, the first surface is subjected to element precipitation treatment in the reaction chamber used to form the epitaxial layer.
[0017] Optionally, when the heat treatment is performed multiple times, the second preset temperature of the last heat treatment is equal to the preset growth temperature of the epitaxial layer; after the element precipitation treatment is completed, an epitaxial layer covering the first surface of the substrate is formed at the preset growth temperature.
[0018] Optionally, the heat treatment is performed multiple times, and the parameters of the first baking treatment corresponding to the last heat treatment include: the process time is 50 seconds to 150 seconds.
[0019] Optionally, the heat treatment includes at least one high-temperature heat treatment, wherein the second preset temperature corresponding to the high-temperature heat treatment is higher than the preset growth temperature of the epitaxial layer, and when the heat treatment is performed multiple times, at least the first heat treatment is a high-temperature heat treatment.
[0020] Optionally, the parameters of the first baking process corresponding to the high-temperature heat treatment include: the process gas includes a gas containing hydrogen, the second preset temperature is 1100 degrees Celsius to 1200 degrees Celsius, and the process time is 100 seconds to 200 seconds.
[0021] Optionally, before performing element precipitation treatment on the first surface, the formation method further includes: performing gas cleaning treatment on the reaction chamber used to form the epitaxial layer at a third preset temperature, the third preset temperature being equal to the first preset temperature corresponding to the first heat treatment; in the first heat treatment, after performing gas cleaning treatment on the reaction chamber used to form the epitaxial layer, the substrate is heated until a second preset temperature is reached.
[0022] Optionally, the gas cleaning process includes: purging the reaction chamber used to form the epitaxial layer with hydrogen gas to remove impurity gases from the reaction chamber.
[0023] Optionally, after completing the element precipitation process and before forming the epitaxial layer covering the first side of the substrate at the preset growth temperature, the method further includes: performing a second baking process on the substrate at the preset growth temperature.
[0024] Optionally, after the substrate undergoes a second baking treatment at the preset growth temperature, and before forming an epitaxial layer covering the first side of the substrate at the preset growth temperature, the method further includes: stabilizing the flow rate of the epitaxial process gas.
[0025] Optionally, the process for removing the diffusion barrier layer includes a wet etching process.
[0026] Optionally, the diffusion barrier layer can be formed using a furnace tube process.
[0027] Optionally, in the step of forming the diffusion barrier layer, the material of the diffusion barrier layer includes silicon oxide.
[0028] Optionally, the first dopant ion is a group IIIA element and the second dopant ion is a group VA element.
[0029] Optionally, in the step of forming an epitaxial layer covering the first side of the substrate, the epitaxial layer has a third doped ion, which is of the same type as the first doped ion.
[0030] Optionally, an ion implantation process is used to form a pre-embedded layer in the substrate.
[0031] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:
[0032] This invention provides a method for forming a semiconductor structure, comprising: providing a substrate having a first doped ion, the substrate including a first surface and a second surface opposite to the first surface; forming a buried layer on the first surface of the substrate, the buried layer having a second doped ion, wherein the first doped ion and the second doped ion are inversely related; after forming the buried layer, pre-treating the substrate, the pre-treating including one or both of element precipitation treatment on the first surface and element blocking treatment on the second surface; and after pre-treating the substrate, forming an epitaxial layer covering the first surface of the substrate. In this embodiment, if the second surface is subjected to element blocking treatment, the probability of elements in the substrate and the embedded layer escaping from the second surface is reduced. Consequently, during the epitaxial layer growth process, the probability of self-doping effect is easily reduced, thereby enabling the spreading resistivity profile (SRP) curve to be closer to the substrate region. If the first surface is subjected to element precipitation treatment, the probability of element neutralization between the substrate and the embedded layer is reduced, thereby enabling the spreading resistivity profile curve to be closer to the substrate region. In summary, using either or both of element precipitation treatment and element blocking treatment can make the spreading resistivity profile curve closer to the substrate region, thus reducing the resistivity of the working region of the semiconductor device, thereby making the working region of the semiconductor device wider and improving the performance of the semiconductor device accordingly. Attached Figure Description
[0033] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0034] Figure 5 Is adopted Figures 1 to 4 The diffusion resistivity distribution curve of the semiconductor structure formed by the method;
[0035] Figures 6 to 10 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention;
[0036] Figure 11 This is a temperature curve diagram of each step in the epitaxial growth process in the formation method of this embodiment of the invention;
[0037] Figure 12This is a comparison diagram of the diffusion resistivity distribution curve of a semiconductor structure formed by the formation method of this invention and the diffusion resistivity distribution curve of a semiconductor structure formed by the prior art. Detailed Implementation
[0038] Currently, it is difficult for diffusion resistivity distribution curves to closely approximate the substrate region. This paper analyzes the reasons why diffusion resistivity distribution curves are difficult to approximate the substrate region, using a semiconductor structure formation method as an example.
[0039] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0040] refer to Figure 1 A substrate 10 is provided, the substrate 10 having a first doped ion.
[0041] Continue to refer to Figure 1 An embedded layer 11 is formed in the substrate 10, the embedded layer 11 having a second doped ion, wherein the first doped ion is inversely related to the second doped ion.
[0042] It should be noted that the inversion of the first dopant ion and the second dopant ion means that the doping types of the first dopant ion and the second dopant ion are opposite. For example, when the first dopant ion is N-type, the second dopant ion is P-type; when the first dopant ion is P-type, the second dopant ion is N-type.
[0043] refer to Figure 2 The substrate 10 is subjected to a high-temperature annealing process to form a diffusion barrier layer 14 covering the substrate 10.
[0044] refer to Figure 3 Remove the diffusion barrier layer 14 covering the substrate 10.
[0045] refer to Figure 4 An epitaxial layer 15 is formed on the substrate 10.
[0046] Reference Figure 5 , Figure 5 This is a diffusion resistivity distribution curve of the aforementioned semiconductor structure. The horizontal axis represents the depth from the top surface of the epitaxial layer 15 to the substrate 10, the origin of the coordinate system indicates the position of the top surface of the epitaxial layer 15, and the vertical axis represents the corresponding diffusion resistivity. Because elements in the buried layer 11 and the substrate 10 readily diffuse into the epitaxial layer 15, an auto-doping effect occurs in the epitaxial layer 15 during epitaxial growth, causing the diffusion resistivity distribution curve to move away from the substrate region. Simultaneously, because elements in the buried layer 11 and the substrate 10 readily neutralize each other, this also causes the diffusion resistivity distribution curve to move away from the substrate region.
[0047] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate having a first doped ion, the substrate including a first surface and a second surface opposite to the first surface; forming a buried layer in the first surface of the substrate, the buried layer having a second doped ion, wherein the first doped ion and the second doped ion are inversely related; after forming the buried layer, pre-treating the substrate, the pre-treating including one or both of element precipitation treatment on the first surface and element blocking treatment on the second surface; and after pre-treating the substrate, forming an epitaxial layer covering the first surface of the substrate.
[0048] In the embodiments of this invention, if the second surface is subjected to element blocking treatment, the probability of elements in the substrate and the embedded layer escaping from the second surface is reduced. Consequently, during the epitaxial layer growth process, the probability of self-doping is easily reduced, thereby enabling the diffusion resistivity distribution curve to approach the substrate region. If the first surface is subjected to element precipitation treatment, the probability of element neutralization between elements in the substrate and the embedded layer is reduced, thereby enabling the diffusion resistivity distribution curve to approach the substrate region. In summary, using either or both of element precipitation treatment and element blocking treatment can make the diffusion resistivity distribution curve approach the substrate region, thus reducing the resistivity of the working area of the semiconductor device, thereby making the working area of the semiconductor device wider and correspondingly improving the performance of the semiconductor device.
[0049] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0050] Figures 6 to 10 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Figure 11 This is a temperature curve diagram of each step in the epitaxial growth process in the formation method of this embodiment of the invention. Figure 12 This is a comparison diagram of the diffusion resistivity distribution curve of a semiconductor structure formed by the formation method of this invention and the diffusion resistivity distribution curve of a semiconductor structure formed by the prior art.
[0051] refer to Figure 6 A substrate 100 is provided, the substrate 100 having a first doped ion, the substrate 100 including a first surface 101 and a second surface 102 opposite to the first surface 101.
[0052] Substrate 100 is used to provide a process platform for the formation of semiconductor structures.
[0053] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium bismuth. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.
[0054] As an example, if the substrate 100 is a P-type substrate (P-Sub), then the first dopant ion in the substrate 100 is a P-type dopant ion. Specifically, the P-type dopant ion (i.e. the first dopant ion) is a group IIIA element, such as boron (B).
[0055] Continue to refer to Figure 6 An embedded layer 103 is formed on the first surface 101 of the substrate 100. The embedded layer 103 has a second doped ion and is located in the first surface 101 of the substrate 100. The first doped ion is inversely related to the second doped ion.
[0056] The embedded layer 103 is located in the first surface 101 of the substrate 100 and is used to provide a substrate 100 that meets the device performance requirements for the semiconductor structure, thereby realizing basic device functions.
[0057] It should be noted that the inversion of the first dopant ion and the second dopant ion means that the doping types of the first dopant ion and the second dopant ion are opposite. For example, when the first dopant ion is N-type, the second dopant ion is P-type; when the first dopant ion is P-type, the second dopant ion is N-type.
[0058] Therefore, in this embodiment, the second dopant ion is an N-type dopant ion. Specifically, the N-type dopant ion (i.e., the second dopant ion) is a group VA element, such as arsenic (As), antimony (Sb), and phosphorus (P).
[0059] In this embodiment, an ion implantation process is used to form a pre-buried layer 103 in the substrate 100.
[0060] Specifically, ion implantation offers advantages such as high resolution, precise control, suitability for customized modification, and no need for physical contact. It can be used to achieve highly controllable ion implantation, which is beneficial for the precise formation of a pre-buried layer 103 in the substrate 100.
[0061] refer to Figures 7 to 9 After the embedded layer 103 is formed, the substrate 100 is pretreated. The pretreatment includes performing element blocking treatment on the second surface 102 and element precipitation treatment on the first surface 101 in sequence.
[0062] It should be noted that if the second surface 102 is subjected to element blocking treatment, the probability of elements in the substrate 100 and the embedded layer 103 escaping from the second surface 102 is reduced. Consequently, during the epitaxial layer growth process, the probability of self-doping effect is reduced, thereby making the diffusion resistivity distribution curve closer to the substrate 100 region. If the first surface 101 is subjected to element precipitation treatment, the probability of element neutralization between the substrate 100 and the embedded layer 103 is reduced, thereby making the diffusion resistivity distribution curve closer to the substrate region. In summary, using either or both of element precipitation treatment and element blocking treatment can make the diffusion resistivity distribution curve closer to the substrate 100 region, thus reducing the resistivity of the working region of the semiconductor device, thereby making the working region of the semiconductor device wider and improving the performance of the semiconductor device accordingly.
[0063] In this embodiment, the preprocessing includes sequentially performing element blocking processing on the second surface 102 and element precipitation processing on the first surface 101.
[0064] The element blocking process of the second surface 102 will be described in detail below with reference to the accompanying drawings.
[0065] Reference Figures 7 to 8 The step of performing element blocking treatment on the second surface 102 includes: forming a diffusion barrier layer 104 covering the second surface 102 of the substrate 100.
[0066] In subsequent processes, the diffusion barrier layer 104 is used to prevent elements in the substrate 100 and the embedded layer 103 from escaping from the surface of the substrate 100.
[0067] In this embodiment, the diffusion barrier layer 104 is formed using a furnace tube process.
[0068] It should be noted that, due to the high process temperature of the furnace tube process, the elements in the embedded layer 103 diffuse towards the second surface 102 of the substrate 100, thereby increasing the depth of the embedded layer 103. Simultaneously, a diffusion barrier layer 104 (such as...) is formed on the surface of the substrate 100. Figure 7 As shown, this can prevent elements in the substrate 100 and the embedded layer 103 from escaping from the surface of the substrate 100, thereby precisely controlling the distribution of doped elements in the substrate 100 and thus optimizing the electrical performance of the semiconductor structure.
[0069] In this embodiment, the material of the diffusion barrier layer 104 in the step of forming the diffusion barrier layer 104 includes silicon oxide.
[0070] It should be noted that silicon oxide has a good diffusion barrier effect, which can effectively prevent elements in the substrate 100 and the embedded layer 103 from escaping from the surface of the substrate 100. At the same time, silicon oxide is easy to grow on the substrate 100, which improves production efficiency and reduces production costs.
[0071] refer to Figure 7 In this embodiment, in the step of forming the diffusion barrier layer 104, a diffusion barrier layer 104 is formed covering the first surface 101 and the second surface 102 of the substrate 100.
[0072] Specifically, a diffusion barrier layer 104 is formed covering the first surface 101 and the second surface 102 of the substrate 100. During the high-temperature furnace tube process, this helps to reduce the loss of dopants in the substrate 100 and the embedded layer 103. In other words, it can reduce the probability of dopants in the substrate 100 and the embedded layer 103 escaping from the surface of the substrate 100.
[0073] It should be noted that by using a furnace tube process to form the diffusion barrier layer 104, it is easy to form the diffusion barrier layer 104 on both the first surface 101 and the second surface 102.
[0074] refer to Figure 8 Before forming the epitaxial layer covering the first surface 101 of the substrate 100, the method further includes: removing the diffusion barrier layer 104 of the first surface 101 to expose the first surface 101 of the substrate 100, and retaining the diffusion barrier layer 104 of the second surface 102 of the substrate 100.
[0075] It should be noted that removing the diffusion barrier layer 104 of the first surface 101 to expose the first surface 101 of the substrate 100 is to prepare for the subsequent formation of the epitaxial layer. At the same time, the diffusion barrier layer 104 of the second surface 104 of the substrate 100 is retained, so that the second surface 102 is subjected to element blocking treatment by retaining the diffusion barrier layer 104 of the second surface 102.
[0076] It should also be noted that forming a diffusion barrier layer 104 on the first surface 101 and the second surface 102 of the substrate 100 and then removing the diffusion barrier layer 104 on the first surface 101 is beneficial for repairing defects present in the first surface 101 of the substrate 100, thereby improving the flatness of the first surface 101 of the substrate 100 and correspondingly reducing the probability of defects present in the subsequent formation of an epitaxial layer on the first surface 101.
[0077] In this embodiment, the process for removing the diffusion barrier layer 104 of the first surface 101 includes a wet etching process.
[0078] Specifically, wet etching processes can easily achieve a high etching selectivity between the object being etched (the diffusion barrier layer 104 of the first surface 101) and other film layers (e.g., the substrate 100, the buried layer 103), thereby reducing damage to other film layers.
[0079] In this embodiment, the mechanism for removing the diffusion barrier layer 104 of the first surface 101 and retaining the diffusion barrier layer 104 of the second surface 102 using a wet etching process is as follows: During the wet etching process, nitrogen gas is used to passivate the diffusion barrier layer 104 of the second surface 102, thereby reducing the probability of removing the diffusion barrier layer 104 of the second surface 102. At the same time, during the removal of the diffusion barrier layer 104 of the first surface 101, the substrate 100 is also rotated, which helps to reduce the time that the etching solution exists on the second surface 102 of the substrate 100, thereby reducing the probability of removing the diffusion barrier layer 104 of the second surface 102.
[0080] In this embodiment, after removing the diffusion barrier layer 104 of the first surface 101, the first surface 101 is subjected to element precipitation treatment.
[0081] It should be noted that after removing the diffusion barrier layer 104 of the first surface 101, it is beneficial for the doped elements in the substrate 100 and the embedded layer 103 to diffuse to the first surface 101 of the substrate 100, thereby reducing the difficulty of performing element precipitation treatment on the first surface 101.
[0082] In this embodiment, the first surface 101 is subjected to element precipitation treatment in the reaction chamber used to form the epitaxial layer.
[0083] The first surface is subjected to element precipitation in the reaction chamber used to form the epitaxial layer, and there is no need to transfer the substrate 100 to other equipment or chambers for epitaxial processing, thereby simplifying the process flow and improving production efficiency.
[0084] Reference Figure 11 , Figure 11 This is a temperature curve diagram of each step in the epitaxial growth process in the formation method of this embodiment of the invention.
[0085] refer to Figure 11 Before performing element precipitation treatment on the first surface 101, the forming method further includes: performing gas cleaning treatment on the reaction chamber used to form the epitaxial layer at a third preset temperature C (as shown in line segment 1), wherein the third preset temperature C is equal to the first preset temperature A corresponding to the first heat treatment.
[0086] Specifically, the reaction chamber used to form the epitaxial layer is subjected to gas purging to provide a clean environment for subsequent steps.
[0087] In this embodiment, the epitaxial growth process includes gas cleaning of the reaction chamber used to form the epitaxial layer. Therefore, an element precipitation treatment step is added to the epitaxial growth process.
[0088] It should be noted that element precipitation treatment usually needs to be carried out in the epitaxial reaction chamber, which makes it easy to add the element precipitation treatment step to the epitaxial growth process.
[0089] It should also be noted that by adding an element precipitation treatment step to the epitaxial growth process, there is no need to add an additional gas cleaning treatment step before the element precipitation treatment, or any additional treatment steps (such as cooling treatment) after the element precipitation treatment, which helps to shorten the overall process time and increase the production capacity.
[0090] In other embodiments, depending on actual process requirements, element precipitation treatment may be performed separately before the epitaxial growth process used to form the epitaxial layer.
[0091] In this embodiment, the gas cleaning process includes: introducing hydrogen gas into the reaction chamber used to form the epitaxial layer for purging (i.e., H2 purge) to remove impurity gases from the reaction chamber.
[0092] It should be noted that because hydrogen has a small molecular weight, it diffuses quickly within the reaction chamber, which accelerates the removal of impurity gases and improves production efficiency.
[0093] Specifically, in this embodiment, nitrogen gas is removed from the reaction chamber.
[0094] In this embodiment, the step of performing element precipitation treatment on the first surface 101 includes: performing one or more heat treatments on the substrate 100 to remove the elements diffused from the first surface 101. Therefore, after performing gas cleaning treatment on the reaction chamber used to form the epitaxial layer, the substrate 100 is heated to start the first heat treatment.
[0095] refer to Figure 11The steps within the dashed box include: heating the substrate 100 from a first preset temperature A to a second preset temperature B; maintaining the second preset temperature B after heating the substrate 100 and performing a first baking process on the substrate 100; wherein, when the heat treatment is performed multiple times, the step of performing element precipitation treatment on the first surface 101 further includes: cooling the substrate 100 between two adjacent heat treatments, from the second preset temperature B of the previous heat treatment to the first preset temperature A of the next heat treatment.
[0096] It should be noted that when the heat treatment is performed multiple times, the first preset temperature A of two adjacent heat treatments can be the same or different, and the second preset temperature B of two adjacent heat treatments can be the same or different.
[0097] refer to Figure 11 As an example, the heat treatment is performed twice. Line segments 2 and 3 represent the first heat treatment, line segments 5 and 6 represent the second heat treatment, and line segment 4 represents the cooling treatment of the substrate 100 between the first and second heat treatments; wherein, line segment 2 represents the heating treatment of the first heat treatment, line segment 3 represents the first baking treatment of the first heat treatment, and line segment 6 represents the first baking treatment of the second heat treatment.
[0098] In this embodiment, during the first heat treatment, after the reaction chamber used to form the epitaxial layer is subjected to gas purging, the substrate is subjected to a heating treatment (e.g., Figure 11 As shown in line segment 2), until the second preset temperature B is reached (as shown in line segment 2).
[0099] In this embodiment, during each heat treatment, the substrate 100 is heated until it reaches a second preset temperature B, in preparation for the subsequent first baking treatment at the second preset temperature B; at the same time, heating the substrate 100 can promote the diffusion of elements in the substrate 100 and the elements in the embedded layer 103 to the first surface 101 of the substrate 100.
[0100] In this embodiment, the temperature rise corresponding to the heating process should not be too large. If the temperature rise corresponding to the heating process is too large, it is easy to cause an excessively large temperature gradient between different regions of the substrate 100, which can easily lead to thermal expansion inside the substrate 100 and thus cause deformation of the substrate 100. Therefore, in this embodiment, the temperature rise corresponding to the heating process is less than or equal to 500 degrees Celsius.
[0101] It should be noted that the temperature rise range corresponding to the heating process refers to the difference between the first preset temperature A and the second preset temperature B in the same heating process step.
[0102] It should also be noted that after heating the substrate 100, the second preset temperature B is maintained, and the substrate 100 is subjected to a first baking treatment in order to remove the elements diffused from the first surface 101 of the substrate 100.
[0103] In this embodiment, the gas used in the first baking process includes a gas containing hydrogen.
[0104] Since the gas containing hydrogen has reducing properties, it can react with the elements in the substrate 100 and the embedded layer 103 to form corresponding hydrides. Under certain conditions, these hydrides are easily volatilized, thereby removing the elements diffused from the first surface 101.
[0105] As an example, the gas containing hydrogen includes hydrogen gas.
[0106] It should also be noted that when the heat treatment is performed multiple times, the substrate 100 is cooled between two adjacent heat treatments to reduce the temperature from the second preset temperature B of the previous heat treatment to the first preset temperature A of the next heat treatment, in preparation for the next heat treatment.
[0107] In this embodiment, the cooling range corresponding to the cooling process should not be too large. If the cooling range corresponding to the cooling process is too large, it is easy to cause an excessively large temperature gradient between different regions of the substrate 100, which can easily lead to shrinkage inside the substrate 100 and thus deformation of the substrate 100. Therefore, in this embodiment, the cooling range corresponding to the cooling process is less than or equal to 500 degrees Celsius.
[0108] It should be noted that the cooling range corresponding to the cooling treatment refers to the difference between the second preset temperature B of the previous heat treatment and the first preset temperature A of the next heat treatment.
[0109] In this embodiment, when the heat treatment is performed multiple times, the second preset temperature B of the last heat treatment is equal to the preset growth temperature of the epitaxial layer.
[0110] It should be noted that since the second preset temperature B of the last heat treatment is equal to the preset growth temperature of the epitaxial layer, the step of lowering the temperature from the second preset temperature B of the last heat treatment to the preset growth temperature of the epitaxial layer is omitted, and the epitaxial layer can be grown directly, thereby improving production efficiency.
[0111] It should also be noted that, in this embodiment, the heat treatment is performed twice, and the second heat treatment is the last heat treatment.
[0112] In this embodiment, the heat treatment is performed multiple times, and the parameters of the first baking treatment corresponding to the last heat treatment include: the process gas includes a gas containing hydrogen (e.g., hydrogen), and the process time is 50 to 150 seconds.
[0113] The process time for the first baking process corresponding to the final heat treatment should not be too long or too short. If the process time for the first baking process corresponding to the final heat treatment is too long, it may damage the semiconductor structure due to prolonged high-temperature processing; if the process time for the first baking process corresponding to the final heat treatment is too short, it may result in poor removal of elements diffused from the first surface 101. Therefore, in this embodiment, the process time for the first baking process corresponding to the final heat treatment is 50 to 150 seconds.
[0114] In this embodiment, the heat treatment includes at least one high-temperature heat treatment. The second preset temperature B corresponding to the high-temperature heat treatment is higher than the preset growth temperature of the epitaxial layer. When the number of heat treatments is multiple, at least the first heat treatment is a high-temperature heat treatment.
[0115] It should be noted that the heat treatment includes at least one high-temperature heat treatment. The second preset temperature B corresponding to the high-temperature heat treatment is higher than the preset growth temperature of the epitaxial layer. That is, the second preset temperature B of the high-temperature heat treatment is higher, which is beneficial to diffuse most of the elements in the substrate 100 and most of the elements in the embedded layer 103 to the first surface 101 of the substrate 100, thereby facilitating the subsequent removal of the elements diffused from the first surface 101.
[0116] It should also be noted that when the heat treatment is performed multiple times, the first heat treatment is a high-temperature heat treatment, which is beneficial to diffuse most of the elements in the substrate 100 and most of the elements in the embedded layer 103 to the first surface 101 of the substrate 100 during the first heat treatment, thereby reducing the number of heat treatments, reducing production time accordingly, and thus improving production efficiency.
[0117] In this embodiment, the heat treatment is performed twice, and the first heat treatment is a high-temperature heat treatment.
[0118] It should be noted that performing two heat treatments reduces the number of process steps, thereby improving production efficiency and reducing production costs.
[0119] In this embodiment, the parameters of the first baking process corresponding to the high-temperature heat treatment include: the process gas includes a gas containing hydrogen (e.g., hydrogen), the second preset temperature B is 1100 degrees Celsius to 1200 degrees Celsius, and the process time is 100 seconds to 200 seconds.
[0120] The process temperature of the first baking process corresponding to the high-temperature heat treatment should not be too high or too low. If the process temperature of the first baking process corresponding to the high-temperature heat treatment is too high, it is easy to generate thermal stress inside the substrate 100, which can easily cause the substrate 100 to deform; if the process temperature of the first baking process corresponding to the high-temperature heat treatment is too low, it is easy to make the removal of elements diffused from the first surface 101 ineffective. Therefore, in this embodiment, the process temperature of the first baking process corresponding to the high-temperature heat treatment is 1100 degrees Celsius to 1200 degrees Celsius.
[0121] The process time for the first baking process corresponding to the high-temperature heat treatment should not be too long or too short. If the process time for the first baking process corresponding to the high-temperature heat treatment is too long, it is easy to damage the semiconductor structure due to prolonged high-temperature treatment; if the process time for the first baking process corresponding to the high-temperature heat treatment is too short, it is easy to result in poor removal of elements diffused from the first surface 101. Therefore, in this embodiment, the process time for the first baking process corresponding to the high-temperature heat treatment is 100 seconds to 200 seconds.
[0122] It should be noted that this embodiment uses preprocessing including element blocking and element precipitation as an example. In some embodiments, the preprocessing may only include element precipitation on the first surface. In other embodiments, the preprocessing may only include element blocking on the second surface.
[0123] refer to Figure 11 In this embodiment, after completing the pretreatment of the substrate 100 and before forming the epitaxial layer covering the first surface 101 of the substrate 100 at the preset growth temperature, the method further includes: performing a second baking treatment on the substrate 100 at the preset growth temperature (as shown in line segment 7).
[0124] It should be noted that in semiconductor manufacturing processes, the surface of substrate 100 is in contact with air, which easily generates a native oxide layer. The second baking process is performed on substrate 100 to remove the native oxide layer and provide a better growth interface for subsequent processes.
[0125] It should also be noted that performing a second baking treatment on the substrate 100 at the preset growth temperature eliminates the step of lowering the process temperature of the second baking treatment on the substrate 100 to the preset growth temperature of the epitaxial layer, allowing the epitaxial layer to be grown directly, thereby improving production efficiency.
[0126] In this embodiment, the process gas used for the second baking process of the substrate 100 is hydrogen.
[0127] refer to Figure 11In this embodiment, after the substrate 100 is subjected to a second baking treatment at the preset growth temperature, and before the epitaxial layer covering the first side of the substrate 100 is formed at the preset growth temperature, the method further includes: stabilizing the flow rate of the epitaxial process gas (as shown in line segment 8).
[0128] It should be noted that stabilizing the flow rate of the epitaxial process gas prepares for the formation of a third dopant ion in the epitaxial layer.
[0129] Reference Figure 9 and Figure 11 After pretreatment of the substrate 100, an epitaxial layer 105 is formed covering the first surface 101 of the substrate 100 (e.g., ...). Figure 11 (As shown in segment 9 of the middle line).
[0130] An epitaxial layer 105 is grown on a substrate 100 to form a substrate with a resistivity that meets process requirements, thereby controlling the resistivity required for the semiconductor structure device.
[0131] In this embodiment, after the element precipitation process is completed, an epitaxial layer 105 covering the first surface 101 of the substrate 100 is formed at the preset growth temperature.
[0132] It should be noted that after the element precipitation process is completed, an epitaxial layer 105 covering the first surface 101 of the substrate 100 is formed at the preset growth temperature. This helps to reduce the probability of neutralization between the elements in the substrate 100 and the elements in the pre-embedded layer 103, thereby enabling the diffusion resistivity distribution curve to be closer to the substrate region.
[0133] In this embodiment, the epitaxial layer 105 is grown on the first surface 101 of the substrate 100 by epitaxy.
[0134] Epitaxial growth process allows for better control of process parameters, resulting in high process controllability and easy acquisition of precise film thickness dimensions. Furthermore, epitaxial growth process is more likely to form film layers with fewer impurities, leading to higher quality of epitaxial layer 105.
[0135] In this embodiment, during the step of forming an epitaxial layer 105 covering the first surface 101 of the substrate 100, the epitaxial layer 105 contains a third doped ion, which is of the same type as the first doped ion.
[0136] It should be noted that the third dopant ion is of the same type as the first dopant ion. During the growth of the epitaxial layer 105, the elements in the pre-buried layer 103 can easily diffuse into the epitaxial layer 105. The third dopant ion is of the same type as the first dopant ion, that is, the doping type of the third dopant ion is the opposite of that of the second dopant ion. Therefore, the third dopant ion in the epitaxial layer 105 can neutralize the second dopant ion, which helps to reduce the self-doping effect.
[0137] refer to Figure 12 , Figure 12 This is a comparison chart of the diffusion resistivity distribution curve of a semiconductor structure formed by the formation method of this invention and a semiconductor structure formed by prior art. The horizontal axis represents the depth from the top surface of epitaxial layer 105 to the substrate 100, the origin represents the position of the top surface of epitaxial layer 150, and the vertical axis represents the corresponding resistivity. Curve 1 is the diffusion resistivity distribution curve of the semiconductor structure formed by prior art, and curve 2 is the diffusion resistivity distribution curve of the semiconductor structure of this invention. Figure 12 As can be seen, compared with curve 1, curve 2 is further away from the origin, that is, curve 2 is closer to the substrate region.
[0138] Therefore, in this embodiment, performing element precipitation treatment on the first surface 101 of the substrate 100 and element blocking treatment on the second surface 102 of the substrate 100 can make the diffusion resistivity distribution curve closer to the substrate region.
[0139] Continue to refer to Figure 11 In this embodiment, after forming the epitaxial layer 105 covering the first surface 101 of the substrate 100 and before removing the diffusion barrier layer 104 covering the second surface 102 of the substrate 100, the method further includes: removing residual gas in the reaction chamber (as shown in line segment 10); cooling the substrate 100 (as shown in line segment 11); and performing gas cleaning treatment on the reaction chamber again (as shown in line segment 12).
[0140] The substrate 100 is cooled to a temperature that allows it to exit the reaction chamber; the reaction chamber is then subjected to gas cleaning to provide a suitable process environment for the next wafer fabrication process.
[0141] refer to Figure 10 In this embodiment, after forming the epitaxial layer 105 covering the first surface 101 of the substrate 100, the method further includes removing the diffusion barrier layer 104 covering the second surface 102 of the substrate 100.
[0142] It should be noted that, since a third ion doping process is required during the formation of the epitaxial layer 105, the diffusion barrier layer 104 on the second side 102 of the substrate 100 may also contain third doped ions. Therefore, removing the diffusion barrier layer 104 covering the second side 102 of the substrate 100 reduces the probability of third doped ions on the second side of the substrate, thereby making the electrical characteristics of the second side 102 of the substrate less susceptible to the influence of third doped ions.
[0143] In this embodiment, the process for removing the diffusion barrier layer 104 includes a wet etching process.
[0144] Specifically, wet etching processes can easily achieve a high etching selectivity between the object being etched (the diffusion barrier layer 104 of the first surface 101) and other film layers (e.g., the substrate 100, the buried layer 103), thereby reducing damage to other film layers.
[0145] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate having a first doped ion, the substrate including a first surface and a second surface opposite to the first surface; An embedded layer is formed on a first surface of the substrate, the embedded layer having a second doped ion, wherein the first doped ion is inversely related to the second doped ion; After the embedded layer is formed, the substrate is pretreated. The pretreatment includes one or both of element precipitation treatment on the first surface and element blocking treatment on the second surface. After pretreatment of the substrate, an epitaxial layer is formed covering the first surface of the substrate.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of performing element blocking treatment on the second surface includes: forming a diffusion barrier layer covering the second surface of the substrate.
3. The method for forming a semiconductor structure as described in claim 2, characterized in that, After forming the epitaxial layer covering the first side of the substrate, the process further includes removing the diffusion barrier layer covering the second side of the substrate.
4. The method for forming a semiconductor structure as described in claim 2, characterized in that, In the step of forming a diffusion barrier layer covering the second side of the substrate, a diffusion barrier layer covering the first side and the second side of the substrate is formed; Before forming the epitaxial layer covering the first side of the substrate, the method further includes: removing the diffusion barrier layer on the first side to expose the first side of the substrate, and retaining the diffusion barrier layer on the second side of the substrate.
5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The preprocessing includes sequentially performing element blocking processing on the second surface and element precipitation processing on the first surface; In this process, after removing the diffusion barrier layer on the first surface, element precipitation is performed on the first surface.
6. The method for forming a semiconductor structure according to any one of claims 1 to 5, characterized in that, The step of performing element precipitation treatment on the first surface includes: performing one or more heat treatments on the substrate to remove elements diffused from the first surface, wherein the heat treatment includes: heating the substrate from a first preset temperature to a second preset temperature; and after heating the substrate, maintaining the second preset temperature and performing a first baking treatment on the substrate. When the heat treatment is performed multiple times, the step of performing element precipitation treatment on the first surface further includes: performing a cooling treatment on the substrate between two adjacent heat treatments, for cooling from the second preset temperature of the previous heat treatment to the first preset temperature of the next heat treatment.
7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The temperature rise corresponding to the heating process is less than or equal to 500 degrees Celsius.
8. The method for forming a semiconductor structure as described in claim 6, characterized in that, The cooling process corresponds to a temperature reduction of less than or equal to 500 degrees Celsius.
9. The method for forming a semiconductor structure as described in claim 6, characterized in that, The gas used in the first baking process includes a gas containing hydrogen.
10. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the first baking process, the gas containing hydrogen includes hydrogen gas.
11. The method for forming a semiconductor structure as described in claim 6, characterized in that, The first surface is subjected to element precipitation treatment in the reaction chamber used to form the epitaxial layer.
12. The method for forming a semiconductor structure as described in claim 11, characterized in that, When the heat treatment is performed multiple times, the second preset temperature of the last heat treatment is equal to the preset growth temperature of the epitaxial layer. After the element precipitation process is completed, an epitaxial layer covering the first side of the substrate is formed at the preset growth temperature.
13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The heat treatment is performed multiple times, and the parameters of the first baking process corresponding to the last heat treatment include: the process time is 50 seconds to 150 seconds.
14. The method for forming a semiconductor structure as described in claim 11, characterized in that, The heat treatment includes at least one high-temperature heat treatment, wherein the second preset temperature corresponding to the high-temperature heat treatment is higher than the preset growth temperature of the epitaxial layer, and when the heat treatment is performed multiple times, at least the first heat treatment is a high-temperature heat treatment.
15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The parameters of the first baking process corresponding to the high-temperature heat treatment include: the process gas includes a gas containing hydrogen, the second preset temperature is 1100 degrees Celsius to 1200 degrees Celsius, and the process time is 100 seconds to 200 seconds.
16. The method for forming a semiconductor structure as described in claim 11, characterized in that, Before performing element precipitation treatment on the first surface, the forming method further includes: performing gas cleaning treatment on the reaction chamber used to form the epitaxial layer at a third preset temperature, wherein the third preset temperature is equal to the first preset temperature corresponding to the first heat treatment; In the first heat treatment, after the reaction chamber used to form the epitaxial layer is gas-cleaned, the substrate is heated until a second preset temperature is reached.
17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The gas cleaning process includes: purging the reaction chamber used to form the epitaxial layer with hydrogen gas to remove impurity gases from the reaction chamber.
18. The method for forming a semiconductor structure as described in claim 11, characterized in that, After the element precipitation process is completed, and before forming an epitaxial layer covering the first side of the substrate at the preset growth temperature, the process further includes: performing a second baking process on the substrate at the preset growth temperature.
19. The method for forming a semiconductor structure as described in claim 18, characterized in that, After the substrate is subjected to a second baking treatment at the preset growth temperature, and before the epitaxial layer covering the first side of the substrate is formed at the preset growth temperature, the method further includes: stabilizing the flow rate of the epitaxial process gas.
20. The method for forming a semiconductor structure as described in claim 3 or 4, characterized in that, The process for removing the diffusion barrier layer includes a wet etching process.
21. The method for forming a semiconductor structure as described in claim 2 or 4, characterized in that, The diffusion barrier layer is formed using a furnace tube process.
22. The method for forming a semiconductor structure as described in claim 2 or 4, characterized in that, In the step of forming the diffusion barrier layer, the material of the diffusion barrier layer includes silicon oxide.
23. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first doped ion is a group IIIA element, and the second doped ion is a group VA element.
24. The method for forming a semiconductor structure as described in claim 1 or 23, characterized in that, In the step of forming an epitaxial layer covering the first side of the substrate, the epitaxial layer has a third doped ion, which is of the same type as the first doped ion.
25. The method for forming a semiconductor structure as described in claim 1, characterized in that, An ion implantation process is used to form a pre-embedded layer in the substrate.