Chip detection device and chip detection method

Abstract

This invention discloses a chip testing device and a chip testing method. The device includes a probe module, a polarization-modulated multispectral optical path system, an excitation sampling unit, and a heterogeneous data fusion processing system. The probe module includes an opaque carrier, a transparent element embedded in a hole in the carrier, and a cantilever probe array arranged at the bottom of the carrier. The polarization-modulated multispectral optical path system is arranged above the transparent element. The excitation sampling unit is used to apply power pulse excitation to the chip under test, and can simultaneously acquire the electrical response sequence generated by the probe module and the optical feature image stream acquired by the polarization-modulated multispectral optical path system. The heterogeneous data fusion processing system includes a visual recognition module and a physical inversion module. The visual recognition module is used to identify stress distortion regions from the optical feature images. The physical inversion module substitutes the stress distortion regions into the PINN model, combines the electrical response sequence, and inversely deduces the deep physical state variables inside the chip under test.

Description

Technical Field

[0001] This invention relates to the field of chip inspection technology, and in particular to a chip inspection device and method that utilizes probes and vision to perform multimodal chip inspection. Background Technology

[0002] As power semiconductor chips develop towards higher frequencies and higher power densities, their transient thermal stress reliability during operation has become a focus of industry attention. Microscopic defects at the chip interface (such as holes and cracks) can easily lead to system failure under high temperature and high pressure environments, making high-precision in-situ testing during the production process crucial.

[0003] Currently, various solutions have emerged in the semiconductor testing field to improve testing efficiency. For example, prior art CN221946296 U discloses a chip measurement device that, through the cooperation of a moving platform, an image acquisition module, and a probe card module, enables the testing of the electrical characteristics (such as short circuits and dead pixels) and optical indicators (such as reflectivity and phase modulation depth) of LCoS chips before the bonding process, effectively shortening the process time and reducing material costs. Prior art CN 102445668 A proposes a wafer-level light-emitting diode chip testing method. This method utilizes a transparent probe card to cover the wafer and perform a lighting test. Through imaging processing, it acquires the light field and position information of all LED chips at once, solving the problem of low efficiency in point-by-point testing.

[0004] However, the aforementioned existing technologies still have significant limitations: (1) Most existing automated optical inspection (AOI) focuses on the observation of surface display effects or geometric dimensions, and cannot detect internal defects; (2) Although traditional transient electrical tests can reflect the overall performance deviation of the chip, it is difficult to spatially correlate the changes in electrical signals with the specific physical damage locations inside the chip. Summary of the Invention

[0005] Purpose of the invention: In order to overcome the shortcomings of the existing technology, the present invention provides a chip inspection device and chip inspection method that can realize the combined analysis of electrical detection, visual inspection, and stress analysis to discover hidden internal defects of chips.

[0006] Technical solution: To achieve the above objectives, the chip detection device of the present invention includes a probe module, a polarization modulation multispectral optical path system, an excitation sampling unit, and a heterogeneous data fusion processing system; The probe module includes an opaque carrier, a transparent element embedded in a hole in the carrier, and a cantilever probe array arranged at the bottom of the carrier; the carrier can be made of alumina ceramic; the transparent element can be made of materials such as magnesium aluminate spinel. The polarization-modulated multispectral optical path system is arranged above the transparent element and can transform the stress field evolution inside the chip under test into a visualized optical feature image through polarization modulation; the optical feature image appears as colorful interference fringe shapes. The excitation sampling unit is used to apply power pulse excitation to the chip under test through a portion of the cantilever probes in the cantilever probe array, and can simultaneously acquire the electrical response sequence generated by the probe module and the optical feature image stream acquired by the polarization modulation multispectral optical path system. Specifically, the excitation sampling unit includes a synchronization trigger, which can generate a microsecond-level synchronization pulse when the rising edge of the test current reaches a preset threshold to synchronously activate the oscilloscope acquisition card connected to a portion of the cantilever probes in the cantilever probe array and the imaging sensor in the polarization modulation multispectral optical path system. This allows the data acquired by the oscilloscope acquisition card and the imaging sensor to be phase-aligned on the time axis.

[0007] The heterogeneous data fusion processing system includes a visual recognition module and a physical inversion module. The visual recognition module is used to identify stress distortion regions from the optical feature images. The physical inversion module substitutes the stress distortion regions into the PINN model and combines them with the electrical response sequence to reverse-engineer the deep physical state variables inside the chip under test and draw a defect conclusion.

[0008] Furthermore, the wall of the central hole of the bearing seat has a supporting step, and the transparent element has a flange that abuts against the supporting step; and a polyimide buffer layer with a thickness of 10μm-50μm is provided between the outer peripheral surface of the transparent element and the hole wall.

[0009] Furthermore, the difference between the coefficient of thermal expansion of the transparent element and the coefficient of thermal expansion of the substrate of the chip under test does not exceed 2.0 × 10⁻⁶. -6 / ℃ During operation, there is a gap of 50μm-100μm between the bottom surface of the transparent element and the top surface of the chip under test. As the chip under test heats up rapidly under the excitation of power pulse, the transparent element will also heat up. By making the thermal expansion coefficients of the two similar, the thermal drift and blurring of the pattern caused by the large increase in chip temperature can be effectively eliminated, ensuring the stability of the acquired image quality.

[0010] Furthermore, the surface of the transparent element is covered with a transparent conductive ITO shielding layer, and a metal ring is fixed at the upper end of the support to press down the edge of the transparent element and is electrically connected to the ITO shielding layer; the metal ring is electrically connected to the grounding terminal of the probe module.

[0011] Furthermore, the lower side of the transparent element protrudes beyond the support, and the bottom side of the transparent element has a slot for inserting the contact section of the cantilever probe. The cantilever probe has a fixed section, an elastic transition section, and a contact section. The fixed section is fixed to the support, the elastic transition section extends laterally, and the contact section is used to contact the pads of the chip.

[0012] Furthermore, the polarization-modulated multispectral optical path system also includes a coaxial light source, a polarizer, an analyzer, a dichroic prism assembly, and an imaging sensor; The coaxial light source can provide a broadband detection light covering the visible to near-infrared band; the polarizer is arranged in the incident light path of the coaxial light source and can modulate the detection light into linearly polarized light in a first polarization direction. The analyzer and the dichroic prism group are arranged in the reflected light path between the transparent element and the imaging sensor, and the dichroic prism group is located behind the analyzer; the polarization transmission axis of the analyzer is arranged at a 90° angle with the first polarization direction to form an orthogonal polarization field; the dichroic prism group decomposes the reflected light carrying phase delay information into multiple spectral channels according to the wavelength, and maps them to the corresponding imaging sensors respectively.

[0013] In this invention, a coaxial light source with a wavelength range covering 400nm to 1100nm is used. The dichroic prism group decomposes the reflected light into three channels: ultraviolet light, visible light, and near-infrared light. The imaging sensor corresponding to the ultraviolet light channel is used to detect microcracks. The imaging sensor corresponding to the visible light channel is used to lock the surface deformation and extract the region of interest of YOLOv11n. The imaging sensor corresponding to the infrared light channel is used to capture the stress concentration inside the chip and at the solder joint interface.

[0014] A chip testing method, applied to the aforementioned chip testing apparatus, the method comprising: The excitation sampling unit is controlled to apply a power pulse excitation to the chip under test, while simultaneously acquiring the optical feature image stream and electrical response sequence V of the chip under test. ds (t); The YOLOv11n algorithm is used to scan the optical feature image stream in real time, and the defect geometric parameters F of the region of interest are output. S The region of interest includes the center coordinates (x, y), the coverage area (w, h), and the confidence level C, where w and h represent the width and height of the region of interest, respectively. In this step, the stress singular region, i.e. the region of interest, is locked by identifying the topological distortion points of the interference fringes. The region of interest is transformed into a physical domain boundary operator Γ, and the confidence level C is mapped to the weight coefficient λ of the physical constraint term; With the electrical response sequence V ds(t) is used as the input to the PINN model. Within the Γ-constrained space, the loss function is used to iterate the neuron weights and calculate the deep physical state variables inside the chip. The deep physical state variables include the maximum temperature rise at the interface ΔT. int and the maximum stress gradient ∇σ inside the chip max The loss function is: ; Where L is the total loss function; the first term after the equals sign is the data-driven error, and the second term is the physical residual term based on Fourier's law of thermal conductivity; The chip output voltage waveform value predicted by the neural network. The actual acquired chip output voltage waveform value; k is the thermal conductivity of the material; For temperature gradient; It represents the amount of heat that enters a unit volume per unit time through thermal conduction; This is the internal heat source, that is, the Joule heat generated by the current flowing through the chip; The density of the material; The specific heat capacity at constant pressure of the material; It represents the rate of change of energy per unit volume over time; it couples the surface features of the chip under test, the deep physical state variables, and the electrical offset to determine whether the chip has an early latent failure risk.

[0015] Furthermore, the coupling of the surface features of the chip under test, the deep state variables, and the electrical offset to determine whether the chip has an early latent failure risk includes: Extract the defect geometric parameters F S The highest temperature rise ΔT at the interface int Maximum stress gradient ∇σ inside the chip max and electrical deviation ΔV ds Normalize the four elements to construct a normalized discriminant vector: F respectively S ΔT int 、∇σ max ΔV ds The normalized parameters are w1, w2, w3, and w4, which are the weights of the corresponding parameters. Calculate the partial derivatives of the rate of change of electrical parameters with respect to the internal stress gradient, and construct the sensitivity matrix. If the eigenvalue of S exceeds the preset structural instability threshold, it is determined that the chip has a structural damage evolution trend that cannot be eliminated even if the electrical parameters are qualified. The normalized discriminant vector H is input into the pre-stored chip health digital model, and the spatial correlation coefficient residual R between the measured field and the ideal field is calculated by comparison. The sensitivity analysis and residual discrimination results are coupled to output the chip's health score.

[0016] Furthermore, the coupling of the sensitivity analysis and residual discrimination results to output the chip's health score includes: The comprehensive damage index, which characterizes the degree of chip damage, is calculated based on the following formula: ; Wherein, DI is the comprehensive damage index; The magnitude of the normalized discriminant vector represents the overall degree of anomaly observed at present; The largest eigenvalue of the sensitivity matrix represents the direction in which the structure is least stable. The average residual output by the chip health digital model represents the deviation between the measured physical field and the ideal model; γ, α, and β are sensitivity adjustment coefficients. The determination of whether the chip has an early latent failure risk includes: When DI exceeds the preset upper limit threshold τ1, the chip is determined to be severely faulty, and the hardware interlock of the test device is triggered to stop subsequent high voltage pulses and prevent damage to the probe and circuit. When DI is greater than the preset lower threshold τ2 and not greater than the upper threshold τ1, it is determined to be a sub-healthy chip.

[0017] Beneficial effects: The chip detection device and chip detection method of the present invention have the following beneficial effects: (1) The chip inspection device of the present invention integrates the cantilever probe group with the polarization modulation multispectral optical path system, realizing the collaborative operation of electrical inspection, stress analysis and visual inspection. The probe module can not only detect the electrical performance of the chip, but also electrically excite the chip under inspection to induce stress changes inside the chip. The polarization modulation multispectral optical path system reflects the stress situation as image texture, so that the heterogeneous data fusion processing system can judge the internal defect status of the chip based on the image texture. The above-mentioned electrical inspection and stress inspection are closely linked, and are not limited to the detection of power-on state and surface defects that can only be performed in the prior art, but can also detect internal defects that affect the chip life in a timely manner.

[0018] (2) The chip detection method of the present invention determines the region of interest by using the lightweight YOLOv11n algorithm, and then constructs a Γ operator for layered defects based on the region of interest, realizing the mapping from the visual pixel domain to the physical continuous domain, which serves as the prior boundary of the PINN model. When the visual algorithm detects a region of interest with suspected defects, the Γ operator automatically replaces the displacement continuity constraint at the corresponding coordinate with the stress free boundary condition, thereby forcing the PINN model to simulate the stress concentration phenomenon in this local area, so that the deep stress field obtained by inversion conforms to the actual physical evolution law, realizing the deduction of the internal problems of the chip, and under the action of the Γ operator, the model can achieve rapid convergence, avoiding the problem of full convergence and low accuracy in global calculation. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the chip detection device. Figure 2 This is a cross-sectional view of the probe module. Figure 3 This is a bottom view of the probe module. Figure 4 This is a top view of the probe module. Figure 5 This is a flowchart illustrating the chip testing method.

[0020] In the figure: 1-Probe module; 11-Bearing seat; 11a-Supporting step; 12-Transparent element; 12a-Flange; 12b-Slot; 13-Cantilever probe; 13a-Fixed section; 13b-Elastic transition section; 13c-Contact section; 14-Metal ring; 2-Polarization modulation multispectral optical path system; 21-Coaxial light source; 22-Polarizer; 23-Analyzer; 24-Dialectical prism group; 25-Imaging sensor; 26-Beam splitter. Detailed Implementation

[0021] The invention will now be further described with reference to the accompanying drawings.

[0022] like Figure 1 The chip detection device shown includes a probe module 1, a polarization modulation multispectral optical path system 2, an excitation sampling unit, and a heterogeneous data fusion processing system. like Figures 2 to 4 As shown, the probe module 1 includes an opaque support 11, a transparent element 12 embedded in the hole of the support 11, and a cantilever probe array arranged at the bottom of the support 11; the support 11 can be made of alumina ceramic; the transparent element 12 can be made of materials such as magnesium aluminate spinel. The polarization-modulated multispectral optical path system 2 is arranged above the transparent element 12, and can transform the stress field evolution inside the chip under test into a visualized optical feature image through polarization modulation; the optical feature image is presented as a colorful interference fringe shape. The excitation sampling unit is used to apply power pulse excitation to the chip under test through a portion of the cantilever probes 13 in the cantilever probe array, and can simultaneously acquire the electrical response sequence generated by the probe module 1 and the optical feature image stream acquired by the polarization modulation multispectral optical path system 2. Specifically, the excitation sampling unit includes a synchronization trigger, which can generate a microsecond-level synchronization pulse when the rising edge of the test current reaches a preset threshold to synchronously activate the oscilloscope acquisition card connected to a portion of the cantilever probes 13 in the cantilever probe array and the imaging sensor 25 in the polarization modulation multispectral optical path system 2. This allows the data acquired by the oscilloscope acquisition card and the imaging sensor 25 to be phase-aligned on the time axis.

[0023] The heterogeneous data fusion processing system includes a visual recognition module and a physical inversion module. The visual recognition module is used to identify stress distortion regions from the optical feature images. The physical inversion module substitutes the stress distortion regions into the PINN model and combines them with the electrical response sequence to reverse-engineer the deep physical state variables inside the chip under test and draw a defect conclusion.

[0024] The chip inspection device of this invention integrates a cantilever probe group with a polarization-modulated multispectral optical path system, achieving collaborative operation of electrical inspection, stress analysis, and visual inspection. The probe module 1 not only detects the electrical performance of the chip but also electrically excites it, inducing stress changes within the chip. The polarization-modulated multispectral optical path system 2 reflects this stress as image texture, enabling the heterogeneous data fusion processing system to determine the internal defect status of the chip based on this texture. The aforementioned electrical and stress inspections are interconnected, extending beyond the detection of only electrical states and surface defects found in existing technologies, and enabling the timely detection of internal defects affecting chip lifespan.

[0025] In the structure of probe module 1, the transparent element 12 embedded in the hole of the support 11 realizes the physical gain of stress signal through its optical birefringence characteristics, so that stress characteristics can be reflected as optical characteristics.

[0026] Preferably, the wall of the central hole of the bearing seat 11 has a supporting step 11a, and the transparent element 12 has a flange 12a that abuts against the supporting step 11a; and a polyimide buffer layer with a thickness of 10μm-50μm is provided between the outer peripheral surface of the transparent element 12 and the hole wall.

[0027] The interlocking structure of the support 11 and the transparent element 12 can ensure the stability of the connection between the two and the structural strength of the support 11. The setting of the polyimide buffer layer can prevent the two materials from accumulating and causing stress concentration due to the different thermal expansion coefficients of the two materials.

[0028] Furthermore, the difference between the coefficient of thermal expansion of the transparent element 12 and the coefficient of thermal expansion of the substrate of the chip under test does not exceed 2.0 × 10⁻⁶. -6 / ℃ During operation, there is a gap of 50μm-100μm between the bottom surface of the transparent element 12 and the upper surface of the chip under test. As the chip under test heats up rapidly under the excitation of power pulse, the transparent element 12 will also heat up. By making the thermal expansion coefficients of the two similar, the thermal drift and blurring of the pattern caused by the large increase in chip temperature can be effectively eliminated, ensuring the stability of the acquired image quality.

[0029] Preferably, the surface of the transparent element 12 is covered with a transparent conductive ITO shielding layer, and a metal ring 14 is fixed to the upper end of the support 11, pressing down the edge of the transparent element 12 and electrically connected to the ITO shielding layer; the metal ring 14 is electrically connected to the grounding terminal of the probe module 1. The ITO shielding layer is designed for high-voltage testing environments, and can discharge static charges induced by strong electric fields in real time, preventing static electricity from interfering with the fringes of optical interference images, and further protecting precision electronic devices from the risk of electrical breakdown during testing.

[0030] Preferably, the lower side of the transparent element 12 protrudes beyond the support base 11, and the bottom side of the transparent element 12 has a slot 12b for inserting the contact section of the cantilever probe 13. The cantilever probe 13 has a fixed section 13a, an elastic transition section 13b, and a contact section 13c. The fixed section 13a is fixed to the support base 11, the elastic transition section 13b extends laterally, and the contact section 13c is used to contact the pads of the chip. With the above structure, it is possible to ensure that the end of the cantilever probe 13 contacts the pads of the chip under test while ensuring that there is a very small gap between the upper surface of the chip and the bottom end of the transparent element 12.

[0031] Preferably, the polarization modulation multispectral optical path system 2 further includes a coaxial light source 21, a polarizer 22, an analyzer 23, a dichroic prism group 24, and an imaging sensor 25; The coaxial light source 21 can provide a broadband detection light covering the visible to near-infrared band; the polarizer 22 is arranged in the incident light path of the coaxial light source 21 and can modulate the detection light into linearly polarized light in the first polarization direction; the linearly polarized light is reflected to the transparent element 12 by the beam splitter 26.

[0032] The analyzer 23 and the dichroic prism group 24 are arranged in the reflected light path between the transparent element 12 and the imaging sensor 24, and the dichroic prism group 24 is located behind the analyzer 23; the polarization transmission axis of the analyzer 23 is arranged at a 90° angle with the first polarization direction to form an orthogonal polarization field; the dichroic prism group 24 decomposes the reflected light carrying phase delay information into multiple spectral channels according to the wavelength, and maps them to the corresponding imaging sensor 25 respectively.

[0033] During operation, there is a 50μm-100μm gap between the bottom surface of the transparent element 12 and the top surface of the chip under test. If there are defects inside the chip, thermal mismatch can lead to stress concentration, which manifests as deformation of the chip surface. This causes a slight deflection of the linearly polarized light incident on the surface. The birefringence of the transparent element 12 amplifies this slight deflection, resulting in an interference fringe pattern. This interference fringe pattern reflects the stress concentration within the chip; the fringe density represents the stress gradient, and the fringe shape represents the stress distribution direction. The reflected light can pass through the beam splitter 26.

[0034] In this invention, a coaxial light source with a wavelength range covering 400nm to 1100nm is used. The dichroic prism group 24 decomposes the reflected light into three channels: ultraviolet light, visible light, and near-infrared light. The imaging sensor 25 based on the ultraviolet light channel is used to detect microcracks. The imaging sensor 25 based on the visible light channel is used to lock the surface deformation and extract the region of interest of YOLOv11n. The imaging sensor 25 based on the infrared light channel is used to capture the stress concentration inside the chip and at the solder joint interface.

[0035] A chip testing method, applied to the aforementioned chip testing apparatus, such as... Figure 5 As shown, the method includes the following steps S1-S5: Step S1: Control the excitation sampling unit to apply power pulse excitation to the chip under test, and simultaneously acquire the optical feature image stream and electrical response sequence V of the chip under test. ds (t); Step S2: Run the YOLOv11n algorithm to scan the optical feature image stream in real time and output the defect geometric parameters F of the region of interest. S The region of interest includes the center coordinates (x, y), the coverage area (w, h), and the confidence level C, where w and h represent the width and height of the region of interest, respectively. In this step, the stress singular region, i.e. the region of interest, is locked by identifying the topological distortion points of the interference fringes. Step S3: Transform the region of interest into the physical domain boundary operator Γ, and map the confidence level C into the weight coefficient λ of the physical constraint term; Step S4, using the electrical response sequence V ds (t) is used as the input to the PINN model. Within the Γ-constrained space, the loss function is used to iterate the neuron weights and calculate the deep physical state variables inside the chip. The deep physical state variables include the maximum temperature rise at the interface ΔT. int and the maximum stress gradient ∇σ inside the chip max The loss function is: ; Where L is the total loss function; the first term after the equals sign is the data-driven error, and the second term is the physical residual term based on Fourier's law of thermal conductivity; The output voltage waveform value of the chip predicted by the neural network. The actual acquired chip output voltage waveform value; k is the thermal conductivity of the material; For temperature gradient; It represents the amount of heat that enters a unit volume per unit time through thermal conduction; This is the internal heat source, that is, the Joule heat generated by the current flowing through the chip; The density of the material; The specific heat capacity at constant pressure of the material; Represents the rate of change of energy per unit volume over time; The first term in the loss function is used to ensure the generation of the PINN model. The second requirement is that the PINN model must match the actual acquired waveforms, and that its prediction of temperature distribution must conform to the laws of thermodynamics. The waveform matched the actual data, but the temperature change did not conform to the laws of thermodynamics, so L increased, forcing the PINN model to relearn.

[0036] Step S5: Couple the surface features of the chip under test, the deep physical state variables, and the electrical offset to determine whether the chip has an early latent failure risk.

[0037] The chip inspection method of this invention determines the region of interest (ROI) using a lightweight YOLOv11n algorithm, and then constructs a Γ operator for layered defects based on the ROI, realizing the mapping from the visual pixel domain to the physical continuous domain, serving as the prior boundary of the PINN model. When the visual algorithm detects a ROI with suspected defects, the Γ operator automatically replaces the displacement continuity constraint at the corresponding coordinates with stress-free boundary conditions, thereby forcing the PINN model to simulate stress concentration phenomena in that local area. This ensures that the deep stress field obtained by inversion conforms to the actual physical evolution law, enabling the deduction of internal chip problems. Furthermore, under the action of the Γ operator, the model can achieve rapid convergence, avoiding the problems of full convergence and low accuracy in global calculations.

[0038] Preferably, the coupling of the surface features of the chip under test, the deep state variables, and the electrical offset in step S5 above to determine whether the chip has an early latent failure risk includes the following steps S51-S54: Step S51, extract the defect geometric parameters F S The highest temperature rise ΔT at the interface int Maximum stress gradient ∇σ inside the chip max and electrical deviation ΔV ds Normalize the four elements to construct a normalized discriminant vector: ;in, They are respectively The normalized parameters are w1, w2, w3, and w4, which are the weights of the corresponding parameters. Step S52: Calculate the partial derivatives of the rate of change of electrical parameters with respect to the internal stress gradient, and construct the sensitivity matrix. If the eigenvalue of S exceeds the preset structural instability threshold, it is determined that the chip has a structural damage evolution trend that cannot be eliminated even if the electrical parameters are qualified. Step S53: Input the normalized discriminant vector H into the pre-stored chip health digital model, and calculate the spatial correlation coefficient residual R between the measured field and the ideal field by comparison; Step S54: Couple the sensitivity analysis and residual discrimination results to output the health score of the chip.

[0039] By comprehensively extracting and quantifying surface geometric features, internal temperature rise, stress gradient, and electrical parameter deviations, a feature vector reflecting the overall state of the chip is constructed. Like forecasting weather changes, it can capture early defects that, although the electrical signals are currently qualified, have already shown instability in their internal structure and have a tendency to deteriorate. This changes the limitations of previous single-parameter detection and enables the system to have the ability to detect latent failure risks of chips.

[0040] Preferably, the coupling of the sensitivity analysis and residual discrimination results in step S54 above to output the health score of the chip includes: The comprehensive damage index, which characterizes the degree of chip damage, is calculated based on the following formula: ; Wherein, DI is the comprehensive damage index; The modulus of the normalized discrimination vector represents the overall degree of anomaly observed at present; The largest eigenvalue of the sensitivity matrix represents the direction in which the structure is least stable. The average residual output by the chip health digital model represents the deviation between the measured physical field and the ideal model; γ, α, and β are sensitivity adjustment coefficients. The determination of whether the chip has an early latent failure risk in step S5 above includes: When DI exceeds the preset upper limit threshold τ1, the chip is determined to be severely faulty, and the hardware interlock of the test device is triggered to stop subsequent high voltage pulses and prevent damage to the probe and circuit. When DI is greater than the preset lower threshold τ2 and not greater than the upper threshold τ1, it is determined to be a sub-healthy chip.

[0041] The aforementioned comprehensive damage index score can keenly amplify subtle but highly threatening structural hazards, significantly improving the accuracy of identifying latent faults. Simultaneously, severely failed chips are immediately shut down for protection; risky chips are marked, enabling precise grading and safety control of product quality.

[0042] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A chip detection device, characterized in that, It includes a probe module (1), a polarization modulation multispectral optical path system (2), an excitation sampling unit, and a heterogeneous data fusion processing system; The probe module (1) includes an opaque carrier (11), a transparent element (12) embedded in a hole in the carrier (11), and a cantilever probe array arranged at the bottom of the carrier (11). The polarization-modulated multispectral optical path system (2) is arranged above the transparent element (12), and can transform the stress field evolution inside the chip under test into a visualized optical feature image through polarization modulation. The excitation sampling unit is used to apply power pulse excitation to the chip under test, and can simultaneously acquire the electrical response sequence generated by the probe module (1) and the optical feature image stream acquired by the polarization modulation multispectral optical path system (2); The heterogeneous data fusion processing system includes a visual recognition module and a physical inversion module. The visual recognition module is used to identify stress distortion regions from the optical feature images. The physical inversion module substitutes the stress distortion regions into the PINN model and combines them with the electrical response sequence to reverse-engineer the deep physical state variables inside the chip under test and draw a defect conclusion.

2. The chip testing device according to claim 1, characterized in that, The bore wall of the bearing seat (11) has a supporting step (11a), and the transparent element (12) has a flange (12a) that abuts against the supporting step (11a); and a polyimide buffer layer with a thickness of 10μm-50μm is provided between the outer peripheral surface of the transparent element (12) and the bore wall.

3. The chip testing device according to claim 1, characterized in that, The surface of the transparent element (12) is covered with a transparent conductive ITO shielding layer. The upper end of the support (11) is fixed with a metal ring (14) that presses down the edge of the transparent element (12) and is electrically connected to the ITO shielding layer. The metal ring (14) is electrically connected to the grounding terminal of the probe module (1).

4. The chip testing device according to claim 1, characterized in that, The lower side of the transparent element (12) protrudes beyond the support base (11), and the bottom side of the transparent element (12) has a slot (12b) for inserting the contact section of the cantilever probe (13).

5. The chip testing device according to claim 1, characterized in that, The polarization modulation multispectral optical path system (2) also includes a coaxial light source (21), a polarizer (22), an analyzer (23), a dichroic prism group (24), and an imaging sensor (25). The coaxial light source (21) can provide a broadband detection light covering the visible to near-infrared band; the polarizer (22) is arranged in the incident light path of the coaxial light source (21) and can modulate the detection light into linearly polarized light in the first polarization direction. The analyzer (23) and the dichroic prism group (24) are arranged in the reflected light path between the transparent element (12) and the imaging sensor (24), and the dichroic prism group (24) is located behind the analyzer (23); the polarization transmission axis of the analyzer (23) is arranged at a 90° angle with the first polarization direction; the dichroic prism group (24) decomposes the reflected light carrying phase delay information into multiple spectral channels according to the wavelength, and maps them to the corresponding imaging sensor (25) respectively.

6. A chip detection method, applied to the chip detection apparatus according to any one of claims 1-5, characterized in that the method... include: The excitation sampling unit is controlled to apply a power pulse excitation to the chip under test, while simultaneously acquiring the optical feature image stream and electrical response sequence V of the chip under test. ds (t); The YOLOv11n algorithm is used to scan the optical feature image stream in real time, and the defect geometric parameters F of the region of interest are output. S The region of interest includes the center coordinates (x, y), the coverage area (w, h), and the confidence level C, where w and h represent the width and height of the region of interest, respectively. The region of interest is transformed into a physical domain boundary operator Γ, and the confidence level C is mapped to the weight coefficient λ of the physical constraint term; With the electrical response sequence V ds (t) is used as the input to the PINN model. Within the Γ-constrained space, the loss function is used to iterate the neuron weights and calculate the deep physical state variables inside the chip. The deep physical state variables include the maximum temperature rise at the interface ΔT. int and the maximum stress gradient ∇σ inside the chip max The loss function is: ; Where L is the total loss function; the first term after the equals sign is the data-driven error, and the second term is the physical residual term based on Fourier's law of thermal conductivity; The output voltage waveform value of the chip predicted by the neural network. The actual acquired chip output voltage waveform value; k is the thermal conductivity of the material; For temperature gradient; It represents the amount of heat that enters a unit volume per unit time through thermal conduction; This is the internal heat source, that is, the Joule heat generated by the current flowing through the chip; The density of the material; The specific heat capacity at constant pressure of the material; Represents the rate of change of energy per unit volume over time; The surface features of the chip under test, the deep physical state variables, and the electrical offset are coupled to determine whether the chip has an early latent failure risk.

7. The chip detection method according to claim 1, characterized in that, The process of coupling the surface features of the chip under test, the deep state variables, and the electrical offset to determine whether the chip has an early latent failure risk includes: Extract the defect geometric parameters F S The highest temperature rise ΔT at the interface int Maximum stress gradient ∇σ inside the chip max and electrical deviation ΔV ds Normalize the four elements to construct a normalized discriminant vector: F respectively S ΔT int 、∇σ max ΔV ds The normalized parameters are w1, w2, w3, and w4, which are the weights of the corresponding parameters. Calculate the partial derivatives of the rate of change of electrical parameters with respect to the internal stress gradient, and construct the sensitivity matrix. ; The normalized discriminant vector H is input into the pre-stored chip health digital model, and the spatial correlation coefficient residual R between the measured field and the ideal field is calculated by comparison. The sensitivity analysis and residual discrimination results are coupled to output the chip's health score.

8. The chip detection method according to claim 7, characterized in that, The coupling of the sensitivity analysis and residual discrimination results outputs a health score for the chip, including: The comprehensive damage index, which characterizes the degree of chip damage, is calculated based on the following formula: ； Wherein, DI is the comprehensive damage index; The magnitude of the normalized discriminant vector; This represents the largest eigenvalue of the sensitivity matrix; The average residual output by the chip health digital model; γ, α, and β are sensitivity adjustment coefficients; The determination of whether the chip has an early latent failure risk includes: When DI is greater than the preset upper limit threshold τ1, the chip is determined to be severely faulty; When DI is greater than the preset lower threshold τ2 and not greater than the upper threshold τ1, it is determined to be a sub-healthy chip.

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