A start-up circuit for a constant Gm bias circuit

Abstract

This application discloses a startup circuit for a constant Gm bias circuit. By introducing a bias detection branch, an inverter module, and a first switching transistor external to the constant Gm bias circuit, the bias current is sampled and judged in real time. The bias detection branch maps the bias current to a detection voltage that varies with the current and inputs this detection voltage to the inverter module. After conversion by the inverter module, a control signal is output to control the on / off state of the first switching transistor. During the startup phase, the first switching transistor applies an action to the constant Gm bias circuit, causing the core bias circuit to escape the zero-current degeneracy state, and automatically exits operation after the bias current is established. This structure effectively starts the constant Gm bias circuit during power-on, avoiding situations where the circuit cannot enter the normal operating region. Furthermore, it eliminates the need for large-value resistors or large-capacity capacitors, resulting in a simple structure, high integration, and suitability for integrated circuit implementation.

Description

Technical Field

[0001] This application relates to the field of analog integrated circuit technology, and more particularly to a startup circuit for a constant Gm bias circuit. Background Technology

[0002] In analog and mixed-signal integrated circuits, constant Gm bias circuits are a crucial fundamental module. Through specific transistor size ratios and resistive feedback structures, they generate stable bias currents or voltages that are insensitive to changes in power supply voltage and process parameters, providing a stable operating point for amplifiers, analog-to-digital converters, and voltage regulators. Existing constant Gm bias circuits typically utilize a current mirror structure and source resistors to achieve an inverse relationship between transconductance and resistance, thereby eliminating dependence on device mobility, threshold voltage, and power supply voltage. However, such circuits may enter a zero-current degeneracy state during the initial power-on phase and cannot automatically enter the normal operating region, requiring the introduction of a startup circuit.

[0003] Existing solutions mostly use resistor voltage divider sampling or large capacitor coupling. The former has the problems of large resistance, increased area and power consumption, while the latter is limited by the on-chip capacitor implementation capability, making it difficult to balance integration and cost. Summary of the Invention

[0004] The purpose of this application is to overcome the above-mentioned problems and provide a startup circuit and a constant Gm bias circuit for a constant Gm bias circuit.

[0005] The technical solution of this application provides a startup circuit for a constant Gm bias circuit. The startup circuit is connected to the constant Gm bias circuit. The startup circuit includes a bias detection branch for sampling the bias current in the constant Gm bias circuit, an inverter module, and a first switching transistor.

[0006] The bias detection branch is used to map the bias current and output a detection voltage that varies with the bias current. The first end of the bias detection branch is connected to the power supply, and the second end of the bias detection branch is grounded. The input terminal of the inverter module is connected to the third terminal of the bias detection branch, the output terminal of the inverter module is connected to the gate of the first switching transistor, the source of the first switching transistor is grounded, and the drain of the first switching transistor is connected to the constant Gm bias circuit.

[0007] Furthermore, the bias detection branch includes a switching resistor; The switching resistor is located at the second end of the bias detection branch.

[0008] Furthermore, the bias detection branch includes a mirror transistor for forming a mirror bias with the reference transistor of the constant Gm bias circuit; The gate of the mirror transistor is used to connect to the gate of the reference transistor of the constant Gm bias circuit.

[0009] Furthermore, the inverter module includes a first PMOS transistor and a first NMOS transistor; The gate of the first PMOS transistor and the gate of the first NMOS transistor together form the input terminal of the inverter module; The source of the first PMOS transistor is connected to the power supply, the source of the first NMOS transistor is grounded, and the drain of the first PMOS transistor and the drain of the first NMOS transistor together form the output terminal of the inverter module.

[0010] Furthermore, the source of the first PMOS transistor is connected to the power supply through the second PMOS transistor; The gate and drain of the second PMOS transistor are connected, and the drain of the second PMOS transistor is connected to the source of the first PMOS transistor.

[0011] Furthermore, the first switching transistor is an NMOS transistor.

[0012] The technical solution of this application also provides a constant Gm bias circuit, including a bias core circuit and a startup circuit for the constant Gm bias circuit as described above. The bias core circuit includes a reference transistor, a third PMOS transistor, a fourth PMOS transistor, a second NMOS transistor, a third NMOS transistor, and a bias resistor; The reference transistor is a PMOS transistor, and the source of the reference transistor, the source of the third PMOS transistor, and the source of the fourth PMOS transistor are respectively connected to the power supply. The drain and gate of the reference transistor are connected to each other, and the drain of the reference transistor is connected to the drain of the second NMOS transistor and the drain of the first switching transistor, respectively. The gate of the third PMOS transistor and the gate of the fourth PMOS transistor are respectively connected to the gate of the reference transistor, and the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor. The gate and drain of the third NMOS transistor are connected to each other, the gate of the second NMOS transistor is connected to the gate of the third NMOS transistor, the source of the second NMOS transistor is grounded through the bias resistor, and the source of the third NMOS transistor is grounded. The drain of the fourth PMOS transistor is used to output a constant Gm bias current.

[0013] Furthermore, the bias detection branch includes a mirror transistor that forms a mirror bias with the reference transistor of the constant Gm bias circuit; The gate of the mirror transistor is connected to the gate of the reference transistor; The aspect ratio of the mirror transistor to the reference transistor is set to a first preset ratio.

[0014] Furthermore, the first preset ratio is less than 1.

[0015] Furthermore, the width-to-length ratio of the third NMOS transistor to the second NMOS transistor is set to a second preset ratio; Wherein, the second preset ratio is greater than 1.

[0016] The above technical solution has the following beneficial effects: This application discloses a startup circuit for a constant Gm bias circuit. By introducing a bias detection branch, an inverter module, and a first switching transistor external to the constant Gm bias circuit, the bias current is sampled and judged in real time. The bias detection branch maps the bias current to a detection voltage that varies with the current and inputs this detection voltage to the inverter module. After conversion by the inverter module, a control signal is output to control the on / off state of the first switching transistor. During the startup phase, the first switching transistor applies an action to the constant Gm bias circuit, causing the core bias circuit to escape the zero-current degeneracy state, and automatically exits operation after the bias current is established. This structure effectively starts the constant Gm bias circuit during power-on, avoiding situations where the circuit cannot enter the normal operating region. Furthermore, it eliminates the need for large-value resistors or large-capacity capacitors, resulting in a simple structure, high integration, and suitability for integrated circuit implementation. Attached Figure Description

[0017] The disclosure of this application will become more readily understood with reference to the accompanying drawings. It should be understood that these drawings are for illustrative purposes only and are not intended to limit the scope of protection of this application. In the drawings: Figure 1 This is a circuit diagram of the startup circuit and the constant Gm bias circuit used in one embodiment of this application.

[0018] Reference table for attached figures: Start-up circuit 1: Bias detection branch 11: switching resistor 111, mirror transistor 112, Inverter module 12: First PMOS transistor 121, first NMOS transistor 122, second PMOS transistor 123; First switching transistor 13; Power supply 2; Constant Gm bias circuit 3: Bias core circuit 31: reference transistor 311, third PMOS transistor 312, fourth PMOS transistor 313, second NMOS transistor 314, third NMOS transistor 315, bias resistor 316. Detailed Implementation

[0019] The specific embodiments of this application will be further described below with reference to the accompanying drawings.

[0020] It is readily understood that, based on the technical solution of this application, various structural and implementation methods can be interchanged by those skilled in the art without altering the essential spirit of this application. Therefore, the following detailed embodiments and accompanying drawings are merely illustrative examples of the technical solution of this application and should not be considered as the entirety of this application or as limitations or restrictions on the technical solution of the application.

[0021] The directional terms such as up, down, left, right, front, back, front, back, top, and bottom mentioned or possibly used in this specification are defined relative to the structures shown in the accompanying drawings. These are relative concepts and may therefore vary depending on their location and usage. Therefore, these or other directional terms should not be interpreted as restrictive. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0022] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meanings of the above in this application according to the specific circumstances.

[0023] like Figure 1 As shown, in one embodiment of this application, a startup circuit 1 for a constant Gm bias circuit 3 is provided. The startup circuit 1 is connected to the constant Gm bias circuit 3. The startup circuit 1 includes a bias detection branch 11 for sampling the bias current in the constant Gm bias circuit 3, an inverter module 12, and a first switching transistor 13. The bias detection branch 11 is used to map the bias current and output a detection voltage that changes with the bias current. The first end of the bias detection branch 11 is connected to the power supply 2, and the second end of the bias detection branch 11 is grounded. The input terminal of the inverter module 12 is connected to the third terminal of the bias detection branch 11, the output terminal of the inverter module 12 is connected to the gate of the first switching transistor 13, the source of the first switching transistor 13 is grounded, and the drain of the first switching transistor 13 is connected to the constant Gm bias circuit 3.

[0024] In this embodiment, a startup circuit 1 for a constant Gm bias circuit 3 is provided. The startup circuit 1 is connected to the constant Gm bias circuit 3 and includes a bias detection branch 11, an inverter module 12, and a first switching transistor 13. The bias detection branch 11 samples the bias current in the constant Gm bias circuit 3 and maps the bias current to a corresponding detection voltage. The first end of the bias detection branch 11 is connected to a power supply 2, and the second end is grounded, enabling the detection branch to form a stable current path after grounding. The third end of the bias detection branch 11 outputs a detection voltage to reflect the state of the bias current.

[0025] The input terminal of inverter module 12 is connected to the third terminal of bias detection branch 11, and is used to perform level judgment and inversion processing on the detected voltage. The output terminal of inverter module 12 is connected to the gate of first switching transistor 13, and is used to control the conduction or cutoff state of first switching transistor 13 according to the change of detected voltage. The source of first switching transistor 13 is grounded, and its drain is connected to constant Gm bias circuit 3. That is, its drain is connected to the drain of reference transistor 311 in constant Gm bias circuit 3 or the drain of PMOS transistor electrically connected to reference transistor 311; thereby applying a start-up current or start-up disturbance to constant Gm bias circuit 3 during the start-up phase, and automatically removing the influence on constant Gm bias circuit 3 after the bias current is established.

[0026] This embodiment effectively prevents the constant Gm bias circuit 3 from falling into a zero-current degeneracy state during the initial power-on phase, ensuring that the bias core circuit 31 can reliably enter the normal operating region. Simultaneously, the startup circuit 1 automatically exits operation after the bias current is established, without additional impact on the steady-state bias conditions, thereby reducing static power consumption. Compared to startup schemes relying on large-value resistors or large-capacity capacitors, this embodiment has a simple structure, low area overhead, and is easy to integrate, making it suitable for applications of the constant Gm bias circuit 3 in analog and mixed-signal integrated circuits.

[0027] like Figure 1 As shown, in one embodiment, the bias detection branch 11 includes a switching resistor 111; The conversion resistor 111 is disposed at the second end of the bias detection branch 11.

[0028] In this embodiment, the bias detection branch 11 includes a conversion resistor 111, which is disposed at the second terminal of the bias detection branch 11 and connected to the ground terminal. By placing the conversion resistor 111 near the ground terminal of the bias detection branch 11, the current flowing through the bias detection branch 11 generates a corresponding voltage drop across the conversion resistor 111, thereby forming a detection voltage in the bias detection branch 11 that reflects the magnitude of the bias current. This detection voltage is then led out from the third terminal of the bias detection branch 11 for processing by the subsequent inverter module 12.

[0029] In this embodiment, by placing the conversion resistor 111 at the second end of the bias detection branch 11, the potential at the upper end of the detection branch can be made closer to the potential of the power supply 2 while ensuring the bias detection function. This helps to reduce interference with the normal operation of the constant Gm bias circuit 3, improves the stability of the detection voltage as the bias current changes, and enables the startup circuit 1 to more reliably distinguish between the zero current state and the normal bias state in the initial stage of power-on, thereby improving the determinism and consistency of the startup process.

[0030] like Figure 1 As shown, in one embodiment, the bias detection branch 11 includes a mirror transistor 112 for forming a mirror bias with the reference transistor 311 of the constant Gm bias circuit 3; The gate of the mirror transistor 112 is used to connect to the gate of the reference transistor 311 of the constant Gm bias circuit 3.

[0031] In this embodiment, the bias detection branch 11 includes a mirror transistor 112, which is used to form a mirror bias with the reference transistor 311 in the constant Gm bias circuit 3. Specifically, the gate of the mirror transistor 112 is connected to the gate of the reference transistor 311, so that both operate under the same gate control voltage, thereby causing the current flowing through the mirror transistor 112 to change synchronously with the bias current in the reference transistor 311; through the mirror transistor 112, the bias current in the constant Gm bias circuit 3 is introduced into the bias detection branch 11 for subsequent generation of the detection voltage.

[0032] This embodiment, by setting a mirror transistor 112 in the bias detection branch 11 to form a mirror bias with the reference transistor 311, can effectively map the bias current without directly interfering with the main branch of the constant Gm bias circuit 3, thus achieving indirect detection of the bias state and forming a current mirror. This structure avoids the operating point disturbance caused by directly connecting devices in series in the main bias branch, and improves the decoupling degree between the startup circuit 1 and the constant Gm bias circuit 3. At the same time, the detection current obtained by the mirror method maintains a good correspondence with the bias current, which helps to improve the accuracy and consistency of startup judgment, thereby enhancing the reliability of the startup circuit 1 under different process and power supply conditions.

[0033] If the bias current drops abnormally due to external disturbances, the current sampling mechanism will immediately detect and reactivate the startup process, thereby providing additional protection and enhancing the robustness and reliability of the overall circuit.

[0034] like Figure 1 As shown, in another embodiment, the inverter module 12 includes a first PMOS transistor 121 and a first NMOS transistor 122; The gate of the first PMOS transistor 121 and the gate of the first NMOS transistor 122 together form the input terminal of the inverter module 12; The source of the first PMOS transistor 121 is connected to the power supply 2, the source of the first NMOS transistor 122 is grounded, and the drain of the first PMOS transistor 121 and the drain of the first NMOS transistor 122 together form the output terminal of the inverter module 12.

[0035] In this embodiment, the inverter module 12 adopts a complementary metal-oxide-semiconductor (CMOS) structure, including a first PMOS transistor 121 and a first NMOS transistor 122. The gates of the first PMOS transistor 121 and the first NMOS transistor 122 are interconnected, forming the input terminal of the inverter module 12, used to receive the detection voltage signal from the bias detection branch 11. The source of the first PMOS transistor 121 is connected to the power supply 2, the source of the first NMOS transistor 122 is grounded, and the drains of the first PMOS transistor 121 and the first NMOS transistor 122 are interconnected, forming the output terminal of the inverter module 12, used to output a control level signal opposite to the detection voltage.

[0036] This embodiment employs an inverter module 12 composed of a first PMOS transistor 121 and a first NMOS transistor 122, which enables clear level judgment and logic flipping of the detection voltage output from the bias detection branch 11. When the detection voltage is low, the first PMOS transistor 121 is turned on and the first NMOS transistor 122 is turned off, resulting in a high-level output from the inverter. When the detection voltage rises above a threshold, the first PMOS transistor 121 is turned off and the first NMOS transistor 122 is turned on, resulting in a low-level output from the inverter, thus achieving a rapid response to changes in the detection voltage. Compared to inverting methods using a single transistor or resistive load structure, the inverter structure in this embodiment has the advantages of high input impedance, low static power consumption, and clear level flipping boundaries. When the input detection voltage is stable at a high or low level, only one transistor in the inverter module 12 is turned on, and there is no DC path between the power supply 2 and ground. Therefore, theoretically, no static current is consumed in steady state. Furthermore, it is beneficial for reliably determining whether the bias current has been established during the startup process of the constant Gm bias circuit 3. The inverter module 12 can stably drive the first switching transistor 13 in the subsequent stage to be on or off, avoiding the problem of false triggering or failure of the startup circuit 1 due to unclear detection signal, and improving the startup success rate and working stability of the constant Gm bias circuit 3 in the initial stage of power-on.

[0037] like Figure 1 As shown, in one preferred embodiment, the source of the first PMOS transistor 121 is connected to the power supply 2 through the second PMOS transistor 123; The gate of the second PMOS transistor 123 is connected to the drain, and the drain of the second PMOS transistor 123 is connected to the source of the first PMOS transistor 121.

[0038] In this preferred embodiment, the source of the first PMOS transistor 121 is not directly connected to the power supply 2, but is connected to the power supply 2 through the second PMOS transistor 123. The gate and drain of the second PMOS transistor 123 are connected to each other to form a diode connection structure. The drain of the second PMOS transistor 123 is connected to the source of the first PMOS transistor 121, and its source is connected to the power supply 2, thereby forming a controlled pull-up path between the power supply 2 and the first PMOS transistor 121.

[0039] In this embodiment, by introducing a second PMOS transistor 123 connected in a diode configuration between the first PMOS transistor 121 and the power supply 2, adaptive clamping and current limiting control of the source voltage of the first PMOS transistor 121 can be achieved while ensuring the normal pull-up capability of the inverter module 12. This is because, after the gate and drain of the second PMOS transistor 123 are shorted, a voltage drop approximately equal to the threshold voltage will be formed between its source and drain in the on-state. This allows the actual source potential of the first PMOS transistor 121 to be stably clamped within the range of the power supply 2 voltage minus the threshold voltage of the second PMOS transistor 123.

[0040] Secondly, the clamping effect effectively reduces the static power consumption of the inverter module 12. When the inverter input is high and the first PMOS transistor 121 is in the off state, the gate-source voltage amplitude of the first PMOS transistor 121 is reduced accordingly because its source potential is pulled down. This is conducive to the reliable turn-off of the first PMOS transistor 121, suppressing its subthreshold conduction and the formation of leakage current path, improving the isolation in the off state, and avoiding unnecessary power consumption of the constant Gm bias circuit 3 by the startup circuit 1 after startup.

[0041] When the input of inverter module 12 is low, the first NMOS transistor 122 is off, and the first PMOS transistor 121 is driven to conduct when its gate-source voltage meets the conduction condition, thereby pulling the output of inverter module 12 to a high level. At this time, although the first PMOS transistor 121 is in the conducting state, its effective conduction capability is suppressed due to the clamping effect of the second PMOS transistor 123 on its source potential, so that inverter module 12 will not generate excessive transient current when the output is high.

[0042] Specifically, during the conduction of the first PMOS transistor 121, the second PMOS transistor 123, acting as a diode, maintains a potential difference between its source and drain that is close to the threshold voltage. This limits the highest potential of the source of the first PMOS transistor 121, keeping the gate-source voltage of the first PMOS transistor 121 within a controlled range. This structure ensures that the inverter module 12 has sufficient pull-up capability to reliably drive the first switch 13 to conduct, while effectively avoiding problems such as excessive startup current, power supply disturbance, or sudden increase in power consumption caused by an excessively strong pull-up path.

[0043] Therefore, when the inverter input is low, the startup circuit 1 can provide startup current to the constant Gm bias circuit 3 in a limited and controllable manner, ensuring that the bias core circuit 31 can smoothly leave the zero current degeneracy state and establish a normal working point; and after the inverter input flips to high level, combined with the aforementioned clamping and turn-off mechanism, the startup circuit 1 can quickly exit the working state, realizing a smooth transition between the startup stage and the steady state stage.

[0044] like Figure 1 As shown, in one embodiment, the first switch 13 is an NMOS transistor.

[0045] In this embodiment, the gate of the first switching transistor 13 is connected to the output terminal of the inverter module 12, the source of the first switching transistor 13 is grounded, and the drain is connected to the gate of the PMOS transistor in the constant Gm bias circuit 3. This provides a controlled pull-down path for the constant Gm bias circuit 3 during the startup phase. When the gate of the first switching transistor 13 receives a high-level control signal from the inverter module 12, a channel is formed, and the drain and source of the first switching transistor 13 are connected, thereby quickly pulling down the gate of the PMOS transistor in the constant Gm bias circuit 3 connected to its drain, forcibly establishing a bias current path, and preventing the constant Gm bias circuit 3 from falling into a zero-current stable state in the initial stage of power-on. When the gate receives a low level, it is reliably turned off, cutting off the intervention path to the constant Gm bias circuit 3, so that the startup circuit 1 automatically exits during the normal operation phase, avoiding additional power consumption and operating point disturbance to the bias circuit.

[0046] This embodiment uses an NMOS transistor as the first switching transistor 13, which has lower on-resistance and stronger pull-down capability in the same area, effectively improving the determinism and response speed of the startup action, and further enhancing the stability and reliability of the startup circuit 1.

[0047] like Figure 1 As shown, an embodiment of the present invention also provides a constant Gm bias circuit 3, including a bias core circuit 31 and a startup circuit 1 for the constant Gm bias circuit 3 as described in any of the preceding embodiments; The bias core circuit 31 includes a reference transistor 311, a third PMOS transistor 312, a fourth PMOS transistor 313, a second NMOS transistor 314, a third NMOS transistor 315, and a bias resistor 316. The reference transistor 311 is a PMOS transistor, and the source of the reference transistor 311, the source of the third PMOS transistor 312, and the source of the fourth PMOS transistor 313 are respectively connected to the power supply 2. The drain and gate of the reference transistor 311 are connected to each other, and the drain of the reference transistor 311 is connected to the drain of the second NMOS transistor 314 and the drain of the first switching transistor 13 respectively. The gate of the third PMOS transistor 312 and the gate of the fourth PMOS transistor 313 are respectively connected to the gate of the reference transistor 311, and the drain of the third PMOS transistor 312 is connected to the drain of the third NMOS transistor 315. The gate and drain of the third NMOS transistor 315 are connected to each other, the gate of the second NMOS transistor 314 is connected to the gate of the third NMOS transistor 315, the source of the second NMOS transistor 314 is grounded through the bias resistor 316, and the source of the third NMOS transistor 315 is grounded. The drain of the fourth PMOS transistor 313 is used to output a constant Gm bias current.

[0048] In this embodiment, a constant Gm bias circuit 3 includes a bias core circuit 31 and a startup circuit 1 for the constant Gm bias circuit 3 as described in any previous embodiment. The bias core circuit 31 includes a reference transistor 311, a third PMOS transistor 312, a fourth PMOS transistor 313, a second NMOS transistor 314, a third NMOS transistor 315, and a bias resistor 316. The reference transistor 311 is a PMOS transistor, and the source of the reference transistor 311, the source of the third PMOS transistor 312, and the source of the fourth PMOS transistor 313 are respectively connected to a power supply 2.

[0049] The drain and gate of the reference transistor 311 are interconnected, and the drain of the reference transistor 311 is connected to the drain of the second NMOS transistor 314 and the drain of the first switching transistor 13, respectively. The gates of the third PMOS transistor 312 and the fourth PMOS transistor 313 are connected to the gate of the reference transistor 311, and the drain of the third PMOS transistor 312 is connected to the drain of the third NMOS transistor 315. The gate and drain of the third NMOS transistor 315 are interconnected, and the gate of the second NMOS transistor 314 is connected to the gate of the third NMOS transistor 315. The source of the second NMOS transistor 314 is grounded through the bias resistor 316, and the source of the third NMOS transistor 315 is grounded. The drain of the fourth PMOS transistor 313 is used to output a constant Gm bias current.

[0050] This embodiment sets up a bias core circuit 31, and a combination of reference transistor 311, third PMOS transistor 312, fourth POS transistor, second NMOS transistor 314, third NMOS transistor 315, and bias resistor 316 to form a stable transconductance current generation path, so that the output constant Gm bias current has strong robustness to power supply 2 voltage, process deviation and temperature change.

[0051] During the startup phase, by combining the bias detection branch 11 and the first switching transistor 13 of the startup circuit 1, a fast and reliable power-on startup can be effectively achieved. Once the bias core circuit 31 is activated and can work normally, the startup circuit 1 automatically exits without interfering with the stable operation of the bias core circuit 31.

[0052] like Figure 1 As shown, in one embodiment, the bias detection branch 11 includes a mirror transistor 112 that forms a mirror bias with the reference transistor 311 of the constant Gm bias circuit 3; The gate of the mirror transistor 112 is connected to the gate of the reference transistor 311; The aspect ratio of the mirror transistor 112 to the reference transistor 311 is set to a first preset ratio.

[0053] In this embodiment, the bias detection branch 11 includes a mirror transistor 112 that forms a mirror bias with the reference transistor 311 of the constant Gm bias circuit 3. The gate of the mirror transistor 112 is connected to the gate of the reference transistor 311, enabling the mirror transistor 112 to accurately reflect the operating state of the reference transistor 311, thereby outputting a detection voltage signal proportional to the bias current. Through this mirror structure, the bias detection branch 11 can sample the bias current change of the constant Gm bias circuit 3 in real time, providing a reliable control signal for the startup circuit 1 and ensuring that the bias circuit can smoothly enter the normal operating region during the initial power-on stage.

[0054] The aspect ratio of the mirror transistor 112 to the reference transistor 311 is set to a first preset ratio, which can be greater than or less than 1 according to design requirements, to adjust the amplitude of the mirror current. By adjusting the aspect ratio, not only can precise mapping of the bias current be achieved, but power consumption can also be reduced and overall circuit performance optimized while ensuring circuit startup reliability. This design balances startup speed, bias stability, and energy saving, enabling the constant Gm bias circuit 3 to maintain stable operation under different process, power supply, and temperature conditions.

[0055] In one preferred embodiment, the first preset ratio is less than 1.

[0056] In this preferred embodiment, the aspect ratio (i.e., the first preset ratio) of the mirror transistor 112 to the reference transistor 311 is less than 1. By reducing the size of the mirror transistor 112, its conduction current can be reduced, thereby effectively reducing the power consumption of the startup circuit 1 while ensuring the accuracy of bias detection. Furthermore, this configuration helps to avoid excessive transient current surges during the initial power-on phase, improving the stability and reliability of the startup process, while ensuring that the constant Gm bias circuit 3 can quickly enter normal operating mode.

[0057] In another embodiment, the width-to-length ratio of the third NMOS transistor 315 to the second NMOS transistor 314 is set to a second preset ratio; Wherein, the second preset ratio is greater than 1.

[0058] In this embodiment, the width-to-length ratio of the third NMOS transistor 315 to the second NMOS transistor 314 is set to a second preset ratio, and the second preset ratio is greater than 1.

[0059] In this embodiment, by setting the width-to-length ratio of the third NMOS transistor 315 to the second NMOS transistor 314 to a second preset ratio greater than 1, the two transistors exhibit different equivalent transconductance characteristics under the same gate voltage control, thereby forming a stable voltage feedback relationship across the bias resistor 316. This width-to-length ratio, working in conjunction with the bias resistor 316, ensures that the current in the bias branch is determined by both the transistor size ratio and the resistance value. Furthermore, under specific proportional conditions, it eliminates the dependence on process parameters such as carrier mobility, oxide capacitance, and threshold voltage, making the resulting transconductance solely dependent on the bias resistor 316. Therefore, the above structure guarantees that the constant Gm bias circuit 3 obtains stable transconductance characteristics independent of the power supply 2 voltage under normal operating conditions, providing highly accurate and robust bias conditions for subsequent analog circuits.

[0060] In one preferred embodiment, the second preset ratio is 4.

[0061] In this preferred embodiment, the second preset ratio is selected as 4, such that the width-to-length ratio of the third NMOS transistor 315 is four times that of the second NMOS transistor 314. Under this ratio, the drain current capabilities of both transistors correspond to a square relationship under the same gate voltage control, thereby effectively linearizing the voltage-current relationship formed by the transistor size ratio and the bias resistor 316 in the bias branch.

[0062] Specifically, when the second preset ratio is 4, the voltage difference formed across the bias resistor 316 can directly correspond to the linear multiple relationship of the transistor overdrive voltage, so that the process-related parameters such as carrier mobility, oxide layer capacitance and threshold voltage in the transconductance expression are canceled out, so that the transconductance formed is determined only by the bias resistor 316.

[0063] In the constant Gm bias circuit 3, reference transistor 311 and third PMOS transistor 312 form a current mirror structure, and second NMOS transistor 314 and third NMOS transistor 315 form a transconductance setting branch. The sources of reference transistor 311 and third PMOS transistor 312 are both connected to the power supply voltage VDD, and their gates are connected to each other. Reference transistor 311 is connected using a gate-drain short-circuit method, i.e., a diode connection. Reference transistor 311 and third PMOS transistor 312 have the same width-to-length ratio. ; Where W is the channel width of the transistor, and L is the channel length of the transistor.

[0064] Therefore, neglecting the channel length modulation effect, the drain current flowing through the reference transistor 311 and the third PMOS transistor 312 is equal, that is: ; Among them, I P参 To reference the drain current of transistor 311, I P3 I is the drain current of the third PMOS transistor 312. d The reference current is obtained by mirroring.

[0065] The aforementioned PMOS current mirror provides a stable reference current for the entire bias circuit.

[0066] In the second NMOS transistor 314 and the third NMOS transistor 315, their gates are connected to each other, and the third NMOS transistor 315 adopts a structure with its gate and drain shorted, and its source is directly grounded; the source of the second NMOS transistor 314 is grounded through the bias resistor 316. Assume the width-to-length ratio of the second NMOS transistor 314 and the third NMOS transistor 315 satisfies the following proportional relationship: (1) Where W is the gate width of the transistor, L is the gate length, n is the second preset ratio, and n > 1.

[0067] Under saturation operating conditions, the drain current of an NMOS transistor can be expressed as: ; Among them, I d The current flowing through the drain of the NMOS transistor. For electron mobility, Here, W represents the gate oxide capacitance per unit area, W is the gate width of the transistor, and L is the gate length. Gate-source voltage, This is the threshold voltage of the NMOS transistor.

[0068] Therefore, the current in the second NMOS transistor 314 is: (2) Among them, I d2 This is the drain current flowing through the second NMOS transistor 314. For electron mobility, Here, W represents the gate oxide capacitance per unit area, W is the gate width of the transistor, L is the gate length, and (W / L) / N2 is the width-to-length ratio of the third NMOS transistor 315. This is the gate-source voltage of the second NMOS transistor 314. This is the threshold voltage of the second NMOS transistor 314.

[0069] The current in the third NMOS transistor 315 is: (3) Among them, I d3 This is the drain current flowing through the third NMOS transistor 315. For electron mobility, Here, W is the gate oxide capacitance per unit area, W is the gate width of the transistor, L is the gate length, and (W / L) / N3 is the width-to-length ratio of the fourth NMOS transistor. This refers to the gate-source voltage of the third NMOS transistor 315. This is the threshold voltage of the third NMOS transistor 315.

[0070] Since the source of the second NMOS transistor 314 is grounded through the bias resistor 316, while the source of the third NMOS transistor 315 is directly grounded, their gate-source voltages satisfy the following: ；（4） in, This refers to the gate-source voltage of the third NMOS transistor 315. I is the gate-source voltage of the second NMOS transistor 314. d3 This refers to the current flowing through the drain of the third NMOS transistor 315 and the bias resistor 316.

[0071] Combining equations (2), (3), and (4) with equation (1), we can derive the expression for the bias current Id as follows: (5) Among them, I d3 The current flowing through the drain of the third NMOS transistor 315 and the bias resistor 316 is... For electron mobility, The gate oxide capacitance per unit area is given by W, the gate width of the transistor is given by L, (W / L) / N2 is the width-to-length ratio of the third NMOS transistor 315, and R0 is the resistance value of the bias resistor 316.

[0072] If the width-to-length ratio n of the second NMOS transistor 314 and the third NMOS transistor 315 is 4, then formula (5) can be simplified to: (6) Where Id3 is the current flowing through the drain of the third NMOS transistor 315 and the bias resistor 316. For electron mobility, The gate oxide capacitance per unit area is given by W, the gate width of the transistor is given by L, (W / L) / N2 is the width-to-length ratio of the third NMOS transistor 315, and R0 is the resistance value of the bias resistor 316.

[0073] Let the transconductance of the third NMOS transistor 315 be Gm4, then its expression is: (7) Among them, G m4 The transconductance of the third NMOS transistor 315 For electron mobility, The capacitance per unit area of ​​the gate oxide layer is given by W, where W is the gate width of the transistor, L is the gate length, and (W / L) / N2 is the width-to-length ratio of the third NMOS transistor 315.

[0074] Substituting formula (6) into formula (7), and combining this with the width-to-length ratio n=4, we get: (8) Among them, G m4 R0 is the transconductance of the third NMOS transistor 315, and R0 is the resistance value of the bias resistor 316.

[0075] From formula (8), it can be seen that the transconductance Gm4 of the third NMOS transistor 315 is determined only by the bias resistor 316 and is unrelated to the transistor mobility. Oxide layer capacitance The threshold voltage Vt and the power supply voltage VDD are independent.

[0076] In one embodiment, the width-to-length ratio of the fourth PMOS transistor 313 to the reference transistor 311 is set to a third preset ratio.

[0077] In this embodiment, the fourth PMOS transistor 313 serves as the bias output branch of the constant Gm bias circuit 3. Its gate is connected to the gate of the reference transistor 311. Based on forming a current mirror relationship with the reference transistor 311, by setting the width-to-length ratio of the fourth PMOS transistor 313 to the reference transistor 311 to a third preset ratio K, the fourth PMOS transistor 313 can proportionally replicate the bias current of the reference transistor 311 according to the third preset ratio. When the bias current formed by the reference transistor 311 is I... d At that time, the bias current I output by the fourth PMOS transistor 313 b The following relationship must be satisfied: ; Among them, I b I is the bias current flowing through the fourth PMOS transistor. d K is the third preset ratio, which is the ratio of the width-to-length ratio of the fourth PMOS transistor 313 to the reference transistor 311, and is the bias current in the reference transistor 311.

[0078] Therefore, by adjusting the width-to-length ratio K between the fourth PMOS transistor 313 and the reference transistor 311, different amplitudes of bias output current can be flexibly obtained without changing the constant Gm bias core operating state, thereby realizing the configurable adjustment of the bias capability of the subsequent circuit.

[0079] Furthermore, due to the bias current I in the reference transistor 311 d Generated by a constant Gm bias core, its magnitude is only related to the bias resistor 316 and is independent of process parameters such as power supply voltage, device mobility, oxide capacitance, and threshold voltage. Therefore, the bias current I output through the fourth PMOS transistor 313 is... b It also inherits the constant Gm characteristic mentioned above.

[0080] Therefore, the constant Gm bias circuit 3 provided in this embodiment can provide stable bias current or bias voltage for analog or mixed signal functional modules such as amplifiers, filters, oscillators and analog-to-digital converters, thereby effectively ensuring the stability of key performance parameters such as system gain, bandwidth and oscillation frequency under different power supply conditions and process deviations, and improving the overall reliability and consistency of chip operation.

[0081] like Figure 1 As shown, in one preferred embodiment, the constant Gm bias circuit 3 has a zero current degenerate operating point in the initial stage of power-on. In order to ensure that the bias core circuit 31 can reliably enter the normal working state, this embodiment uses the startup circuit 1 to force the bias core circuit 31 to start, and automatically exits after the startup is completed, thereby achieving low power consumption and high stability bias generation.

[0082] Specifically, when power supply 2 is powered on, if startup circuit 1 is not introduced, the initial node voltage of each transistor in the bias core circuit 31 is zero. Reference transistor 311 and the third PMOS transistor 312 and the fourth PMOS transistor 313 that form a current mirror with it are in the off state due to insufficient gate-source voltage. At the same time, the gate-source voltage of the second NMOS transistor 314 and the third NMOS transistor 315 is also less than the threshold voltage, resulting in no current flowing through the bias resistor 316. The entire bias core circuit 31 remains in a degenerate state with zero current and cannot enter the normal bias operating point on its own.

[0083] The startup circuit 1 in this embodiment includes an inverter module 12, a first switch 13, and a bias detection branch 11 coupled to the bias core circuit 31. The inverter module 12 is composed of a first PMOS transistor 121 and a first NMOS transistor 122. Its output terminal is used to control the on and off states of the first switch 13, thereby realizing the startup control of the constant Gm bias core circuit 31.

[0084] The first PMOS transistor 121 and the first NMOS transistor 122 constitute a CMOS inverter structure. Their gates are connected to each other to form the inverter input terminal. The drains of the first PMOS transistor 121 and the drains of the first NMOS transistor 122 are connected to each other to form the inverter output terminal. The source of the first NMOS transistor 122 is grounded.

[0085] In this preferred embodiment, the source of the first PMOS transistor 121 is not directly connected to the power supply 2, but is connected to the power supply 2 through a second PMOS transistor 123 connected in a diode configuration. The gate and drain of the second PMOS transistor 123 are shorted, its source is connected to the power supply 2, and its drain is connected to the source of the first PMOS transistor 121, thus forming a controlled pull-up path between the power supply 2 and the first PMOS transistor 121. With this structure, when the second PMOS transistor 123 is turned on, a voltage drop approximately equal to the threshold voltage is formed between its source and drain. This clamps the source potential of the first PMOS transistor 121 within the range of the power supply 2 voltage minus the threshold voltage of the second PMOS transistor 123, thereby limiting and controlling the pull-up capability of the inverter.

[0086] During the initial power-up phase of the chip, since the constant Gm bias core circuit 31 has not yet established current, the detection signal output by the bias detection branch 11 is in a low-level state. This low-level signal is applied as the inverter input signal to the gates of the first PMOS transistor 121 and the first NMOS transistor 122. At this time, the gate-source voltage of the first PMOS transistor 121 is a large negative value, and the first PMOS transistor 121 is turned on; the gate-source voltage of the first NMOS transistor 122 is lower than its threshold voltage, and it is in a turned-off state. The inverter output is pulled high to a high level by the pull-up action of the first PMOS transistor 121. Since the first switching transistor 13 is an NMOS transistor, its gate is controlled by the inverter output. Therefore, when the inverter output is high, the first switching transistor 13 is reliably turned on, thereby forming a forced intervention path for the constant Gm bias core circuit 31 during the startup phase, forcibly pulling down the drain potential of the reference transistor 311, and breaking the zero-current degeneracy state of the bias core circuit 31.

[0087] After the first switch 13 is turned on, the reference transistor 311 obtains an effective gate-source voltage. The second NMOS transistor 314 and the third NMOS transistor 315 in the bias core circuit 31 gradually enter the conducting state, and a stable voltage drop begins to form across the bias resistor 316. The constant Gm bias circuit 3 converges towards its desired operating point. As the bias current gradually builds up, the mirror transistor 112 in the bias detection branch 11 senses the change in the current of the reference transistor 311, and its output detection signal gradually increases and is fed back to the inverter input.

[0088] After the constant Gm bias core circuit 31 enters a stable operating state, the bias detection branch 11 outputs a high-level signal. This high-level signal is applied as the inverter input signal to the gates of the first PMOS transistor 121 and the first NMOS transistor 122. At this time, the gate-source voltage of the first NMOS transistor 122 is greater than the threshold voltage and it turns on. Because the source of the first PMOS transistor 121 is clamped by the second PMOS transistor 123, the amplitude of its gate-source voltage is significantly reduced, and the first PMOS transistor 121 is reliably turned off. The inverter output is pulled low by the pull-down action of the first NMOS transistor 122. When the inverter output is low, the gate voltage of the first switch transistor 13 is insufficient to maintain conduction, and the first switch transistor 13 enters the off state, achieving electrical isolation between the start-up branch and the constant Gm bias core circuit 31.

[0089] Because the second PMOS transistor 123 is connected in a diode configuration, it adaptively clamps the source potential of the first PMOS transistor 121 during inverter operation. This effectively compresses the gate-source voltage of the first PMOS transistor 121 when the inverter input is high and it should be turned off, thereby suppressing the subthreshold leakage current of the first PMOS transistor 121 and preventing the inverter output from being mistakenly pulled up. This structure ensures that the inverter can output a clean and clear low-level signal in the steady-state phase, enabling the first switching transistor 13 to be reliably turned off. This fundamentally prevents the startup circuit 1 from continuing to consume static power or interfere with bias accuracy after the constant Gm bias circuit 3 is working normally.

[0090] As needed, the above technical solutions can be combined to achieve the best technical effect.

[0091] The above are merely the principles and preferred embodiments of this application. It should be noted that, for those skilled in the art, implementation methods obtained by appropriately combining the technical solutions disclosed in different embodiments are also included within the technical scope of this invention. Based on the principles of this application, several other modifications can also be made, which should also be considered within the protection scope of this application.

Claims

1. An enabling circuit for a constant Gm biasing circuit, characterized by, The startup circuit (1) is connected to the constant Gm bias circuit (3). The startup circuit (1) includes a bias detection branch (11) for sampling the bias current in the constant Gm bias circuit (3), an inverter module (12), and a first switching transistor (13). The bias detection branch (11) is used to map the bias current and output a detection voltage that changes with the bias current. The first end of the bias detection branch (11) is connected to the power supply (2), and the second end of the bias detection branch (11) is grounded. The input terminal of the inverter module (12) is connected to the third terminal of the bias detection branch (11), the output terminal of the inverter module (12) is connected to the gate of the first switch (13), the source of the first switch (13) is grounded, and the drain of the first switch (13) is connected to the constant Gm bias circuit.

2. The start-up circuit for a constant Gm biasing circuit of claim 1, wherein, The bias detection branch (11) includes a switching resistor (111); The switching resistor (111) is located at the second end of the bias detection branch (11).

3. The start-up circuit for a constant Gm bias circuit according to claim 1 or 2, wherein The bias detection branch (11) includes a mirror transistor (112) for forming a mirror bias with the reference transistor (311) of the constant Gm bias circuit (3). The gate of the mirror transistor (112) is used to connect to the gate of the reference transistor (311) of the constant Gm bias circuit.

4. The start-up circuit for a constant Gm biasing circuit of claim 1, wherein, The inverter module (12) includes a first PMOS transistor (121) and a first NMOS transistor (122). The gate of the first PMOS transistor (121) and the gate of the first NMOS transistor (122) together form the input terminal of the inverter module (12); The source of the first PMOS transistor (121) is connected to the power supply (2), the source of the first NMOS transistor (122) is grounded, and the drain of the first PMOS transistor (121) and the drain of the first NMOS transistor (122) together form the output terminal of the inverter module (12).

5. A startup circuit for a constant Gm bias circuit according to claim 4, characterized in that, The source of the first PMOS transistor (121) is connected to the power supply (2) through the second PMOS transistor (123); The gate of the second PMOS transistor (123) is connected to the drain, and the drain of the second PMOS transistor (123) is connected to the source of the first PMOS transistor (121).

6. The startup circuit for a constant Gm bias circuit according to claim 1, characterized in that, The first switch (13) is an NMOS transistor.

7. A constant Gm biasing circuit, comprising: Includes a bias core circuit (31) and a startup circuit (1) for a constant Gm bias circuit as described in any one of claims 1-6; The bias core circuit (31) includes a reference transistor (311), a third PMOS transistor (312), a fourth PMOS transistor (313), a second NMOS transistor (314), a third NMOS transistor (315), and a bias resistor (316). The reference transistor (311) is a PMOS transistor, and the source of the reference transistor (311), the source of the third PMOS transistor (312) and the source of the fourth PMOS transistor (313) are respectively connected to the power supply (2). The drain and gate of the reference transistor (311) are connected to each other, and the drain of the reference transistor (311) is connected to the drain of the second NMOS transistor (314) and the drain of the first switch transistor (13). The gate of the third PMOS (312) and the gate of the fourth PMOS (313) are respectively connected to the gate of the reference transistor (311), and the drain of the third PMOS (312) is connected to the drain of the third NMOS (315). The gate and drain of the third NMOS transistor (315) are connected to each other, the gate of the second NMOS transistor (314) is connected to the gate of the third NMOS transistor (315), the source of the second NMOS transistor (314) is grounded through the bias resistor (316), and the source of the third NMOS transistor (315) is grounded. The drain of the fourth PMOS transistor (313) is used to output a constant Gm bias current.

8. The constant Gm biasing circuit of claim 7, wherein, The bias detection branch (11) includes a mirror transistor (112) that forms a mirror bias with the reference transistor (311) of the constant Gm bias circuit. The gate of the mirror transistor (112) is connected to the gate of the reference transistor (311); The width-to-length ratio of the mirror transistor (112) to the reference transistor (311) is set to a first preset ratio.

9. The constant Gm biasing circuit of claim 8, wherein, The first preset ratio is less than 1.

10. A constant Gm bias circuit according to claim 7, characterized in that, The width-to-length ratio of the third NMOS transistor (315) to the second NMOS transistor (314) is set to a second preset ratio; Wherein, the second preset ratio is greater than 1.

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