A storage device and an electronic device

Abstract

This disclosure provides a storage device and an electronic device. The storage device includes a carrier for carrying and conducting electronic components, a conversion chip disposed on the carrier, and a storage module. The storage device can be detachably connected to an electronic device. The carrier is provided with a first connection interface, through which the storage device can establish a first communication connection with the electronic device. A second communication connection is established between the storage module and the conversion chip. The conversion chip is used to convert first protocol data obtained from the first communication connection into second protocol data and transmit the second protocol data to the storage module through the second communication connection. The storage module can respond to the second protocol data by performing corresponding target read operations and / or target write operations. The first communication connection is a high-speed serial computer expansion bus standard PCIe connection, and the second communication connection is a general-purpose flash memory storage (UFS) connection.

Description

Technical Field

[0001] This disclosure relates to the field of storage technology, and more specifically, to a storage device and an electronic device. Background Technology

[0002] When the interfaces used for data communication between different devices are incompatible with each other, data read and write operations may fail or communication efficiency may be reduced. For example, when existing PC devices use Universal Flash Storage (UFS) devices, the motherboard of the PC device needs to support the UFS protocol. On platforms that only provide Peripheral Component Interconnect Express (PCIe) interfaces, it is impossible to use the UFS protocol or only a few channels can be used, resulting in reduced transmission speed and poor versatility. Summary of the Invention

[0003] In view of this, the present disclosure provides a storage device and an electronic device.

[0004] A first aspect of this disclosure provides a storage device including a carrier for carrying and conducting electronic components, a conversion chip disposed on the carrier, and a storage module, wherein the storage device is detachably connected to an electronic device; wherein...

[0005] The carrier is provided with a first connection interface, and the storage device can establish a first communication connection with the electronic device through the first connection interface;

[0006] A second communication connection is established between the storage module and the conversion chip;

[0007] The conversion chip is used to convert the first protocol data obtained from the first communication connection into the second protocol data, and to send the second protocol data to the storage module through the second communication connection;

[0008] The storage module can respond to the second protocol data to perform the corresponding target read operation and / or target write operation;

[0009] The first communication connection is a high-speed serial computer expansion bus standard PCIe connection, and the second communication connection is a general-purpose flash memory storage UFS connection.

[0010] According to embodiments of this disclosure, the conversion chip includes a high-speed serial computer expansion bus standard PCIe interface layer, a universal flash memory storage UFS interface layer, and a protocol conversion layer disposed between the two.

[0011] The PCIe interface layer is used to implement the first communication connection, and the UFS interface layer is used to implement the second communication connection.

[0012] The protocol conversion layer is used to parse the first protocol data based on the maintained target mapping relationship, and encapsulate the parsed target extraction data into a general flash memory storage protocol information unit to obtain the second protocol data.

[0013] And / or,

[0014] The conversion chip is also used to convert the second protocol data obtained through the second communication connection into first protocol data, and to send the first protocol data back to the electronic device through the first communication connection.

[0015] According to embodiments of this disclosure, the conversion chip further includes a first controller and a system control module;

[0016] The first controller is capable of controlling the system control module to perform clock and power timing management, configuring the operating parameters of the storage module, and providing at least one of the following error recovery mechanisms:

[0017] And / or,

[0018] The conversion chip also includes a second controller for transferring data streams between electronic devices and storage modules.

[0019] A second aspect of this disclosure provides an electronic device, including a device body and a storage device detachably disposed on the device body. The storage device includes a carrier for carrying and conducting electronic components, a conversion chip disposed on the carrier, and a storage module; wherein...

[0020] The carrier is provided with a first connection interface, and the storage device establishes a first communication connection with the electronic device through the first connection interface;

[0021] A second communication connection is established between the storage module and the conversion chip;

[0022] The conversion chip is used to convert the first protocol data obtained through the first communication connection into the second protocol data, and to send the second protocol data to the storage module through the second communication connection;

[0023] The storage module can respond to the second protocol data to perform the corresponding target read operation and / or target write operation;

[0024] The first communication connection is a high-speed serial computer expansion bus standard PCIe connection, and the second communication connection is a general-purpose flash memory storage UFS connection.

[0025] According to embodiments of this disclosure, the conversion chip includes a high-speed serial computer expansion bus standard PCIe interface layer, a universal flash memory storage UFS interface layer, and a protocol conversion layer disposed between the two.

[0026] The PCIe interface layer is used to implement the first communication connection, and the UFS interface layer is used to implement the second communication connection.

[0027] The protocol conversion layer is used to parse the first protocol data based on the maintained target mapping relationship, and encapsulate the parsed target extraction data into a general flash memory storage protocol information unit to obtain the second protocol data.

[0028] And / or,

[0029] The conversion chip is also used to convert the second protocol data obtained through the second communication connection into first protocol data, and to send the first protocol data back to the electronic device through the first communication connection.

[0030] According to embodiments of this disclosure, when the electronic device receives first instruction data to read first data content from the storage module, the conversion chip performs the following operations:

[0031] Parse the first instruction data and convert the obtained target read command into a general flash memory standard read command;

[0032] The generic flash storage protocol information unit obtained by encapsulating the generic flash storage standard read command is sent to the storage module to trigger the storage module to execute the corresponding target read operation;

[0033] The target data frame returned by the storage module is converted into a protocol, and the resulting protocol conversion result is transmitted back to the electronic device through the first communication connection. The target data frame can represent the first data content.

[0034] According to embodiments of this disclosure, when the electronic device receives second instruction data to write second data content to the storage module, the conversion chip performs the following operations:

[0035] Convert the target write command obtained by parsing the second instruction data into a general flash memory standard write command;

[0036] The second data content obtained through the first communication connection is converted into a protocol and encapsulated with the general flash memory storage standard write command into a general flash memory storage protocol information unit, and sent to the storage module through the second communication connection to trigger the storage module to execute the corresponding target write operation;

[0037] After receiving status identification data from the storage module indicating that the General Flash Memory Protocol (GPLP) information unit has been successfully written, the status identification data is sent back to the electronic device.

[0038] According to embodiments of this disclosure, the electronic device is configured to prioritize the initialization process of the storage module during startup, and enter an enumerable state after the storage module completes initialization, whereby the electronic device performs high-speed serial computer expansion bus standard PCIe enumeration of the storage device through a first connection interface.

[0039] According to embodiments of this disclosure, the storage device further includes a power management integrated circuit;

[0040] The electronic device is configured to perform initialization of the conversion chip and power management integrated circuit after the storage device is connected to the electronic device, and after the initialization is completed, the power management integrated circuit controls the storage module to perform initialization.

[0041] The initialization status of the storage module is detected by the embedded controller of the electronic device;

[0042] If the storage module is not fully initialized, the embedded controller sends a clock signal to the conversion chip to extend the enumeration window period of the high-speed serial computer expansion bus standard PCIe.

[0043] After the storage module completes initialization, the boot system of the electronic device is notified to perform a high-speed serial computer expansion bus standard PCIe enumeration on the storage device.

[0044] According to embodiments of this disclosure, the electronic device is configured to power on the high-speed serial computer expansion bus standard PCIe link between the storage device and the electronic device after the conversion chip and power management integrated circuit have completed initialization, and the electronic device's boot system identifies the identification information of the storage device to trigger a delay strategy for high-speed serial computer expansion bus standard PCIe enumeration based on the identification information.

[0045] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0046] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0047] Figure 1 The schematic diagram illustrates one of the schematic principles of a storage device according to an embodiment of the present disclosure;

[0048] Figure 2 The illustration schematically depicts a flow diagram of interaction between a storage device and an electronic device according to an embodiment of the present disclosure;

[0049] Figure 3 A schematic diagram of a storage device according to an embodiment of the present disclosure is shown in the second example.

[0050] Figure 4 A schematic diagram of a storage device according to an embodiment of the present disclosure is shown in Figure 3.

[0051] Figure 5 This illustration schematically shows one of the interaction flow diagrams between an electronic device, a conversion chip, and a storage module according to an embodiment of the present disclosure;

[0052] Figure 6 This illustration shows a second schematic diagram of the interaction process between an electronic device, a conversion chip, and a storage module according to an embodiment of the present disclosure;

[0053] Figure 7 A schematic diagram of a storage device according to an embodiment of the present disclosure is shown in Figure 4.

[0054] Figure 8 The illustration schematically shows a flow chart of a storage device initialization power-on process according to an embodiment of the present disclosure;

[0055] Figure 9 A schematic diagram of a storage device according to an embodiment of the present disclosure is shown in Figure 5.

[0056] Figure 10 The schematic diagram illustrates a principle schematic of a conversion chip according to an embodiment of the present disclosure;

[0057] Figure 11 A block diagram of an electronic device according to an embodiment of the present disclosure is shown schematically. Detailed Implementation

[0058] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0059] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0060] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0061] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0062] The relevant terms in the embodiments of this disclosure are explained below.

[0063] The Peripheral Component Interconnect Express (PCIe) standard is a high-speed serial bus standard used to connect computer motherboards to high-speed peripherals. It is widely used in storage, graphics cards, and other devices.

[0064] Universal Flash Storage (UFS) is a high-performance flash storage standard for mobile devices and embedded systems, featuring high-speed read / write speeds and low power consumption.

[0065] A Transaction Layer Packet (TLP) is the basic data unit of the transaction layer in the PCIe protocol, used to carry commands, data, and status information.

[0066] The Universal Flash Storage Protocol Information Unit (UPIU) is the basic transmission unit in the UFS protocol used for command, data, and status interaction.

[0067] The UniPro Controller is the core control unit of the UFS protocol link layer, responsible for reliable data transmission and link management between UFS devices.

[0068] The Multi-lane High-speed Physical Layer Controller (M-PHY Controller) is the drive control unit of the UFS protocol physical layer, responsible for the electrical signal transmission and rate configuration of the UFS link.

[0069] Non-Volatile Memory Express (NVMe) is a high-efficiency storage protocol designed specifically for PCIe SSDs, which can improve the read and write performance and response speed of storage devices.

[0070] A phase-locked loop (PLL) is a circuit module used for clock signal multiplication, phase calibration, and frequency stabilization, providing a precise clock reference for chips.

[0071] A data buffer (DBUF) is a high-speed temporary storage unit inside a chip, used to cache data streams between different protocols and solve the problem of data loss caused by differences in transmission rates.

[0072] An Advanced RISC Machines Central Processing Unit (ARM CPU) is a low-power processor that uses a reduced instruction set architecture and can be used as the main control unit of a conversion chip in this disclosure.

[0073] Direct Memory Access (DMA) is a hardware data transfer technology that enables high-speed data transfer without CPU intervention. In this solution, it is executed by the DMAC (DMA controller).

[0074] A logical block address (LBA) is a linear address used to locate data blocks in a storage device and is the core address identifier for interaction between the operating system and the storage device.

[0075] An embedded controller (EC) is a dedicated microcontroller in an electronic device that is responsible for low-level hardware management, status monitoring, and timing control.

[0076] A power management integrated circuit (PMIC) is a special-purpose integrated circuit used to manage the power domain, voltage regulation, and power-up sequence of a device, ensuring a stable power supply for the hardware.

[0077] The Basic Input Output System (BIOS) is the low-level firmware that runs when an electronic device starts up. It is responsible for hardware initialization, device enumeration, and booting the operating system.

[0078] The first aspect of this disclosure provides a storage device, including a carrier for carrying and conducting electronic components, a conversion chip disposed on the carrier, and a storage module. The storage device is detachably connected to an electronic device. The carrier is provided with a first connection interface, through which the storage device can establish a first communication connection with the electronic device. A second communication connection is established between the storage module and the conversion chip. The conversion chip is used to convert first protocol data obtained from the first communication connection into second protocol data and to transmit the second protocol data to the storage module through the second communication connection. The storage module is capable of performing corresponding target read and / or target write operations in response to the second protocol data. The first communication connection is a high-speed serial computer expansion bus standard PCIe connection, and the second communication connection is a general-purpose flash memory (UFS) connection.

[0079] In the embodiments of this disclosure, the storage device has a specific hardware structure that enables data storage function and can be detachably connected to a data storage device of an electronic device. It can realize data conversion of different protocols through an internal conversion chip to adapt to the read / write operation of the storage module.

[0080] In the embodiments of this disclosure, the carrier is a physical medium for carrying and conducting electronic components, such as a PCB board, providing mounting positions and electrical connection paths for components such as conversion chips and storage modules, and enabling collaborative work between the components; in this embodiment, the carrier is an M.2 board that carries conversion chips and storage modules.

[0081] The conversion chip has a protocol conversion function, which can convert the first protocol data obtained through the first communication connection into second protocol data and transmit it to the storage module; it can also perform reverse conversion to realize data interaction between different communication protocols. The storage module is responsible for performing data write and read operations. In response to the second protocol data transmitted by the conversion chip, it completes the target read operation and / or target write operation to realize data storage and retrieval.

[0082] In the embodiments of this disclosure, the first connection interface is a physical interface disposed on the carrier, through which the storage device and the electronic device establish a first communication connection; the first communication connection is a communication link established between the storage device and the electronic device based on a specific protocol.

[0083] For example, the first connection interface can be a PCIe interface set on the M.2 board, which builds a data transmission link based on the high-speed serial computer expansion bus standard protocol to realize high-speed data transmission and ensure the transmission of data and instructions between electronic devices and storage devices.

[0084] In the embodiments of this disclosure, the second communication connection is a communication link established between the storage module and the conversion chip based on a specific protocol; the second communication connection is established between the storage module and the conversion chip through the second connection interface provided on the carrier.

[0085] For example, the second connection interface is a Universal Flash Storage (UFS) interface, used to transfer converted protocol data between the conversion chip and the storage module.

[0086] In the embodiments of this disclosure, the first protocol data is sent between the electronic device and the storage device via a PCIe connection, and includes information such as instructions, addresses, and data; the first protocol data is converted into data recognizable by the UFS protocol by a conversion chip.

[0087] In the embodiments of this disclosure, the second protocol data is UFS protocol format data obtained by the conversion chip after converting the first protocol data, which can be received and parsed by the storage module to perform corresponding read or write operations.

[0088] In the embodiments of this disclosure, a target read operation can be an operation in which the storage module reads specific data from the storage medium according to a read command contained in the received second protocol data. A target write operation can also be an operation in which the storage module writes specific data to the storage module according to a write command contained in the received second protocol data.

[0089] By employing the aforementioned storage devices, the integration of PCIe interface and UFS storage module is achieved. A bridging chip enables data conversion between the PCIe and UFS interfaces, allowing for more efficient communication between the host and peripheral storage devices. Through the introduction of the bridging chip, the PCIe interface layer interfaces with the host PCIe interface, the protocol conversion layer converts PCIe protocol data to UFS protocol data based on the target mapping relationship, and the UFS interface layer communicates with the UFS storage module. During data return, the conversion is reversed, achieving efficient data conversion between PCIe and UFS. This significantly improves the communication speed between the host and peripheral storage devices and enhances scalability, allowing platforms with only PCIe interfaces to successfully connect to UFS storage devices, effectively solving the problem of data read / write and communication efficiency limitations caused by incompatible interface communication protocols between different devices.

[0090] The following will be through Figures 1-10 The storage device according to embodiments of the present disclosure will be described in detail.

[0091] Figure 1 One of the schematic diagrams of a storage device according to an embodiment of the present disclosure is shown.

[0092] like Figure 1As shown, the storage device 200 includes a conversion chip 210 and a storage module 220. The conversion chip 210 transmits data with the electronic device 100 through a first communication interface, and the conversion chip 210 and the storage module 220 transmit data through a second communication interface. The first communication interface is a high-speed serial computer expansion bus standard interface, and the second communication interface is a general flash memory interface.

[0093] Figure 2 The illustration schematically depicts a flow diagram of interaction between a storage device and an electronic device according to an embodiment of the present disclosure.

[0094] like Figure 2 As shown, either the storage device or the electronic device can initiate the establishment of a communication connection. Simultaneously, the conversion chip and the storage module establish a second communication connection after the storage device is powered on. Subsequently, when the electronic device 100 sends first protocol data conforming to the PCIe communication protocol to the conversion chip 210 via the first communication interface, the conversion chip 210 converts the first protocol data into second protocol data adapted to the general flash memory interface. The conversion chip 210 then transmits the second protocol data to the storage module 220. When the second protocol data represents a write operation, the target data carried in the second protocol data is written to the target address in the storage module 220. When the second protocol data represents a read operation, the target data is selected from the target address in the storage module 220 based on the instruction information carried in the second protocol data, and the target data is transmitted back to the electronic device 100 via the conversion chip 210.

[0095] Figure 3 The schematic diagram illustrates a second schematic diagram of a storage device according to an embodiment of the present disclosure.

[0096] According to embodiments of this disclosure, such as Figure 3 As shown, the conversion chip includes a high-speed serial computer expansion bus standard PCIe interface layer 2110, a universal flash memory storage UFS interface layer 2130, and a protocol conversion layer 2120 disposed between the two.

[0097] The PCIe interface layer 2110 is used to implement the first communication connection, and the UFS interface layer 2130 is used to implement the second communication connection.

[0098] The protocol conversion layer 2120 is used to parse the first protocol data based on the maintained target mapping relationship, and encapsulate the parsed target extraction data into a general flash memory storage protocol information unit to obtain the second protocol data.

[0099] The conversion chip 210 is also used to convert the second protocol data obtained through the second communication connection into first protocol data, and to send the first protocol data back to the electronic device 100 through the first communication connection.

[0100] Specifically, such as Figure 3 As shown, the PCIe interface layer 2110 is responsible for interacting with the PCIe interface of the electronic device 110, the UFS interface layer 2130 is responsible for interacting with the UFS interface of the storage module 220, and the protocol conversion layer 2120 parses and encapsulates data based on a preset target mapping relationship to realize the conversion between the two protocols. In addition, the conversion chip 210 also has a reverse conversion function, converting the UFS protocol data returned by the storage module 220 into PCIe protocol data and sending it back to the electronic device 210.

[0101] In the embodiments of this disclosure, the PCIe interface layer is a functional layer in the conversion chip responsible for interacting with electronic devices, realizing physical layer interaction and data packet processing of the PCIe protocol, and ensuring smooth communication between the conversion chip and electronic devices based on the PCIe protocol.

[0102] In the embodiments of this disclosure, the UFS interface layer is a functional layer in the conversion chip responsible for interacting with the UFS interface of the storage module, realizing the interaction between the physical layer and the protocol layer of the UFS protocol, and ensuring normal communication between the conversion chip and the storage module based on the UFS protocol.

[0103] In the embodiments of this disclosure, the protocol conversion layer is the core functional layer of the conversion chip. By maintaining the target mapping relationship, it parses the first protocol data of the PCIe protocol, extracts key information and encapsulates it into a Universal Flash Memory Protocol Information Unit (UPIU) of the UFS protocol, thereby realizing the data conversion between the PCIe protocol and the UFS protocol.

[0104] The target mapping relationship is a mapping table stored in the protocol conversion layer, used to establish the correspondence between commands, parameters, and other information between the PCIe and UFS protocols, enabling conversion between the two protocols. Target extracted data is key information used to construct the UPIU, parsed from the first protocol data by the protocol conversion layer, including address, data, and control information. The UPIU is the core data packet format of the UFS protocol, carrying key information such as commands and data from the UFS protocol, used for transmission between UFS devices.

[0105] In some scenarios, the PCIe interface layer 2110 of the conversion chip 210 includes a PCIe physical layer, a PCIe link layer, and a PCIe transaction layer. The PCIe physical layer is used to implement PCIe electrical characteristics and serial / deserialization functions; the PCIe link layer handles packet acknowledgment and flow control management; and the PCIe transaction layer is used to generate and parse transaction layer packets (TLPs). The protocol conversion layer 2120 maintains a mapping table between PCIe and UFS commands. When a read command in TLP form is received from the electronic device 100, the TLP parsing module in the protocol conversion layer 2120 converts it into an internal bus format, extracts address, data, and other information, and the UPIU packet encapsulation module in the protocol conversion layer 2120 encapsulates this information into UFS protocol information units (UPIUs). Finally, the UPIU is output to the storage module 220 through the UFS interface layer.

[0106] In some scenarios, the UFS interface layer adapts to the UFS 3.0 protocol, interacting with the UFS storage module through the UniPro controller, M-PHY controller, and UFS protocol engine. When the UFS storage module returns data, the conversion chip converts it into PCIe format data and sends it back to the laptop.

[0107] By adopting the aforementioned storage device, the roles of each functional layer in the conversion chip are clarified, making the conversion between PCIe and UFS protocols more efficient. The collaborative work of the PCIe interface layer, UFS interface layer, and protocol conversion layer ensures accurate conversion and transmission of data between different protocols. At the same time, the reverse conversion function guarantees the integrity of data interaction, enabling bidirectional and smooth data communication between the storage device and electronic devices.

[0108] Figure 4 The schematic diagram shows a third schematic diagram of a storage device according to an embodiment of the present disclosure.

[0109] According to embodiments of this disclosure, such as Figure 4 As shown, the conversion chip 210 also includes a first controller 2140 and a system control module 2160; the first controller 2140 is capable of controlling the system control module 2160 to perform clock and power timing management control, configure the operating parameters of the storage module 220, and provide at least one of the error recovery mechanisms; and / or, the conversion chip 210 also includes a second controller 2150 for transferring data streams between the electronic device 100 and the storage module 220.

[0110] In the embodiments of this disclosure, the first controller is used for power-on initialization control of the conversion chip. When the storage device is connected to the electronic device through the first connection interface and receives power, the first controller first starts and executes the power-on initialization process of the entire conversion chip module. By issuing configuration instructions to the system control module, it completes the parameter configuration of the PCIe interface layer and the PCIe physical layer. At the same time, it completes the clock frequency calibration and clock signal distribution of the multiple clock domains inside the conversion chip, as well as the voltage adjustment and power timing control of each module in the conversion chip. This ensures that all modules such as the PCIe interface layer, protocol conversion layer, and UFS interface layer complete the initialization according to the preset timing and enter the ready state. After the initialization is completed, it sends back a "chip initialization completed" status signal to the electronic device.

[0111] In the embodiments of this disclosure, the first controller is also used for full-process command management of protocol data transmission. When the electronic device sends the first protocol data of the PCIe / NVMe protocol through the first communication connection, the first controller first triggers the protocol conversion layer to parse the first protocol data, extract the core information such as instruction type and operation parameters, and complete the accurate identification of PCIe / NVMe commands. Then, it calls the PCIe / NVMe-UFS command mapping table maintained by the protocol conversion layer, matches the corresponding UFS standard command according to the identified PCIe / NVMe command type, and completes the format conversion and parameter adaptation of the command. Finally, the converted UFS standard command is sent to the UFS interface layer, which encapsulates it into a UPIU data packet and sends it to the storage module through the second communication connection. At the same time, the sent UFS command is registered and recorded to realize the full-process control of the command from reception, parsing, mapping to sending. After the command is sent, the controller sends back the intermediate state "command has been sent to storage module" to the electronic device.

[0112] In the embodiments of this disclosure, the first controller is also used for handling abnormalities and interruptions in the protocol data transmission process. During the operation of the conversion chip and the entire data transmission process, the first controller monitors the operating status of the PCIe communication link, the UFS communication link, and each functional module in real time. When abnormal situations such as link disconnection, data transmission verification error, or command execution failure are detected, or when interruption requests are received from each module, the corresponding abnormality handling mechanism is immediately activated.

[0113] For example, for minor data transmission errors, a data retransmission mechanism is triggered and the command is reissued; for command execution timeouts, a timeout query command is first sent to the storage module, and if no response is received, the command execution process is re-initiated; for serious link or module failures, information such as the error type, error occurrence time, and faulty module is immediately recorded in the error log, and an error status message containing the specific error code is sent back to the electronic device. At the same time, the corresponding fault recovery strategy is triggered to ensure the normal operation of the conversion chip as much as possible. If the fault cannot be recovered, a status signal of "device failure, unable to perform operation" is sent back to the electronic device.

[0114] In the embodiments of this disclosure, the first controller is also used for firmware logic execution and policy control. The first controller has a built-in dedicated firmware program containing security, power consumption, and performance-related control policies, which are automatically executed and dynamically adjusted during the operation of the conversion chip. Regarding security policies, it performs permission verification on received PCIe / NVMe commands and issued UFS commands, and encrypts / decrypts transmitted data to prevent unauthorized operations and data leakage. Regarding power consumption policies, it dynamically adjusts the operating frequency and power supply mode of each module based on power control instructions issued by the electronic device or the actual workload of the storage device. Under low load, it controls some non-core modules to enter a low-power sleep state to reduce overall power consumption. Regarding performance policies, it dynamically adjusts the communication rate and link width of the PCIe and UFS interfaces according to data transmission rate requirements, optimizes protocol conversion efficiency, and ensures high-speed and stable data transmission. Furthermore, the first controller transmits the current power consumption mode, performance level, and security status back to the electronic device in real time for monitoring and control.

[0115] In the embodiments of this disclosure, the first controller is able to control the circuit components of each part of the system control module, thereby realizing the control functions described in the above embodiments.

[0116] The system control module includes, but is not limited to, clock control circuit, power / reset control circuit, global configuration register group, interrupt aggregation and error monitoring circuit, multi-clock domain synchronization logic circuit, and chip status monitoring circuit.

[0117] In the embodiments of this disclosure, the clock control circuit integrates a PLL (phase-locked loop), a clock divider, a power switch, a reset signal generator, and a UFS power consumption mode control circuit, and is controlled by instructions from a first controller. For example, during the power-on initialization phase, the first controller issues a clock configuration instruction, the PLL completes the frequency multiplication and phase calibration of the clock signal, and generates different frequency reference clocks required by the PCIe interface layer, UFS interface layer, and protocol conversion layer. Then, the clock divider completes the clock division according to the requirements of each module, providing a stable clock signal for the conversion chip. During the operation of the conversion chip, the first controller issues instructions according to the power consumption / performance strategy. The clock control circuit realizes the on / off control of non-core clock modules through the power switch, and at the same time adjusts the clock rate of the UFS interface layer through the UFS power consumption mode control circuit to match the UFS storage module's Active, Idle, Sleep, and other power consumption modes. When the conversion chip detects an abnormality, the first controller issues a reset instruction, and the reset signal generator immediately generates a global or local reset clock signal to realize the clock reset and recovery of the faulty module.

[0118] For example, Active power mode represents the state of the UFS device when executing commands or performing background tasks; Idle power mode represents the state of the UFS device when it is idle, that is, when there are no commands from the UFS host and no background tasks to process; in Sleep power mode, the VCC power supply of the storage module is cut off.

[0119] In the embodiments of this disclosure, the power / reset control circuit provides power supply and reset control for each module of the conversion chip and the external UFS storage module, and is controlled by the power timing instructions of the first controller. For example, during the power-on phase, the first controller issues a power supply instruction based on the strategy of "powering on UFS first and enabling PCIe later". It first outputs the VCC / VCCQ standard voltage to the UFS interface layer and the external UFS storage module. After the UFS side is initialized and ready, it gradually supplies power to the PCIe interface layer and the protocol conversion layer, strictly controlling the power-on sequence of each power domain to avoid voltage surges that could damage the chip. During operation, the first controller issues dynamic power supply instructions according to the workload. When the conversion chip experiences abnormalities such as link disconnection or data verification errors, the first controller issues a reset instruction, and the power / reset control circuit immediately generates a reset signal to perform a power-off-reset operation on the faulty module to restore normal operation. At the same time, the power / reset control circuit has built-in overvoltage and overcurrent protection logic. When an abnormal power supply is detected, it automatically cuts off the corresponding power domain and sends an abnormal signal to the first controller.

[0120] In the embodiments of this disclosure, the global configuration register group is the hardware carrier for all configuration parameters of the storage chip, including multiple sub-register groups such as PCIe configuration registers, UFS configuration registers, protocol conversion registers, and power control registers, supporting read and write operations and parameter configuration by the first controller. For example, during the power-on initialization phase, the first controller writes initialization parameters such as the PCIe interface speed and link width, the UFS interface communication level and protocol version, the command mapping table parameters of the protocol conversion layer, and the power consumption thresholds of each module into the corresponding registers. Each module reads the parameters from the registers and completes its own configuration. During operation, the first controller can dynamically modify the configuration parameters in the registers according to the instructions of the electronic device or the real-time working status, realizing flexible switching of the chip's working mode. At the same time, the register group stores the chip's current working parameters in real time for the first controller and the electronic device to read and query.

[0121] In the embodiments of this disclosure, the interrupt aggregation and error monitoring circuit is used to realize the abnormal monitoring and signal aggregation of the conversion chip, and to collect various error signals in real time, such as link errors and data verification errors of the PCIe interface layer, transmission errors and command execution errors of the UFS interface layer, and parsing errors of the protocol conversion layer. At the same time, it monitors the working timeout status of each module. When an error or timeout is detected, a corresponding error interrupt signal is immediately generated. The interrupt aggregation circuit aggregates and prioritizes all interrupt signals of the entire chip and sends them to the first controller. After receiving the interrupt signal, the first controller issues corresponding processing instructions according to the error type and priority. The interrupt aggregation and error monitoring circuit records information such as error code, error occurrence module, and error time according to the instructions, and at the same time cooperates to complete recovery operations such as error retransmission and fault reset.

[0122] In the embodiments of this disclosure, the multi-clock domain synchronization logic circuit addresses the multi-clock domain differences between the PCIe interface layer, UFS interface layer, and protocol conversion layer, ensuring stable data transmission between modules and is controlled by the timing synchronization instructions of the first controller.

[0123] In some scenarios, due to differences in clock frequencies and data transfer rates between PCIe and UFS, timing misalignments can easily occur during data interaction between modules. Multi-clock domain synchronization logic circuits address this by enabling cross-domain synchronous data transmission between different clock domains, performing buffering, timing calibration, and synchronization verification on the transmitted data. For example, during operation, the first controller monitors the synchronization status of each clock domain in real time. When a timing offset is detected, a calibration command is issued, and the multi-clock domain synchronization logic circuit adjusts the buffer depth of the asynchronous FIFO and the timing of the handshake signals.

[0124] In the embodiments of this disclosure, the chip status monitoring circuit is a terminal for acquiring the working status of the conversion chip. It monitors in real time the link connection status and data transmission rate of the PCIe interface layer, the communication status and storage module interaction status of the UFS interface layer, the protocol conversion efficiency of the protocol conversion layer, and core status parameters such as temperature, power supply voltage, and workload of each module. At the same time, it quantizes and encodes the acquired status data in real time and transmits it to the first controller and the global configuration register group. For example, when a critical state such as excessive module temperature or overload is detected, the chip status monitoring circuit will actively send a warning signal to the first controller and trigger the first controller's power consumption adjustment and other protection strategies.

[0125] In the embodiments disclosed herein, the second controller is a dedicated data flow transport hardware unit in the conversion chip, which operates independently of the first controller and is responsible for migrating PCIe protocol data and UFS protocol data between the electronic device and the storage module. The second controller, in conjunction with the data buffer built into the conversion chip, receives instructions from the first controller for initialization and completes the entire data transfer process. It only sends an interrupt signal to the first controller after the task is completed, thereby improving the overall data transmission efficiency of the PCIe to UFS protocol conversion.

[0126] The following section, combining the read operation process and the overall operating logic of the control chip, elaborates on the operation of the second controller.

[0127] During the process of reading data from the storage module, after the electronic device sends a PCIe read command to the conversion chip, the first controller receives the command, translates it into a UFS read command by querying the command mapping table, and then encapsulates it into a UPIU data packet and sends it to the UFS storage module. At the same time, it sends a read operation trigger command to the second controller and configures relevant parameters. The second controller then enters the ready state. After the UFS storage module responds to the command, it reads the data, sends the data back to the conversion chip, and writes it into the built-in DBUF. The second controller monitors the DBUF data in real time. After the DBUF data reaches the threshold, the second controller automatically converts the data in the DBUF according to the PCIe protocol specification and moves it to the PCIe side without the first controller's intervention. Then, the data is sent back to the electronic device by the PCIe interface layer. After the second controller completes all data transfer, it immediately sends a data transfer completion interrupt signal to the first controller. The first controller receives and parses the signal. After confirming that there is no abnormality, it sends the read operation completion status back to the electronic device. Thus, the read operation is completed. The entire process realizes efficient coordination between the first controller's main control command scheduling and the second controller's autonomous data flow transfer.

[0128] The following section, combining the writing operation process and the overall operating logic of the control chip, elaborates on the operation process of the second controller.

[0129] During the process of writing data to the storage module, after the electronic device sends a PCIe write command and the data to be written to the conversion chip, the first controller first receives and parses the write command, translates it into a UFS write command by querying the command mapping table, encapsulates it into a UPIU data packet and sends it to the UFS storage module. At the same time, it sends a write operation trigger instruction to the second controller and configures relevant parameters such as data length and DBUF read / write threshold. The second controller then enters the ready state. After the data to be written sent by the electronic device enters the conversion chip through the PCIe interface layer, the second controller automatically moves the data to the built-in DBUF for caching, and then converts it according to the UFS protocol specification before moving it to the UFS interface layer. It is then sent to the UFS storage module through the second communication connection, triggering the storage module to perform a write operation. After the UFS storage module completes all data writing and sends back a write success status information, and the second controller confirms that all data has been successfully moved to the UFS side, it immediately sends a data transfer completion interrupt signal to the first controller. The first controller receives and parses the signal, combines it with the success status information of the UFS module, confirms that there is no abnormality, and then sends back the write operation completion status to the electronic device. Thus, a complete write operation is completed.

[0130] For example, the first controller may be an ARM CPU device in the conversion chip, and the second controller may be a DMA device in the conversion chip.

[0131] By employing the aforementioned storage device and utilizing the first controller to manage the system control module, precise control of clock and power timing is achieved, optimizing the operating parameter configuration of the storage module and providing a reliable error recovery mechanism to ensure stable operation of the storage device under various conditions. Simultaneously, the second controller improves data transfer efficiency, accelerates data transfer speed between electronic devices and the storage module, and enhances the overall performance of the storage system.

[0132] A second aspect of this disclosure provides an electronic device, including a device body and a storage device detachably disposed on the device body. The storage device includes a carrier for carrying and conducting electronic components, a conversion chip disposed on the carrier, and a storage module. The carrier is provided with a first connection interface, and the storage device establishes a first communication connection with the electronic device through the first connection interface. A second communication connection is established between the storage module and the conversion chip. The conversion chip is used to convert first protocol data obtained through the first communication connection into second protocol data, and to transmit the second protocol data to the storage module through the second communication connection. The storage module is capable of performing corresponding target read operations and / or target write operations in response to the second protocol data. The first communication connection is a high-speed serial computer expansion bus standard PCIe connection, and the second communication connection is a general-purpose flash memory storage (UFS) connection.

[0133] According to embodiments of this disclosure, the conversion chip includes a high-speed serial computer expansion bus standard PCIe interface layer, a universal flash memory storage UFS interface layer, and a protocol conversion layer disposed between the two; the PCIe interface layer is used to implement a first communication connection, and the UFS interface layer is used to implement a second communication connection; the protocol conversion layer is used to parse the first protocol data based on a maintained target mapping relationship, and encapsulate the parsed target extraction data into a universal flash memory storage protocol information unit to obtain the second protocol data; and / or, the conversion chip is further used to convert the second protocol data obtained through the second communication connection into the first protocol data, and to send the first protocol data back to the electronic device through the first communication connection.

[0134] According to embodiments of this disclosure, when an electronic device receives first instruction data to read first data content from a storage module, the conversion chip performs the following operations:

[0135] Parse the first instruction data and convert the obtained target read command into a general flash memory standard read command;

[0136] The generic flash storage protocol information unit obtained by encapsulating the generic flash storage standard read command is sent to the storage module to trigger the storage module to execute the corresponding target read operation;

[0137] The target data frame returned by the storage module is converted into a protocol, and the resulting protocol conversion result is transmitted back to the electronic device through the first communication connection. The target data frame can represent the first data content.

[0138] Figure 5 The illustration shows one of the interaction flow diagrams between an electronic device, a conversion chip, and a storage module according to an embodiment of the present disclosure.

[0139] Specifically, such as Figure 5 As shown, the electronic device establishes a first communication connection (PCIe connection) with the storage device through the first connection interface on the carrier; the conversion chip establishes a second communication connection (UFS connection) with the storage module, completing the initialization of the physical link and protocol link, and preparing for data transmission.

[0140] Furthermore, the electronic device 100 obtains first instruction data (such as an NVMe read command, including parameters such as LBA address and data length) for reading target data from the storage module 220, and sends the instruction data to the conversion chip 210 through the first communication connection. After receiving the instruction data, the conversion chip 210 parses the first instruction data to extract the target read command, converts it into a UFS standard read command based on a preset PCIe-UFS command mapping table, and encapsulates it into a Universal Flash Memory Protocol Information Unit (UPIU), which is then sent to the storage module 220 through the second communication connection to trigger the storage module 220 to perform the target read operation.

[0141] Subsequently, after receiving the UPIU, the storage module 220 parses the read command parameters (address, length). The main control chip of the storage module 220 reads the target data content from the corresponding location of its own storage medium (such as non-volatile flash memory), encapsulates the read data into a target data frame (including checksum, data payload, etc.) according to the UFS protocol specification, and sends the target data frame back to the conversion chip 210 through the second communication connection. After receiving the target data frame, the conversion chip 210 first performs verification and decapsulation on the data frame, extracts the original data, and then converts the UFS protocol format data into first protocol data conforming to the PCIe protocol specification. Subsequently, it sends the protocol conversion result back to the electronic device 100 through the first communication connection. After receiving and parsing the first protocol data, the electronic device 100 completes the read operation.

[0142] In some scenarios, the target data frame returned by the storage module can be all the data that the electronic device wants to read from the first instruction data sent by the electronic device, or it can be at least part of the data.

[0143] By employing the aforementioned electronic devices and utilizing the interactive process of the conversion chip to perform read operations, the conversion chip can accurately convert the PCIe read commands of the electronic devices into UFS standard read commands and send them out. After the storage module returns the target data, it is then converted back to the PCIe protocol format for transmission. This ensures both the integrity and accuracy of the read data and enables the conversion of different types of protocol data.

[0144] In embodiments of this disclosure, when the electronic device receives second instruction data to write second data content to the storage module, the conversion chip performs the following operations:

[0145] Convert the target write command obtained by parsing the second instruction data into a general flash memory standard write command;

[0146] The second data content obtained through the first communication connection is converted into a protocol and encapsulated with the general flash memory storage standard write command into a general flash memory storage protocol information unit, and sent to the storage module through the second communication connection to trigger the storage module to execute the corresponding target write operation;

[0147] After receiving status identification data from the storage module indicating that the General Flash Memory Protocol (GPLP) information unit has been successfully written, the status identification data is sent back to the electronic device.

[0148] Figure 6 The illustration shows a second schematic diagram of the interaction process between an electronic device, a conversion chip, and a storage module according to an embodiment of the present disclosure.

[0149] Specifically, such as Figure 6As shown, the electronic device 100 establishes a first communication connection with the storage device via the first connection interface on the storage device carrier using the high-speed serial computer expansion bus standard (PCIe), and this connection completes pre-operations such as link initialization; at the same time, the conversion chip 210 establishes a second communication connection with the storage module 220 using universal flash storage (UFS), ensuring that both communication links are in a ready state.

[0150] Furthermore, when the electronic device 100 receives second instruction data (i.e., a PCIe / NVMe write command, including parameters such as the target logical block address LBA and the length of the data to be written) to write second data content (such as user documents or multimedia files) to the storage module 220, it sends the second instruction data and the second data content to be written together to the conversion chip 210 through the first communication connection. After receiving the data, the conversion chip 210 first parses the second instruction data to extract the target write command, and converts it into a universal flash memory standard write command that conforms to the UFS protocol specification based on the preset PCIe-UFS command mapping table. Then, after the second data content is converted into a protocol, it is encapsulated together with the standard write command into a Universal Flash Memory Protocol Information Unit (UPIU) and sent to the storage module 220 through the second communication connection to trigger the storage module 220 to execute the target write operation. After receiving the UPIU, the storage module 220 parses the write command parameters (target address, data length) and the second data content, and writes the second data content to the corresponding location on its own storage medium. After the write is completed, the storage module 220 generates status flag data indicating that "data has been successfully written" (including success flag, number of bytes written, etc.), and sends the status flag data back to the conversion chip 210 through the second communication connection. After receiving the status flag data, the conversion chip 210 performs protocol conversion, converting the UFS protocol format status flag data into first protocol data conforming to the PCIe protocol specification; then, it sends the protocol conversion result back to the electronic device 100 through the first communication connection. After receiving and parsing the data, the electronic device 100 confirms that the write operation is complete.

[0151] By employing the aforementioned electronic device and utilizing the interactive process of the conversion chip to perform write operations, the conversion chip can convert the electronic device's write command and the data to be written into UFS format and send it to the storage module. After the write is completed, it receives the status flag and sends it back to the electronic device. This not only ensures the reliable storage of the written data, but also allows the electronic device to confirm the write result in real time through the status feedback mechanism, effectively avoiding the problems of incomplete or lost data writing.

[0152] According to embodiments of this disclosure, the electronic device is configured to prioritize the initialization process of the storage module during startup, and enter an enumerable state after the storage module completes initialization, whereby the electronic device performs high-speed serial computer expansion bus standard PCIe enumeration of the storage device through a first connection interface.

[0153] Specifically, during the power-on process of the storage device, there is a timing difference between the PCIe interface and the storage module in terms of power-on completion. To avoid the storage module's initialization power-on process not being completed after the PCIe interface has completed power-on, resulting in read / write operations sent to the conversion chip through the PCIe interface not being executed normally by the storage module and thus causing read / write operations to fail, in this embodiment of the present disclosure, a series of initialization processes of the storage module are executed first during the startup process. After the storage module completes initialization and enters an enumerable state, the electronic device performs high-speed serial computer expansion bus standard PCIe enumeration of the storage device through the first connection interface.

[0154] For example, the electronic device is pre-configured with a dedicated boot timing control strategy. During the device's boot process, after the storage device establishes a physical connection with the electronic device through the M.2 PCIe slot, the electronic device prioritizes providing power to the storage device's UFS storage module, triggering the storage module to execute the initialization process, completing operations such as UFS protocol adaptation, storage unit self-test, and hardware status readiness. The electronic device monitors the initialization status of the storage module in real time through its built-in detection module. Only when the storage module has completed all initialization operations and is in a ready state will the electronic device's PCIe interface layer be controlled to enter an enumerable state. Subsequently, the electronic device's boot system performs a high-speed serial computer extended bus standard PCIe enumeration operation on the storage device through the first connection interface, completing device identification, address allocation, and communication parameter configuration, ensuring that the storage device and the electronic device establish a stable first communication connection.

[0155] By using the aforementioned electronic devices, the device recognition failure problem caused by the difference in power-on and initialization timing between PCIe and UFS is avoided. By completing the initialization of the storage module first and then performing PCIe enumeration, it is ensured that the storage device is already in a stable and working state when it is recognized by the electronic devices, thereby improving the compatibility and stability of the devices and reducing data transmission failures caused by timing issues.

[0156] Figure 7 The schematic diagram shows the fourth schematic diagram of a storage device according to an embodiment of the present disclosure.

[0157] According to embodiments of this disclosure, such as Figure 7 As shown, the storage device 200 also includes a power management integrated circuit 230.

[0158] The electronic device 100 is configured to perform initialization of the conversion chip 210 and the power management integrated circuit 230 after the storage device 200 is connected to the electronic device 100, and after the initialization is completed, the power management integrated circuit 230 controls the storage module 220 to perform initialization.

[0159] The initialization status of the storage module 220 is detected by the embedded controller 110 of the electronic device 100;

[0160] If the storage module 220 has not been initialized, the embedded controller 110 sends a clock signal to the conversion chip 210 to extend the enumeration window period of the high-speed serial computer expansion bus standard PCIe.

[0161] After the storage module 220 completes initialization, it notifies the boot system of the electronic device 100 to perform a high-speed serial computer expansion bus standard PCIe enumeration on the storage device 200.

[0162] Figure 8 The illustration schematically shows a flow chart of a storage device initialization power-on process according to an embodiment of the present disclosure.

[0163] For example, such as Figure 8 As shown, when the storage device is connected to the M.2 slot of the electronic device through the first connection interface on the carrier, the electronic device first outputs 3.3V main power to the M.2 interface and enters the timing stage of the bridge chip and PMIC initialization, including the following steps one to two.

[0164] Step 1: The conversion chip (PCIe-UFS bridge chip) and PMIC (power management integrated circuit) first complete their own hardware initialization, including the reset and release of each module inside the conversion chip, clock reference calibration, loading of default register configuration, and initialization operations such as power output enable and voltage threshold configuration of the PMIC.

[0165] Step 2: After the conversion chip and PMIC are initialized, the PMIC starts to output the core power supply voltages such as VCC and VCCQ required by the UFS module according to the preset power timing strategy, triggering the UFS storage module startup initialization process. The UFS storage module startup initialization process follows the hardware timing of "UFS module power-on initialization first, then PCIe link ready", avoiding the problem of UFS not being ready due to PCIe enumeration too early.

[0166] Furthermore, the UFS module initialization status monitoring and PCIe clock control stage includes the following steps three to five.

[0167] Step three: Under the power supply control of the PMIC, the UFS storage module performs internal initialization operations such as protocol handshake, storage cell self-test, and parameter configuration; simultaneously, the embedded controller (EC) of the electronic device monitors the initialization status of the UFS storage module in real time.

[0168] Step 4: If the EC detects that the UFS storage module has not completed initialization (i.e., returns a not ready signal), the EC immediately sends a clock control command to the conversion chip through the CLKREQ# (clock request) signal of the M.2 interface. After receiving the command, the conversion chip dynamically adjusts the clock signal of the PCIe interface, including reducing the clock rate or temporarily pausing the PCIe clock output, thereby extending the PCIe enumeration window period, reserving sufficient time for UFS module initialization, and avoiding link identification failure triggered by enumeration too early.

[0169] Step 5: If the EC continuously detects that the UFS storage module initialization is incomplete, it will continue to slow down / pause the PCIe clock to extend the PCIe enumeration window until the UFS storage module completes all initialization operations and sends a ready signal back to the EC.

[0170] Furthermore, the UFS Ready Notification and PCIe Enumeration Startup phase includes steps six through eight as follows.

[0171] Step 6: Once the EC detects that the UFS storage module has completed initialization and confirms that it has entered a normal working state, it immediately executes Steps 7 and 8.

[0172] Step 7: Send a clock recovery command to the conversion chip. After receiving the command, the conversion chip restores the PCIe clock to the normal operating rate and notifies the PCIe link that preparation is complete, thus completing the basic link preparation before enumeration.

[0173] Step 8: Simultaneously send a UFS module ready notification to the electronic device's boot system (BIOS) to trigger the boot system to start the PCIe enumeration process.

[0174] Finally, after receiving the EC's readiness notification, the boot system (BIOS) performs the formal PCIe enumeration operation, including steps nine through ten below.

[0175] Step nine: The BIOS reads the PCIe device information (including device ID, manufacturer information, capacity, etc.) mapped by the conversion chip through the M.2 first connection interface, and completes the identification, parameter negotiation and address allocation of the PCIe device;

[0176] Step 10: Once the PCIe enumeration is complete, the conversion chip of the storage device and the UFS storage module establish a stable and normal communication connection through the bridging chip. The entire power timing control process ends, and the storage device enters normal working state, capable of responding to read and write operations initiated by electronic devices.

[0177] By employing the aforementioned electronic devices, and through power timing control of the power management integrated circuit, real-time status monitoring and clock regulation of the embedded controller, and enumeration triggering of the boot system, a timing control is formed that first completes UFS initialization and then performs PCIe enumeration. This effectively solves the problem of device identification failure caused by asynchronous power-on and initialization of PCIe and UFS, and ensures stable connection between storage devices and electronic devices.

[0178] According to embodiments of this disclosure, the electronic device is configured to power on the high-speed serial computer expansion bus standard PCIe link between the storage device and the electronic device after the conversion chip and power management integrated circuit have completed initialization, and the electronic device's boot system identifies the identification information of the storage device to trigger a delay strategy for high-speed serial computer expansion bus standard PCIe enumeration based on the identification information.

[0179] Specifically, such as Figure 8 As shown, after the PCIe link is initially powered on, the electronic device's boot system (BIOS) begins performing device enumeration pre-operations. Through the first connection interface, it sends a standard PCIe configuration read request to the conversion chip. The conversion chip, through its internal protocol conversion logic, sends its preset identification information back to the BIOS. Upon receiving this identification information, the BIOS parses and matches it, identifying that the currently connected device is not a traditional PCIe hard drive, but a PCIe-UFS bridged storage device with special initialization timing requirements.

[0180] Subsequently, based on the device identification information, the BIOS triggers a PCIe enumeration delay strategy, including: the BIOS actively suspends the execution of the formal PCIe enumeration process and enters a preset delay waiting phase (e.g., waiting 500ms-700ms). The purpose of the delay strategy is to allow sufficient time for the storage module to complete all initialization operations, such as UFS protocol handshake, storage cell self-test, and clock stabilization, under the power control of the PMIC, thereby avoiding the risk of PCIe enumeration failure due to incomplete UFS module initialization at the software level.

[0181] Finally, after the BIOS's preset delay time expires, it is confirmed that the UFS storage module has completed all initialization and is ready under the coordination of the PMIC power supply and conversion chip. Then, the normal PCIe enumeration process is resumed, that is, the BIOS re-initiates the PCIe enumeration request and completes the entire process of device enumeration, address allocation, interrupt configuration, etc. After the enumeration is completed, the conversion chip of the storage device establishes a stable and normal communication connection with the UFS storage module. The entire power supply and timing control process is completed synchronously. The electronic device recognizes the storage device as a normal PCIe storage device, and the device enters a normal working state, which can respond to various operation requests such as read and write initiated by the electronic device.

[0182] By employing the aforementioned electronic devices, precise control over the timing of PCIe enumeration is achieved, ensuring that formal enumeration is performed only after the UFS module has completed initialization. This effectively solves the problem of UFS module recognition failure caused by premature PCIe enumeration and ensures a stable and reliable connection between the PCIe-UFS bridged storage device and the electronic device.

[0183] The following is an illustrative description of the improvements to the storage module in an embodiment of this disclosure.

[0184] Figure 9 The fifth schematic diagram illustrates a storage device according to an embodiment of the present disclosure.

[0185] like Figure 9 As shown in the figure, a structural comparison between a traditional UFS storage device and the improved PCIe-UFS bridged storage device of this solution is presented, clearly demonstrating the core improvements and hardware implementation of this solution:

[0186] Figure 9 The upper and middle parts are traditional UFS storage devices, which are simple UFS architectures. They integrate only a single UFS storage chip on the PCB carrier. The interface and protocol are all UFS standard, which cannot be directly compatible with electronic devices that support PCIe protocol (such as consumer PCs and laptops). The application scenarios are limited, and it can only be adapted to devices with native UFS interfaces (such as some mobile phones and tablets). Figure 9 The lower middle part is a UFS storage device provided in this embodiment of the present disclosure. Based on the traditional UFS storage device, a conversion chip is added, and the bridging chip and the UFS storage chip are integrated together on a pre-configured carrier to form a complete pluggable storage device.

[0187] Figure 10 The schematic diagram illustrates a principle schematic of a conversion chip according to an embodiment of the present disclosure.

[0188] The following is combined Figure 10 The internal structure, module division, and interaction logic of the conversion chip are described in detail.

[0189] like Figure 10 As shown, the conversion chip adopts a layered architecture, mainly including a PCIe interface layer, a protocol conversion layer, a UFS interface layer, and a core control and data transfer module. Each module achieves high-speed interconnection through an internal data bus and control bus. The command path (Cmd Path) is indicated by a red arrow, and the data path (Data Path) by a black arrow. The specific structure and functions are as follows:

[0190] The PCIe interface layer is located on the left side of the chip and is physically connected to the Host-PCIe (electronic device). It is used to establish the first communication connection and includes: PCIe-PHY (physical layer circuit), which is responsible for the electrical connection, signal equalization and rate negotiation of the PCIe link (such as PCIe Gen3 / Gen4); PCIe (link layer and transaction layer circuit), which handles the framing, disframing, error checking and link management of PCIe data packets; and NVMe (command layer circuit), which parses NVMe protocol commands from the electronic device and provides input for subsequent protocol conversion.

[0191] The UFS interface layer is located on the right side of the chip and is physically connected to the external UFS storage module. It is used to establish a second communication connection and includes: M-PHY (UFS physical layer circuit), which is responsible for the electrical drive of the UFS link and HS-Gear rate configuration; UniPro (UFS link layer circuit), which realizes reliable data transmission and link management between UFS devices; and UFS protocol: command layer circuit, which encapsulates / parses UFS protocol information units (UPIU) and interacts with the UFS storage module with commands.

[0192] The ARM CPU (first controller) serves as the main control unit of the chip. It connects to various modules through the control bus and is responsible for receiving and parsing PCIe / NVMe commands, querying the command mapping table to convert them into UFS standard commands, encapsulating them into UPIUs, and sending them to the UFS interface layer. At the same time, it handles abnormal interrupts, executes firmware security / power consumption policies, and returns the operation completion status to the electronic device after the data transfer is completed.

[0193] The system control module provides hardware support for the conversion chip, including functions such as clock / power control, global configuration register, interrupt aggregation, error monitoring, multi-clock domain synchronization, and chip status monitoring, ensuring the stable operation of each module under the scheduling of the ARM CPU.

[0194] The DMAC (Second Controller) is a dedicated data transfer unit that is directly connected to the DBUF, PCIe interface layer, and UFS interface layer via a data bus. It can automatically transfer data in the DBUF between the PCIe and UFS sides at high speed without intervention from the ARM CPU, and only sends an interrupt signal to the ARM CPU after the task is completed.

[0195] DBUF (Data Buffer) is a high-speed temporary storage unit used to cache data streams caused by the difference in transmission rates between UFS and PCIe. It works with DMAC to enable read and write operations that move data while writing, thus avoiding data loss.

[0196] It should be noted that the electronic devices in the embodiments of this disclosure correspond to the storage devices in the embodiments of this disclosure, and their specific implementation details are the same. For embodiments not mentioned, please refer to the related embodiments of storage devices, which will not be repeated here.

[0197] Figure 11 A block diagram of an electronic device suitable for implementing the methods described above, according to embodiments of the present disclosure, is illustrated schematically. Figure 11 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0198] like Figure 11 As shown, an electronic device 1100 according to an embodiment of the present disclosure includes a processor 1101, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1102 or a program loaded from a storage portion 1108 into a random access memory (RAM) 1103. The processor 1101 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 1101 may also include onboard memory configured for caching purposes. The processor 1101 may include a single processing unit or multiple processing units configured to perform different actions of the method flow according to an embodiment of the present disclosure.

[0199] RAM 1103 stores various programs and data required for the operation of electronic device 1100. Processor 1101, ROM 1102, and RAM 1103 are interconnected via bus 1104. Processor 1101 performs various operations of the method flow according to embodiments of the present disclosure by executing programs in ROM 1102 and / or RAM 1103. It should be noted that the programs may also be stored in one or more memories other than ROM 1102 and RAM 1103. Processor 1101 may also perform various operations of the method flow according to embodiments of the present disclosure by executing programs stored in said one or more memories.

[0200] According to embodiments of this disclosure, the electronic device 1100 may further include an input / output (I / O) interface 1105, which is also connected to a bus 1104. The electronic device 1100 may also include one or more of the following components connected to the input / output (I / O) interface 1105: an input section 1106 including a keyboard, mouse, etc.; an output section 1107 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 1108 including a hard disk, etc.; and a communication section 1109 including a network interface card such as a LAN card, modem, etc. The communication section 1109 performs communication processing via a network such as the Internet. A drive 1110 is also connected to the input / output (I / O) interface 1105 as needed. A removable medium 1111, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 1110 as needed so that computer programs read from it can be installed into the storage section 1108 as needed.

[0201] According to embodiments of this disclosure, the method flow according to embodiments of this disclosure can be implemented as a computer software program. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable storage medium, the computer program containing program code configured to perform the methods shown in the flowchart. In such embodiments, the computer program can be downloaded and installed from a network via communication section 1109, and / or installed from removable medium 1111. When the computer program is executed by processor 1101, it performs the functions defined in the system of embodiments of this disclosure. According to embodiments of this disclosure, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0202] This disclosure also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs that, when executed, implement the method according to the embodiments of this disclosure.

[0203] According to embodiments of this disclosure, the computer-readable storage medium can be a non-volatile computer-readable storage medium. Examples include, but are not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this disclosure, the computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0204] For example, according to embodiments of this disclosure, a computer-readable storage medium may include one or more memories other than the ROM 1102 and / or RAM 1103 described above and / or ROM 1102 and RAM 1103.

[0205] Embodiments of this disclosure also include a computer program product comprising a computer program containing program code configured to perform the methods provided in the embodiments of this disclosure. When the computer program product is run on an electronic device, the program code is configured to cause the electronic device to implement the display control methods provided in the embodiments of this disclosure.

[0206] When the computer program is executed by the processor 1101, it performs the functions defined in the system / apparatus of this disclosure embodiments. According to embodiments of this disclosure, the systems, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0207] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and may be downloaded and installed via the communication section 1109, and / or installed from the removable medium 1111. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0208] According to embodiments of this disclosure, program code configured to execute the computer programs provided in embodiments of this disclosure can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can execute entirely on a user's computing device, partially on a user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0209] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions configured to perform a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions. Those skilled in the art will understand that the features described in the various embodiments of the present disclosure can be combined and / or combined in various ways, even if such combinations are not explicitly described in the present disclosure. In particular, the features described in the various embodiments of this disclosure may be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0210] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A storage device comprising a carrier for carrying and conducting electronic components, a conversion chip disposed on the carrier, and a storage module, the storage device being detachably connected to an electronic device; wherein, The carrier is provided with a first connection interface, and the storage device can establish a first communication connection with the electronic device through the first connection interface; A second communication connection is established between the storage module and the conversion chip; The conversion chip is used to convert the first protocol data obtained from the first communication connection into second protocol data, and to send the second protocol data to the storage module through the second communication connection; The storage module can respond to the second protocol data to perform the corresponding target read operation and / or target write operation; The first communication connection is a high-speed serial computer expansion bus standard PCIe connection, and the second communication connection is a general-purpose flash memory storage UFS connection.

2. The storage device according to claim 1, wherein the conversion chip comprises a high-speed serial computer expansion bus standard PCIe interface layer, a universal flash memory storage UFS interface layer, and a protocol conversion layer disposed between the two; The PCIe interface layer is used to implement the first communication connection, and the UFS interface layer is used to implement the second communication connection. The protocol conversion layer is used to parse the first protocol data based on the maintained target mapping relationship, and encapsulate the parsed target extraction data into a general flash memory storage protocol information unit to obtain the second protocol data. And / or, The conversion chip is also used to convert the second protocol data obtained through the second communication connection into first protocol data, and to send the first protocol data back to the electronic device through the first communication connection.

3. The storage device according to claim 2, wherein the conversion chip further comprises a first controller and a system control module; The first controller is capable of controlling the system control module to perform clock and power timing management control, configuring the operating parameters of the storage module, and providing at least one of the following error recovery mechanisms: And / or, The conversion chip also includes a second controller for transferring data streams between the electronic device and the storage module.

4. An electronic device, comprising a device body and a storage device detachably disposed on the device body, the storage device comprising a carrier for carrying and conducting electronic components, a conversion chip disposed on the carrier, and a storage module; wherein, The carrier is provided with a first connection interface, and the storage device establishes a first communication connection with the electronic device through the first connection interface; A second communication connection is established between the storage module and the conversion chip; The conversion chip is used to convert the first protocol data obtained through the first communication connection into second protocol data, and to send the second protocol data to the storage module through the second communication connection; The storage module can respond to the second protocol data to perform the corresponding target read operation and / or target write operation; The first communication connection is a high-speed serial computer expansion bus standard PCIe connection, and the second communication connection is a general-purpose flash memory storage UFS connection.

5. The electronic device according to claim 4, wherein the conversion chip includes a high-speed serial computer expansion bus standard PCIe interface layer, a universal flash memory storage UFS interface layer, and a protocol conversion layer disposed between the two; The PCIe interface layer is used to implement the first communication connection, and the UFS interface layer is used to implement the second communication connection. The protocol conversion layer is used to parse the first protocol data based on the maintained target mapping relationship, and encapsulate the parsed target extraction data into a general flash memory storage protocol information unit to obtain the second protocol data. And / or, The conversion chip is also used to convert the second protocol data obtained through the second communication connection into first protocol data, and to send the first protocol data back to the electronic device through the first communication connection.

6. The electronic device according to claim 4 or 5, wherein, When the electronic device receives first instruction data to read first data content from the storage module, the conversion chip performs the following operations: Parse the first instruction data and convert the obtained target read command into a general flash memory standard read command; The generic flash storage protocol information unit obtained by encapsulating the generic flash storage standard read command is sent to the storage module to trigger the storage module to execute the corresponding target read operation; The target data frame returned by the storage module is subjected to protocol conversion, and the resulting protocol conversion result is transmitted back to the electronic device through the first communication connection. The target data frame can represent the first data content.

7. The electronic device according to claim 4 or 5, wherein, When the electronic device receives a second instruction to write second data content to the storage module, the conversion chip performs the following operations: The target write command obtained by parsing the second instruction data is converted into a general flash memory standard write command. The second data content obtained through the first communication connection is converted into a protocol and encapsulated with the general flash memory storage standard write command into a general flash memory storage protocol information unit, and sent to the storage module through the second communication connection to trigger the storage module to execute the corresponding target write operation; After receiving status identification data from the storage module indicating that the General Flash Memory Protocol information unit has been successfully written, the status identification data is sent back to the electronic device.

8. The electronic device according to claim 4 or 5, wherein the electronic device is configured to preferentially execute the initialization process of the storage module during startup, and enter an enumerable state after the storage module has completed initialization, and the electronic device performs high-speed serial computer expansion bus standard PCIe enumeration of the storage device through the first connection interface.

9. The electronic device according to claim 8, wherein, The storage device also includes a power management integrated circuit; The electronic device is configured to perform initialization of the conversion chip and the power management integrated circuit after the storage device is connected to the electronic device, and after the initialization is completed, the power management integrated circuit controls the storage module to perform initialization. The initialization status of the storage module is detected by the embedded controller of the electronic device; If the storage module has not been initialized, the embedded controller sends a clock signal to the conversion chip to extend the enumeration window period of the high-speed serial computer expansion bus standard PCIe. After the storage module completes initialization, the boot system of the electronic device is notified to perform a high-speed serial computer expansion bus standard PCIe enumeration on the storage device.

10. The electronic device according to claim 9, wherein the electronic device is configured to, after the conversion chip and the power management integrated circuit have completed initialization, control the high-speed serial computer expansion bus standard PCIe link between the storage device and the electronic device to start power-on, and the boot system of the electronic device identifies the identification information of the storage device to trigger a delay strategy for high-speed serial computer expansion bus standard PCIe enumeration based on the identification information.

Images