Bit error rate determination architecture and bit error rate determination method

Abstract

This disclosure provides a bit error rate (BER) determination architecture and method, applied in the field of computer technology. The architecture includes: a field-programmable gate array (FPGA), a pressure generator, a controller, a link loss compensation board, a first test fixture board, and a second test fixture board. The FPGA is used to send a first test signal to the pressure generator based on a first channel; the pressure generator processes the first test signal based on pressure eye parameters to obtain a second test signal, and transmits the second test signal through the link loss compensation board to the first test fixture board based on the first channel. The controller is used to receive the second test signal transmitted from the first test fixture board based on the first channel, and transmit the second test signal to the FPGA based on the second channel. The FPGA is also used to determine the BER based on the first test signal and the second test signal received through the second channel. Thus, the source of the problem can be determined when a controller NAND error occurs.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a bit error rate determination architecture and bit error rate determination method. Background Technology

[0002] The reliability of non-volatile flash memory (NAND) in solid-state drives (SSDs) directly affects their durability, data retention, and overall performance. This primarily includes cell degradation due to increased program / erase cycles (P / E cycles), data retention issues caused by natural charge loss, read / write interference effects, and initial and newly added bad blocks. With the shrinking of process nodes and the increase in the number of stacked layers in 3D NAND flash memory, reliability challenges such as vertical interference become increasingly significant.

[0003] In SSD controller NAND interfaces, signal integrity and timing issues are crucial for reliable data transmission. With interface speeds increasing to 1600 mega-transfers per second (MT / s) and above, signal quality problems caused by impedance mismatch, crosstalk, and power supply noise, as well as timing issues such as insufficient setup / hold time margin, can easily lead to data transmission errors and controller NAND errors. While related technologies employ measures such as on-die termination (ODT) impedance matching, timing calibration, and printed circuit board (PCB) optimization to improve interface performance, they still cannot solve the problem of difficulty in pinpointing the cause of controller NAND errors.

[0004] Currently, SSD controller NAND errors are frequently occurring in the market. The causes are complex and may stem from multiple aspects such as the controller hardware NAND interface, SSD firmware, or PCB design. Existing technologies lack effective methods for troubleshooting error causes, making it difficult to quickly locate the source of the fault, which affects the maintenance efficiency and user experience of SSDs. Summary of the Invention

[0005] This disclosure provides a bit error rate determination architecture and a bit error rate determination method to at least solve the above-mentioned technical problems existing in the prior art.

[0006] According to a first aspect of this disclosure, a bit error rate determination architecture is provided, the architecture comprising: a field-programmable gate array (FPGA), a stress generator, a controller, a link loss compensation board, a first test fixture board, and a second test fixture board;

[0007] The FPGA is communicatively connected to the second test fixture board and the pressure generator, respectively; the link loss compensation board is communicatively connected to the first test fixture board and the pressure generator, respectively; the controller is connected to the first test fixture board and the second test fixture board, respectively. The FPGA is used to send a first test signal to the pressure generator based on a first channel; so that the pressure generator processes the first test signal based on pressure eye parameters to obtain a second test signal, and transmits the second test signal to the first test fixture board through the link loss compensation board based on the first channel; The controller is configured to receive a second test signal transmitted from the first test fixture board via a first channel, and transmit the second test signal to the FPGA via a second channel. The FPGA is also used to determine the bit error rate based on the first test signal and the second test signal received through the second channel.

[0008] In the above scheme, the FPGA is also communicatively connected to the first test fixture board; The FPGA is also used to simulate a first non-volatile flash memory NAND chip, and to send a first test signal to the controller through a first channel when the controller performs a read operation. The FPGA is also used to simulate a second NAND flash chip, and to receive the second test signal through a second channel when the controller performs a write operation.

[0009] In the above scheme, the controller, the first test fixture board and the second test fixture board are all mounted on a printed circuit board; The controller is also configured to transmit a first drive signal to the FPGA via the first test fixture board, so that the FPGA can simulate the first NAND chip based on the first drive signal; The controller is also configured to transmit a second drive signal to the FPGA via the second test fixture board, so that the FPGA can simulate a second NAND chip based on the second drive signal.

[0010] In the above scheme, the FPGA includes a first channel control interface, an Ethernet interface, a second channel control interface, and a second channel data interface; The first channel control interface is used to receive the first drive signal transmitted by the controller; The Ethernet interface is used to send a first test signal to the generator; The second channel control interface is used to receive the second drive signal transmitted by the controller; The second channel data interface is used to receive the second test signal transmitted by the controller based on the second channel.

[0011] In the above scheme, the controller includes at least one set of channel interfaces, and each set of channel interfaces includes at least a read interface and a write interface; The read interface is used to receive test data sent by the first test fixture board; The write interface is used to send test data to the second test fixture board; The read interface and the write interface correspond to different channels.

[0012] In the above scheme, the controller is specifically used for: The second test data transmitted through the first channel is received based on the read interface; Write the first test data into the memory corresponding to the second channel; The second test data is obtained from the memory corresponding to the second channel through the write interface, and then sent to the second channel data interface of the FPGA through the second channel.

[0013] In the above scheme, the first test fixture board includes n data input / output interfaces, a sampling reference clock interface, a read enable signal interface, a chip select signal interface, a write enable interface, a command latch enable interface, and an address latch enable interface; The interface for sampling the reference clock signal on the controller is connected to the corresponding sampling reference clock interface on the first test fixture board via a coaxial cable. The interface for reading the enable signal on the controller is connected to the corresponding interface for reading the enable signal on the first test fixture board via a coaxial cable.

[0014] In the above scheme, any one read interface on the controller corresponds to n data input and output signals; Each data input / output signal of the read interface is connected to the corresponding data input / output interface on the first test fixture board via a coaxial cable.

[0015] In the above scheme, the second test fixture board includes n data input / output interfaces, a sampling reference clock interface, a write enable signal interface, a chip select signal interface, a read enable interface, a command latch enable interface, and an address latch enable interface; The interface for sampling the reference clock signal on the controller is connected to the corresponding sampling reference clock interface on the second test fixture board via a coaxial cable. The write enable signal interface on the controller is connected to the corresponding write enable signal interface on the second test fixture board via a coaxial cable.

[0016] In the above scheme, any one write interface on the controller corresponds to n data input / output signals; Each data input / output signal of the write interface is connected to the corresponding data input / output interface on the second test fixture board via a coaxial cable.

[0017] In the above scheme, the pressure eye parameters include the target eye diagram voltage and the target harmonic voltage; the FPGA can also be physically connected to the link loss compensation board via an oscilloscope; the FPGA is also used for: A third test signal is sent to the pressure generator so that the pressure generator processes the third test signal to obtain a fourth test signal, and the fourth test signal is input to the oscilloscope through the link loss compensation board; The eye diagram of the fourth test signal transmitted by the oscilloscope is received, and a target eye diagram voltage is determined based on the eye diagram of the fourth test signal, so that the pressure generator processes the third test signal based on the target eye diagram voltage to obtain a fifth test signal that meets the preset conditions. The preset conditions include the worst signal quality that can be transmitted under the eye diagram template conditions.

[0018] In the above scheme, the FPGA is also used for: The eye diagram of the fifth test signal transmitted by the oscilloscope is received, and a target harmonic voltage is determined based on the eye diagram of the fifth test signal, so that the pressure generator processes the fifth test signal based on the target harmonic voltage to obtain a sixth test signal that meets preset conditions.

[0019] In the above scheme, the pressure generator is specifically used for: Receive pressure eye parameters; The second, third, and fifth harmonics corresponding to the first test signal are determined based on the pressure eye parameters. The second test signal is determined based on the first test signal and the second, third, and fifth harmonics corresponding to the first test signal.

[0020] In the above scheme, the characteristic impedance of the link loss compensation board is 50 ohms.

[0021] According to a second aspect of this disclosure, a method for determining bit error rate is provided, the method comprising: The FPGA sends a first test signal to the pressure generator based on the first channel; so that the pressure generator processes the test signal based on the pressure eye parameters to obtain a second test signal, and transmits the second test signal to the first test fixture board through the link loss compensation board based on the first channel; The controller receives the second test signal transmitted from the first test fixture board based on the first channel, and transmits the second test signal to the FPGA based on the second channel; The FPGA determines the bit error rate based on the first test signal and the second test signal received from the second channel.

[0022] The bit error rate (BER) determination architecture and method disclosed herein are as follows: An FPGA is communicatively connected to a second test fixture board and a pressure generator; a link loss compensation board is communicatively connected to a first test fixture board and a pressure generator; a controller is connected to both the first and second test fixture boards. The FPGA is used to send a first test signal to the pressure generator via a first channel; the pressure generator processes the first test signal based on pressure eye parameters to obtain a second test signal, and transmits the second test signal to the first test fixture board via the link loss compensation board via the first channel. The controller is used to receive the second test signal transmitted from the first test fixture board via the first channel, and transmit the second test signal to the FPGA via the second channel. The FPGA is also used to determine the BER based on the first test signal and the second test signal received via the second channel. Thus, the signal reception capability of each interface of the controller, as well as the channel signal capability, can be determined. In the event of a controller NAND error, the source of the problem can be identified according to the architecture or method described herein.

[0023] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0024] The above and other objects, features, and advantages of this disclosure will become readily apparent from the following detailed description of exemplary embodiments, taken in conjunction with the accompanying drawings. Several embodiments of this disclosure are illustrated in the drawings by way of example and not limitation, in which: In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0025] Figure 1 A schematic diagram of a first alternative structure of the bit error rate determination architecture provided in this disclosure embodiment is shown; Figure 2 A schematic diagram of a second alternative structure of the bit error rate determination architecture provided in this disclosure embodiment is shown; Figure 3 A schematic diagram of a third optional structure of the bit error rate testing architecture provided in this disclosure embodiment is shown; Figure 4 A schematic diagram of an optional structure of the test fixture plate provided in an embodiment of this disclosure is shown; Figure 5 A schematic diagram of a fourth optional structure of the bit error rate testing architecture provided in this disclosure embodiment is shown; Figure 6 A schematic diagram of a fifth optional structure of the bit error rate determination architecture provided in this disclosure embodiment is shown; Figure 7 A schematic diagram of a first optional process for determining the bit error rate provided in an embodiment of this disclosure is shown; Figure 8 A schematic diagram of a second optional process for determining the bit error rate provided in an embodiment of this disclosure is shown. Detailed Implementation

[0026] To make the objectives, features, and advantages of this disclosure more apparent and understandable, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0027] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0028] In the following description, the terms "first" and "second" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first" and "second" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0029] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in this disclosure is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0030] It should be understood that in the various embodiments of this disclosure, the sequence number of each implementation process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0031] Common problems with NAND flash memory in solid-state drives (SSDs) mainly fall into the following categories: First, cell degradation due to increased P / E cycle counts manifests as a narrowing threshold voltage window and increased bit error rate. Second, data retention issues arise, as stored charge naturally dissipates over time, particularly noticeable in high-temperature environments. Third, read / write interference effects exist, including interference from read operations on adjacent cells (read interference) and the impact of programming on neighboring cells (write interference). Additionally, bad block issues exist, including initial bad blocks at the factory and bad blocks added during use. As process nodes shrink, these reliability challenges become more significant, especially the vertical interference issues in 3D NAND due to the increased number of stacked layers. Furthermore, signal integrity and timing issues at the NAND interface can also lead to data transmission errors during high-speed transmission. These problems collectively affect the durability, data retention capabilities, and overall performance of SSDs, requiring mitigation through techniques such as ECC error correction, wear leveling, and bad block management.

[0032] In SSD controller NAND interfaces, signal integrity and timing issues are critical factors affecting data transmission reliability. As interface speeds increase to 1600MT / s or even higher, signal integrity issues primarily manifest as reflections due to impedance mismatch, signal distortion caused by crosstalk, and jitter caused by power supply noise. These factors significantly increase the bit error rate (BER). Timing issues are concentrated in insufficient setup and hold time margins, excessive clock-data skew, and access time (tR / tPROG) fluctuations, especially prominent during multi-channel parallel operations. To address these issues, the industry primarily employs impedance matching designs (such as on-chip ODT), differential signal architectures (Toggle mode), pre-emphasis, and equalization techniques to improve signal quality; precise timing calibration algorithms, Dynamic Timing Compensation (DTS), and JEDEC-standardized timing parameter constraints ensure sufficient timing margins; and strict length matching, layered routing, and power integrity optimization schemes are used in the PCB design phase. These measures collectively ensure the stability and reliability of high-speed NAND interfaces under various operating conditions, laying the foundation for continuous improvements in SSD performance.

[0033] Since 2011, the JEDEC Solid State Technology Association has released the first universal NAND standard, compatible with ONFI and Toggle, unifying the interface and command set. With the continuous improvement of NAND interface speeds and the transition of storage types from SLC to MLC, TLC, and QLC, the increasing capacity of single NAND chips has placed increasingly higher demands on the signal integrity of chips and PCBs. Bit error rate (BER) is a commonly used indicator for evaluating the signal quality of high-speed interfaces. The JESD218 specification defines a typical uncorrectable BER of ≤1e-17 for NAND in SSDs. The industry method for calculating BER is to send specific data packets to the NAND, then read these specific data packets out, and perform verification between the written and read data to calculate the BER.

[0034] Currently, SSD controller NAND errors are frequently occurring in the market. The causes are complex and may stem from multiple aspects such as the controller hardware NAND interface, SSD firmware, or PCB design. Existing technologies lack effective methods for troubleshooting error causes, making it difficult to quickly locate the source of the fault, which affects the maintenance efficiency and user experience of SSDs.

[0035] Figure 1 A schematic diagram of a first alternative architecture for determining bit error rate provided in an embodiment of this disclosure is shown, and will be described in terms of each part.

[0036] like Figure 1 As shown, the bit error rate determination architecture includes: an FPGA, a pressure generator, a controller, a link loss compensation board, a first test fixture board, and a second test fixture board; the controller can be an SSD controller.

[0037] In some embodiments, the FPGA is communicatively connected to the second test fixture board and the pressure generator, respectively; the link loss compensation board is communicatively connected to the first test fixture board and the pressure generator, respectively; and the controller is connected to the first test fixture board and the second test fixture board, respectively.

[0038] In some embodiments, the FPGA is configured to send a first test signal to a pressure generator based on a first channel; so that the pressure generator processes the first test signal based on pressure eye parameters to obtain a second test signal, and transmits the second test signal to the first test fixture board via the link loss compensation board based on the first channel.

[0039] In some embodiments, the controller is configured to receive a second test signal transmitted from a first test fixture board via a first channel, and transmit the second test signal to the FPGA via a second channel. In some embodiments, the FPGA is further configured to determine the bit error rate based on the first test signal and the second test signal received through the second channel.

[0040] In some embodiments, the transmission link consisting of the FPGA, pressure generator, link loss compensation board, first test fixture board and controller corresponds to the first channel; the transmission link consisting of the controller, second test fixture board and FPGA corresponds to the second channel.

[0041] In practice, the FPGA generates a first test signal and sends the first test signal to the pressure generator through a first channel.

[0042] After receiving the first test signal, the pressure generator generates a harmonic corresponding to the first test signal and adjusts the eye diagram voltage and harmonic voltage of the first test signal and the harmonic to obtain a second test signal. Based on the first channel, the second test signal is transmitted to the first test fixture board through the link loss compensation board, and the first test fixture board transmits the second test signal to the controller.

[0043] The link loss compensation board is used to compensate for link loss.

[0044] In some embodiments, the controller receives the second test signal based on the interface corresponding to the first channel, and transmits the second test signal to the FPGA through the second test fixture board via the interface corresponding to the second channel, so that the FPGA determines the bit error rate based on the first test signal and the second test signal received through the second channel.

[0045] Furthermore, in the event of a NAND error in the SSD corresponding to the controller, the fault source is located by the bit error rate. Specifically, if the bit error rate is within a preset threshold, it is determined that the NAND interface, SSD, or PCB is not faulty, and the problem may be with the reliability of the NAND. Alternatively, if the bit error rate is greater than or equal to the preset threshold, the fault source is determined to be the controller, specifically including the controller's NAND interface, the controller itself, or the PCB.

[0046] Thus, the bit error rate determination architecture provided by the embodiments of this disclosure can determine the signal reception capability of each interface of the controller and the channel signal capability. In the event of a controller NAND error, the source of the problem can be determined according to the architecture described in this disclosure.

[0047] Figure 2 A schematic diagram of a second alternative architecture for determining bit error rate provided in an embodiment of this disclosure is shown, and will be described in terms of each part.

[0048] In some embodiments, the FPGA includes a first channel control interface, an Ethernet interface, a second channel control interface, and a second channel data interface.

[0049] The first channel control interface is used to receive a first drive signal transmitted by the controller; the Ethernet interface is used to send a first test signal to the generator; the second channel control interface is used to receive a second drive signal transmitted by the controller; and the second channel data interface is used to receive a second test signal transmitted by the controller based on the second channel.

[0050] In some embodiments, the FPGA is also used to emulate a first NAND flash chip, and to send a first test signal to the controller via a first channel when the controller performs a read operation.

[0051] In some embodiments, the FPGA is further configured to simulate a second NAND flash chip, and to receive the second test signal via a second channel when the controller performs a write operation.

[0052] Thus, in this embodiment of the disclosure, NAND flash memory is simulated using an FPGA for bit error rate testing, which facilitates the location of the fault source in the event of an SSD failure. Furthermore, the FPGA simulates a first NAND flash memory chip used for reading data and a second NAND flash memory chip used for writing data separately, achieving read-write separation. This avoids the time wasted on erasing and reprogramming the NAND flash memory chip during bit error rate testing when simulating NAND flash memory chips with both read and write capabilities. Simulating both the first and second NAND flash memory chips with an FPGA also avoids the inaccurate bit error rate results caused by changes in test conditions due to increased P / E ratios when repeatedly testing the same NAND flash memory chip.

[0053] In the architecture provided in this disclosure, NAND flash memory is simulated using FPAG, thus avoiding changes in test conditions and increased test time caused by NAND flash memory involvement in testing.

[0054] In some embodiments, the FPGA is also communicatively connected to the first test fixture board; the controller, the first test fixture board, and the second test fixture board are all disposed on a printed circuit board.

[0055] In some embodiments, the controller is further configured to transmit a first drive signal to the FPGA via a first test fixture board, so that the FPGA simulates a first NAND chip based on the first drive signal; In some embodiments, the controller is further configured to transmit a second drive signal to the FPGA via a second test fixture board, so that the FPGA simulates a second NAND flash chip based on the second drive signal.

[0056] In some embodiments, the controller drives the FPAG to simulate the first NAND flash memory and the second NAND flash memory based on the first drive signal and the second drive signal.

[0057] In some embodiments, the first NAND flash memory chip is used to implement read operations and corresponds to the first channel; the second NAND flash memory chip is used to implement write operations and corresponds to the second channel.

[0058] In some embodiments, the FPGA sends a first test signal to the pressure generator via an Ethernet interface and a first channel; so that the pressure generator processes the first test signal based on pressure eye parameters to obtain a second test signal, and transmits the second test signal to the first test fixture board via the link loss compensation board based on the first channel.

[0059] In some embodiments, the controller is configured to receive a second test signal transmitted from a first test fixture board based on a first channel, and transmit the second test signal to the second channel data interface of the FPGA based on a second channel.

[0060] In some embodiments, the FPGA is further configured to determine the bit error rate based on the first test signal and the second test signal received through the second channel.

[0061] In practice, the FPGA generates a first test signal through an Ethernet interface and sends the first test signal to the pressure generator through a first channel.

[0062] After receiving the first test signal, the pressure generator generates a harmonic corresponding to the first test signal and adjusts the eye diagram voltage and harmonic voltage of the first test signal and the harmonic to obtain a second test signal. Based on the first channel, the second test signal is transmitted to the first test fixture board through the link loss compensation board, and the first test fixture board transmits the second test signal to the controller.

[0063] The link loss compensation board is used to compensate for link loss.

[0064] In some embodiments, the controller receives the second test signal based on the interface corresponding to the first channel, and transmits the second test signal through the interface corresponding to the second channel to the second channel data interface of the FPGA via the second test fixture board, so that the FPGA determines the bit error rate based on the first test signal and the second test signal received through the second channel.

[0065] Figure 3 A schematic diagram of a third optional structure of the bit error rate testing architecture provided in this disclosure is shown, and will be described in terms of each part.

[0066] like Figure 3As shown, the controller is an SSD master controller, and its NAND physical layer (PHY) includes 16 channel interfaces: CHANNEL0, CHANNEL1, ..., CHANNEL14, CHANNEL15. Since two channel interfaces can be defined as a group of channel interfaces, the controller includes at least one group of channel interfaces. Each group of channel interfaces includes at least a read interface and a write interface. The read interface is used to receive test data sent by the first test fixture board; the write interface is used to send test data to the second test fixture board.

[0067] like Figure 3 The interface corresponding to the first channel (CHANNEL1) is the read interface (R), and the interface corresponding to the second channel (CHANNEL0) is the write interface (W). Figure 3 The read interface of CHANNEL1 and the write interface of CHANNEL0 form a group of channel interfaces. Optionally, the read interface of CHANNEL3 and the write interface of CHANNEL2 form a group of channel interfaces, ..., the read interface of CHANNEL15 and the write interface of CHANNEL14 form a group of channel interfaces.

[0068] In some embodiments, the controller receives second test data transmitted through the first channel based on the read interface; writes the first test data into the memory corresponding to the second channel; retrieves the second test data from the memory corresponding to the second channel through the write interface; and sends the second test data to the second channel data interface of the FPGA through the second channel.

[0069] In specific implementation, the FPGA sends a first test signal to the pressure generator through the Ethernet interface and the first channel; so that the pressure generator processes the first test signal based on the pressure eye parameters to obtain a second test signal, and transmits the second test signal to the first test fixture board through the link loss compensation board based on the first channel.

[0070] In some embodiments, the controller is configured to receive a second test signal transmitted from the first test fixture board based on the read interface corresponding to the first channel, and transmit the second test signal to the second channel data interface of the FPGA based on the write interface corresponding to the second channel.

[0071] In some embodiments, the FPGA is further configured to determine the bit error rate based on the first test signal and the second test signal received through the second channel.

[0072] Figure 4 A schematic diagram of an optional structure of the test fixture plate provided in an embodiment of this disclosure is shown, and the details will be explained based on each part.

[0073] Figure 4(a) shows a schematic diagram of the interface of the first test fixture board or the second test fixture board, which includes 12 coaxial cable interfaces and 4 solder points; Figure 4 (b) shows a schematic diagram of the interface data of the first test fixture board or the second test fixture board.

[0074] like Figure 4 As shown, the first test fixture board includes n data input / output interfaces, where n is a positive integer. Figure 4 In this case, n is 8. The sampling reference clock (DQS) is a differential signal. The first test fixture board includes two sampling reference clock interfaces: one is DQS+ for receiving positive signals, and the other is DQS- for receiving negative signals.

[0075] The first test fixture board is used to transmit signals in the data reading link. Its corresponding enable signal interface is the read enable signal interface. The read enable signal (RE) is a differential signal. The first test fixture board includes two read enable signal interfaces, one is RE+ for receiving positive signals, and the other is RE for receiving negative signals.

[0076] The chip select signal interface, write enable interface, command latch enable interface, and address latch enable interface are soldered to the corresponding interfaces of the controller.

[0077] In some embodiments, the n data input / output interfaces, sampling reference clock interface, and read enable signal interface on the first test fixture board are connected to the controller via coaxial cables; the chip select signal interface, write enable interface, command latch enable interface, and address latch enable interface on the first test fixture board are connected to the controller via soldering.

[0078] In specific implementation, the interface for sampling the reference clock signal on the controller is connected to the corresponding sampling reference clock interface on the first test fixture board via a coaxial cable; the interface for reading the enable signal on the controller is connected to the corresponding read enable signal interface on the first test fixture board via a coaxial cable.

[0079] In some embodiments, any one read interface on the controller corresponds to n data input / output signals; the interface corresponding to each data input / output signal of the read interface is connected to the corresponding data input / output interface on the first test fixture board via a coaxial cable.

[0080] In some embodiments, the controller, the first test fixture board, and the second test fixture board are soldered onto the same printed circuit board, and data is transmitted through the printed circuit board.

[0081] In this way, the data output signals are connected via a coaxial cable, facilitating the switching of channel interfaces during testing. For example, it is easy to switch CHANNEL0 on the controller to CHANNEL2. Only the interface connected to the controller needs to be changed.

[0082] The second test fixture board includes n data input / output interfaces, a sampling reference clock interface, a write enable signal interface, a chip select signal interface, a read enable interface, a command latch enable interface, and an address latch enable interface. The sampling reference clock signal interface on the controller is connected to the corresponding sampling reference clock interface on the second test fixture board via a coaxial cable. The write enable signal interface on the controller is connected to the corresponding write enable signal interface on the second test fixture board via a coaxial cable. Each write interface on the controller corresponds to n data input / output signals; the interface corresponding to each data input / output signal of the write interface is connected to the corresponding data input / output interface on the second test fixture board via a coaxial cable. The second test fixture board is similar to the first test fixture board and will not be described again here.

[0083] Figure 5 A schematic diagram of a fourth optional structure of the bit error rate testing architecture provided in this disclosure is shown.

[0084] like Figure 5 As shown, the bit error rate test architecture includes an FPGA, a stress generator, a link loss compensation board, and an oscilloscope. Figure 5 The architecture shown is used to determine the pressure eye parameters, which include the target eye diagram voltage and the target harmonic voltage.

[0085] like Figure 5 As shown, the FPAG is connected to the pressure generator and the oscilloscope for communication, and the link loss compensation board is connected to the pressure generator and the oscilloscope for communication, respectively.

[0086] In some embodiments, the FPGA sends a third test signal to the pressure generator, so that the pressure generator processes the third test signal to obtain a fourth test signal, and inputs the fourth test signal to the oscilloscope through a link loss compensation board; receives the eye diagram of the fourth test signal transmitted by the oscilloscope, determines a target eye diagram voltage based on the eye diagram of the fourth test signal, so that the pressure generator processes the third test signal based on the target eye diagram voltage to obtain a fifth test signal that meets preset conditions; wherein, the preset conditions include the worst signal quality that can be transmitted under the eye diagram template conditions.

[0087] In some embodiments, the FPGA receives the eye diagram of the fifth test signal transmitted by the oscilloscope, determines the target harmonic voltage based on the eye diagram of the fifth test signal, and enables the pressure generator to process the fifth test signal based on the target harmonic voltage to obtain a sixth test signal that meets preset conditions. The corresponding target eye diagram voltage and target harmonic voltage are then stored in the FPGA's memory.

[0088] In practice, the FPGA sends a third test signal (PRBS7 pattern) to the AFG via Ethernet. The pressure generator converts the first test signal into a fourth test signal (PRBS7 waveform) with a preset voltage and frequency. After the link loss compensation board compensates for the loss, an eye diagram test is performed using an oscilloscope. The eye diagram template is the SSD controller's NAND Read template. Since the pressure generator can only support one of the host computer communication interfaces, ETH or USB, and cannot use both interfaces simultaneously, the oscilloscope feeds back the eye diagram analysis to the FPGA. The FPGA then controls the pressure generator to adjust the PRBS7 waveform voltage until the oscilloscope analyzes and records the amplitude corresponding to the target eye diagram voltage. Based on the amplitude corresponding to the target eye diagram voltage, a fifth test signal is generated. The FPGA controls the pressure generator to couple the harmonic noise of this frequency, gradually increasing the harmonic amplitude until the highest harmonic noise required by the eye diagram is met. The target eye diagram voltage and the target harmonic noise voltage of the sixth test signal (PRBS7 waveform) are recorded, and this coupled signal is used as the bit error rate test signal.

[0089] Figure 6 A schematic diagram of a fifth alternative architecture for determining bit error rate provided in an embodiment of this disclosure is shown, and will be described in terms of each part.

[0090] like Figure 6 As shown, the bit error rate determination architecture includes a controller, a first test fixture board, a second test fixture board, a link loss compensation board, a stress generator, and an FPGA. It is used to test at least one NAND channel link on the controller.

[0091] In some embodiments, the first test fixture board and the second test fixture board each include n data input / output interfaces; the read interface or write interface on the controller corresponds to the n data input / output interfaces; the n data input interfaces corresponding to the read interface on the controller are connected to the n data input / output interfaces of the first test fixture board via coaxial cables; the n data input interfaces corresponding to the write interface on the controller are connected to the n data input / output interfaces of the second test fixture board via coaxial cables.

[0092] In some embodiments, the controller includes multiple read interfaces and multiple write interfaces. Different NAND channel links on the controller can be tested by changing the connection relationship between the n data input / output interfaces corresponding to the read interfaces or write interfaces and the first test fixture board or the second test fixture board.

[0093] like Figure 3 As shown, the controller includes 16 NAND channel links, namely CHANNEL0 to CHANNEL15; each NAND channel link corresponds to an interface, which is defined as a read interface or a write interface depending on the architecture used to determine the bit error rate. For example, CHANNEL0 is a write interface and CHANNEL1 is a read interface. During testing, the interface to be tested is connected to the first test fixture board or the second test fixture board via a coaxial cable.

[0094] Specifically, if the interfaces to be tested are CHANNEL0 and CHANNEL1, the read interface corresponding to CHANNEL0 has 8 data input / output interfaces. Use a coaxial cable to connect the 8 data input / output interfaces corresponding to the read interface of CHANNEL0 to the 8 data input / output interfaces of the first test fixture board; use a coaxial cable to connect the 8 data input / output interfaces corresponding to the write interface of CHANNEL1 to the 8 data input / output interfaces of the second test fixture board.

[0095] After testing CHANNEL0 and CHANNEL1, the connection between CHANNEL0 and the first test fixture board, as well as the connection between CHANNEL1 and the second test fixture board, can be disconnected. Use a coaxial cable to connect the channel interface of the next set of channels to be tested to the first and second test fixture boards.

[0096] The principle and steps for testing any group of channels are the same. Taking the testing of CHANNEL0 and CHANNEL1 as an example, this will be explained.

[0097] refer to Figure 5 Determine the target eye diagram voltage and the target harmonic voltage.

[0098] In some embodiments, the FPGA emulates the first NAND flash memory and the second NAND flash memory; the controller In some embodiments, the FPGA’s Ethernet interface (ETH) sends a first test signal to the pressure generator through a first channel. The first test signal can be a PRBS7 code, i.e., a 7th-order pseudo-random binary sequence.

[0099] The pressure generator converts the PRBS7 code pattern into a PRBS7 waveform according to a preset frequency and couples the second, third, and fifth harmonics of that frequency. The PRBS7 waveform is adjusted based on the target eye diagram voltage, and the second, third, and fifth harmonics are adjusted based on the target harmonic voltage. The adjusted signals are coupled to obtain a second test signal, which is then transmitted to the link loss compensation board through the first channel.

[0100] The link loss compensation board simulates link loss. The second test signal is limited by the first test fixture board and then sent to the CHANNEL1 interface (data IO interface) of the controller NAND PHY. After receiving the second test signal, the CHANNEL1 interface writes the second test signal into the buffer register corresponding to the write interface of CHANNEL0, and then sends it back to the second channel data interface of the FPGA through the write interface of CHANNEL0 and the second channel. The FPGA compares the bits of the first test signal and the second test signal, and the error counter accumulates the number of errors.

[0101] In some embodiments, the characteristic impedance of the FPGA, pressure generator, link loss compensation board, first test fixture board, controller, and second test fixture board is 50Ω to reduce reflection effects. Two sets of NAND PHY bit error rate test interfaces, CHANNEL0 and CHANNEL1, are designed using a high-performance FPGA. Channel0 includes a second channel data interface (Data IO) and a second channel control interface (Control IO), while Channel1 includes a first channel control interface (Control IO) and an Ethernet interface (ETH AFG). Because bit error rate testing focuses on Data and has low requirements for Control IO signal quality, in this embodiment, the corresponding interfaces on the test fixture board used for transmitting drive signals are fixed by soldering. The interfaces on the test fixture board used for transmitting input and output data are connected using MMPX coaxial cables for easy replacement of test channels.

[0102] The interfaces on the test fixture board are as follows Figure 4 As shown, DQ0~DQ7 are eight data input / output interfaces. DQS is the DQ sampling reference clock, and RE is the read enable signal with a specific phase relationship to DQS. These signals have high signal quality requirements and are all connected using MMPX RF interfaces. The test fixture board is widely used in high-frequency SI testing environments and can support high-frequency signals up to 50GHz. The remaining CE, WE, CLE, and ALE command lines have lower signal quality requirements and are soldered to SMA configurations.

[0103] Since the structural dimensions of common 2.5-inch and E3 SSDs are clearly defined, the link length of the NAND channel mounted by the controller will not exceed a certain empirical value. The NAND PCB Trace Length of the farthest SSD trace is read as the standard value for testing the link length. If the test channel does not reach this standard value, it is compensated by an external link loss compensation board.

[0104] Figure 7 A schematic diagram of a first optional process for determining the bit error rate provided in an embodiment of this disclosure is shown, and the steps will be described accordingly.

[0105] In step S101, the FPGA sends a first test signal to the pressure generator based on the first channel.

[0106] In some embodiments, the FPGA emulates a first NAND flash memory chip and a second NAND flash memory chip. The controller transmits a first drive signal to the FPGA's first channel control interface based on a first test fixture board to drive the FPGA to emulate the first NAND flash memory chip; the controller also transmits a second drive signal to the FPGA's second channel control interface based on a second test fixture board to drive the FPGA to emulate the second NAND flash memory chip.

[0107] In some embodiments, the pressure generator determines the pressure eye parameters.

[0108] In some embodiments, the FPGA sends a first test signal to the pressure generator via an Ethernet interface, so that the pressure generator processes the test signal based on pressure eye parameters to obtain a second test signal, and transmits the second test signal to the first test fixture board via the link loss compensation board based on the first channel.

[0109] In step S102, the controller receives the second test signal transmitted from the first test fixture board based on the first channel, and transmits the second test signal to the FPGA based on the second channel.

[0110] In some embodiments, the controller receives a second test signal and parses the PRBS7 code pattern of the second test signal.

[0111] In some embodiments, the first channel and the second channel in the controller form a loop. The controller stores the PRBS7 code received by the first channel into the memory corresponding to the second channel, and transmits it to the FPGA through the second test fixture board via the interface corresponding to the second channel.

[0112] In step S103, the FPGA determines the bit error rate based on the first test signal and the second test signal received from the second channel.

[0113] In some embodiments, the FPGA compares the first test signal and the second test signal to determine the number of bits with different values ​​in the first test signal and the second test signal, and determines the bit error rate based on the number of bits with different values ​​and the total number of bits in the first test signal.

[0114] Figure 8 A second alternative flowchart of the bit error rate determination method provided in this disclosure embodiment is shown, and the steps will be described accordingly.

[0115] In step S201, the FPGA sends a third test signal to the pressure generator.

[0116] In step S202, the pressure generator processes the third test signal based on the first eye diagram voltage to obtain the fourth test signal.

[0117] In some embodiments, the first eye voltage can be any eye voltage.

[0118] Step S203: Receive the eye diagram of the fourth test signal transmitted by the oscilloscope, and determine the target eye diagram voltage based on the eye diagram of the fourth test signal.

[0119] In some embodiments, the fourth test signal is input to the FPGA after passing through the link loss compensation board and the oscilloscope.

[0120] The FPGA controls the pressure generator to adjust the first eye diagram voltage until the waveform output by the oscilloscope is the minimum eye diagram, then the current eye diagram voltage is determined to be the first eye diagram voltage.

[0121] In step S204, the FPGA sends the seventh test signal to the pressure generator.

[0122] In step S205, the pressure generator determines the fifth test signal based on the target eye diagram voltage and the first harmonic voltage.

[0123] In some embodiments, the first harmonic voltage can be any harmonic voltage; the pressure generator processes the seventh test signal based on the target eye diagram voltage and the first harmonic voltage to obtain the fifth test signal.

[0124] Step S206: Receive the eye diagram of the fifth test signal transmitted by the oscilloscope, and determine the target harmonic voltage based on the eye diagram of the fifth test signal.

[0125] In some embodiments, the fifth test signal is input to the FPGA after passing through the link loss compensation board and the oscilloscope.

[0126] The FPGA controls the pressure generator to adjust the first harmonic voltage until the waveform output by the oscilloscope is the minimum eye diagram, then the current eye diagram voltage is determined to be the target harmonic voltage.

[0127] The target eye diagram voltage and the target harmonic voltage are pressure eye parameters.

Claims

1. A bit error rate determination architecture, characterized in that, The architecture includes: a field-programmable gate array (FPGA), a pressure generator, a controller, a link loss compensation board, a first test fixture board, and a second test fixture board; The FPGA is communicatively connected to the second test fixture board and the pressure generator, respectively; the link loss compensation board is communicatively connected to the first test fixture board and the pressure generator, respectively; the controller is connected to the first test fixture board and the second test fixture board, respectively. The FPGA is used to send a first test signal to the pressure generator based on a first channel; so that the pressure generator processes the first test signal based on pressure eye parameters to obtain a second test signal, and transmits the second test signal to the first test fixture board through the link loss compensation board based on the first channel; The controller is configured to receive a second test signal transmitted from the first test fixture board via a first channel, and transmit the second test signal to the FPGA via a second channel. The FPGA is also used to determine the bit error rate based on the first test signal and the second test signal received through the second channel.

2. The architecture according to claim 1, characterized in that, The FPGA is also used to simulate a first non-volatile flash memory NAND chip, and to send a first test signal to the controller through a first channel when the controller performs a read operation. The FPGA is also used to simulate a second NAND flash chip, and to receive the second test signal through a second channel when the controller performs a write operation.

3. The architecture according to claim 2, characterized in that, The FPGA is also communicatively connected to the first test fixture board; the controller, the first test fixture board, and the second test fixture board are all mounted on a printed circuit board. The controller is also configured to transmit a first drive signal to the FPGA via the first test fixture board, so that the FPGA can simulate the first NAND chip based on the first drive signal; The controller is also configured to transmit a second drive signal to the FPGA via the second test fixture board, so that the FPGA can simulate a second NAND chip based on the second drive signal.

4. The architecture according to claim 3, characterized in that, The FPGA includes a first channel control interface, an Ethernet interface, a second channel control interface, and a second channel data interface. The first channel control interface is used to receive the first drive signal transmitted by the controller; The Ethernet interface is used to send a first test signal to the generator; The second channel control interface is used to receive the second drive signal transmitted by the controller; The second channel data interface is used to receive the second test signal transmitted by the controller based on the second channel.

5. The architecture according to claim 1, characterized in that, The controller includes at least one set of channel interfaces, and each set of channel interfaces includes at least a read interface and a write interface; The read interface is used to receive test data sent by the first test fixture board; The write interface is used to send test data to the second test fixture board; The read interface and the write interface correspond to different channels.

6. The architecture according to claim 5, characterized in that, The controller is specifically used for: The second test data transmitted through the first channel is received based on the read interface; Write the first test data into the memory corresponding to the second channel; The second test data is obtained from the memory corresponding to the second channel through the write interface, and then sent to the second channel data interface of the FPGA through the second channel.

7. The architecture according to claim 1, characterized in that, The first test fixture board includes n data input / output interfaces, a sampling reference clock interface, a read enable signal interface, a chip select signal interface, a write enable interface, a command latch enable interface, and an address latch enable interface; The interface for sampling the reference clock signal on the controller is connected to the corresponding sampling reference clock interface on the first test fixture board via a coaxial cable. The interface for reading the enable signal on the controller is connected to the corresponding interface for reading the enable signal on the first test fixture board via a coaxial cable.

8. The architecture according to claim 7, characterized in that, Each read interface on the controller corresponds to n data input / output signals; Each data input / output signal of the read interface is connected to the corresponding data input / output interface on the second test fixture board via a coaxial cable.

9. The architecture according to claim 1, characterized in that, The second test fixture board includes n data input / output interfaces, a sampling reference clock interface, a write enable signal interface, a chip select signal interface, a read enable interface, a command latch enable interface, and an address latch enable interface; The interface for sampling the reference clock signal on the controller is connected to the corresponding sampling reference clock interface on the second test fixture board via a coaxial cable. The write enable signal interface on the controller is connected to the corresponding write enable signal interface on the second test fixture board via a coaxial cable.

10. The architecture according to claim 9, characterized in that, Any write interface on the controller corresponds to n data input / output signals; Each data input / output signal of the write interface is connected to the corresponding data input / output interface on the second test fixture board via a coaxial cable.

11. The architecture according to claim 1, characterized in that, The pressure eye parameters include the target eye diagram voltage and the target harmonic voltage; the FPGA can also be physically connected to the link loss compensation board via an oscilloscope; the FPGA is also used for: A third test signal is sent to the pressure generator so that the pressure generator processes the third test signal to obtain a fourth test signal, and the fourth test signal is input to the oscilloscope through the link loss compensation board; The eye diagram of the fourth test signal transmitted by the oscilloscope is received, and a target eye diagram voltage is determined based on the eye diagram of the fourth test signal, so that the pressure generator processes the third test signal based on the target eye diagram voltage to obtain a fifth test signal that meets the preset conditions. The preset conditions include the worst signal quality that can be transmitted under the eye diagram template conditions.

12. The architecture according to claim 11, characterized in that, The FPGA is also used for: The eye diagram of the fifth test signal transmitted by the oscilloscope is received, and a target harmonic voltage is determined based on the eye diagram of the fifth test signal, so that the pressure generator processes the fifth test signal based on the target harmonic voltage to obtain a sixth test signal that meets preset conditions.

13. The architecture according to claim 11, characterized in that, The pressure generator is specifically used for: Receive pressure eye parameters; The second, third, and fifth harmonics corresponding to the first test signal are determined based on the pressure eye parameters. The second test signal is determined based on the first test signal and the second, third, and fifth harmonics corresponding to the first test signal.

14. The architecture according to claim 1, characterized in that, The characteristic impedance of the link loss compensation board is 50 ohms.

15. A method for determining bit error rate, characterized in that, The method includes: The FPGA sends a first test signal to the pressure generator based on the first channel; so that the pressure generator processes the test signal based on the pressure eye parameters to obtain a second test signal, and transmits the second test signal to the first test fixture board through the link loss compensation board based on the first channel; The controller receives the second test signal transmitted from the first test fixture board based on the first channel, and transmits the second test signal to the FPGA based on the second channel; The FPGA determines the bit error rate based on the first test signal and the second test signal received from the second channel.

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