MOSFET parallel connection method and circuit for high-voltage cascade energy storage system

Abstract

This application discloses a method and circuit for parallel connection of MOSFETs in a high-voltage cascaded energy storage system. The method includes establishing at least one drive loop connected to a target drive control chip; constructing a single-phase full-bridge inverter circuit with multiple MOSFETs connected in parallel; and realizing drive control of the multiple parallel MOSFETs through the at least one drive loop. By optimizing the layout to reduce stray parameters, optimizing the drive configuration circuit layout, optimizing the current-carrying loop layout, and optimizing the heat dissipation layout, this application enables multiple MOSFETs to be connected in parallel with a single drive loop.

Description

Technical Field

[0001] This application relates to the field of high-voltage cascaded energy storage system technology, and in particular to a MOSFET parallel connection method and circuit for a high-voltage cascaded energy storage system. Background Technology

[0002] With the continuous development of new energy technologies, the penetration rate of high-voltage cascaded energy storage in the power grid is increasing, and power electronic devices are an indispensable part of energy storage inverters. High-voltage cascaded energy storage connects multiple low-voltage energy storage units (PCs) in series to form a chain structure, allowing direct connection to the power grid system, thus saving the step-up transformer required by traditional energy storage systems. Furthermore, the more energy storage units (PCs) connected in series in the chain structure, the closer the system output waveform is to a sine wave, and the smaller the total harmonic distortion (THD). However, high-voltage cascaded energy storage also has its limitations, mainly reflected in the following aspects:

[0003] (1) The energy storage unit PC of high voltage cascaded energy storage is usually configured with a single-phase full-bridge inverter circuit. Compared with the three-level H-bridge inverter circuit used in conventional string energy storage, its DC bus voltage fluctuation is greater, and the power device needs to bear the entire DC bus voltage when it is turned off, which places higher demands on the withstand voltage of the power device.

[0004] (2) IGBTs are often used in high-voltage cascaded energy storage because of their high withstand voltage and high current carrying capacity. However, since the single-phase full-bridge inverter circuit used in high-voltage cascaded energy storage requires the power devices to withstand the entire DC bus voltage, the withstand voltage capability of IGBTs is required to be high. At the same time, MOSFETs are not commonly used in high-voltage cascaded energy storage because of their lower withstand voltage. Summary of the Invention

[0005] This application provides a method and circuit for parallel connection of MOSFETs in a high-voltage cascaded energy storage system to achieve the design and operation of 8 parallel MOSFETs.

[0006] The embodiments of this application adopt the following technical solutions:

[0007] In a first aspect, embodiments of this application provide a method for parallel connection of MOSFETs in a high-voltage cascaded energy storage system, characterized in that the method includes:

[0008] Establish at least one drive loop connected to the target drive control chip;

[0009] A single-phase full-bridge inverter circuit with multiple MOSFETs connected in parallel is constructed, and the drive control of the multiple parallel MOSFETs is realized through the at least one drive circuit.

[0010] In some embodiments, establishing at least one drive loop connected to the target drive control chip includes:

[0011] The busbar board is designed using a grouping and segmentation, symmetrical arrangement, and copper component busbar design.

[0012] The grouping and segmentation includes: dividing the 8 TO packaged single MOSFETs into 2 groups of 4 in parallel, each group is arranged in a square, the square area is the current carrying area, and a current-carrying copper stud is set in the center of the current carrying area to collect the current of the group and conduct it to the capacitor plate;

[0013] The symmetrical arrangement includes: adopting a symmetrical layout of upper bridge, lower bridge, lower bridge and upper bridge in the entire bus board, so that the stray inductance of the MOSFET commutation circuit tends to be consistent;

[0014] The copper busbar includes: any upper or lower arm of the single-phase full-bridge inverter circuit is composed of a single 4-in-1 parallel group, and the upper and lower arms are connected by soldered copper terminals; the two groups of arms are connected by connecting copper busbars and soldered copper terminals, ultimately forming an 8-in-1 parallel structure.

[0015] In some embodiments, establishing at least one drive loop connected to the target drive control chip includes:

[0016] The drain (D) and source (S) of the MOSFET are arranged in a square configuration, with a current-conducting copper stud in the center to ensure that the stray inductance of each commutation circuit is consistent.

[0017] At the same time, shortening the spacing between MOSFETs in each parallel group reduces the area of ​​the square current-carrying region and shortens the PCB current-carrying path.

[0018] In some embodiments, the construction of a single-phase full-bridge inverter circuit with multiple MOSFETs connected in parallel, and the driving control of the multiple parallel MOSFETs through the at least one drive circuit, includes:

[0019] By meticulously designing the drive signal lines and configuration circuits, the drive parameters and operating timing of the eight MOSFETs are ensured to be consistent.

[0020] The drive signal lines include: a shared source-S drive signal line, which increases the copper area to reduce wiring impedance and makes the gate-G reference potential of each MOSFET consistent; and independent equal-length gate high voltage GH / gate low voltage GL drive signal lines to ensure that the impedance of each MOSFET drive signal line is consistent.

[0021] The configuration circuit includes: independently configured drive configuration circuits for the turn-on resistor, turn-off resistor, and absorption capacitor, which are arranged close to the MOSFET gate pin to reduce the influence of stray parameters in the PCB drive wiring.

[0022] In some embodiments, the construction of a single-phase full-bridge inverter circuit with multiple MOSFETs connected in parallel, and the driving control of the multiple parallel MOSFETs through the at least one drive circuit, includes:

[0023] The capacitor board and busbar board are stacked on top of each other, and the DC positive busbar or DC negative busbar is arranged on the front and back sides of the capacitor board respectively.

[0024] Built-in capacitor discharge resistor and capacitor voltage equalization resistor;

[0025] The current-conducting copper studs on the busbar are connected in parallel to form a complete 8-parallel MOSFET structure from two independent 4-parallel groups.

[0026] In some embodiments, the method further includes: improving the timing consistency of MOSFET operation and optimizing the dynamic parameter balance of MOSFET.

[0027] In some embodiments, the method further includes: dispersing the concentrated current-carrying region into multiple square current-carrying regions by symmetrically arranging the eight parallel MOSFETs in groups.

[0028] In some embodiments, the method further includes: after dispersing the concentrated current-carrying region into multiple square current-carrying regions, increasing the selection of current-carrying devices while dispersing the heat dissipation of the busbar to each square current-carrying region.

[0029] In some embodiments, the method further includes: using a TO-247 packaged single-transistor MOSFET for multiple parallel connections.

[0030] Secondly, embodiments of this application also provide a MOSFET parallel circuit for a high-voltage cascaded energy storage system, employing the method described in the first aspect.

[0031] The at least one technical solution adopted in the embodiments of this application can achieve the following beneficial effects: establishing at least one drive circuit connected to the target drive control chip; constructing a single-phase full-bridge inverter circuit with multiple MOSFETs connected in parallel, and realizing drive control of multiple parallel MOSFETs through the at least one drive circuit. Through the above methods, the layout is optimized to reduce stray parameters, and the layout of the drive configuration circuit and current-carrying circuit are optimized.

[0032] By using the above methods, the layout of the drive configuration circuit is optimized, thereby ensuring the consistency of MOSFET operation timing.

[0033] By using the above methods, the current-carrying circuit layout is optimized, thereby optimizing the dynamic parameters of the MOSFET during operation and improving the operational stability of the MOSFET.

[0034] By optimizing the heat dissipation layout through the above method, the 8 parallel MOSFETs are rationally divided and symmetrically grouped, and the area that was originally concentrated on the busbar is evenly distributed to multiple square current-carrying areas. At the same time, the current is collected and output after using devices such as connecting copper busbars and current-conducting copper studs. This design allows for more flexible selection of current-carrying devices (such as soldered copper terminals and current-conducting copper studs), and also allows the heat of the busbar to be distributed to each square current-carrying area, avoiding the problem of PCB board damage caused by heat accumulation in a single area. Attached Figure Description

[0035] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0036] Figure 1 This is a schematic diagram of a MOSFET parallel design scheme in related technologies;

[0037] Figure 2 This is a schematic flowchart of the MOSFET parallel connection method for a high-voltage cascaded energy storage system in an embodiment of this application.

[0038] Figure 3 This is a schematic diagram of multiple MOSFET parallel connection schemes in the MOSFET parallel connection method of the high-voltage cascaded energy storage system in the embodiments of this application;

[0039] Figure 4 This is a schematic diagram of the simplified design scheme of the bus plate and capacitor plate in the MOSFET parallel connection method of the high-voltage cascaded energy storage system in the embodiments of this application.

[0040] Figure 5 This is a schematic diagram of the left bridge arm circuit of the parallel MOSFET single-phase full-bridge inverter circuit in the MOSFET parallel connection method of the high-voltage cascaded energy storage system in the embodiments of this application.

[0041] Figure 6 This is a schematic diagram of the drive signal line routing within the parallel group in the MOSFET parallel connection method of the high-voltage cascaded energy storage system in the embodiments of this application;

[0042] Figure 7 This is a schematic diagram of the square current-carrying region layout design of the parallel group in the MOSFET parallel connection method of the high-voltage cascaded energy storage system in this application embodiment;

[0043] Figure 8 This is a schematic diagram of the upper and lower bridge circuit distribution of the left and right bridge arms of the busbar in the MOSFET parallel connection method of the high-voltage cascaded energy storage system in this application embodiment. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0045] The application of MOSFETs in the energy storage industry is mainly concentrated in commercial products such as electric vehicle charging piles, portable energy storage devices, and mobile phone chargers, and the number of parallel connections in these applications typically does not exceed four. To meet the demand for higher power MOSFET applications, the following two methods are commonly used:

[0046] One implementation method is to use a driver chip to control multiple drive loops, with each drive loop driving four parallel MOSFETs; then, multiple sets of parallel MOSFET circuits are further parallelized to achieve the parallel connection of multiple MOSFETs.

[0047] Another approach is to use a three-level H-bridge inverter topology to increase the system's withstand DC voltage. This reduces the MOSFET's on-current requirement while keeping the system output power constant, thereby indirectly improving the MOSFET's power output capability.

[0048] Finally, select MOSFETs made of special materials with higher voltage tolerance and stronger current conduction capability, such as SiCMOSFETs and GaN MOSFETs.

[0049] like Figure 1 As shown, current parallel (4 or more) MOSFET designs have the following shortcomings:

[0050] (1) When most MOSFETs are connected in parallel, conventional PCB components cannot meet their current carrying requirements;

[0051] (2) When most MOSFETs are connected in parallel, the difference in their drive circuits leads to inconsistent MOSFET operating timing, which in turn reduces the current sharing capability of the MOSFETs in parallel and greatly affects the power density of the MOSFETs.

[0052] (3) When most MOSFETs are connected in parallel, there are significant differences between the commutation circuits of MOSFETs at different locations, which affects their stray parameters and leads to poor dynamic parameters (peak voltage, turn-off time, etc.) of the MOSFETs.

[0053] The technical solutions provided by the various embodiments of this application are described in detail below with reference to the accompanying drawings.

[0054] This application provides a method for parallel connection of MOSFETs in a high-voltage cascaded energy storage system, such as... Figure 1 The diagram shows a flowchart of a MOSFET parallel connection method for a high-voltage cascaded energy storage system according to an embodiment of this application. The method includes at least the following steps S210 to S220:

[0055] Most parallel MOSFET technology solutions are based on the core design idea of ​​rationally dividing multiple parallel MOSFETs, converging current through devices such as current-carrying copper studs and soldered copper terminals, and finally achieving the parallel connection of multiple MOSFETs through the cooperation of the bus plate and capacitor plate.

[0056] Step S210: Establish at least one drive loop connected to the target drive control chip.

[0057] like Figure 2 As shown, the drive circuit connected to the target drive control chip is established. The drive circuit and the bus board structure are optimized through design. Specifically, when establishing the drive circuit connected to the target drive control chip, the bus board is designed with grouping, symmetrical arrangement and copper component busbars.

[0058] In some embodiments, group segmentation is employed:

[0059] The eight TO-packaged single MOSFETs are divided into two groups of four in parallel, each group arranged in a square. The square area is the current-carrying area. A current-carrying copper stud is set in the center of the current-carrying area to collect the current of the group and conduct it to the capacitor plate, so as to achieve current concentration and unified path.

[0060] In some embodiments, a symmetrical arrangement is adopted:

[0061] The busbar adopts a symmetrical layout of upper bridge, lower bridge, lower bridge and upper bridge, so that the electrical length and magnetic circuit length of the MOSFET commutation circuit tend to be consistent, thereby making the stray inductance of each parallel branch tend to be consistent, reducing switching spikes and oscillations.

[0062] In some embodiments, copper busbars are used:

[0063] Any upper or lower arm of a single-phase full-bridge inverter circuit is composed of a single 4-in-1 parallel group; the upper and lower arms are connected by soldered copper terminals; the two groups of arms are connected by connecting copper busbars and soldered copper terminals, ultimately forming an 8-in-1 parallel structure, reducing on-resistance and bus impedance.

[0064] Furthermore, based on the layout of the drain (D) and source (S) of the MOSFETs, each of the 4 parallel groups adopts a square arrangement with a central current-carrying copper stud to ensure consistent stray inductance in each commutation circuit. At the same time, the spacing between the MOSFETs in each parallel group is shortened, reducing the area of ​​the square current-carrying region and shortening the PCB current-carrying path, further reducing stray inductance and conduction losses.

[0065] Step S220: Construct a single-phase full-bridge inverter circuit with multiple MOSFETs connected in parallel, and realize the drive control of multiple parallel MOSFETs through the at least one drive circuit.

[0066] Based on the construction and drive control of a single-phase full-bridge inverter circuit, a single-phase full-bridge inverter circuit with multiple MOSFETs connected in parallel was constructed, and the drive control of multiple parallel MOSFETs was realized through a drive loop. Through meticulous design of the drive signal lines and configuration circuits, the drive parameters and operating timing of the eight MOSFETs were ensured to be consistent.

[0067] In some embodiments, a drive signal line design is employed:

[0068] The source and S-pole drive signal lines are shared, and the copper area is increased to reduce wiring impedance, so that the gate and G-pole reference potentials of each MOSFET are consistent.

[0069] The gate high voltage (GH) and gate low voltage (GL) drive signal lines are arranged independently with equal lengths to ensure that the impedance of each MOSFET drive signal line is consistent and to avoid inconsistent drive delays due to differences in line length.

[0070] In some embodiments, a configuration circuit design is employed:

[0071] The turn-on resistor, turn-off resistor, and absorption capacitor are configured independently and arranged close to the MOSFET gate pin to reduce loop area, reduce the influence of stray parameters in PCB drive wiring, and improve the consistency of switching action.

[0072] Through the above steps, overall optimization of drive consistency, current balance, and stray inductance consistency is achieved when multiple transistors are connected in parallel. Based on a single-phase H-bridge inverter topology, compared to a three-level circuit design, the single-phase full-bridge inverter circuit used in this invention significantly simplifies the modulation logic of the inverter circuit, resulting in simpler and more efficient control logic.

[0073] In one embodiment of this application, establishing at least one drive circuit connected to the target drive control chip includes: designing a busbar using a grouping, symmetrical arrangement, and copper busbar configuration; the grouping includes: dividing eight TO-packaged single-transistor MOSFETs into two groups of four in parallel, each group arranged in a square, with the square area being the current-carrying area, and a current-conducting copper stud placed at the center of the current-carrying area to collect the current of the group and conduct it to the capacitor board; the symmetrical arrangement includes: adopting a symmetrical layout of upper bridge, lower bridge, lower bridge, and upper bridge in the overall busbar configuration to make the stray inductance of the MOSFET commutation circuit tend to be consistent; the copper busbar configuration includes: any upper or lower bridge arm of the single-phase full-bridge inverter circuit is composed of a single group of four in parallel, and the upper and lower bridge arms are connected by soldering copper terminals; the two groups of bridge arms are connected by connecting copper busbars and soldering copper terminals to finally form an eight-parallel structure.

[0074] like Figure 3 As shown, a busbar board and a capacitor board are designed separately, stacked one on top of the other, with current-carrying copper studs used for support in the middle. The design of the current-carrying busbar board involves implementing a parallel design of 8 MOSFETs on this board to form a complete single-phase full-bridge inverter circuit. Figure 4 As shown, the specific design scheme is as follows:

[0075] (1) Divide the eight single-tube MOSFETs packaged as TO-247 into two groups and arrange them on the bus board. Each group of four MOSFETs forms a four-parallel group and is arranged in a square. The square area is the current-carrying area. A conductive copper stud is set in the square area to collect the current of the four-parallel group and conduct it to the capacitor board.

[0076] (2) The upper or lower bridge of any bridge arm in the single-phase full-bridge inverter circuit can be formed by any of the above 4 parallel groups, and the upper bridge circuit and the lower bridge circuit are connected by soldered copper terminals.

[0077] The two sets of bridge arms mentioned above can be connected using connecting copper busbars and soldered copper terminals to ultimately form a parallel design of 8 MOSFETs. Using 8 parallel single-transistor MOSFETs to construct a single-phase full-bridge inverter circuit can greatly reduce the size of high-power MOSFET inverters, achieving greater power output without increasing the DC voltage, thus resulting in higher power density.

[0078] In one embodiment of this application, establishing at least one drive circuit connected to the target drive control chip includes: arranging the drain (D) and source (S) of the MOSFETs, with each 4-parallel group arranged in a square, and a current-conducting copper stud set in the center to make the stray inductance of each commutation circuit consistent; at the same time, shortening the spacing between the MOSFETs in each parallel group, reducing the area of ​​the square current-carrying region, and shortening the PCB current-carrying path.

[0079] like Figure 5 As shown, in most parallel designs of single-MOSFETs, the wiring design of the drive circuit must be considered. A good drive circuit wiring design can ensure that the operating timing of each parallel MOSFET is consistent, reducing the problem of uneven current distribution among MOSFETs in the case of multiple parallel connections. The drive layout scheme in the embodiment of this application is as follows:

[0080] The S-pole drive signal line is shared to increase the copper coverage area of ​​the S-pole drive signal line, minimize the wiring impedance, and make the S-pole drive signal impedance value as consistent as possible at different locations, thereby making the gate reference potential of each MOSFET consistent.

[0081] The GH / GL drive signal lines are used independently by their respective MOSFETs, and the GH / GL drive signal lines at different positions are arranged with equal lengths, so that the impedance of the drive signal line of each MOSFET is as consistent as possible. This ensures that the drive parameters and drive signal timing of the MOSFETs at different positions are consistent, thereby maximizing the consistency of MOSFET operation.

[0082] Each MOSFET's drive configuration circuit (such as turn-on resistor, turn-off resistor, snubber capacitor, etc.) is used independently by its respective MOSFET and arranged on the bus board as close as possible to the MOSFET gate pin; this design can reduce the impact of stray parameters in PCB drive routing and make the MOSFET's operating timing consistency better.

[0083] The construction and drive control of a single-phase full-bridge inverter circuit involves building a single-phase full-bridge inverter circuit with multiple MOSFETs connected in parallel, and implementing drive control of these parallel MOSFETs through a drive loop. Specifically, this includes:

[0084] By meticulously designing the drive signal lines and configuration circuits, the drive parameters and operating timing of the eight MOSFETs are ensured to be consistent.

[0085] 1) Drive signal line design

[0086] The source and S-pole drive signal lines are shared, and the copper area is increased to reduce wiring impedance, so that the gate and G-pole reference potentials of each MOSFET are consistent.

[0087] The gate high voltage (GH) and gate low voltage (GL) drive signal lines are arranged independently with equal lengths to ensure that the impedance of each MOSFET drive signal line is consistent and to avoid inconsistent drive delays due to differences in line length.

[0088] 2) Configuration circuit design

[0089] The turn-on resistor, turn-off resistor, and absorption capacitor are configured independently and arranged close to the MOSFET gate pin to reduce loop area, reduce the influence of stray parameters in PCB drive wiring, and improve the consistency of switching action.

[0090] Using a single drive loop to drive 8 parallel MOSFETs significantly reduces the number of drive circuit components, lowers component costs, and improves MOSFET timing consistency compared to using multiple drive loops to drive MOSFETs separately and then connect them in parallel.

[0091] In one embodiment of this application, the construction of a single-phase full-bridge inverter circuit with multiple MOSFETs connected in parallel, and the driving control of the multiple parallel MOSFETs through the at least one driving circuit, includes: ensuring that the driving parameters and operating timing of the eight MOSFETs are consistent through the refined design of the driving signal lines and configuration circuits; the driving signal lines include: the source and S-terminal driving signal lines are shared, the copper area is increased to reduce the wiring impedance, and the gate (G) reference potential of each MOSFET is consistent; the gate high voltage (GH) and gate low voltage (GL) driving signal lines are arranged independently with equal lengths to ensure that the impedance of each MOSFET driving signal line is consistent; the configuration circuit includes: the driving configuration circuits of the turn-on resistor, turn-off resistor, and absorption capacitor are independently configured and arranged close to the MOSFET gate pins to reduce the influence of stray parameters in the PCB driving wiring.

[0092] like Figure 6 As shown, the PCB layout scheme in this embodiment focuses on the layout design of the MOSFET drain (D) and source (S), and its key points are as follows:

[0093] Each group consists of four MOSFETs connected in parallel, arranged in a square configuration with a current-conducting copper pillar at the center of the square area. This symmetrical arrangement helps to uniformly distribute the stray inductance of the MOSFET commutation circuit, thereby reducing losses and voltage spikes during MOSFET turn-on / turn-off. Figure 7 As shown.

[0094] The four MOSFETs in each parallel group are spaced as close together as possible to minimize the area of ​​the square region and reduce the current-carrying area on the busbar PCB. This allows the current to converge on the central conductive copper pillar, further reducing the current-carrying distance on the busbar. This design reduces busbar heat generation and prevents damage due to overheating. The overall busbar layout uses an "upper bridge-lower bridge-lower bridge-upper bridge" pattern. This symmetrical arrangement helps to equalize the stray inductance of the MOSFET commutation circuit, thereby reducing losses and voltage spikes during MOSFET turn-on / turn-off. Figure 8 As shown.

[0095] The construction and drive control of a single-phase full-bridge inverter circuit involves building a single-phase full-bridge inverter circuit with multiple MOSFETs connected in parallel, and implementing drive control of these parallel MOSFETs through a drive loop. Specifically, this includes:

[0096] By meticulously designing the drive signal lines and configuration circuits, the drive parameters and operating timing of the eight MOSFETs are ensured to be consistent.

[0097] 1) Drive signal line design

[0098] The source and S-pole drive signal lines are shared, and the copper area is increased to reduce wiring impedance, so that the gate and G-pole reference potentials of each MOSFET are consistent.

[0099] The gate high voltage (GH) and gate low voltage (GL) drive signal lines are arranged independently with equal lengths to ensure that the impedance of each MOSFET drive signal line is consistent and to avoid inconsistent drive delays due to differences in line length.

[0100] 2) Configuration circuit design

[0101] The turn-on resistor, turn-off resistor, and absorption capacitor are configured independently and arranged close to the MOSFET gate pin to reduce loop area, reduce the influence of stray parameters in PCB drive wiring, and improve the consistency of switching action.

[0102] In one embodiment of this application, the construction of a single-phase full-bridge inverter circuit with multiple MOSFETs connected in parallel, and the driving control of the multiple parallel MOSFETs through the at least one driving circuit, includes: adopting a stacked structure of capacitor plate and bus plate, arranging DC positive bus or DC negative bus on the front and back of the capacitor plate respectively; incorporating capacitor discharge resistor and capacitor voltage equalization resistor; and connecting the current-conducting copper studs of the bus plate in parallel, so that two independent 4-parallel groups form a complete 8-parallel MOSFET structure.

[0103] The core design of the capacitor board has two aspects: first, to provide DC support capacitors for the single-phase full-bridge inverter circuit; and second, to connect the current-conducting copper studs from the busbars in parallel, ultimately connecting the four independent parallel groups on the busbars into eight parallel groups, forming a complete eight-parallel MOSFET single-phase full-bridge inverter circuit. The specific capacitor board design scheme in this embodiment is as follows:

[0104] The positive and negative DC buses of a single-phase full-bridge inverter circuit are arranged on the front and back sides of the capacitor board, respectively. The positive and negative DC buses are separated by the PCB board body to form a high insulation gap. Compared with the scheme of arranging the positive and negative DC buses on the same PCB board, the capacitor board layout scheme designed in this embodiment can greatly reduce the waste of PCB board area caused by the insulation distance requirement between the positive and negative DC buses, thereby increasing the PCB copper area, reducing heat generation, and reducing costs.

[0105] The capacitor board designed in this embodiment is equipped with a capacitor discharge resistor and a capacitor voltage equalization resistor, so there is no need for an external capacitor, which effectively reduces the design complexity of the DC support capacitor scheme for the single-phase full-bridge inverter circuit and improves the utilization rate of the board.

[0106] Stacked structures and parallel integration:

[0107] When building a single-phase full-bridge inverter circuit, a stacked structure of capacitor board and busbar board is adopted:

[0108] A DC positive bus or a DC negative bus is arranged on the front and back sides of the capacitor plate, respectively.

[0109] Built-in capacitor discharge resistor and capacitor voltage equalization resistor enable safe discharge and voltage equalization of DC-side capacitors;

[0110] By connecting the current-conducting copper studs of the busbar in parallel, the two independent 4-in-4 parallel groups form a complete 8-in-8 parallel MOSFET structure, thus achieving natural and even current distribution.

[0111] In one embodiment of this application, the method further includes: improving the timing consistency of MOSFET operation and optimizing the dynamic parameter balance of MOSFET.

[0112] This method also includes: improving the timing consistency of MOSFET operation, optimizing the dynamic parameter balance of MOSFET, and reducing parallel circulating current and device stress.

[0113] In one embodiment of this application, the method further includes: dispersing the concentrated current-carrying region into multiple square current-carrying regions by symmetrically arranging the 8 parallel MOSFETs in groups.

[0114] In one embodiment of this application, the method further includes: after dispersing the concentrated current-carrying area into multiple square current-carrying areas, increasing the selection of current-carrying devices while dispersing the heat dissipation of the busbar to each square current-carrying area.

[0115] By symmetrically arranging 8 parallel MOSFETs in groups, the traditional centralized high current-carrying area is dispersed into multiple square current-carrying areas. This improves the uniformity of current distribution, increases the flexibility of current-carrying device selection, and distributes the heat dissipation of the busbar to each square current-carrying area, thereby improving the overall temperature rise distribution and enhancing the system power density and reliability.

[0116] In one embodiment of this application, the method further includes: using a TO-247 packaged single-transistor MOSFET for multiple parallel connections.

[0117] In one specific embodiment, multiple TO-247 packaged single MOSFETs are connected in parallel. Combined with the aforementioned grouping, symmetry, bus, and drive schemes, stable, reliable, and efficient parallel operation of eight MOSFETs can be achieved in a high-voltage cascaded energy storage system, meeting the requirements of high-power, high-voltage, and high-switching-frequency application scenarios. By using multiple TO-247 packaged single MOSFETs connected in parallel and utilizing vertical space with connecting copper busbars and current-conducting copper studs, the size of the MOSFET inverter can be greatly reduced, increasing power density.

[0118] This application discloses a MOSFET parallel connection method for a high-voltage cascaded energy storage system, which aims to solve the problems of uneven device stress, uneven heating and decreased reliability caused by stray inductance, inconsistent drive timing and current imbalance when multiple transistors are connected in parallel. It is especially suitable for single-phase full-bridge inverter circuits in high-voltage cascaded energy storage converters.

[0119] This application embodiment also provides a MOSFET parallel circuit for a high-voltage cascaded energy storage system, implemented using the method described above, the method comprising:

[0120] Establish at least one drive loop connected to the target drive control chip;

[0121] A single-phase full-bridge inverter circuit with multiple MOSFETs connected in parallel is constructed, and the drive control of the multiple parallel MOSFETs is realized through the at least one drive circuit.

[0122] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A MOSFET parallel connection method of a high-voltage cascade energy storage system, characterized in that, The method includes: Establish at least one drive loop connected to the target drive control chip; A single-phase full-bridge inverter circuit with multiple MOSFETs connected in parallel is constructed, and the drive control of the multiple parallel MOSFETs is realized through the at least one drive circuit.

2. The method according to claim 1, characterized in that, The establishment of at least one drive circuit connected to the target drive control chip includes: The busbar board is designed using a grouping and segmentation, symmetrical arrangement, and copper component busbar design. The grouping and segmentation includes: dividing the 8 TO packaged single MOSFETs into 2 groups of 4 in parallel, each group is arranged in a square, the square area is the current carrying area, and a current-carrying copper stud is set in the center of the current carrying area to collect the current of the group and conduct it to the capacitor plate; The symmetrical arrangement includes: adopting a symmetrical layout of upper bridge, lower bridge, lower bridge and upper bridge in the entire bus board, so that the stray inductance of the MOSFET commutation circuit tends to be consistent; The copper busbar includes: any upper or lower arm of the single-phase full-bridge inverter circuit is composed of a single 4-in-1 parallel group, and the upper and lower arms are connected by soldered copper terminals; the two groups of arms are connected by connecting copper busbars and soldered copper terminals, ultimately forming an 8-in-1 parallel structure.

3. The method according to claim 1 or 2, characterized in that, The establishment of at least one drive circuit connected to the target drive control chip includes: The drain (D) and source (S) of the MOSFET are arranged in a square configuration, with a current-conducting copper stud in the center to ensure that the stray inductance of each commutation circuit is consistent. At the same time, shortening the spacing between MOSFETs in each parallel group reduces the area of ​​the square current-carrying region and shortens the PCB current-carrying path.

4. The method according to claim 1, characterized in that, The single-phase full-bridge inverter circuit, which constructs multiple MOSFETs connected in parallel, achieves drive control of the multiple parallel MOSFETs through the at least one drive circuit, including: By meticulously designing the drive signal lines and configuration circuits, the drive parameters and operating timing of the eight MOSFETs are ensured to be consistent. The drive signal lines include: a shared source-S drive signal line, which increases the copper area to reduce wiring impedance and makes the gate-G reference potential of each MOSFET consistent; and independent equal-length gate high voltage GH / gate low voltage GL drive signal lines to ensure that the impedance of each MOSFET drive signal line is consistent. The configuration circuit includes: independently configured drive configuration circuits for the turn-on resistor, turn-off resistor, and absorption capacitor, which are arranged close to the MOSFET gate pin to reduce the influence of stray parameters in the PCB drive wiring.

5. The method according to claim 2, characterized in that, The single-phase full-bridge inverter circuit, which constructs multiple MOSFETs connected in parallel, achieves drive control of the multiple parallel MOSFETs through the at least one drive circuit, including: The capacitor board and busbar board are stacked on top of each other, and the DC positive busbar or DC negative busbar is arranged on the front and back sides of the capacitor board respectively. Built-in capacitor discharge resistor and capacitor voltage equalization resistor; The current-conducting copper studs on the busbar are connected in parallel to form a complete 8-parallel MOSFET structure from two independent 4-parallel groups.

6. The method according to claim 1, characterized in that, The method also includes: improving the timing consistency of MOSFET operation and optimizing the dynamic parameter balance of MOSFET.

7. The method according to claim 1, characterized in that, The method further includes: dispersing the concentrated current-carrying region into multiple square current-carrying regions by symmetrically arranging the 8 parallel MOSFETs in groups.

8. The method according to claim 7, characterized in that, The method further includes: after dispersing the concentrated current-carrying area into multiple square current-carrying areas, increasing the selection of current-carrying devices while dispersing the heat dissipation of the busbar to each square current-carrying area.

9. The method according to claim 1, characterized in that, The method also includes: using a TO-247 packaged single-transistor MOSFET for multiple parallel connections.

10. A MOSFET parallel circuit for a high-voltage cascaded energy storage system, characterized in that, The method described in any one of claims 1-9 shall be employed.

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