A method for efficient full-duplex communication between DSP programmable chips via SPI

Abstract

This invention discloses a method for high-efficiency full-duplex SPI communication between DSP programmable chips, relating to the technical field of chip communication. It ensures that both the master and slave devices have DSP chips and SPI transceivers as communication ports. Since the communication process is bidirectional, both the master and slave can be either the transmitter or receiver, determined by the communication direction. The master sends data to the slave to wake it up. The method includes the following steps: generating a frame of transmitter data; filling the transmitter data into the transmitter's transmit buffer and sending the filled transmitter data to the receiver; receiving receiver data; and repeating the above steps. The receiver data is generated by the receiver and filled into its transmit buffer. When the receiver data in the transmitter buffer is sent, the receiver data is immediately regenerated, effectively improving the communication efficiency and quality between the master and slave devices.

Description

Technical Field

[0001] This invention relates to the field of chip communication, and specifically to a method for high-efficiency full-duplex SPI communication between DSP programmable chips. Background Technology

[0002] From the discovery of semiconductor materials to the creation of the first semiconductor-based chip, and now to the dazzling array of chips in various devices, we marvel at the rapid advancements in technology and the ingenuity and power of chip structures. Integrated chips, in particular, achieve results far exceeding the simple sum of individual chips. This is thanks to the collaborative work between chips. The key to this collaboration lies in effective communication between them, allowing multiple chips to work together to maximize the performance of each individual chip.

[0003] Traditional communication methods use half-duplex operation, where the master chip first sends read / write commands, and then the slave chip sends or reads data through its port. This approach is increasingly out of step with current demands for fast processing and response speeds in machinery. This is mainly because traditional communication requires a delay between communication sessions. Sending a command to the slave, waiting for processing, and then reading or writing data all contribute to low communication efficiency between chips. Furthermore, due to its low efficiency, high interference during communication, and significant errors in communication quality detection, traditional methods often lack proper communication quality checks, making it difficult for users or engineers to monitor the communication status.

[0004] In conclusion, addressing the low efficiency of traditional half-duplex communication and the difficulty in quality testing of the communication method is key to improving the overall quality of chips. Summary of the Invention

[0005] To improve communication efficiency between chips and address the mismatch between existing chip-to-chip communication quality and production / consumption needs, this application proposes a method for high-efficiency full-duplex SPI communication between DSP programmable chips.

[0006] A method for high-efficiency full-duplex SPI communication between DSP programmable chips adopts the following technical solution:

[0007] A method for high-efficiency full-duplex SPI communication between DSP programmable chips is disclosed for communication between a master and a slave device. Both the master and the slave device are equipped with DSP chips and SPI transceivers as communication ports. Since the communication process is bidirectional, both the master and the slave device can be either the transmitter or the receiver, depending on the communication direction. The master device sends data to the slave device to wake it up. The method further includes the following steps:

[0008] Generate a frame of data for the sending end;

[0009] The data from the transmitting end is filled into the transmitting buffer of the transmitting end, and the filled data from the transmitting end is sent to the receiving end;

[0010] Receive data from the receiving end;

[0011] Repeat the above steps;

[0012] The receiving data is generated by the receiving end and filled into the sending buffer of the receiving end after it is generated. When the receiving data in the sending buffer of the receiving end is sent, the receiving data is immediately regenerated.

[0013] After the data from the transmitting end is sent to the receiving end, the receiving end reads the data from the transmitting end according to the receiving logic and performs verification, parsing and storage; after the transmitting end receives the data from the receiving end, it reads the data from the transmitting end according to the receiving logic and performs verification, parsing and storage.

[0014] The receiving end calculates the transmission success rate of the transmitting end after receiving data from the sending end; the transmitting end calculates the transmission success rate of the receiving end after receiving data from the receiving end.

[0015] By adopting the above technical solution, taking the host as the sender and the slave as the receiver as an example, the receiver wakes up and generates receiver data after receiving the sender's data for the first time. After receiving the receiver data, the sender regenerates the sender data and repeats the above process. After the receiver sends the receiver data, it immediately generates new receiver data and prepares to send it, avoiding gaps in the communication process, thus improving the communication efficiency between the host and the slave. At the same time, a parsing process is added. When the host and / or the slave receives the data sent by the other party, it reads and parses it, and stores the result. This can be used as a basis for calculating the success rate of the communication process and as a log file for easy reading later.

[0016] To facilitate user customization of the transmitting and / or receiving data, and to enable the host and / or slave to read and identify the transmitting and / or receiving data, both the transmitting and receiving data further include communication frames, which include:

[0017] The frame header is used to identify the start character of the transmitted frame;

[0018] Function codes are used to expand functionality based on logical requirements;

[0019] Heartbeat counting is used to count the number of communications and detect communication status.

[0020] The transceiver transmission success rate is calculated by the receiving end and is updated periodically.

[0021] Several key parameters are used for user-defined data;

[0022] Verification is used to terminate communication frames, making it easy to identify the data sent and received, and also allowing users to programmatically adjust it to meet actual communication needs.

[0023] To simplify and efficiently calculate the transceiver transmission success rate during master-slave communication, the SPI transceiver at the transmitting end includes heartbeat counts within the communication frames of the transmitted data. The SPI transceiver at the receiving end counts the number of communication frames within the received transmitted data. The receiving end obtains the transmission success rate by dividing the total number of communication frames within the transmitted data received by its SPI transceiver by the heartbeat count recorded in the last communication frame. This simplifies the transceiver transmission success rate calculation, provides rapid output, and offers intuitive results, facilitating monitoring of the communication quality between the master and slave devices and ensuring communication efficiency.

[0024] The receiving logic includes the following steps:

[0025] A1: Determine if there is data in the send buffer. If there is, execute step A11; otherwise, execute step A5.

[0026] A11: Read the transmitted data and parse the frame header;

[0027] A2: Search for the frame header. If the frame header is found, execute A21; otherwise, return to execute A1.

[0028] A21: Data reception begins with the frame header;

[0029] A3: Determine if reception is complete. If complete, execute A4; otherwise, return to execute A1.

[0030] A4: Parse the data, and return to execute A1 after parsing is complete;

[0031] A5: End communication to shorten the process of receiving data from the sending end when the host and slave are acting as receiving ends during communication and to reduce the difficulty of judgment, so as to adapt to the fast and efficient communication process.

[0032] To ensure fast and complete bidirectional communication between the master and slave devices, the sending buffer further adopts a FIFO buffer mode with a length of 16 bytes. This ensures that the generated data, whether sent or received, is in the correct order. This is an advantage of the FIFO buffer mode, which strictly follows the rule of "first-in, first-out," perfectly adapting to all scenarios that require processing data in chronological / generational order and better conforming to the conventional human / device interaction logic. Simultaneously, the FIFO buffer mode isolates the sending and receiving ends, balancing processing speeds. In specific situations, the FIFO buffer can temporarily cache excess data to prevent data loss. When the operating frequencies of the sending and receiving ends are inconsistent, the FIFO buffer allows the end with the lower operating frequency to read data on demand without waiting, improving overall efficiency. The receiving and sending ends also do not need to work synchronously, thereby reducing the coupling between modules. The 16-byte length also effectively prevents data overflow.

[0033] To ensure smooth communication between the master and slave devices, both the master and slave devices adopt an interrupt-driven operating mode, wherein the interrupt frequency of the master is less than that of the slave device, so that the master can generate data periodically. At the same time, the first data generated by the master as the sender before starting work is sent to the slave as the receiver, which can serve to wake up the slave device and thus start reliable communication between the master and slave devices.

[0034] To improve the self-testing capability of the transmitting and receiving ends after the communication frame is received, the verification adopts CRC. Since the core advantages of CRC are strong error detection capability, high computational efficiency and easy hardware implementation, the self-testing difficulty is simplified while ensuring the accuracy and speed of the self-test, and the resource performance allocation of the host and slave is optimized.

[0035] To reduce communication losses, the communication baud rate between the master and slave is further set to 4MHz, the communication data length of the master is 12 bytes, and the data of the slave is 11 bytes, so that the master and slave can communicate in a low-frequency manner, effectively reducing communication losses.

[0036] In summary, this application has at least the following beneficial effects:

[0037] 1. After the receiving end receives the data from the sending end for the first time, it wakes up and generates receiving end data. After the sending end receives the receiving end data, it regenerates sending end data and repeats the above process. After the receiving end sends the receiving end data, it immediately generates new receiving end data and prepares to send it, avoiding the interval during the communication process, which improves the communication efficiency between the master and slave. The receiving end generates new data immediately after sending data, eliminating the communication interval.

[0038] 2. The FIFO buffer mode is adopted to ensure data order, avoid data loss, balance the sending and receiving speed, and reduce module coupling. Both the master and slave are interrupt mode, and the master data can wake up the slave to achieve reliable bidirectional communication. The sending buffer is 16 bytes, which can hold most of the data and avoid data overflow.

[0039] 3. Both the transmitting and receiving ends calculate the success rate of the other party's transmission. The result is quickly obtained by comparing the heartbeat count with the number of received frames, allowing for intuitive monitoring of communication quality.

[0040] 4. The communication frame contains log-related storage data for easy subsequent traceability. The communication frame structure is standardized, including fields such as frame header, function code, and heartbeat count. It supports function expansion and key parameter customization to meet actual programming needs. It adopts CRC checksum, which has strong error detection capability, high computational efficiency, and is easy to implement in hardware. The baud rate is set to 4MHz, and the master and slave data lengths are 12 / 11 bytes respectively. A small amount of high-frequency communication reduces losses.

[0041] 5. The receiving logic steps are clear, shortening the receiving time, reducing the difficulty of judgment, and adapting to high-efficiency communication scenarios. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the structure of the host and slave devices during operation as proposed in this application;

[0043] Figure 2 This is a flowchart illustrating the sending process proposed in this application;

[0044] Figure 3 This is the receiving flowchart proposed in this application;

[0045] Figure 4 This is a time-domain diagram showing the operation of the host and slave devices as proposed in this application;

[0046] Figure 5 This is a schematic diagram of the content of the communication frame proposed in this application;

[0047] Figure 6 This is a schematic diagram of the structure of the host transmit buffer and the slave transmit buffer during operation as proposed in this application. Detailed Implementation

[0048] To further understand the content of this invention, a detailed description of the invention will be provided in conjunction with the accompanying drawings and embodiments.

[0049] Example 1

[0050] A method for high-efficiency full-duplex SPI communication between DSP programmable chips, used for communication between master and slave devices, referenced. Figure 1The master unit includes a DSP chip, an SPI transceiver, and a transmit buffer. The transmit buffer and SPI transceiver are electrically connected to the DSP chip. The slave unit has a similar structure to the master unit, containing an electrically connected transmit buffer, SPI transceiver, and DSP chip. It's important to note that both the master and slave units operate in interrupt mode, with different interrupt frequencies. Communication between the master and slave units uses the SPI protocol. (See reference...) Figure 4 In this application, the interrupt frequency of the host's DSP chip is 16kHz and the interrupt frequency of the slave is 36kHz.

[0051] Further reference Figure 1 The send buffer adopts a FIFO buffer mode, which has the following advantages: The FIFO buffer mode strictly follows the rule of "first-in, first-out", which can perfectly adapt to all scenarios that need to process data in time / generation order and is more in line with the normal interaction logic of humans / devices; At the same time, the FIFO buffer mode can isolate the sender and receiver, balance the processing speed, and in certain cases, the FIFO buffer can temporarily cache redundant data to avoid data loss. When the working frequency of the sender and receiver is inconsistent, the FIFO buffer allows the end with the lower working frequency to read data on demand without waiting, thus improving the overall efficiency; The receiver and sender do not need to work synchronously, thereby reducing the coupling between modules.

[0052] Refer again Figure 1 In this embodiment, the length of the sending buffer is 16 bytes to accommodate most communication needs.

[0053] A method for high-efficiency full-duplex SPI communication between DSP programmable chips is disclosed to achieve bidirectional communication between a master and a slave device. This method includes a transmitter and a receiver. It's important to note that the transmitter and receiver are not fixed; they are determined by the direction of each communication session. That is, when the master sends data to the slave, the master is the transmitter, and vice versa. Before the transmission process begins, the master first sends data to the slave to wake it up. (See reference...) Figure 2 With the sender as the main entity, the sending process includes the following steps:

[0054] Generate a frame of data for the sending end;

[0055] The data from the sending end is filled into the transmitting buffer at the transmitting end, and the filled data from the sending end is sent to the receiving end.

[0056] Receive data from the receiving end;

[0057] Repeat the above steps;

[0058] The receiving data is generated by the receiving end and then filled into the receiving end's transmission buffer. When the receiving data in the receiving end's transmission buffer is sent, the receiving data is immediately regenerated.

[0059] After the data from the sending end is sent to the receiving end, the receiving end reads the data from the sending end according to the receiving logic and performs verification, parsing and storage; after the sending end receives the data from the receiving end, it reads the data from the sending end according to the receiving logic and performs verification, parsing and storage.

[0060] The receiving end calculates the transmission success rate after receiving data from the sending end; the sending end calculates the transmission success rate after receiving data from the receiving end.

[0061] refer to Figure 3 The receiving process includes the following steps:

[0062] A1: Determine if there is data in the send buffer. If there is, execute step A11; otherwise, execute step A5.

[0063] A11: Read the transmitted data and parse the frame header;

[0064] A2: Search for the frame header. If the frame header is found, execute A21; otherwise, return to execute A1.

[0065] A21: Data reception begins with the frame header;

[0066] A3: Determine if reception is complete. If complete, execute A4; otherwise, return to execute A1.

[0067] A4: Parse the data, and return to execute A1 after parsing is complete;

[0068] A5: End communication.

[0069] Combination Figure 3 And refer to Figure 5 The data sent and received includes communication frames, which include:

[0070] The frame header is used to identify the start character of the transmitted frame;

[0071] Function codes are used to expand functionality based on logical requirements;

[0072] Heartbeat counting is used to count the number of communications and detect communication status.

[0073] The transceiver transmission success rate is calculated by the receiving end and is updated periodically.

[0074] Several key parameters are used for user-defined data;

[0075] Verification is used to terminate communication frames.

[0076] Verification can be performed in various ways. In order to improve the self-testing capability of the transmitting and receiving ends after the communication frame is received, and because the core advantages of CRC are strong error detection capability, high computational efficiency and easy hardware implementation, in order to simplify the self-testing difficulty and optimize the resource performance allocation of the host and slave while ensuring the accuracy and speed of self-testing, CRC is used for verification.

[0077] Combination Figure 3 , 5 And refer to Figure 6 When communication occurs between the master and slave devices, after determining the sending and receiving ends for a single communication, the success rate of the transceiver needs to be calculated. The calculation method is as follows:

[0078] The communication frames in the data sent by the SPI transceiver at the transmitting end include the number of heartbeats. The SPI transceiver at the receiving end counts the number of communication frames in the data sent by the transmitting end. The receiving end obtains the transmission success rate by dividing the total number of communication frames in the data sent by the SPI transceiver at the receiving end by the number of heartbeats recorded in the last communication frame.

[0079] Meanwhile, the communication baud rate between the master and slave is set to 4MHz, the communication data length of the master is 12 bytes, and the data of the slave is 11 bytes. Communication between the master and slave is carried out in a low-frequency manner, which effectively reduces the loss in the communication process and thus improves the success rate of the transceiver.

[0080] The present invention and its embodiments have been described above illustratively. This description is not restrictive, and the figures shown are only one embodiment of the present invention; the actual structure is not limited thereto. Therefore, if those skilled in the art are inspired by this description and design similar structures and embodiments without departing from the spirit of the present invention, such designs should fall within the protection scope of the present invention.

Claims

1. A method for high-efficiency full-duplex SPI communication between DSP programmable chips, used for communication between a master and a slave device, wherein both the master and the slave device are equipped with DSP chips and SPI transceivers as communication ports, and since the communication process is bidirectional, both the master and the slave device can be either a transmitter or a receiver, determined by the communication direction, characterized in that... The process of the host sending data to the slave to wake up the slave also includes the following steps: Generate a frame of data for the sending end; The data from the transmitting end is filled into the transmitting buffer of the transmitting end, and the filled data from the transmitting end is sent to the receiving end; Receive data from the receiving end; Repeat the above steps; The receiving data is generated by the receiving end and filled into the sending buffer of the receiving end after it is generated. When the receiving data in the sending buffer of the receiving end is sent, the receiving data is immediately regenerated. After the data from the transmitting end is sent to the receiving end, the receiving end reads the data from the transmitting end according to the receiving logic and performs verification, parsing and storage; after the transmitting end receives the data from the receiving end, it reads the data from the transmitting end according to the receiving logic and performs verification, parsing and storage. The receiving end calculates the transmission success rate of the transmitting end after receiving data from the sending end; the transmitting end calculates the transmission success rate of the receiving end after receiving data from the receiving end.

2. The method for high-efficiency full-duplex SPI communication between DSP programmable chips according to claim 1, characterized in that, Both the transmitting end data and the receiving end data include communication frames, and the communication frames include: The frame header is used to identify the start character of the transmitted frame; Function codes are used to expand functionality based on logical requirements; Heartbeat counting is used to count the number of communications and detect communication status. The transceiver transmission success rate is calculated by the receiving end and is updated periodically. Several key parameters are used for user-defined data; Verification is used to terminate communication frames.

3. The method for high-efficiency full-duplex SPI communication between DSP programmable chips according to claim 2, characterized in that, The communication frames in the data sent by the SPI transceiver at the transmitting end include the number of heartbeats. The SPI transceiver at the receiving end counts the number of communication frames in the received data. The receiving end obtains the transmission success rate by dividing the total number of communication frames in the data received by the SPI transceiver at the receiving end by the number of heartbeats recorded in the last communication frame.

4. The method for high-efficiency full-duplex SPI communication between DSP programmable chips according to claim 1, characterized in that, The receiving logic includes the following steps: A1: Determine if there is data in the send buffer. If there is, execute step A11; otherwise, execute step A5. A11: Read the transmitted data and parse the frame header; A2: Search for the frame header. If the frame header is found, execute A21; otherwise, return to execute A1. A21: Data reception begins with the frame header; A3: Determine if reception is complete. If complete, execute A4; otherwise, return to execute A1. A4: Parse the data, and return to execute A1 after parsing is complete; A5: End communication.

5. The method for high-efficiency full-duplex SPI communication between DSP programmable chips according to claim 1, characterized in that, The transmit buffer adopts the FIFO buffer mode and the length of the transmit buffer is 16 bytes.

6. The method for high-efficiency full-duplex SPI communication between DSP programmable chips according to claim 1, characterized in that, Both the host and the slave operate in interrupt mode, with the interrupt frequency of the host being lower than that of the slave.

7. The method for high-efficiency full-duplex SPI communication between DSP programmable chips according to claim 2, characterized in that, The verification uses CRC.

8. A method for high-efficiency full-duplex SPI communication between DSP programmable chips according to any one of claims 1-7, characterized in that, The communication baud rate between the master and slave is set to 4MHz, the communication data length of the master is 12 bytes, and the data of the slave is 11 bytes.

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