Modular Instrument Architecture-Based Automated Functional Testing System for Avionics Bus

Abstract

This invention relates to the field of avionics bus testing and modular instrument technology, specifically to an automated functional testing system for avionics buses based on a modular instrument architecture. The system includes a communication acquisition node, a backplane transmission channel with a first-in-first-out buffer, a low-level bus probe, a status acquisition module, a congestion quantization module, a strategy generation module, and an adaptive scheduling module. The status acquisition module acquires memory access channel occupancy, trigger synchronization clock phase jitter parameters, and system interrupt response differences. The congestion quantization module uses weighted summation to obtain the system's micro-congestion entropy index. The strategy generation module generates full-load concurrent injection, local frequency reduction, or backbone communication deterministic protection strategies based on a first risk threshold and a second limit threshold. The adaptive scheduling module uses feedback sampling to adjust control quantities, correcting the time difference between excitation transmission and response reception, and improving timing reliability in high-concurrency closed-loop testing.

Description

Technical Field

[0001] This invention relates to the field of avionics bus testing and modular instrument technology, specifically to an automated functional testing system for avionics bus based on a modular instrument architecture. Background Technology

[0002] Currently, avionics bus automated functional test systems based on modular instrument architecture typically perform stimulus delivery and response acquisition on the device under test according to a preset test rhythm. When multiple buses are injected concurrently, fault message impacts occur, or high-frequency discrete trigger feedback occurs during hardware closed-loop joint testing, existing test systems often cannot perceive and schedule the congestion status of their own backplane transmission channels, clock synchronization links, and interrupt response links in real time. Each test may still continuously send stimuli and receive responses at the original frequency, resulting in internal buffer queuing, timestamp drift, and sampling action misalignment, which reduces the time reliability of test conclusions and the accuracy of functional judgment. Summary of the Invention

[0003] The purpose of this invention is to provide an automated functional testing system for avionics bus based on a modular instrument architecture, and to solve the following technical problems: Used in high-concurrency, high-interference hardware-in-loop closed-loop testing scenarios, this system quantifies and corrects the congestion of the underlying resources of the test system in real time, avoiding excitation lag, sampling misalignment, or timestamp drift caused by congestion of the internal backplane transmission channel, thereby ensuring the timing credibility and reliability of test results of critical backbone links.

[0004] The objective of this invention can be achieved through the following technical solutions: An automated functional test system for avionics bus based on modular instrument architecture is used to test the device under test. The test system and the device under test are connected by a signal cable to form a hardware closed loop. The system includes a communication acquisition node and a backplane transmission channel with a first-in-first-out buffer space. The communication acquisition node sends test excitation signals to the device under test and receives status response data through the backplane transmission channel. The system also includes: a low-level bus probe; a status acquisition module, used to collect the current low-level transmission status data of the backplane transmission channel through the low-level bus probe; the low-level transmission status data is defined as data including memory access channel occupancy rate, phase jitter parameters of the trigger synchronization clock, and response difference at the system interrupt level; The congestion quantization module is used to perform a weighted summation of the occupancy rate, the phase jitter parameter, and the response difference based on a preset weight coefficient. The preset weight coefficient is pre-calibrated offline by the test system according to the communication deterministic sensitivity of different avionics bus protocols and stored to calculate the system micro-congestion entropy index. The system micro-congestion entropy index is a normalized value that characterizes the degree of conflict of underlying resources in the backplane transmission channel. The strategy generation module is used to compare the system micro-congestion entropy index with a first risk threshold and a larger second limit threshold to generate an adaptive degradation scheduling strategy: if the index is less than the first risk threshold, the strategy is a full-load concurrent injection mode, that is, maintaining the preset concurrent test intensity. If the indicator is not less than the first risk threshold and less than the second limit threshold, the strategy is a local frequency reduction mode; if the indicator is not less than the second limit threshold, the strategy is a backbone communication deterministic protection mode. An adaptive scheduling module is used to calculate and adjust the control quantity based on the strategy and feed it back to the communication acquisition node to correct the time difference between sending the test excitation signal and receiving the status response data.

[0005] In one possible implementation, the test system is in a hardware closed-loop loop with the device under test; In response to the device under test sending a high-frequency discrete trigger request to form a transient high-concurrency communication storm in which the number of requests per unit time exceeds a preset concurrency threshold, the underlying bus probe triggers the operation of collecting the underlying transmission status data based on the detected transient high-concurrency communication storm.

[0006] In one possible implementation, during the process of the adaptive scheduling module injecting the sampling adjustment control quantity feedback into the communication acquisition node, the communication acquisition node includes at least a core protocol node and a non-core acquisition node. In response to the adaptive degradation scheduling strategy as the backbone communication deterministic defense mode, the issuance of new test task instructions to the non-core acquisition nodes is stopped, and maintenance control is performed on the queued tasks to ensure orderly termination or cache reclamation. The available bandwidth resources within the test system are merged and redirected to the core protocol node. The priority weight of the core protocol node in the backplane transmission channel is increased to ensure that the frame drop rate of the data frame is zero and the error range of the timestamp is within the preset accuracy threshold.

[0007] In one possible implementation, the test stimulus signal includes a fault burst message. In response to the adaptive degradation scheduling strategy being a local frequency reduction mode, the frequency of sending the fault burst message to the device under test is reduced, thereby reducing resource contention caused by the fault burst message and releasing the first-in-first-out buffer space at the bottom layer of the backplane transmission channel.

[0008] In one possible implementation, the underlying bus probe is embedded in the field-programmable gate array inside the test system to determine whether the system's micro-congestion entropy index has reached a preset error trigger threshold according to a nanosecond-level detection cycle. If the system's micro-congestion entropy index is greater than or equal to the error trigger threshold, in response to reaching the error trigger threshold, an interrupt signal is sent to the main control layer of the test system to perform a timestamp resynchronization operation, thereby preventing the timestamp of the test system from drifting beyond the error range.

[0009] In one possible implementation, the test system also includes a report generation and determination module; After the adaptive scheduling module corrects the action time difference to form a stable state, the report generation and judgment module is used to perform a comprehensive functional status judgment on the device under test based on the response sequence message composed of the status response data after the timing correction is completed, and outputs the final device qualification judgment result with timing reliability mark. The timing reliability marker indicates that the response sequence messages in the process of generating the final equipment qualification result are not affected by the error accumulation caused by internal backplane transmission channel congestion.

[0010] 7. The avionics bus automated functional testing system based on modular instrument architecture according to claim 3, characterized in that the testing system is deployed in an industrial computer control chassis oriented towards high-speed component peripheral interfaces; The core protocol node includes a first-class deterministic aviation integrated bus communication protocol module with full-load virtual link scheduling, and the non-core acquisition node includes a second-class low-speed serial aviation bus protocol module for operational status monitoring and an analog discrete waveform capture module.

[0011] The beneficial effects of this invention are: 1. This invention addresses the problem that test systems cannot perceive underlying resource congestion. This system obtains backplane transmission channel status data through underlying probes, quantifies micro-congestion entropy indicators, generates adaptive degradation scheduling strategies, dynamically corrects the time difference between incentives and responses, effectively avoids cache queuing and sampling misalignment, and ensures the accuracy of closed-loop testing. 2. To address the problem of missed reports or wasted resources in constant-period polling, this invention introduces a storm-triggered detection mechanism. When the device under test experiences a transient high-concurrency communication storm, it triggers the acquisition of underlying state data. This not only captures sudden resource shortages in a timely manner but also reduces the system's computing resource consumption during stable phases, thereby improving the agility of test response. 3. In response to the problem of critical backbone damage caused by global load reduction, this invention stops non-core node instructions when under extreme congestion, merges and redirects internal bandwidth to core protocol nodes, prioritizes ensuring zero frame drop of critical data frames and high accuracy of timestamps, and ensures the reliability of core conclusions by limiting the bandwidth allocation of secondary observation channels when approaching the failure boundary. 4. This invention addresses the problem of high cache queuing caused by sudden fault impacts. Under moderate congestion risk, this system releases first-in-first-out cache space by reducing the frequency of fault-prone message delivery. Without significantly compromising test fault tolerance coverage, it prioritizes reducing aggressive injection load in exchange for overall timing stability. 5. In response to the problem that congestion worsens faster than the response of the upper-level software, this invention embeds probes into field-programmable gate arrays to identify congestion risks in nanosecond-level hardware and send interrupts to the main control layer to perform timestamp resynchronization, thus moving the instability detection point forward and blocking the continued accumulation of timestamp errors with hardware-level response delay. 6. In response to the problem of unclear boundaries in the corrected test data, this system performs a comprehensive functional judgment based on the response sequence message after completing the timing correction, and outputs the final qualification judgment result with timing reliability marking, which clarifies whether the time basis of the functional conclusion is reliable and improves the verifiability of the automated test results. Attached Figure Description

[0012] The invention will now be further described with reference to the accompanying drawings.

[0013] Figure 1 This is a schematic diagram of the modular instrument architecture-based avionics bus automated functional testing system provided in this application embodiment. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] Please see Figure 1An automated functional test system for avionics bus based on a modular instrument architecture is used to test the device under test. The test system and the device under test are connected by a signal cable to form a hardware closed loop, including a communication acquisition node and a backplane transmission channel with a first-in-first-out buffer space. The communication acquisition node sends test excitation signals to the device under test and receives status response data through the backplane transmission channel. The system also includes: a low-level bus probe; a status acquisition module, used to collect the current low-level transmission status data of the backplane transmission channel through the low-level bus probe; the low-level transmission status data is defined as data including memory access channel occupancy, phase jitter parameters of the trigger synchronization clock, and response difference at the system interrupt level; The congestion quantization module is used to perform a weighted summation of occupancy rate, phase jitter parameters, and response difference based on preset weight coefficients. The preset weight coefficients are pre-calibrated offline by the test system according to the communication deterministic sensitivity of different avionics bus protocols and stored to calculate the system micro-congestion entropy index. The system micro-congestion entropy index is a normalized value that characterizes the degree of resource conflict at the underlying layer of the backplane transmission channel. The strategy generation module is used to compare the system micro-congestion entropy index with the first risk threshold and the second limit threshold, and generate an adaptive degradation scheduling strategy: if the index is less than the first risk threshold, the strategy is the full-load concurrent injection mode, that is, to maintain the preset concurrent test intensity. If the indicator is not less than the first risk threshold and is less than the second limit threshold, the strategy is a local frequency reduction mode; if the indicator is not less than the second limit threshold, the strategy is a backbone communication deterministic protection mode. The adaptive scheduling module is used to calculate and adjust the control quantity based on the strategy and feed it back to the communication acquisition node to correct the time difference between sending the test excitation signal and receiving the status response data.

[0016] This embodiment provides an automated functional testing mechanism for avionics bus based on a modular instrument architecture. Specifically, the system is deployed in a single-chassis modular test platform to conduct hardware-in-the-loop closed-loop testing on the redundant flight control computer of a certain type of fighter jet. The platform simultaneously loads a deterministic Ethernet avionics bus module, a 1553B bus module, and an analog discrete quantity acquisition module. Multiple modules share the backplane transmission channel and trigger synchronization clock. Therefore, during extreme stress testing, the test system itself may enter a resource congestion state before the device under test. To avoid false alarms or missed alarms caused by internal congestion in the test system, this embodiment does not regard the backplane transmission channel as an ideal lossless link. Instead, it continuously monitors the actual operating status inside the system through the underlying bus probe and dynamically adjusts the test rhythm based on the quantification results. Specifically, the communication acquisition node is used to perform two types of actions: excitation transmission and response reception; excitation transmission includes standard bus messages, fault injection messages, discrete trigger sequences, and analog drive waveforms; The response reception includes bus return frames, status variables, fault words, and waveform sample values; the backplane transmission channel has a first-in-first-out buffer space, and when multiple communication acquisition nodes perform DMA transfer, interrupt reporting, and clock trigger alignment at the same time, the buffer space will queue up; The low-level bus probes can be placed in the FPGA logic, driver layer, or a combination of both to collect at least three types of low-level transmission status data: the memory access channel occupancy rate, the phase jitter parameter of the trigger synchronization clock, and the response difference at the system interrupt level. To facilitate the public disclosure of the data flow process, a simplified micro-example is used below; assuming that the length of a certain sampling window is 100 microseconds, and the DMA channel busy time is detected to be 72 microseconds within this window, then the memory access channel occupancy rate can be recorded as 0.72. The normalized jitter parameter after peak-to-peak conversion of the triggered clock phase deviation is 0.18; the interrupt response difference, i.e. the deviation between the expected interrupt response time and the actual response time, is 0.25 after normalization; the congestion quantization module pre-stores three sets of weights, such as 0.5, 0.3 and 0.2. The specific values ​​of the preset weight coefficients are dynamically calibrated based on the performance sensitivity of various underlying transmission status parameters according to the communication protocol of the device under test. For example, for bus protocols that require high synchronization clock accuracy, the weight ratio of the phase jitter parameter will be increased accordingly, while for throughput-sensitive protocols, the weight ratio of the memory access channel occupancy rate will be increased. Therefore, the system's micro-congestion entropy index can be obtained by weighted summation: When the first risk threshold is set to 0.40 and the second limit threshold is set to 0.70, 0.464 falls between the two thresholds, so the strategy generation module determines the current state as a local frequency reduction mode. The first risk threshold is set based on the empirical critical point at which non-idle queues begin to accumulate in the system's internal cache space but have not yet caused global communication delays; the second limit threshold is set based on the theoretical maximum tolerance limit before the system experiences irreversible frame drops or severe timing distortions. Both thresholds can be pre-determined and solidified through step pressure calibration tests of the test system from no load to full load. In this mode, the adaptive scheduling module does not simply stop the test, but calculates the sampling adjustment control quantity and feeds it back to the communication acquisition node; the sampling adjustment control quantity may include the message transmission interval correction quantity, the sampling period expansion quantity, the trigger phase compensation quantity, and the node priority reordering instruction; The adaptive scheduling module has a preset control quantity calculation rule. Based on the difference between the system's micro-congestion entropy index and the lower limit of the current mode interval, it uses a positive proportional mapping or a step-increasing function mapping to dynamically calculate the specific values ​​of the required interval correction and periodic expansion and contraction quantities in order to achieve closed-loop negative feedback regulation. For example, the current original excitation transmission period is 50 microseconds. Because the interrupt response difference is detected to be too large, the adaptive scheduling module gives a transmission interval correction of +10 microseconds. At the same time, it gives a sampling decimation coefficient of 2 for non-critical waveform channels, that is, it changes from sampling every time to sampling once every two times. This can directly correct the time difference between the excitation action and the response action, and suppress excitation lag and sampling misalignment caused by internal congestion accumulation. If, within the same calculation window, the system's micro-congestion entropy index is less than the first risk threshold, for example, 0.28, the system maintains full-load concurrent injection mode. At this time, multiple fault messages and multi-channel sampling can run simultaneously to ensure pressure coverage. If the system's micro-congestion entropy index is greater than or equal to the second limit threshold, for example, reaching 0.81, the policy generation module switches to backbone communication deterministic protection mode. At this time, the scheduling core shifts from maintaining maximum test concurrency to prioritizing the reliability of critical backbone timing. In abnormal situations, if only two types of underlying transmission status data are successfully acquired within a certain sampling window, such as the clock jitter parameter being temporarily missing due to transient phase-locked loop switching, the effective value of the previous window, the factory default value, or the conservative estimation branch can be used. The conservative estimation branch prioritizes the larger risk value in the calculation to prevent underestimating the congestion risk. If critical states are missing in multiple consecutive windows, the system directly enters the backbone communication deterministic defense mode and triggers the host computer to record the abnormal flag to avoid continuing to use an aggressive pressure injection rhythm during the period when the underlying state is unobservable; when conducting a full-machine power-on test on a certain type of flight control computer, the test platform simultaneously injects a full-load virtual link pressure message into the ARINC664 network, sends a fault status word to the 1553B bus, and collects the waveforms returned by the actuators from the analog discrete board; During a reconfiguration switch, the device under test suddenly sent back a large number of abnormal discrete flip signals, which intensified the contention for DMA and interrupt resources within the test platform. The underlying bus probe observed that the memory access channel utilization rate increased from 0.58 to 0.79, the clock jitter parameter increased from 0.11 to 0.22, and the interrupt response difference increased from 0.14 to 0.31 within two consecutive windows. The system micro-congestion entropy increased from 0.37 to 0.55 accordingly. As a result, the platform automatically switched from full-load concurrent injection mode to local frequency reduction mode, reducing the load on non-critical channels according to the preset mapping ratio to avoid timestamp distortion on the main avionics bus. The purpose of this step is to enable the testing system to detect and correct the time mismatch risk caused by its own underlying resource constraints, so as to maintain the time reliability of the test conclusions in high-concurrency, strong-interference, and closed-loop joint testing scenarios.

[0017] In a preferred embodiment of the present invention, the test system is in a hardware closed loop formed with the device under test; in response to the device under test sending a high-frequency discrete trigger request to form a transient high-concurrency communication storm in which the number of requests per unit time exceeds a preset concurrency threshold, the underlying bus probe triggers the operation of collecting underlying transmission status data based on the detected transient high-concurrency communication storm.

[0018] This embodiment provides a storm-triggered detection mechanism for hardware closed-loop systems. Specifically, in the previous embodiment, the underlying state can be acquired periodically according to a fixed sampling window. However, in a real flight control test environment, the system pressure does not change uniformly, but often manifests as millisecond-level bursts. If a constant period polling is still used, there are two types of defects: one is that the sampling is too sparse and cannot capture transient storms; the other is that the sampling is too dense and will needlessly occupy additional resources during the stable phase. Therefore, this embodiment introduces a trigger-based acquisition mechanism that first identifies the storm and then increases the detection density. Specifically, the test system and the flight control computer under test form a hardware closed loop. The test platform sends bus excitation and discrete drive, and the device under test responds according to its internal control law. It then sends back messages, discrete states and waveforms to the test platform. When the device under test restarts abnormally, switches modes or the fault isolation logic is triggered, it may send back a large number of high-frequency discrete trigger requests in a very short time. The system pre-sets a threshold for the number of requests per unit time. For example, more than 800 discrete flip requests within 1 millisecond are considered a transient high-concurrency communication storm. The underlying bus probe can monitor the edge counter, interrupt queue length, and return request density of the discrete quantity acquisition board. Once the threshold is reached, the underlying transmission status data acquisition operation is triggered. For ease of explanation, assume that under steady-state conditions, the average number of discrete requests is 120 per millisecond, and the underlying probe collects the status once every 500 microseconds; during an abnormal restart, the number of discrete requests has accumulated to 260 in the first 200 microseconds. Extrapolating from this trend, the total number of requests in this millisecond will significantly exceed 800, so the probe enters storm mode ahead of schedule. After entering storm mode, the status acquisition module shortens the sampling period from 500 microseconds to 50 microseconds and simultaneously enables joint acquisition of DMA channel occupancy, clock jitter, and interrupt response difference; this allows the micro-congestion entropy rise curve to be obtained earlier before the system becomes completely unstable. Furthermore, storm identification can be based not only on the total number of requests, but also on the growth slope; if the previous window had 80 requests and the next window suddenly increased to 240 requests, even if the absolute threshold has not been reached, it can be determined as an abnormal growth trend and detection can be initiated in advance. Conversely, if the number of requests is high but comes from a single source and does not cause DMA and interrupt queuing, it can be marked as a local peak instead of immediately escalating into a global storm, thus preventing false triggering. It should be noted that, in order to be consistent with the number of requests per unit time exceeding the preset concurrency threshold in this embodiment, the aforementioned judgment based on the growth slope is used in this embodiment for early warning and to increase the monitoring density. Its function is to shorten the sampling period in advance, preload the acquisition resources, or open the candidate observation channel. The criterion for formally triggering the execution of underlying transmission status data collection operations is still based on the actual number of requests within the observation window exceeding the preset concurrency threshold, or on the storm criterion that is equivalent to the concurrency threshold being confirmed by alternative indicators; in other words, the growth slope is used for advance preparation, and exceeding the threshold or equivalent confirmation is used for formal triggering. The two are connected in the process and are not used interchangeably as the same criterion. As a backup fault-tolerance mechanism, if the discrete request counting channel itself temporarily fails, the system can also use alternative indicators to judge, such as the FIFO depth change rate, the number of interrupts suspended, or the number of backplane read / write retries. If multiple alternative indicators indicate a sudden increase, and the main counting channel data is missing, the system will also enter storm mode. If the counter experiences abnormal rollback or short-term zeroing, time alignment and count de-glitching will be performed first, and then it will be decided whether to trigger storm sampling to avoid misjudging the counter failure as a normal state. The preferred alternative criterion for judging this is the equivalent criterion corresponding to the preset concurrency threshold. That is, a transient high-concurrency communication storm is only considered to have been detected when at least one of the FIFO depth change rate, the number of interrupted pending events, or the number of backplane read / write retries reaches the pre-calibrated storm equivalent threshold, and the equivalent threshold is consistent with the risk level of the number of requests exceeding the preset concurrency threshold per unit time. This limitation can prevent the misinterpretation of general local fluctuations as storm triggering conditions in this embodiment. During the emergency restart verification of the flight control computer, the test platform sent it an abnormal attitude condition and a power drop recovery sequence. During the restart process, the device under test instantly output a large number of non-standard discrete triggers to simulate the reset jitter of the actuator. The discrete edge counter recorded 310 flips within 300 microseconds, and the request density exceeded the preset allowable error range of normal operating conditions. The underlying bus probe triggers storm mode, compresses the status sampling period to 50 microseconds, and detects a synchronous increase in DMA channel occupancy and interrupt response difference; the scheduling module can intervene in time to prevent the storm from further propagating into overall timing drift; the purpose of this step is to replace simple timed polling with event triggering, and improve the ability to capture sudden resource squeeze without adding external hardware. In a preferred embodiment of the present invention, during the process of the adaptive scheduling module injecting the sampling adjustment control quantity feedback into the communication acquisition node, the communication acquisition node includes at least a core protocol node and a non-core acquisition node. In response to the adaptive degradation scheduling strategy as the deterministic defense mode of backbone communication, the system stops issuing new test task instructions to non-core acquisition nodes and performs maintenance control such as orderly termination or cache reclamation of tasks already in the queue. The system merges the available bandwidth resources inside the test system and redirects the output to the core protocol node, increases the priority weight of the core protocol node in the backplane transmission channel, so as to ensure that the frame drop rate of data frames is zero and the error range of timestamps is within the preset accuracy threshold.

[0019] This embodiment provides a core-priority bandwidth protection mechanism; specifically, in the aforementioned scheme, when the system's micro-congestion entropy enters a high-risk range, simply reducing the overall frequency may still be insufficient; the reason is that different communication acquisition nodes contribute differently to the test reliability. If all nodes are deloaded at the same ratio, although it appears fair on the surface, under extreme conditions, the critical backbone bus and auxiliary monitoring channels may be damaged simultaneously, ultimately failing to guarantee the timing accuracy of the critical links. Therefore, this embodiment further divides the communication acquisition nodes into core protocol nodes and non-core acquisition nodes, and performs resource redirection under high-risk conditions. Specifically, core protocol nodes undertake the verification tasks of the flight control main channel, such as carrying flight control backbone network frames, command response timing and fault isolation key signals; non-core acquisition nodes undertake auxiliary observation tasks, such as low-priority serial monitoring, additional waveform capture or environmental status bypass recording. When the strategy generation result is in the deterministic defense mode of backbone communication, the adaptive scheduling module stops issuing new instruction data to non-core acquisition nodes; this stop can be a complete pause or no longer issuing new tasks, only retaining the termination processing and cache reclamation instructions of the currently unresolved tasks; the released DMA time slots, backplane bandwidth, master control polling time and interrupt budget are uniformly redirected to the core protocol nodes; For clarity, assume the system has five nodes, two of which are core protocol nodes and three are non-core acquisition nodes. Under normal conditions, the backplane bandwidth budget is allocated as follows: 40%, 20%, 15%, 15%, and 10%. When the system's micro-congestion entropy reaches 0.73, which is higher than the second limit threshold of 0.70, the system enters protection mode. At this point, the three non-core acquisition nodes no longer receive new waveform sampling commands and status polling commands. The released 40% bandwidth is redistributed to the first two core protocol nodes, increasing their bandwidth budget to 65% and 35%, respectively. Since subsequent bus frame packing, DMA transfer, and timestamp writing are all centralized at the critical nodes, the frame drop rate of critical data frames can be compressed to zero, and the timestamp error can be controlled within, for example... Within the nanosecond precision threshold; It should be noted that in this embodiment, the objects that ensure the frame drop rate of data frames is zero and the error range of the timestamp is within the preset accuracy threshold refer to the set of target data frames that are included in the protection scope of the core protocol node after entering the backbone communication deterministic protection mode. Historical queuing that occurred before the mode switch, old data that has been distorted, or non-core historical frames that have not been included in the core resource pool are not included in this protection scope. The system can attach boundary markers, low-confidence markers, or archive the data separately. This limitation ensures that the protection effect in this embodiment is consistent with the temporal boundaries during implementation, avoiding the misinterpretation of existing losses before the protection mode switch as the protection result after the switch. The available bandwidth resources for merging here are not limited to the data channel itself, but also include trigger slot priority, interrupt service sequence, FIFO write watermark, and software task queue length. For example, in guard mode, the system can increase the send descriptor queue length of the core protocol node from 64 items to 128 items, while freezing the sampling descriptors of non-core acquisition nodes at their existing values ​​and prohibiting expansion. Another example is that the core protocol node can be bound to a high-priority interrupt service thread to reduce the jitter caused by waiting for low-priority sampling tasks to release their CPU time slices. Furthermore, the aforementioned cessation of issuing instruction data to non-core acquisition nodes is preferably interpreted in engineering as ceasing the issuance of instructions for new test tasks, without excluding the following maintenance controls: orderly completion of queued tasks, cache reclamation, exception clearing, minimum heartbeat maintenance, and security interlock confirmation. The maintenance control does not change the degraded state of non-core acquisition nodes, nor does it conflict with the stop issuing command data. Its purpose is to avoid cache residue or interface suspension caused by sudden stop, which may in turn interfere with core protocol nodes. As a backup fault tolerance mechanism, if a non-core acquisition node also undertakes the role of safety interlock monitoring, then the node should not be unconditionally shut down; in this case, it can be switched to the minimum maintenance mode, that is, only retain the low-frequency heartbeat sampling and over-limit alarm functions, while stopping the high-density raw waveform capture. If the core protocol node itself experiences link synchronization failure or buffer corruption, even if it has entered the protection mode, a higher level of exception handling should be triggered, such as freezing the test process, performing timestamp resynchronization, or requiring manual confirmation before continuing, in order to prevent the output of conclusions when the critical backbone has been distorted. During a flight control full-state coverage test, the device under test continuously fed back state data to the platform due to switching to the emergency control law, causing the analog quantity capture module and the low speed monitoring module to occupy a large number of DMA channels. The system measured a micro-congestion entropy of 0.78 and immediately stopped issuing new tasks to the waveform capture module and the low-speed serial monitoring module. The released backplane transmission quota was concentrated on the ARINC664 backbone node and the 1553B critical channel. The backbone data frames were continuously collected without any frame drops, and the critical timestamps remained within the accuracy threshold. Non-core monitoring was kept running at the minimum necessary frequency. The purpose of this step is to prioritize the protection of the critical backbone that determines the credibility of test conclusions when approaching the failure boundary, in exchange for the reliability of the core conclusions by sacrificing the integrity of secondary observations.

[0020] In a preferred embodiment of the present invention, the test excitation signal includes a fault burst message. In response to the adaptive degradation scheduling strategy, the frequency of sending fault burst messages to the device under test is reduced to reduce resource contention caused by fault burst messages and release the first-in-first-out buffer space at the bottom layer of the backplane transmission channel.

[0021] This embodiment provides a local frequency reduction mechanism for fault injection intensity. Specifically, in the aforementioned scheme, when the system micro-congestion entropy is in the intermediate risk range, directly stopping non-core nodes will cause the test coverage to drop too quickly; however, if the fault injection intensity is not adjusted at all, it will continue to push up the cache queuing. Therefore, this embodiment prioritizes adjusting the sending frequency of fault burst messages under the medium risk state, rather than immediately terminating the entire test task. Specifically, fault burst messages can include link anomaly messages, status word inversion messages, frame interval distortion messages, and multi-source concurrent impact messages. These messages are usually used to approach the fault tolerance limit of the device under test. The higher the frequency and the more comprehensive the coverage, the more likely they are to cause resource contention within the test platform. When the scheduling result is a local frequency reduction mode, the adaptive scheduling module rearranges the packet sending rhythm of fault burst messages; for example, it adjusts the fault burst messages that were originally injected once every 100 microseconds to be injected once every 250 microseconds, or changes the burst mode of 5 consecutive frames to 2 consecutive frames and inserts a recovery window between groups. A simplified simulation is used to illustrate its effect; assuming the total capacity of the backplane FIFO is 100 buffer units, 40 are used for normal services, 25 are used temporarily for each group of fault-related messages, and 20 are used for status response feedback. When running in high-frequency mode, at a certain moment, it may occur The competitive demand from individual units exceeds the FIFO capacity, causing queuing and delays. After adjusting to a localized frequency reduction mode, only one set of fault bursts is retained at any given time, and the demand becomes... Each unit returns to its capacity; thus, the freed-up FIFO space can be used to promptly receive status feedback from the device under test, reducing response time drift. The frequency reduction here can be achieved by either a fixed percentage reduction or by continuous mapping based on micro-congestion entropy. For example, when the micro-congestion entropy is between 0.40 and 0.55, the fault injection frequency decreases by 20%; when it is between 0.55 and 0.70, it decreases by 50%. If the system recovers and remains below the first risk threshold for several consecutive windows, the original fault injection frequency is gradually restored to avoid remaining at a conservative test intensity for an extended period, which could affect coverage efficiency. As a backup fault tolerance mechanism, if an uninterruptible critical fault tolerance verification sequence is currently being executed, such as a sequence that requires a fixed number of consecutive executions of a fatal fault impact, the number of injections cannot be simply reduced. In this case, alternative methods such as extending the inter-group interval, reducing the number of concurrent channels, or postponing non-critical sampling tasks can be used to release resources. If the fault burst message itself is the only triggering condition for the protection action of the device under test, then when reducing the frequency, it is necessary to ensure that at least the minimum injection density that reaches the trigger threshold is retained, so as not to mistakenly reduce the test target from verifying the fault tolerance boundary to ordinary functional regression. In the flight control computer fault reconfiguration verification, the platform originally planned to inject link jitter messages into the backbone network at a frequency of once every 100 microseconds, while simultaneously maintaining the capture of actuator feedback waveforms; when the test reached the 17th second, the system micro-congestion entropy rose to 0.52. The platform did not interrupt all tests, but instead adjusted the injection frequency of fault-prone messages to once every 250 microseconds, while keeping the main function messages and key status acquisition unchanged. After the adjustment, the backplane FIFO occupancy decreased from a peak of 92% to 68%, and the return status frames resumed queuing on schedule. The purpose of this step is to prioritize reducing the aggressive injection load that is most likely to induce internal resource contention without significantly disrupting the main test objectives, thereby improving the stability of the system transmission timing while meeting the preset minimum test coverage.

[0022] In a preferred embodiment of the present invention, the underlying bus probe is embedded in the field-programmable gate array inside the test system to determine whether the system micro-congestion entropy index has reached a preset error trigger threshold according to the nanosecond-level detection cycle; if the system micro-congestion entropy index is greater than or equal to the error trigger threshold, in response to reaching the error trigger threshold, an interrupt signal is sent to the main control layer of the test system to perform a timestamp resynchronization operation, thereby preventing the timestamp of the test system from drifting beyond the error range.

[0023] This embodiment provides a nanosecond-level low-level alarm and timestamp resynchronization mechanism; specifically, the aforementioned scheme can suppress most resource congestion through status acquisition and scheduling adjustment, but under extreme conditions, the congestion rise rate may be faster than the response speed of the upper-level software. If the main control layer detects the anomaly during its periodic tasks, the critical timestamp may have already drifted irreversibly. Therefore, in this embodiment, the underlying bus probe is embedded in the field-programmable gate array, which enables the early warning and hardware triggering to be completed with finer time granularity. Specifically, the underlying bus probes in the FPGA can be directly connected to the DMA handshake signal, trigger clock monitoring signal, FIFO level signal, and interrupt request edge counter; The probe operates with a nanosecond-level detection cycle, for example, performing a lightweight discrimination every 100 nanoseconds. Based on the same input source as the aforementioned system micro-congestion entropy index, it performs hardware-side fixed-point updates on memory access channel occupancy, phase jitter parameters of the trigger synchronization clock, and response differences at the system interrupt level. When the system micro-congestion entropy index obtained by the hardware side update reaches the preset error trigger threshold, it does not wait for the next master control poll, but immediately sends an interrupt signal to the master control layer. After receiving the signal, the master control layer performs a timestamp resynchronization operation. It should be noted that when FPGA logic resources are limited, the above nanosecond-level discrimination does not require the execution of complex software floating-point operations in each detection cycle. Instead, the aforementioned weighted summation rules can be pre-fixed into hardware equivalents such as table lookup, shift accumulation, or threshold segmentation comparison. In other words, the hardware side can use a fast risk discriminant to carry the real-time judgment result of the system's micro-congestion entropy, but the input dimension, risk direction and threshold mapping relationship of the fast risk discriminant are consistent with the system's micro-congestion entropy index, and it is not interpreted as another independent index that is detached from the congestion quantification logic. Specifically, the preset mapping table is essentially a set of lookup tables or combinational logic circuits configured inside the field-programmable gate array. Its working mechanism is to map the raw parameters directly collected by the hardware into equivalent normalized memory access channel occupancy rate, normalized jitter parameter and normalized response difference, respectively, and perform fixed-point multiplication and addition operations, so as to output a unified system micro-congestion entropy index at the hardware layer for threshold comparison. The preset mapping table inside the field-programmable gate array (FPGA) performs fixed-point normalization on the FIFO water level, DMA handshake waiting time slot and offset clock phase acquired by the hardware, making it equivalent to the input dimension of the software-side micro-congestion entropy index. Through this limitation, the nanosecond-level fast discrimination on the FPGA side and the software-side micro-congestion entropy calculation of the main control layer are consistent in engineering meaning, with differences only in implementation accuracy and calculation granularity. Furthermore, in this embodiment, the error triggering threshold, the first risk threshold, and the second limit threshold are thresholds for different purposes: the first risk threshold and the second limit threshold are used by the strategy generation module to select the full-load concurrent injection mode, the local frequency reduction mode, or the backbone communication deterministic protection mode. The error trigger threshold is used by the FPGA to execute hardware-triggered alarms and initiate timestamp resynchronization at the nanosecond level detection cycle. The judgment object of the three is the same system micro-congestion entropy index, but the service level and triggering action are different. The first two correspond to scheduling level, and the latter corresponds to time base protection. Through this distinction, the error trigger threshold can be avoided from being misunderstood as a renamed reuse of the first risk threshold or the second limit threshold. For ease of understanding, assume that the hardware-side fast judgment consists of three simplified parts: whether the FIFO level exceeds 80%, whether the clock phase deviation exceeds 150 nanoseconds, and whether the DMA handshake wait exceeds 3 probe cycles; the above three conditions correspond to three types of underlying transmission states: memory access channel occupancy, phase jitter, and interrupt or handshake response lag. When two of the three conditions are met simultaneously, and the system micro-congestion entropy index corresponding to the preset mapping table has reached the error triggering threshold, it is determined that the error triggering threshold has been reached. At a certain moment, the probe observes that the FIFO level remains above 85% in three consecutive 100 nanosecond windows, and the DMA handshake wait continues to exceed the threshold, so an interrupt is issued directly. After receiving the interrupt, the main control layer freezes the new timestamp allocation, reads the reference clock and re-marks the subsequent sampling frames, and marks the boundaries of the data segments before and after the exception. This can prevent erroneous timestamps from spreading to subsequent reports; timestamp resynchronization can be achieved in several ways; for example, the master control layer can relock to the chassis reference clock, or rebuild the timeline using a stable time base output by the core protocol node; For data frames that have been enqueued but not yet dequeued, a correction mark can be inserted at the resynchronization time; for data that has been dequeued but not yet participated in the judgment, linear compensation can be performed based on the previous and next reference points; if the compensation error cannot be guaranteed to fall within the preset accuracy threshold, the data segment can be marked as a low confidence area and removed from the final judgment sample. Furthermore, to maintain terminology consistency, the FIFO level, DMA wait, and clock phase deviation involved in the hardware-side judgment are only used as the underlying observation source or equivalent mapping source of memory access channel occupancy, phase jitter parameters, and response differences, and not as another set of new criteria independent of the underlying transmission state data. That is, the hardware probe first merges, reduces or maps these underlying observations to a fixed point, and then obtains three types of underlying transmission state data representations that are consistent with them, and judges whether the system micro-congestion entropy index has reached the error triggering threshold. In abnormal situations, if the FPGA probe detects an abnormal switching of its own clock domain, which may cause the detection results to be distorted, it will not perform complex real-time weighted floating-point calculations, but will directly enter the conservative alarm mode, report an undeterminable steady state flag to the main control layer, and suspend the extended test task. If the main control layer does not respond to the interrupt within the specified time limit, the FPGA side can further perform local protection actions, such as preventing new non-core sampling descriptors from being enqueued and prioritizing the saving of critical bus timestamp registers, in order to reduce the chain distortion caused by the main control layer's failure to respond; During the high-speed reconfiguration phase of the flight control closed-loop test, the test platform encountered a high-frequency transient request pulse of abnormal discrete flipping of the device under test; the FPGA probe continuously detected FIFO water level exceeding the limit and DMA waiting intensified within 300 nanoseconds, and immediately initiated an interrupt to the main control layer; The main control layer then performed timestamp resynchronization, uniformly switching subsequent sampled frames to the new synchronization reference, and adding correction marks to the boundary data segments before and after the storm; as a result, although the underlying layer experienced a short-term impact, the timestamps of critical backbone messages did not drift out of range. The purpose of this step is to move the detection point of congestion and instability forward to the hardware layer, so as to block the continued accumulation of timestamp errors with an extremely short response link and ensure that subsequent function judgments are based on traceable time.

[0024] In a preferred embodiment of the present invention, the test system further includes a report generation and determination module; after the adaptive scheduling module corrects the action time difference to form a stable state, the report generation and determination module is used to perform a comprehensive functional status determination of the device under test based on the response sequence message composed of status response data after the timing correction is completed, and outputs the final device qualification determination result with timing reliability mark; Among them, the timing reliability marker indicates that the response sequence messages in the process of generating the final equipment qualification result are not affected by the error accumulation caused by the congestion of the internal backplane transmission channel.

[0025] This embodiment provides a test report generation mechanism with timing reliability marking; specifically, the aforementioned solution mainly addresses how to monitor and suppress internal congestion during the testing process; however, scheduling control alone is insufficient to support the regulatory and engineering traceability of the final conclusions. The reason is that even if the system eventually stabilizes, it is necessary to clarify which response data was obtained during the stable period and which data has experienced congestion shocks and time corrections; otherwise, the final qualification or failure may still be based on a data set with unclear boundaries; therefore, this embodiment introduces a time-series reliability marker in the report output stage. Specifically, after the adaptive scheduling module corrects the action time difference, the system enters a stable state; the report generation and judgment module does not directly make a unified judgment on all the original response data, but first generates response sequence messages based on timestamp resynchronization records, congestion state switching records and data segment integrity check results. The response sequence message can be understood as a set of data segments with time-series source descriptions; for each segment, the system records whether its acquisition phase belongs to normal mode, local frequency reduction mode or backbone communication deterministic protection mode, and records whether it has undergone timestamp resynchronization or compensation. The following is a simplified deduction; assume that a test yields a total of three response segments S1, S2, and S3; S1 was acquired in normal mode, with a length of 100 frames and no timestamp correction; S2 was acquired during the post-storm recovery phase, with a length of 80 frames, having undergone one timestamp resynchronization but with the compensation error below the accuracy threshold; S3 was acquired in defense mode, with a length of 120 frames, and no frame drops on the critical backbone; the report generation and judgment module can first check the credibility of each segment: S1 is highly credible, S2 is calibrable and credible, and S3 is highly credible; If the comprehensive judgment rules allow the combination of high confidence + correctable confidence + high confidence to participate in the conclusion output, the system can calculate the function result based on the three data segments and add a time-series confidence mark to the final report; if the compensation error of a certain segment exceeds the preset accuracy threshold, the segment is excluded or downgraded to require manual review, and the final report shall not output an unconditionally qualified conclusion. The comprehensive functional status determination here may include timing consistency check, protocol response correctness check, fault reconstruction result check, and closed-loop control effect check. For example, the system first determines whether the network main channel switching delay of the flight control computer after fault injection is lower than the target value, then determines whether the actuator feedback status is consistent with the mode switching, and combines the continuity of multiple segments to confirm whether there is a false recovery phenomenon caused by frame loss. As a backup fault tolerance mechanism, if the stable state does not continuously reach the minimum monitoring window, for example, if the system enters the storm state again after completing the scheduling correction, the report generation module will only output the interim results and not the final pass / fail judgment. If all available response fragments have time errors exceeding the threshold, then even if the functional logic appears correct, only an invalid conclusion of insufficient timing reliability can be output; if some fragments are reliable and some fragments are missing, then the output can be split according to the granularity of the test items: give valid results for items that have met the timing reliability conditions, and give a mark for the remaining items to be retested. After a flight control fault-tolerant test was completed, the platform recorded that the data was in normal mode for the first 12 seconds, experienced a resource storm from the 13th to the 13.2nd second, and entered the recovery and stabilization phase after the 13.2nd second. The report generation and judgment module incorporates the pre-storm backbone bus segment, the corrected recovery segment, and the critical response segment collected in defense mode into the judgment; since none of the segments exhibited out-of-range timestamp errors, The final result is a qualified and time-reliable device; the report also includes an explanation that the result was not affected by the accumulation of backplane congestion errors. The purpose of this step is to ensure that the test report not only provides functional conclusions, but also whether the time basis of those conclusions is reliable, thereby improving the verifiability and engineering acceptance of automated test results.

[0026] In a preferred embodiment of the present invention, the test system is deployed in an industrial computer control chassis oriented towards the peripheral interface of high-speed components; wherein, the core protocol node includes a first type of deterministic avionics integrated bus communication protocol module with full load virtual link scheduling, and the non-core acquisition nodes include a second type of low-speed serial avionics bus protocol module for operational status monitoring and an analog discrete waveform capture module.

[0027] This embodiment provides a node layering implementation mechanism adapted to specific chassis deployment forms; specifically, the logical division of core protocol nodes and non-core acquisition nodes has been explained in the aforementioned scheme; however, without further description in conjunction with the actual modular chassis environment, it is still difficult to clearly explain how the resource redirection action is implemented; Therefore, this embodiment deploys the system in an industrial computer control chassis oriented towards high-speed component peripheral interfaces, and provides a typical node configuration; specifically, the industrial computer control chassis can adopt a high-speed backplane interconnect structure, and the chassis is equipped with a main control computing board, an FPGA coprocessor board, a deterministic avionics integrated bus communication module, a low-speed serial avionics bus module, and an analog discrete waveform capture module; the first type of deterministic avionics integrated bus communication module can undertake full-load virtual link scheduling tasks, and is used to simulate the deterministic message exchange of the flight control backbone network under high load; The second type of low-speed serial aviation bus module is used for operational status monitoring, such as collecting maintenance status, auxiliary sensor status, or low-speed feedback from peripheral subsystems; the analog discrete waveform acquisition module is used to collect actuator position feedback, level inversion, and related waveforms. The reason for this layering is that in the engineering field, different modules have significantly different degrees of dependence on the backplane and clock. The first type of module is usually most sensitive to message transmission time slots, timestamp accuracy, and frame drop rate. Once affected by congestion, the test results may be directly distorted. The second type of low-speed serial modules and waveform capture modules are more responsible for auxiliary observation functions, and their sampling frequency and delay tolerance are higher. Therefore, when scheduling resources in the same industrial chassis, the first type of modules should be given priority to be defined as core protocol nodes, which is more in line with the actual system risk distribution. To illustrate with a simplified example: a chassis contains six service boards: two deterministic aviation integrated bus modules, two low-speed serial bus modules, and two analog discrete quantity acquisition modules; during normal operation, all six boards work simultaneously. When the system enters the backbone communication deterministic protection mode, the main control board sends a stop to add new tasks or minimum maintenance mode control word to the last four boards, and at the same time concentrates the priority of chassis clock synchronization correction, DMA arbitration and main control polling to the first two deterministic bus modules; in this way, the hardware resource allocation at the industrial chassis level corresponds to the logical layering mentioned above. Furthermore, the chassis deployment for high-speed component peripheral interfaces facilitates the formation of short-link connections with the flight control system under test, reducing uncertain delays introduced by external cables; the backbone module can be directly connected to the main network of the device under test through a dedicated high-speed interface, while the low-speed serial module and waveform capture module are connected to the auxiliary signal source through an expansion interface; thus, when executing the protection strategy, the physical path of the backbone link is shorter and more controllable, which is conducive to maintaining timestamp accuracy; In abnormal situations, if a low-speed serial module undertakes the critical health monitoring function required by the system in a certain test, one of them can be temporarily promoted to a quasi-core node, retaining only its minimum sampling traffic, while the other is still degraded as a non-core module; if the simulated waveform capture module contains a single critical channel directly related to backbone fault verification, that channel can be extracted and bound to the core resource pool, while the remaining waveform channels are still degraded. Therefore, the node division is not fixed, but rather a dynamic layering based on task credibility within the chassis deployment structure. In a certain type of fighter jet flight control integrated test platform, the industrial computer chassis is equipped with two fully loaded virtual link scheduling modules for backbone avionics network testing, as well as a 1553B status monitoring module, a low-speed serial monitoring module, and two discrete waveform capture modules. When the tested device experiences a cross-module resource rush during an emergency restart, the platform protects the two backbone modules, suspends low-speed monitoring and most waveform capture, and retains only one critical discrete channel related to the control surface lock status; the time determinism of the backbone network is guaranteed, while auxiliary monitoring is maintained at a level that meets the minimum safety monitoring requirements. The purpose of this step is to implement the aforementioned adaptive scheduling framework onto actual industrial chassis and specific board types, so that the resource protection strategy has a clear hardware mapping relationship and engineering implementation path.

[0028] The foregoing has provided a detailed description of one embodiment of the present invention, but this description is merely a preferred embodiment and should not be construed as limiting the scope of the invention. All equivalent variations and modifications made within the scope of the claims of this invention should still fall within the patent coverage of this invention.

Claims

1. An automated functional test system for avionics bus based on a modular instrument architecture, used to test the device under test (DUT), wherein the test system and the DUT are connected via signal cables to form a hardware closed-loop circuit, characterized in that... It includes a communication acquisition node and a backplane transmission channel with a first-in-first-out buffer. The communication acquisition node sends test excitation signals to the device under test and receives status response data through the backplane transmission channel. The system also includes: a low-level bus probe; a status acquisition module, used to collect the current low-level transmission status data of the backplane transmission channel through the low-level bus probe; the low-level transmission status data is defined as data including memory access channel occupancy rate, phase jitter parameters of the trigger synchronization clock, and response difference at the system interrupt level; The congestion quantization module is used to perform a weighted summation of the occupancy rate, the phase jitter parameter, and the response difference based on a preset weight coefficient. The preset weight coefficient is pre-calibrated offline by the test system according to the communication deterministic sensitivity of different avionics bus protocols and stored to calculate the system micro-congestion entropy index. The system micro-congestion entropy index is a normalized value that characterizes the degree of conflict of underlying resources in the backplane transmission channel. The strategy generation module is used to compare the system micro-congestion entropy index with a first risk threshold and a larger second limit threshold to generate an adaptive degradation scheduling strategy: if the index is less than the first risk threshold, the strategy is a full-load concurrent injection mode, that is, maintaining the preset concurrent test intensity. If the indicator is not less than the first risk threshold and less than the second limit threshold, the strategy is a local frequency reduction mode; if the indicator is not less than the second limit threshold, the strategy is a backbone communication deterministic protection mode. An adaptive scheduling module is used to calculate and adjust the control quantity based on the strategy and feed it back to the communication acquisition node to correct the time difference between sending the test excitation signal and receiving the status response data.

2. The modular instrument rack architecture based avionics bus automated function test system of claim 1, wherein, The testing system is located in a hardware closed-loop circuit with the device under test; In response to the device under test sending a high-frequency discrete trigger request to form a transient high-concurrency communication storm in which the number of requests per unit time exceeds a preset concurrency threshold, the underlying bus probe triggers the operation of collecting the underlying transmission status data based on the detected transient high-concurrency communication storm.

3. The modular instrument architecture based avionics bus automated function test system of claim 1, wherein, During the process of the adaptive scheduling module injecting the sampling adjustment control quantity feedback into the communication acquisition node, the communication acquisition node includes at least a core protocol node and a non-core acquisition node. In response to the adaptive degradation scheduling strategy as the backbone communication deterministic defense mode, the issuance of new test task instructions to the non-core acquisition nodes is stopped, and maintenance control is performed on the queued tasks to ensure orderly termination or cache reclamation. The available bandwidth resources within the test system are merged and redirected to the core protocol node. The priority weight of the core protocol node in the backplane transmission channel is increased to ensure that the frame drop rate of the data frame is zero and the error range of the timestamp is within the preset accuracy threshold.

4. The modular instrument architecture based avionics bus automated function test system of claim 1, wherein, The test stimulus signal includes a fault burst message. In response to the adaptive degradation scheduling strategy being a local frequency reduction mode, the frequency of sending the fault burst message to the device under test is reduced, so as to reduce resource contention caused by the fault burst message and release the first-in-first-out buffer space at the bottom layer of the backplane transmission channel.

5. The modular instrument architecture based avionics bus automated function test system of claim 1, wherein, The underlying bus probe is embedded in the field-programmable gate array inside the test system and is used to determine whether the system's micro-congestion entropy index has reached a preset error trigger threshold according to a nanosecond-level detection cycle. If the system micro-congestion entropy index is greater than or equal to the error trigger threshold, in response to reaching the error trigger threshold, an interrupt signal is sent to the main control layer of the test system to perform a timestamp resynchronization operation, thereby preventing the timestamp of the test system from drifting beyond the error range.

6. The modular instrument rack architecture based avionics bus automated function test system of claim 1, wherein, The testing system also includes a report generation and judgment module; After the adaptive scheduling module corrects the action time difference to form a stable state, the report generation and judgment module is used to perform a comprehensive functional status judgment on the device under test based on the response sequence message composed of the status response data after the timing correction is completed, and outputs the final device qualification judgment result with timing reliability mark. The timing reliability marker indicates that the response sequence message in the process of generating the final equipment qualification result is not affected by the error accumulation caused by internal backplane transmission channel congestion.

7. The modular instrument rack architecture based avionics bus automated function test system of claim 3, wherein, The testing system is deployed in an industrial computer control chassis oriented towards the peripheral interfaces of high-speed components; The core protocol node includes a first-class deterministic aviation integrated bus communication protocol module with full-load virtual link scheduling, and the non-core acquisition node includes a second-class low-speed serial aviation bus protocol module for operational status monitoring and an analog discrete waveform capture module.

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