Semiconductor structure and method of forming the same

Abstract

This invention provides a semiconductor structure and a method for forming the same. The semiconductor structure includes: a substrate, a logic gate structure, a capping layer, an interlayer dielectric layer, a barrier layer, and a first contact. The substrate includes a peripheral region and an array region. The logic gate structure is disposed in the peripheral region and on the substrate. The capping layer is disposed on the logic gate structure. The interlayer dielectric layer is disposed on the capping layer. The barrier layer includes a first portion located in the peripheral region and a second portion located in the array region. The first portion is disposed on the interlayer dielectric layer and located directly above the logic gate structure. The first contact is disposed in the interlayer dielectric layer and contacts the substrate. The width of the logic gate structure is smaller than the width of the first portion.

Description

Technical Field

[0001] This invention relates to semiconductor structures and methods of forming them, and particularly to semiconductor structures including barrier layers and methods of forming them. Background Technology

[0002] As semiconductor structures become increasingly miniaturized, the size of memory devices continues to shrink to increase integration and improve performance. However, the continuous reduction in size leads to problems such as leakage current between adjacent components, damage to existing components during the formation of subsequent components, insufficient component reliability, and insufficient process margin, all of which adversely affect the performance of the semiconductor structure. Summary of the Invention

[0003] The present invention may include a barrier layer, which may include a first portion in a peripheral region and a second portion in an array region. The barrier layer can reduce leakage current between adjacent components, prevent damage to components below the barrier layer, improve component reliability and / or increase process margin, thereby obtaining an improved semiconductor structure and its formation method.

[0004] In some embodiments, a semiconductor structure is provided, comprising a substrate, a logical gate structure, a capping layer, an interlayer dielectric layer, a barrier layer, and a first contact. The substrate includes a peripheral region and an array region. The logical gate structure is disposed in the peripheral region and on the substrate. The capping layer is disposed on the logical gate structure. The interlayer dielectric layer is disposed on the capping layer. The barrier layer includes a first portion located in the peripheral region and a second portion located in the array region. The first portion is disposed on the interlayer dielectric layer and located directly above the logical gate structure. The first contact is disposed in the interlayer dielectric layer and contacts the substrate. The width of the logical gate structure is smaller than the width of the first portion.

[0005] In some embodiments, a method for forming a semiconductor structure includes providing a substrate, the substrate including a peripheral region and an array region. A logic gate structure is formed in the peripheral region and on the substrate. A capping layer is formed on the logic gate structure. An interlayer dielectric layer is formed on the capping layer. A first trench is formed in the interlayer dielectric layer. A barrier layer is formed in the first trench. A first contact is formed on the substrate. The width of the logic gate structure is smaller than the width of the first trench.

[0006] The invention comprises a first portion and a second portion disposed above the bit line structure in the array region. For example, the first portion of the barrier layer can prevent leakage current between the logic gate structure and the first contact and / or prevent damage to the logic gate structure. For example, the second portion of the barrier layer can prevent leakage current between the bit line structure and the second contact and / or prevent damage to the bit line structure. Accordingly, the reliability of the semiconductor structure can be improved. Furthermore, in the semiconductor structure formation method of the present invention, since the first and second portions of the barrier layer can respectively serve as masks to limit the placement positions of the first and second contacts, a self-aligning effect can be achieved. Therefore, the barrier layer can prevent damage to other components during the formation process of the first or second contact. In addition, the first and second portions of the barrier layer can be formed simultaneously to simplify the process steps. Accordingly, the process margin of the formation method can be improved. Attached Figure Description

[0007] Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A ,as well as Figure 1B , Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B Cross-sectional schematic diagrams of semiconductor structures according to some embodiments are shown at various stages of the formation method.

[0008] Figure 16A and Figure 16B Cross-sectional schematic diagrams of semiconductor structures according to some embodiments are shown respectively.

[0009] Symbol Explanation

[0010] 1, 2: Semiconductor structure

[0011] 100: Substrate

[0012] 110: Isolation Structure

[0013] 111: Gate dielectric layer

[0014] 112: Logic gate

[0015] 113, 119: Spacers

[0016] 114: Tunneling Dielectric Layer

[0017] 115: Floating gate

[0018] 116, 118: Dielectric layer

[0019] 117: Control Gate

[0020] 120: Cap layer

[0021] 120S, 310S, BLSS: Side surfaces

[0022] 200: Interlayer dielectric layer

[0023] 201: Conductive layer

[0024] 202: First trench

[0025] 203: Second trench

[0026] 210, 220, 320: Mask

[0027] 230, 330: Photoresist layer

[0028] 300: Barrier layer

[0029] 300a: Part 1

[0030] 300a1: First sidewall

[0031] 300a2: First bottom

[0032] 300b: Part Two

[0033] 300b1: Second sidewall

[0034] 300b2: Second bottom

[0035] 310: Planarization layer

[0036] 310B: Bottom surface

[0037] 340: First Opening

[0038] 350: Second opening

[0039] 410: First contact object

[0040] 420: Second contact object

[0041] AA: Array area

[0042] BLS: Bit Line Structure

[0043] BLST: Top Surface

[0044] d1: First distance

[0045] d2: Second distance

[0046] D1: First Direction

[0047] D2: Second Direction

[0048] D3: Third direction

[0049] LGS: Logic Gate Structure

[0050] PA: Surrounding Area

[0051] TP: pointed tip

[0052] t1: First thickness

[0053] t2: Second thickness

[0054] t3: Third thickness

[0055] t4: Fourth thickness

[0056] w1: First width

[0057] w1', w3': Total width

[0058] w2: Second width

[0059] w3: Third width

[0060] w4: Fourth width

[0061] w5: Fifth width

[0062] w6: Sixth width

[0063] w7: Seventh width Detailed Implementation

[0064] In this invention, the directions are not limited to the three axes of a Cartesian coordinate system such as the X, Y, and Z axes, and can be interpreted in a broader sense. For example, the X, Y, and Z axes may be perpendicular to each other, or different directions that are not perpendicular to each other, but are not limited thereto. In the following, the X-axis direction is the first direction D1 (width direction), the Y-axis direction is the second direction D2, and the Z-axis direction is the third direction D3 (thickness direction). In some embodiments, the cross-sectional view described herein is a cross-sectional view of the XZ plane. In some embodiments, the cross-sectional view described herein is a cross-sectional view taken along the extension direction parallel to the wordline of the semiconductor structure. In some embodiments, the normal direction of the substrate 100 is the third direction D3.

[0065] Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A The diagrams show cross-sectional views of the peripheral region PA of the substrate 100 of the semiconductor structure 1. Figure 1B , Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B These are schematic cross-sectional views of the array region AA of the substrate 100 of the semiconductor structure 1. Figure 16A This diagram shows a cross-sectional view of the peripheral region PA of the substrate 100 of the semiconductor structure 2. Figure 16B A cross-sectional schematic diagram of the array region AA of the substrate 100 of the semiconductor structure 2 is shown.

[0066] Reference Figure 1A and Figure 1BThe substrate 100 may include a silicon wafer, a bulk semiconductor, or a semiconductor-on-insulation (SOI) substrate. Other types of substrates 100 include, for example, multilayer substrates or gradient substrates. The substrate 100 may include a peripheral region PA and an array region AA, and the peripheral region PA may be disposed adjacent to the array region AA. Memory cells may be disposed in the array region AA, and peripheral logic circuits for controlling the memory cells may be disposed in the peripheral region PA.

[0067] like Figure 1A As shown, an isolation structure 110 can be formed in the peripheral region PA of the substrate 100 to provide electrical isolation. The isolation structure 110 may include a single-layer or multi-layer structure. For example, the isolation structure 110 may include an oxide of silicon oxide, a nitride of silicon nitride, an oxide oxynitride of silicon oxynitride, other suitable dielectric materials, the like, or combinations thereof. In some embodiments, a plurality of trenches (not shown) may be formed in the substrate 100, and the depth, shape, and spacing of the plurality of trenches may be adjusted according to the desired electrical isolation properties. Next, a first dielectric liner (not shown) is compliantly formed in the trenches, and a second dielectric liner (not shown) is compliantly formed on the first dielectric liner. Then, a dielectric filler (not shown) is formed on the second dielectric liner in a blanket-like manner. The isolation structure 110 may be formed by a deposition process such as chemical vapor deposition.

[0068] like Figure 1AAs shown, a logic gate structure LGS can be formed in the peripheral region PA and on the substrate 100. The logic gate structure LGS may include a gate dielectric layer 111, a logic gate 112, and a spacer 113. The gate dielectric layer 111 may be disposed on the substrate 100, the logic gate 112 may be disposed on the gate dielectric layer 111, and the spacer 113 may be disposed on the logic gate 112. In the first direction D1, the spacer 113 may be disposed on the opposite side of the logic gate 112. The gate dielectric layer 111 may include an oxide such as silicon oxide, but the invention is not limited thereto. The gate dielectric layer 111 may include a dielectric material with a high dielectric constant. The logic gate 112 may include polycrystalline silicon; amorphous silicon; metals such as tungsten (W), copper (Cu), silver (Ag), gold (Au), and cobalt (Co); metal nitrides such as tungsten nitride (WN) and titanium nitride (TiN); conductive metal oxides; other suitable materials; the like or combinations thereof. For example, the logic gate 112 may include polycrystalline silicon. The spacer 113 may include a single-layer or multi-layer structure. For example, the spacer 113 may include oxides of silicon oxide, nitrides of silicon nitride, oxides of silicon oxynitride, other suitable dielectric materials, the like or combinations thereof, but the invention is not limited thereto. The spacer 113 may include an oxide-nitride-oxide structure or an oxide-nitride-oxide-nitride-oxide structure. The logic gate structure LGS may be formed by chemical vapor deposition, physical vapor deposition, or a combination thereof.

[0069] like Figure 1A As shown, a capping layer 120 can be compliantly formed on a logic gate structure LGS. For example, capping layer 120 may include an oxide of silicon oxide, a nitride of silicon nitride, an oxide oxynitride of silicon oxynitride, other suitable dielectric materials, the like, or combinations thereof. For example, capping layer 120 may include silicon nitride. Capping layer 120 may be formed by a deposition process such as chemical vapor deposition. In some embodiments, an interlayer dielectric layer 200 may be formed on capping layer 120 in a blanket manner. The material and formation method of interlayer dielectric layer 200 may be the same as or different from the material and formation method of capping layer 120, but the invention is not limited thereto. For example, interlayer dielectric layer 200 may include spin-on-glass (SOG) oxide.

[0070] like Figure 1BAs shown, a bit line structure (BLS) can be formed in the array region AA and on the substrate 100. The bit line structure (BLS) may include a tunneling dielectric layer 114, a floating gate 115, a dielectric layer 116, a control gate 117, a dielectric layer 118, and spacers 119. The tunneling dielectric layer 114 may be disposed on the substrate 100, the floating gate 115 may be disposed on the tunneling dielectric layer 114, the dielectric layer 116 may be disposed on the floating gate 115, the control gate 117 may be disposed on the dielectric layer 116, and the dielectric layer 118 may be disposed on the control gate 117. The spacers 119 may be disposed on the control gate 117. The spacers 119 may be disposed on opposite sides of the tunneling dielectric layer 114, the floating gate 115, the dielectric layer 116, the control gate 117, and the dielectric layer 118. The materials and formation methods of the tunneling dielectric layer 114, dielectric layer 116, dielectric layer 118, and spacer 119 may be the same as or different from those of the capping layer 120. For example, the tunneling dielectric layer 114, dielectric layer 116, and dielectric layer 118 may each comprise silicon oxide, and the spacer 119 may comprise silicon oxide and silicon nitride. The structure of the spacer 119 may be the same as or different from that of the spacer 113. The materials and formation methods of the floating gate 115 and control gate 117 may be the same as or different from those of the logic gate 112, but the present invention is not limited thereto. For example, the floating gate 115 and control gate 117 may each comprise polysilicon.

[0071] like Figure 1B As shown, a capping layer 120 can be compliantly formed on the bit line structure (BLS). In some embodiments, a conductive layer 201 can be formed on the capping layer 120. The material and formation method of the conductive layer 201 may be the same as or different from the material and formation method of the logic gate 112, but the invention is not limited thereto. For example, the conductive layer 201 may include polysilicon.

[0072] like Figure 1A and Figure 1B As shown, a mask 210 may be formed on the interlayer dielectric layer 200 and the conductive layer 201, and a mask 220 may be formed on the mask 210. The mask 210 may include silicon nitride, and the mask 220 may include a carbon-based material such as silicon carbonitride. In some embodiments, a photoresist layer 230 may be formed on the mask 220.

[0073] Reference Figure 2A and Figure 2BThe photoresist layer 230 can be used as an etching mask to perform an etching process to pattern masks 220 and 210. The etching process may include dry etching, wet etching, other suitable removal processes, or combinations thereof. For example, the etching process may use reactive ion etching (RIE), but the invention is not limited thereto. Subsequently, a removal process such as ashing can be used to remove the photoresist layer 230.

[0074] Reference Figure 3A and Figure 3B The mask 220 can be removed. For example, a cleaning process can be used to remove the mask 220.

[0075] Reference Figure 4A and Figure 4B A mask 210 can be used as an etching mask to perform an etching process to form a first trench 202 in the interlayer dielectric layer 200. The first trench 202 can be located in the peripheral region PA. The etching rate for oxides can be greater than the etching rate for polysilicon, thus substantially avoiding damage to the conductive layer 201. For example, reactive ion etching (RIE) can be used, but the invention is not limited thereto. In some embodiments, the first trench 202 can be located directly above the logic gate structure LGS. The bottom surface of the first trench 202 can be spaced from the top surface of the capping layer 120 by a first distance d1 to avoid the first trench 202 damaging the logic gate structure LGS. In other words, the first trench 202 may not contact the capping layer 120.

[0076] like Figure 4A As shown, in the first direction D1, the logic gate structure LGS may have a first width w1, and the first trench 202 may have a second width w2, and the first width w1 of the logic gate structure LGS may be smaller than the second width w2 of the first trench 202. In other words, the projection range of the logic gate structure LGS onto the substrate 100 may be located within the projection range of the first trench 202 onto the substrate 100. In some embodiments, in the first direction D1, the total width w1' of the logic gate structure LGS and the capping layer 120 may be less than or equal to the second width w2 of the first trench 202. Wherein, the total width w1' may be the maximum total width of the logic gate structure LGS and the capping layer 120 disposed on the logic gate structure LGS in the first direction D1. Accordingly, the width of the barrier layer (e.g., the first portion 300a of the barrier layer 300) subsequently formed in the first trench 202 may be greater than the first width w1 of the logic gate structure LGS, and may be greater than or equal to the total width w1' of the logic gate structure LGS and the capping layer 120. Therefore, the barrier layer can serve as a barrier and / or mask to protect the logic gate structure LGS located directly beneath the barrier layer.

[0077] Reference Figure 5A and Figure 5B A mask 210 can be used as an etching mask to perform an etching process to form a second trench 203 in the conductive layer 201. The second trench 203 can be located in the array region AA. The etching rate for oxides can be lower than the etching rate for polysilicon, thus substantially preserving the interlayer dielectric layer 200. For example, reactive ion etching (RIE) can be used, but the invention is not limited thereto. In some embodiments, the second trench 203 can be located directly above the bit line structure BLS. The second trench 203 can expose the capping layer 120 to avoid damaging the bit line structure BLS.

[0078] like Figure 5B As shown, in the first direction D1, the bit line structure BLS may have a third width w3, and the second trench 203 may have a fourth width w4, and the third width w3 of the bit line structure BLS may be smaller than the fourth width w4 of the second trench 203. In other words, the projection range of the bit line structure BLS onto the substrate 100 may be located within the projection range of the second trench 203 onto the substrate 100. In some embodiments, in the first direction D1, the total width w3' of the bit line structure BLS and the capping layer 120 may be less than or equal to the fourth width w4 of the second trench 203. Wherein, the total width w3' may be the maximum total width of the bit line structure BLS and the capping layer 120 disposed on the bit line structure BLS in the first direction D1. Accordingly, the width of the barrier layer (e.g., the second portion 300b of the barrier layer 300) subsequently formed in the second trench 203 may be greater than the third width w3 of the bit line structure BLS, and may be greater than or equal to the total width w3' of the bit line structure BLS and the capping layer 120. Therefore, the barrier layer can serve as a barrier and / or mask to protect the bit line structure (BLS) located directly beneath the barrier layer.

[0079] Reference Figure 6A and Figure 6BA barrier layer 300 is compliantly formed in the first trench 202 and the second trench 203. In the peripheral region PA, the barrier layer 300 may be formed on the mask 210 and the interlayer dielectric layer 200. In the array region AA, the barrier layer 300 may be formed on the mask 210, the conductive layer 201, and the capping layer 120. The material and formation method of the barrier layer 300 may be the same as or different from the material and formation method of the capping layer 120, but the invention is not limited thereto. For example, the barrier layer 300 may include silicon nitride. For example, the barrier layer 300 may be formed by a chemical vapor deposition (CVD) process to improve the quality, reliability, and / or step coverage of the formed barrier layer 300. In some embodiments, the barrier layer 300 may have a first thickness t1 in the third direction D3. The barrier layer 300 may have a fifth width w5 in the first direction D1. Since the barrier layer 300 is formed compliantly, the fifth width w5 of the barrier layer 300 can be substantially equal to the first thickness t1 of the barrier layer 300.

[0080] Reference Figure 7A and Figure 7B The horizontal portion of the barrier layer 300 can be at least partially removed, while the vertical portion of the barrier layer 300 may not be substantially removed. In other words, the horizontal portion of the barrier layer 300 can be thinned while maintaining the fifth width w5 of the vertical portion of the barrier layer 300 at a constant value. For example, the removal process can use reactive ion etching (RIE), but the invention is not limited thereto. After at least partially removing the horizontal portion of the barrier layer 300, the horizontal portion of the barrier layer 300 may have a second thickness t2, and the second thickness t2 may be less than the first thickness t1. In some embodiments, the second thickness t2 may be greater than or equal to 0 and less than or equal to 10 nm. For example, the second thickness t2 may be 0, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, or any value or a range of values ​​between the foregoing values, but the invention is not limited thereto. In some embodiments, the ratio of the second thickness t2 to the first thickness t1 (second thickness t2 / first thickness t1) may be 0 to 0.4. For example, the ratio of the second thickness t2 to the first thickness t1 can be 0, 0.05, 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, or any value or range of values ​​between the aforementioned values, but the invention is not limited thereto. Accordingly, because at least partially removing the horizontal portion of the barrier layer 300 facilitates the subsequent formation of a planarization layer (e.g., planarization layer 310) on the barrier layer 300.

[0081] Reference Figure 8A and Figure 8BA planarization layer 310 is formed on the barrier layer 300. The planarization layer 310 may be located in the peripheral region PA and the array region AA. The material and formation method of the planarization layer 310 may be the same as or different from the material and formation method of the capping layer 120, but the present invention is not limited thereto. For example, the planarization layer 310 may include silicon oxide. For example, the planarization layer 310 may include spin-coated glass (SOG) oxide to facilitate the filling of the planarization layer 310 into the first trench 202 and the second trench 203.

[0082] Reference Figure 9A and Figure 9B A removal process can be performed to make the top surface of the planarization layer 310, the top surface of the barrier layer 300, and the top surface of the mask 210 coplanar. For example, the removal process can use a removal process such as chemical mechanical polishing (CMP), but the invention is not limited thereto.

[0083] Reference Figure 10A and Figure 10B A reverse etch process can be performed to remove the mask 210. After the reverse etch process is performed, the top surface of the planarization layer 310 and the top surface of the barrier layer 300 can be coplanar.

[0084] Reference Figure 11A and Figure 11B The conductive layer 201 located in the array region AA can be removed to expose the capping layer 120 in the array region AA.

[0085] Reference Figure 12A and Figure 12B The bottom of the capping layer 120 in the array region AA can be removed to expose the substrate 100 in the array region AA. This results in a first opening 340. The first opening 340 may be located within an adjacent bit line structure (BLS). The first opening 340 can be used to accommodate contacts connected to memory cells. In some embodiments, during the removal of the bottom of the capping layer 120 in the array region AA, a portion of the barrier layer 300 in the peripheral region PA can be removed. Therefore, in the peripheral region PA, the top surface of the barrier layer 300 may be lower than the top surface of the planarization layer 310. The first opening 340 can be formed first, followed by a second opening (e.g., a second opening 350). Accordingly, during the removal of the conductive layer 201 in the array region AA and the capping layer 120 in the array region AA (to form the first opening 340), the barrier layer 300 has a blocking and self-aligning effect, thus improving the accuracy of opening formation and / or preventing damage to the bit line structure (BLS) during the etching process.

[0086] Reference Figure 13A and Figure 13BA mask 320 may be formed. The mask 320 may be formed on the interlayer dielectric layer 200, the barrier layer 300, and the planarization layer 310. In the array region AA, the mask 320 may be formed on the substrate 100, the capping layer 120, the barrier layer 300, and the planarization layer 310. The mask 320 may include a carbon-based material such as silicon carbonitride. In some embodiments, a photoresist layer 330 may be formed on the mask 320. The photoresist layer 330 may expose the mask 320 in the peripheral region PA and cover the mask 320 in the array region AA. The photoresist layer 330 may then be used as an etching mask to perform an etching process to pattern the mask 320. The etching process may include dry etching, wet etching, other suitable removal processes, or combinations thereof. For example, the etching process may use reactive ion etching (RIE), but the invention is not limited thereto. The photoresist layer 330 may then be removed using a removal process such as ashing.

[0087] Reference Figure 14A and Figure 14B In some embodiments, a mask 320 and a barrier layer 300 can be used as etching masks to perform an etching process to form a second opening 350 in the interlayer dielectric layer 200. The mask 320 can then be removed. Accordingly, during the removal of the interlayer dielectric layer 200 located in the peripheral region PA (to form the second opening 350), the barrier layer 300 has a blocking and self-aligning effect, thus improving the accuracy of opening formation and / or preventing damage to the logic gate structure (LGS) during the etching process. It should be noted that although the mask 320 alone can define the position of the second opening 350, using both the mask 320 and the barrier layer 300 together further improves the accuracy, reliability, and / or process margin of opening formation. That is, even if there is an error between the pattern of the mask 320 and the required position of the second opening 350, the barrier layer 300 has a blocking and self-aligning effect, thus more accurately preventing damage to the logic gate structure (LGS) during the etching process.

[0088] like Figure 14A As shown, the second opening 350 can penetrate the interlayer dielectric layer 200 and the capping layer 120, and can expose the substrate 100. The second opening 350 can be used to accommodate contacts connected to the logic gate structure LGS. In some embodiments, in the first direction D1, the side surface 120S of the capping layer 120 can be spaced from the second opening 350 by a second distance d2. The second distance d2 can be adjusted according to electrical requirements. For example, the second distance d2 can be greater than or equal to 0. For example, the second distance d2 can be 0, 25nm, 50nm, 75nm, 100nm, 125nm, 130nm, 135nm, 140nm, 145nm, 150nm, 155nm, 160nm or greater. In some embodiments, the mask 320 and the photoresist layer 330 can be removed.

[0089] Reference Figure 15A and Figure 15B In some embodiments, contact material may be filled into the first opening 340 and the second opening 350 to form a first contact 410 located in the second opening 350 and a second contact 420 located in the first opening 340. The first contact 410 and the second contact 420 may be disposed on the substrate 100. The contact material may be the same as or different from the material of the logic gate 112. For example, the first contact 410 and the second contact 420 may each comprise tungsten.

[0090] like Figure 15A and Figure 15B As shown, in some embodiments, a removal process can be performed to make the top surfaces of the interlayer dielectric layer 200, the first contact 410, the barrier layer 300, and the planarization layer 310 in the peripheral region PA coplanar. A removal process can also be performed to make the top surfaces of the second contact 420, the barrier layer 300, and the planarization layer 310 in the array region AA coplanar. For example, the removal process can use a chemical mechanical polishing process. Thus, a semiconductor structure 1 can be obtained. In some embodiments, the first portion 300a of the barrier layer 300 may cover the side surface 310S and the bottom surface 310B of the planarization layer 310. In some embodiments, the barrier layer 300 may include a first portion 300a and a second portion 300b. The first portion 300a of the barrier layer 300 may be located in the peripheral region PA, and the second portion 300b of the barrier layer 300 may be located in the array region AA.

[0091] like Figure 15A As shown, in some embodiments, in the peripheral region PA, a first portion 300a of the barrier layer 300 may be disposed on the interlayer dielectric layer 200 and may be located directly above the logic gate structure LGS. The first width w1 of the logic gate structure LGS may be smaller than the second width w2 of the first portion 300a of the barrier layer 300. Therefore, when the barrier layer 300 is used as an etching mask to form the second opening 350 for accommodating the first contact 410, the second opening 350 can be prevented from damaging the logic gate structure LGS. Accordingly, leakage current between the logic gate structure LGS and the first contact 410 can be avoided and / or damage to the logic gate structure LGS can be avoided.

[0092] like Figure 15AAs shown, in some embodiments, the first contact 410 may contact a first portion 300a of the barrier layer 300. The first contact 410 may be spaced from the side surface 120S of the cover layer 120 by a second distance d2. Since the first portion 300a of the barrier layer 300 can act as a mask to limit the placement position of the first contact 410, a self-aligning effect can be achieved. In some embodiments, the first portion 300a of the barrier layer 300 may include a first sidewall 300a1 and a first bottom 300a2, and the first bottom 300a2 may be connected to the first sidewall 300a1. The first sidewall 300a1 may surround the first bottom 300a2. In some embodiments, the fifth width w5 of the first sidewall 300a1 may be greater than the second thickness t2 of the first bottom 300a2.

[0093] like Figure 15B As shown, in some embodiments, in the array region AA, the second portion 300b of the barrier layer 300 may be disposed on the capping layer 120 and may be located directly above the bit line structure BLS. The third width w3 of the bit line structure BLS may be smaller than the fourth width w4 of the second portion 300b of the barrier layer 300. Therefore, when the first opening 340 for accommodating the second contact 420 is formed, the first opening 340 can be prevented from damaging the bit line structure BLS. Accordingly, leakage current between the bit line structure BLS and the second contact 420 and / or damage to the bit line structure BLS can be avoided.

[0094] like Figure 15BAs shown, in some embodiments, the second contact 420 may be adjacent to the second portion 300b of the barrier layer 300. The second contact 420 may contact the second portion 300b of the barrier layer 300. Since the second portion 300b of the barrier layer 300 can act as a mask to limit the placement of the second contact 420, a self-aligning effect can be achieved. In some embodiments, the second portion 300b of the barrier layer 300 may include a second sidewall 300b1 and a second bottom 300b2, and the second bottom 300b2 may be connected to the second sidewall 300b1. The second sidewall 300b1 may surround the second bottom 300b2. In some embodiments, the seventh width w7 of the second sidewall 300b1 may be greater than the second thickness t2 of the second bottom 300b2. In some embodiments, the seventh width w7 of the second sidewall 300b1 may be greater than the sixth width w6 of the spacer 119 of the bit line structure BLS to effectively protect the bit line structure BLS. In some embodiments, the seventh width w7 of the second sidewall 300b1 may be at least 1.3 times the sixth width w6 of the spacer 119 of the bitline structure (BLS). For example, the ratio of the seventh width w7 to the sixth width w6 (seventh width w7 / sixth width w6) may be 1.3, 1.4, 1.5, 1.6 or greater, or any value or a range of values ​​between the foregoing values, but the invention is not limited thereto. In some embodiments, the second sidewall 300b1 may have a thickness that gradually increases along a direction away from the second bottom 300b2, for example, changing from a third thickness t3 to a fourth thickness t4.

[0095] like Figure 15B As shown, in some embodiments, the second portion 300b of the barrier layer 300 may include a tip portion TP, which may cover the top surface BLST and side surface BLSS of the bitline structure BLS. In other words, the tip portion TP may cover the top corner of the bitline structure BLS. Since the top corner of the bitline structure BLS is the first point of contact with any energy beam or etchant, it is most vulnerable to damage. Accordingly, the tip portion TP of the barrier layer 300 protects the bitline structure BLS.

[0096] Reference Figure 16A and Figure 16B As mentioned above. Figure 7A and Figure 7B When the second thickness t2 shown is 0, a semiconductor structure 2 can be obtained. In some embodiments, the first portion 300a of the barrier layer 300 may cover the side surface 310S of the planarization layer 310, and the bottom surface 310B of the planarization layer 310 may contact the interlayer dielectric layer 200.

[0097] In some embodiments, semiconductor structure 1 and / or 2 may serve as a memory device such as dynamic random access memory (DRAM), or may be formed as a memory device such as dynamic random access memory after further processing of semiconductor structure 1 and / or 2.

[0098] In summary, the semiconductor structure of the present invention may include a barrier layer, and the barrier layer includes a first portion disposed above the logic gate structure in the peripheral region and a second portion disposed above the bit line structure in the array region. For example, the first portion of the barrier layer can prevent leakage current between the logic gate structure and the first contact and / or prevent damage to the logic gate structure. For example, the second portion of the barrier layer can prevent leakage current between the bit line structure and the second contact and / or prevent damage to the bit line structure. Accordingly, the reliability of the semiconductor structure can be improved.

[0099] Furthermore, in the semiconductor structure formation method of the present invention, since the first and second portions of the barrier layer can respectively serve as masks to restrict the placement positions of the first and second contacts, a self-aligning effect can be achieved. Therefore, the barrier layer can prevent damage to other components during the formation process of the first or second contact. In addition, the first and second portions of the barrier layer can be formed simultaneously to simplify the process steps. Accordingly, the process margin of the formation method can be improved.

[0100] The above outlines several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, including a peripheral region and an array region; A logic gate structure is disposed in the peripheral region and on the substrate; A capping layer is disposed on the logic gate structure; An interlayer dielectric layer is disposed on the cover layer; A barrier layer includes a first portion located in the peripheral region and a second portion located in the array region, wherein the first portion is disposed on the interlayer dielectric layer and is located directly above the logic gate structure; and A first contact is disposed in the interlayer dielectric layer and contacts the substrate. The width of the logic gate structure is smaller than the width of the first part.

2. The semiconductor structure as described in claim 1, characterized in that, The first contacting object comes into contact with the first part.

3. The semiconductor structure as described in claim 1, characterized in that, The first contact object is spaced a distance from the side surface of the cover layer.

4. The semiconductor structure as described in claim 1, characterized in that: This first part further includes: First sidewall; and A first bottom, connected to the first sidewall, The width of the first sidewall is greater than the thickness of the first bottom.

5. The semiconductor structure as described in claim 1, characterized in that, Including: A single-line structure is disposed in the array region and on the substrate. The cover layer is disposed on the bit line structure, the second part is disposed on the cover layer and located directly above the bit line structure, and the width of the bit line structure is smaller than the width of the second part.

6. The semiconductor structure as described in claim 5, characterized in that: This second part further includes: A second sidewall; and A second bottom, connecting to the second sidewall, The width of the second sidewall is greater than the width of a spacer in the bit line structure.

7. The semiconductor structure as described in claim 5, characterized in that, The second part includes a pointed end that covers the top and side surfaces of the bit line structure.

8. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, wherein the substrate includes a peripheral region and an array region; A logic gate structure is formed in the peripheral region and on the substrate; A capping layer is formed on the logic gate structure; A dielectric layer is formed on the capping layer; A first trench is formed in the interlayer dielectric layer; A barrier layer is formed in the first trench; and A first contact is formed on the substrate; The width of the logic gate structure is smaller than the width of the first trench.

9. The forming method as described in claim 8, characterized in that, The formation of the first contact in the interlayer dielectric layer further includes: An opening is formed by using the barrier layer as a mask; and A contact material is filled into the opening to form the first contact.

10. The forming method as described in claim 8, characterized in that, Including: A one-bit line structure is formed in the array region and on the substrate; The capping layer is formed on the bit line structure; A conductive layer is formed on the capping layer; A second trench is formed in the conductive layer; The barrier layer is formed in the second trench; and A second contact is formed on the substrate; The width of the bit line structure is smaller than the width of the second trench.

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