Memory device and manufacturing method thereof, storage system

Abstract

This disclosure provides a memory device and its manufacturing method and memory system; wherein the memory device includes: a first semiconductor structure and a second semiconductor structure stacked in a first direction; the first semiconductor structure includes a connection region and a first circuit region; the connection region and the first circuit region are stacked in the first direction; the second semiconductor structure includes a second circuit region; wherein the memory device includes a first transistor and a second transistor, the first transistor being located in the first circuit region and the second transistor being located in the second circuit region.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a memory device and its manufacturing method and memory system. Background Technology

[0002] Memory can be broadly divided into two categories based on whether it retains stored data when power is off: volatile memory and non-volatile memory. Volatile memory loses its stored data when power is off, while non-volatile memory retains its stored data. In practical applications, non-volatile memory, such as NAND flash memory, has become increasingly widely used in electronic products due to its advantages of low power consumption and high integration density.

[0003] However, as the number of storage cell layers in NAND flash memory gradually increases, the structural layout of NAND flash memory has become an urgent problem to be solved. Summary of the Invention

[0004] According to one aspect of this disclosure, a memory device is provided, the memory device comprising: a first semiconductor structure and a second semiconductor structure stacked in a first direction; the first semiconductor structure including a connection region and a first circuit region stacked in the first direction; the second semiconductor structure including a second circuit region;

[0005] The memory device includes a first transistor and a second transistor, wherein the first transistor is located in the first circuit region and the second transistor is located in the second circuit region.

[0006] In some embodiments, the connection area is located between the first circuit area and the second circuit area.

[0007] In some embodiments, the first circuit region overlaps with the connection region and the second circuit region in the first direction.

[0008] In some embodiments, the connection area, the first circuit area, and the second circuit area have the same width in a second direction; the second direction is perpendicular to the first direction.

[0009] In some embodiments, the first semiconductor structure further includes: a plurality of memory regions arranged in the second direction; the connection region and the first circuit region are located between two adjacent memory regions; the second semiconductor structure further includes: a plurality of peripheral regions arranged in the second direction; the second circuit region is located between two adjacent peripheral regions; wherein, the memory region includes a memory channel structure, the connection region includes a dummy channel structure and a contact structure; the memory channel structure is coupled to the contact structure, and different dummy channel structures are respectively connected to the gate, source or drain of the first transistor.

[0010] In some embodiments, the other end of the dummy channel structure connected to the drain of the first transistor is connected to the contact structure; and the other end of the dummy channel structure connected to the gate or source of the first transistor is connected to the second transistor; or, the other end of the dummy channel structure connected to the gate or source of the first transistor is connected to the circuit in the peripheral region.

[0011] In some embodiments, the first semiconductor structure further includes a third transistor; the positive terminal of the third transistor is coupled to the gate of the first transistor.

[0012] In some embodiments, the number of first transistors disposed in the first circuit region is multiple, and the multiple first transistors are independent of each other.

[0013] In some embodiments, the memory device includes a word line driver circuit, which includes the first transistor and the second transistor.

[0014] According to one aspect of this disclosure, a storage system is provided, comprising: a memory device as described in the above embodiments of this disclosure; and a memory controller connected to the memory device and configured to control the memory device.

[0015] According to one aspect of this disclosure, a method for manufacturing a memory device is provided, the method comprising: forming a first semiconductor structure and a second semiconductor structure stacked in a first direction; the first semiconductor structure including a connection region and a first circuit region stacked in the first direction; the second semiconductor structure including a second circuit region; wherein the memory device includes a word line driver circuit, the word line driver circuit including a first transistor and a second transistor, the first transistor being located in the first circuit region; and the second transistor being located in the second circuit region.

[0016] In some embodiments, the method further includes: forming a plurality of memory regions arranged in a second direction in the first semiconductor structure, such that the connection region and the first circuit region are located between two adjacent memory regions; and forming a plurality of peripheral regions arranged in the second direction in the second semiconductor structure, such that the second circuit region is located between two adjacent peripheral regions; the second direction is perpendicular to the first direction; and forming a memory channel structure in the memory regions, forming a dummy channel structure and a contact structure in the connection regions, such that the memory channel structure is coupled to the contact structure, and different dummy channel structures are respectively connected to the gate, source, or drain of the first transistor.

[0017] In some embodiments, the method further includes: connecting the other end of the dummy channel structure connected to the drain of the first transistor to the contact structure; and connecting the other end of the dummy channel structure connected to the gate or source of the first transistor to the second transistor; or connecting the other end of the dummy channel structure connected to the gate or source of the first transistor to a circuit in the peripheral region.

[0018] In some embodiments, the method further includes: forming a third transistor in the first semiconductor structure, and coupling the positive terminal of the third transistor to the gate of the first transistor.

[0019] In some embodiments, the method further includes: forming a plurality of the first transistors in the first circuit region, and making the plurality of the first transistors independent of each other.

[0020] In this embodiment of the disclosure, by dividing the circuit area into a first circuit area and a second circuit area, and stacking the first circuit area and the second circuit area in a vertical direction, the width of the circuit area in the horizontal direction (perpendicular to the vertical direction) can be reduced. At the same time, the transistors in the memory device are divided into two parts, such as a first transistor and a second transistor, and these two parts of transistors are placed in the first circuit area and the second circuit area respectively. In this way, the overall size of the memory device in the horizontal direction can be reduced without affecting the normal operation of the transistors, thereby achieving the purpose of reducing manufacturing costs. Attached Figure Description

[0021] Figure 1 A schematic diagram of an electronic device provided according to an embodiment of this disclosure;

[0022] Figure 2a This is a schematic diagram of a memory device structure provided in an embodiment of the present disclosure;

[0023] Figure 2bThis is a schematic diagram of the structure of a NAND flash memory cell array provided in an embodiment of the present disclosure;

[0024] Figure 3 A schematic diagram of a storage cell array including NAND flash memory strings provided in an embodiment of this disclosure;

[0025] Figure 4 This is a schematic diagram of the architecture of a NAND-type memory device provided in an embodiment of the present disclosure;

[0026] Figure 5 This is a schematic diagram of the structural layout of a memory device provided in an embodiment of the present disclosure;

[0027] Figure 6 for Figure 5 The diagram shows the structure of the memory device.

[0028] Figure 7 This is a top view of at least a portion of the first semiconductor structure in the XY plane;

[0029] Figure 8 A cross-sectional view of at least a portion of the first semiconductor structure in the XZ plane;

[0030] Figures 9 to 12 This is a schematic flowchart of a method for manufacturing a memory device according to an embodiment of the present disclosure;

[0031] Figure 13 This is a schematic diagram of a storage system provided in an embodiment of the present disclosure.

[0032] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The figures illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Implementation

[0033] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0034] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0035] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0036] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “below” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0038] To gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.

[0039] The memory device involved in the embodiments of this disclosure may be at least a part of the final device structure. Here, the final device may include, but is not limited to, NAND flash memory, vertical NAND flash memory, NOR flash memory, dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), nano random access memory (NRAM), etc. For ease of understanding, the following description uses only NAND type memory as an example. However, it should be noted that the following description of NAND type memory is only used to illustrate this disclosure and is not intended to limit the scope of this disclosure.

[0040] refer to Figure 1 , Figure 1 This is a schematic diagram of an electronic device provided in an embodiment of this disclosure. The electronic device 1 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein.

[0041] like Figure 1 As shown, electronic device 1 may include a storage system 10 and a host 20. The storage system 10 may include a memory controller 110 and a memory device 120. The host 20 may include a processor of electronic device 1, such as a central processing unit (CPU) or a system-on-chip (SoC) (e.g., an application processor (AP)). The memory controller 110 is coupled to both the host 20 and the memory device 120. The memory controller 110 may be configured to communicate with the host 20 and control the memory device 120.

[0042] In some embodiments, the memory controller 110 may be configured to control the operation of the memory device 120, such as read operations, erase operations, write operations, refresh operations, etc. In some embodiments, the memory controller 110 is also configured to process error correction codes (ECCs) regarding data read from or written to the memory device 120. In other embodiments, the memory controller 110 may also be configured to perform any other suitable operation, such as formatting the memory device 120.

[0043] In some embodiments, the memory controller 110 can receive data, commands, and addresses from the host 20, and can send data, commands, and addresses to the memory device 120. Specifically, the memory controller 110 may include a command generator 111, an address generator 112, a device interface 113, and a host interface 114. The memory controller 110 can receive data, commands, and addresses from the host 20 through the host interface 114, decode the commands received from the host 20 through the command generator 111 to generate an access command CMD, and provide the access command CMD to the memory device 120 through the device interface 113. The memory controller 110 can decode the addresses received from the host interface 114 through the address generator 112 to generate an address ADDR to be accessed in the memory cell array 121, and provide the address ADDR to be accessed to the memory device 120 through the device interface 113. The access command may be a signal instructing the memory device 120 to write or read data by accessing one or more memory cells in the memory cell array 121 corresponding to the address ADDR. In addition, the memory controller 110 can also send a refresh command to the memory device 120. The refresh command can be a signal instructing the memory device 120 to read and rewrite data by accessing one or more memory cells in the memory cell array 121 corresponding to the address ADDR.

[0044] In some embodiments, in conjunction with reference Figure 1 and Figure 2a , Figure 2b The memory device 120 includes a memory cell array 121 and peripheral circuitry 122. Here, the memory cell array 121 may be a NAND flash memory cell array, wherein the memory cells are arranged in the form of an array of NAND memory strings 208, each NAND memory string 208 extending vertically above the substrate. Figure 2b An exemplary schematic diagram of a NAND flash memory cell array is provided, such as... Figure 2bAs shown, the NAND flash memory cell array consists of several rows of parallel, staggered cells parallel to the gate isolation structure. Each pair of cells is separated by a gate isolation structure and an up-select gate isolation structure. Each cell row includes multiple cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the cell array into multiple blocks, and the multiple second gate isolation structures can divide each block into multiple sub-blocks. Figure 2b The storage block shown contains 6 sub-blocks. In practical applications, the number of sub-blocks in a storage block is not limited to this.

[0045] In some embodiments, each NAND memory string 208 may include a plurality of memory cells 206 that are series-coupled and vertically stacked. Each memory cell 206 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped within the memory cell region. Additionally, each memory cell 206 in the aforementioned memory cell array 121 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0046] like Figure 2a As shown, each NAND flash memory string 208 may include a source select transistor 210 at its source terminal and a drain select transistor 212 at its drain terminal. The source select transistor may also be referred to as the lower select transistor, and the drain select transistor may also be referred to as the upper select transistor. The source select transistor 210 and the drain select transistor 212 may be configured to activate the selected NAND flash memory string 208 (column of the array) during read and program operations.

[0047] In some implementations, the sources of NAND memory strings 208 within the same block 204 are coupled via a common source line (SL) 214 (e.g., a common source line). In other words, according to some implementations, all NAND memory strings 208 within the same block 204 have an array common source (ACS). According to some implementations, the drain selection transistor 212 of each NAND memory string 208 is coupled to a corresponding bit line 216, allowing data to be read from or written to the bit line 216 via an output bus (not shown).

[0048] In some embodiments, each NAND flash memory string 208 is configured to be selected or deselected by applying a selection voltage (e.g., higher than a threshold voltage having a drain-select transistor 212) or a deselect voltage (e.g., 0V) to the gate of the corresponding drain-select transistor 212 via one or more drain-select gate lines (DSG lines) 213; and / or by applying a selection voltage (e.g., higher than a threshold voltage having a source-select transistor 210) or a deselect voltage (e.g., 0V) to the gate of the corresponding source-select transistor 210 via one or more source-select gate lines 215. The NAND flash memory strings 208 can thus be distinguished as selected NAND flash memory strings or unselected NAND flash memory strings. The selection voltage can also be referred to as a control turn-on voltage, used to turn on the corresponding transistor, and the deselect voltage can also be referred to as a control turn-off voltage, used to turn off the corresponding transistor.

[0049] like Figure 2a As shown, the NAND storage string 208 can be organized into multiple blocks 204, each of which can have a common source line 214 (e.g., coupled to ground). In some embodiments, each block 204 is a basic data unit for an erase operation, i.e., all memory cells 206 on the same block 204 are erased simultaneously. To erase memory cells 206 in a selected block, an erase voltage (Vers), such as a high positive voltage (e.g., 20V or higher), can be used to bias the source line 214 of the selected block and the unselected blocks on the same plane as the selected block. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at any suitable number of blocks or any suitable fraction of blocks.

[0050] Storage cells 206 of adjacent NAND storage strings 208 can be coupled via word lines 218, which select which row of storage cells 206 is affected by read and program operations. In some embodiments, each word line 218 is coupled to a page of storage cell 206, where a page is the basic unit of data used for programming operations.

[0051] refer to Figure 3 , Figure 3 This is a schematic diagram of a memory cell array including NAND memory strings, provided for an embodiment of this disclosure. The NAND memory strings 208 may extend vertically through the memory stack layer 304 above the substrate 302. The substrate 302 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0052] The memory stack 304 may include alternating gate conductive layers 306 and dielectric layers 308, wherein the number of pairs of gate conductive layers 306 and dielectric layers 308 determines the number of memory cells 206 in the memory cell array 121. The gate conductive layer 306 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 306 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 306 includes a doped polysilicon layer. The gate conductive layer 306 may extend laterally at the top of the memory stack 304 as a drain select gate line 213, laterally at the bottom of the memory stack 304 as a source select gate line 215, or laterally between the drain select gate line 213 and the source select gate line 215 as a word line 218. It should be understood that although... Figure 2a The diagram shows a source select gate line (SSG line) 215 and a drain select gate line (DSG line) 213, but the number of source select gate lines 215 and drain select gate lines 213 (and the number of source select transistors 210 and drain select transistors 212 coupled to source select gate lines 215 and drain select gate lines 213, respectively) can vary in other examples.

[0053] like Figure 3 As shown, the NAND flash memory string 208 includes a channel structure 312 extending vertically through the memory stack layer 304. In some embodiments, the channel structure 312 includes channel vias filled with a semiconductor material (e.g., as a semiconductor channel 320) and a dielectric material (e.g., as a memory film 318). In some embodiments, the semiconductor channel 320 includes silicon, for example, polysilicon. In some embodiments, the memory film 318 is a composite dielectric layer including a tunneling layer 326, a storage layer 324 (also referred to as a "charge trapping layer"), and a barrier layer 322. The channel structure 312 may have a pillar shape (e.g., a cylindrical shape). According to some embodiments, the semiconductor channel 320, tunneling layer 326, storage layer 324, and barrier layer 322 are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer 326 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 324 may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer 322 may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film 318 may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0054] In some embodiments, such as Figure 3As shown, a well 314 (e.g., a P-well and / or an N-well) is formed in the substrate 302, and the source terminal of the NAND memory string 208 is in contact with the well 314. For example, a source line 214 may be coupled to the well 314 to apply an erase voltage to the well 314 (i.e., the source of the NAND memory string 208) during an erase operation. In some embodiments, the NAND memory string 208 also includes a channel plug 316 at the drain terminal of the NAND memory string 208, for example, as part of the drain terminal of the NAND memory string 208. It should be understood that... Figure 3 The structure of the channel structure 312 depicted is for illustrative purposes only and may be modified in other examples. It should be understood that, although in Figure 3 Additional components, not shown, may also form the memory cell array. These additional components include, but are not limited to, gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0055] Return to reference Figure 2a The peripheral circuitry 122 can be coupled to the memory cell array 121 via bit line 216, word line 218, source line 214, source select gate line 215, and drain select gate line 213. The peripheral circuitry 122 can include any suitable analog, digital, and mixed-signal circuitry for implementing write and read operations on the memory cell array 121 by applying voltage and / or current signals to each target memory cell 206 and sensing voltage and / or current signals from each target memory cell 206 via bit line 216, word line 218, source line 214, source select gate line 215, and drain select gate line 213. The peripheral circuitry 122 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, the peripheral circuitry 122 can include page buffers / sensor amplifiers, column decoders / BL drivers, row decoders / WL drivers, voltage generators, control logic units, registers, interfaces (I / F), and data buses. The peripheral circuit 122 can be used to receive access command CMD and address ADDR. Based on the parsing of access command CMD and address ADDR, it can independently access each memory cell in memory cell array 121 and perform read, write or refresh operations on the data stored in the accessed memory cell.

[0056] In some embodiments, reference Figure 4 , Figure 4The diagram illustrates one architecture of a NAND flash memory device. The memory device 400 includes a first device 401 and a second device 402. A memory cell array 121 is located in the first device 401, and peripheral circuitry 122 is located in the second device 402. The first device 401 and the second device 402 are connected via a bonding interface 403. It should be noted that the first device 401 and the second device 402 can be connected at the bonding interface 403 using methods such as hybrid bonding, or they can be integrated on the same substrate and directly connected at the bonding interface 403 through one or more interconnect layers.

[0057] As 3D NAND products iterate, storage density can be increased by increasing the number of memory stacking layers in the first device 401; however, increasing the number of memory stacking layers (i.e., increasing the number of memory cells) leads to a corresponding increase in the size of various structures or circuits; for example, refer to Figure 4 The first device 401 also includes a connection region 405, in which contact structures can be disposed. The second device 402 also includes a circuit region 406, in which various transistors can be disposed to form various logic circuits. As the number of memory cells increases, the number of contact structures connecting to the memory cells increases, resulting in an increase in the size of the connection region. Correspondingly, as the number of memory cells increases, the number of transistors used to interact with the memory cells increases, resulting in an increase in the size of the circuit region. In this case, the overall size of the first and second devices increases, and the size increase of the second device is relatively greater. Therefore, as the overall size of memory devices tends to be miniaturized, controlling the size of the circuit region becomes an urgent problem to be solved.

[0058] Based on one or more of the above-mentioned problems, this disclosure provides a memory device comprising: a first semiconductor structure and a second semiconductor structure stacked in a first direction; the first semiconductor structure including a connection region and a first circuit region stacked in the first direction; the second semiconductor structure including a second circuit region; wherein the memory device further includes a first transistor and a second transistor, the first transistor being located in the first circuit region and the second transistor being located in the second circuit region.

[0059] In this way, by splitting the circuit area into a first circuit area and a second circuit area, and stacking the first circuit area and the second circuit area vertically, the width of the circuit area in the horizontal direction (perpendicular to the vertical direction) can be reduced. At the same time, the transistors in the memory device can be split into two parts, such as a first transistor and a second transistor, and these two parts of transistors can be placed in the first circuit area and the second circuit area respectively. In this way, the overall size of the memory device in the horizontal direction can be reduced without affecting the normal operation of the transistors, thereby achieving the goal of reducing manufacturing costs.

[0060] The specific structure of the memory device described above will be described in detail below with reference to the accompanying drawings. Before describing the memory device, the various directions that may be used in the following description are defined. Here, the stacking direction of the first semiconductor structure and the second semiconductor structure is defined as the first direction (Z-axis direction). A second direction (X-axis direction) and a third direction (Y-axis direction) that intersect are defined in a plane perpendicular to the Z-axis direction. In some embodiments, the X-axis direction, the Y-axis direction, and the Z-axis direction can be mutually perpendicular.

[0061] refer to Figure 5 , Figure 5 This is a schematic diagram of the structural layout of a memory device 500 provided in an embodiment of the present disclosure; as shown... Figure 5 As shown, the first semiconductor structure 501 and the second semiconductor structure 502 are stacked in the Z-axis direction, and the first semiconductor structure 502 and the second semiconductor structure 502 can be bonded together through a bonding interface 503. In some specific embodiments, refer to... Figure 6 The first semiconductor structure 501 and the second semiconductor structure 502 are bonded together through a bonding contact 5032 located at the bonding interface 503.

[0062] The first semiconductor structure 501 includes a connection region 5011 and a first circuit region 5012 stacked in the Z-axis direction. The arrangement of the connection region 5011 and the first circuit region 5012 in the Z-axis direction can be selected according to actual needs. Here, the connection region 5011 is located on the side of the first circuit region 5012 closer to the second semiconductor structure 502 in the Z-axis direction, that is, the connection region 5011 is closer to the second semiconductor structure 502.

[0063] In this embodiment of the disclosure, the first semiconductor structure 501 further includes a plurality of memory regions arranged in the X-axis direction, with the connection region 5011 and the first circuit region 5012 located between two adjacent memory regions in the X-axis direction. For example, refer to... Figure 5 Two adjacent storage areas in the X-axis direction are the first storage area 5013 and the second storage area 5014, and the connection area 5011 and the first circuit area 5012 are located between the first storage area 5013 and the second storage area 5014.

[0064] In this embodiment of the disclosure, the second semiconductor structure 502 includes a second circuit region 5022 and a plurality of peripheral regions arranged in the X-axis direction, wherein the second circuit region 5022 is located between two peripheral regions arranged adjacent to each other in the X-axis direction. For example, refer to... Figure 5 The two peripheral regions arranged adjacent to each other in the X-axis direction are the first peripheral region 5021 and the second peripheral region 5023, and the second circuit region 5022 is located between the first peripheral region 5021 and the second peripheral region 5023.

[0065] In some embodiments, reference Figure 5 The second circuit region 5022, the connection region 5011, and the first circuit region 5012 are stacked along the Z-axis. Here, the connection region 5011 is located between the first circuit region 5012 and the second circuit region 5022.

[0066] In some embodiments, the first circuit region 5012 overlaps with the connection region 5011 and the second circuit region 5022 in the Z-axis direction.

[0067] In some embodiments, the connection area 5011, the first circuit area 5012, and the second circuit area 5022 have the same width in the X-axis direction.

[0068] It should be noted that the connection area 5011 is provided with a connection structure (the dummy channel structure described below). The connection structure is used to connect with the logic circuits (such as transistors) in the first circuit area 5012 and the second circuit area 5022 respectively. When the connection area 5011 is located between the first circuit area 5012 and the second circuit area 5022, the size of the connection structure can be shortened, thereby reducing signal delay. Furthermore, when the connection area 5011, the first circuit area 5012, and the second circuit area 5022 overlap in the Z-axis direction, the size of the connection structure can be further reduced, thereby further reducing signal delay and improving signal transmission efficiency.

[0069] For example, refer to Figure 6 , Figure 6 for Figure 5 The diagram shows a partial structural schematic of a memory device 500. The memory device 500 includes a word line driver circuit, which includes a first transistor 601 and a second transistor 602. The first transistor 601 is disposed in a first circuit region 5012, and the second transistor 602 is disposed in a second circuit region 5022. Both the first transistor 601 and the second transistor 602 can be metal-oxide-semiconductor (CMOS) transistors.

[0070] refer to Figure 6The memory device 500 also includes a memory channel structure 603, a contact structure 604, a dummy channel structure 605, a gate line slit (GLS) 608, and a common source line 612. The memory channel structure 603 and the gate line slit 608 are located in a memory region (such as a first memory region 5013), extending along the Z-axis, and one end of each memory channel structure 603 is connected to the common source line 612. The contact structure 604 and the dummy channel structure 605 are located in a connection region 5011, and are used to connect to different transistors.

[0071] refer to Figure 6 The first storage region 5013 has a stacked structure comprising alternating gate conductive layers and dielectric layers. A gate isolation structure 608 and a storage channel structure 603 are arranged along the X-axis and penetrate the stacked structure along the Z-axis. Here, the gate isolation structure 608 can divide a block into multiple sub-storage blocks. The storage channel structure 603 includes a channel via, a memory film located within the channel via, and a semiconductor channel located at the center of the memory film. In some embodiments, the memory film is a composite dielectric layer, including a tunneling layer, a storage layer, and a barrier layer. The storage channel structure may have a pillar shape (e.g., a cylindrical shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. In one example, the memory film may include a composite layer composed of silicon oxide / silicon oxynitride / silicon oxide (ONO). The gate isolation structure 608 may include silicon oxide / polysilicon, etc.

[0072] A stacked structure is provided in the connection region 5011, comprising alternating gate conductive layers and dielectric layers; contact structures 604 and dummy channel structures 605 are arranged along the X-axis and both extend along the Z-axis. The contact structure 604 includes a conductive structure penetrating a portion of the stacked structure and extending to the corresponding gate conductive layer, and an insulating structure surrounding the sidewalls of the conductive structure; the conductive structure extends along the Z-axis, and the insulating structure isolates the conductive structure from other non-connected gate conductive layers. The material of the conductive structure includes, but is not limited to, tungsten (W), and the material of the insulating structure includes, but is not limited to, silicon oxide (SiO2). Here, the dummy channel structure 605 can be the same as the memory channel structure 603, such as including a channel hole, a memory film located in the channel hole, and a semiconductor channel located at the center of the memory film. The dummy channel structure 605 can be used for support and for transmitting electrical signals, etc.

[0073] The methods for forming the memory channel structure 603, contact structure 604, dummy channel structure 605 and gate isolation structure 608 include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD) and atomic layer deposition (ALD) processes.

[0074] Continue to refer to Figure 6 The number of contact structures 604 and dummy channel structures 605 can be multiple. One end of each contact structure 604 is connected to the storage channel structure 603 through a corresponding gate conductive layer, and the other end of the contact structure 604 can be connected to other devices. A dummy channel structure 605 can be connected to a first transistor at one end and a second transistor at the other end, or it can be connected to the first transistor at one end and other circuits at the other end. However, it should be understood that the gate (G), source (S), and drain (D) of the first transistor 601 are each connected to different dummy channel structures 605. Here, of the other ends of the multiple dummy channel structures 605 connected to the gate (G), source (S), and drain (D) of the first transistor 601, a portion are connected to the contact structure 604 at the other end, and another portion are connected to other circuits (such as circuits in the peripheral area).

[0075] For example, one end of the dummy channel structure 605 connected to the drain (D) of the first transistor 601 is connected to the contact structure 604, and the other end of the dummy channel structure 605 connected to the gate (G) or source (S) of the first transistor 601 is connected to the second transistor 602. Alternatively, one end of the dummy channel structure 605 connected to the drain (D) of the first transistor 601 is connected to the contact structure 604, and the other end of the dummy channel structure 605 connected to the gate (G) or source (S) of the first transistor 601 is connected to the circuitry in the peripheral region (first peripheral region 5021 or second peripheral region 5023).

[0076] In some embodiments, the number of first transistors 601 in the first circuit region 5012 may include multiple transistors, and the multiple first transistors 601 are independent of each other. Here, independence can be understood as the multiple first transistors 601 not sharing a common source or drain.

[0077] refer to Figure 7 and Figure 8 , Figure 7 This is a top view of at least a portion of the first semiconductor structure 501 in the XY plane; Figure 8 A cross-sectional view of at least a portion of the first semiconductor structure 501 in the XZ plane; Figure 7The AA region shown can be understood as the active region corresponding to the word line driver circuit in the first semiconductor structure. Among them, Figure 7 The first semiconductor structure shown includes two first transistors (such as 601(A) and 601(B)). The first first transistor 601(A) and the second first transistor 601(B) are independently disposed and separated by a gate isolation structure 608. The source (S) of the second first transistor 601(B) is connected to the PC1 terminal, which is used to connect to external devices.

[0078] Reference Figure 7 and Figure 8 The gate (G) of the first transistor 601 is connected to the dummy channel structure 605(a). The end of the dummy channel structure 605(a) away from the first transistor 601 can be connected to the second transistor or to other circuits in the peripheral area.

[0079] The source (S) of the first transistor 601 is connected to the dummy channel structure 605(b) through the metal line layer 609. The end of the dummy channel structure 605(b) away from the first transistor 601 can be connected to the second transistor or to other circuits in the peripheral area.

[0080] The drain (D) of the first transistor 601 is connected to the dummy channel structure 605(c) through a metal wire layer. The end of the dummy channel structure 605(c) away from the first transistor 601 can be connected through a connection structure ( Figure 8 (Not shown in the diagram) is connected to contact structure 604.

[0081] Here, the multiple first transistors are set up independently (i.e., they do not share a drain). On the one hand, this facilitates the first transistors in the first semiconductor structure to be led out through the PC1 terminal. On the other hand, during the formation of the gate isolation structure and the first transistors, the manufacturing process is prevented from interfering with each other, thus improving the reliability of the memory device.

[0082] In some embodiments, reference Figure 8 The memory device also includes a third transistor 606, which can be an N-type diode. Here, the third transistor 606 is located in the first semiconductor structure 501, and one end of the third transistor 606 (e.g., the positive terminal) is coupled to the gate of the first transistor 601.

[0083] It should be noted that the gate of the first transistor is connected to the dummy channel structure. The formation of the dummy channel structure typically involves plasma etching. The plasma energy and dosage of the plasma etching process usually affect the gate (e.g., gate oxide layer, GOX) of the first transistor, causing plasma-induced damage (PID). Therefore, in the above embodiments of this disclosure, a third transistor (i.e., a diode) is provided in the first semiconductor structure, and the anode of the diode is connected to the gate of the first transistor. This can improve plasma-induced damage. Furthermore, based on the improvement of plasma-induced damage, a complete gate can be formed, thereby improving the integration density of the memory device.

[0084] In some embodiments, the gates of all first transistors on the same block can be connected to a third transistor (the positive terminal of a diode) to reduce manufacturing processes and costs.

[0085] In some embodiments, the overall size of the third transistor is larger than that of the first transistor, which can resolve the impact of the higher voltage domain of the word line driver circuit.

[0086] In some embodiments, reference Figure 6 The memory device 500 further includes a dielectric layer 610; the dielectric layer 610 is located on the side of the first semiconductor structure 501 opposite to the second semiconductor structure 502 in the Z-axis direction. The material of the dielectric layer 610 includes insulating materials, such as silicon, silicon oxide, etc. Methods for forming the dielectric layer 610 include, but are not limited to, PVD, CVD, ALD, etc. It should be understood that the dielectric layer may be located on the side of the first semiconductor structure away from the second semiconductor structure in the Z-axis direction (e.g., ...). Figure 6 (As shown), it can also be located on the side of the second semiconductor structure away from the first semiconductor structure in the Z-axis direction, and this disclosure does not limit it in this way.

[0087] In some embodiments, reference Figure 6 The memory device also includes pads 611, which are located in the dielectric layer 610. Here, pads 611 can be coupled to the first transistor 601 to enable electrical signal interconnection between the first transistor 601 and external devices. The materials of the pads include, but are not limited to, metallic materials such as tungsten, aluminum, and copper. Methods for forming the pads include, but are not limited to, PVD, CVD, and ALD.

[0088] Based on the above-described memory device, this disclosure also provides a method for manufacturing a memory device, the method comprising: forming a first semiconductor structure and a second semiconductor structure stacked in a first direction; the first semiconductor structure including a connection region and a first circuit region stacked in the first direction; the second semiconductor structure including a second circuit region; wherein the memory device includes a first transistor and a second transistor, the first transistor being located in the first circuit region and the second transistor being located in the second circuit region. It should be understood that the order in which the first semiconductor structure and the second semiconductor structure are formed can be interchanged. In some embodiments, the memory device includes a word line driver circuit, the word line driver circuit including a first transistor and a second transistor.

[0089] In some embodiments, reference Figure 9 and Figure 10 Forming a first semiconductor structure includes: providing a substrate and dividing the substrate into a first region 902 and a second region 903 arranged in the X-axis direction. A buried layer 904 is formed in the first region 902, the buried layer 904 being used to form a common source line in a subsequent process. A first transistor 905 is formed in the second region 903 to form a first circuit region 913, thereby forming the first semiconductor structure. The first transistor 905 can be a CMOS transistor, which may include a source (S), a drain (D), and a gate (G). The number of first transistors 905 may include one or more.

[0090] In some embodiments, the method includes: forming a plurality of first transistors in a first circuit region, and making the plurality of first transistors independent of each other.

[0091] refer to Figure 10 Alternating gate conductive layers and dielectric layers are formed on the substrate to form a stacked structure 906; the stacked structure 906 can be divided into a third region 907 and a fourth region 908 arranged in the X-axis direction; the third region 907 is located on one side of the first region 902 in the Z-axis direction; the fourth region 908 is located on one side of the second region 903 in the Z-axis direction.

[0092] A memory channel structure 909 and a gate isolation structure 910 are formed in a third region 907 to form a first memory region 911. The memory channel structure 909 and the gate isolation structure 910 can be arranged in the X-axis direction and extend into the first region 902 along the Z-axis direction. The memory channel structure 909 includes a semiconductor channel, a tunneling layer, a memory layer, and a barrier layer arranged radially from the center of the pillar towards the outer surface of the pillar in sequence. The gate isolation structure 910 is made of an insulating material, such as silicon oxide / polysilicon. Methods for forming the memory channel structure 909 and the gate isolation structure 910 include, but are not limited to, PVD, CVD, and ALD. It should be noted that a buried layer 904 is connected to the semiconductor channel in each memory channel structure 909; this buried layer is the common source line, and one end of multiple memory channel structures is connected to the common source line. In other embodiments, the buried layer may also extend into a second region along the X-axis direction; this disclosure does not limit this.

[0093] In addition, the order in which the stacked structure and the memory channel / gate isolation structure are formed can be selected according to actual needs. For example, one layer of the stacked structure can be formed first, then the memory channel / gate isolation structure can be formed, and finally the other layer of the stacked structure can be formed; this disclosure does not limit this.

[0094] A contact structure 914 and a dummy channel structure 915 are formed in the fourth region 908 to form a connection region 912. It should be understood that the connection region 912 and the first circuit region 913 are stacked along the Z-axis. (See reference...) Figure 10 The contact structure 914 and the dummy channel structure 915 are arranged in the X-axis direction, and both the contact structure 914 and the dummy channel structure 915 extend along the Z-axis direction. Here, the number of dummy channel structures and contact structures can both be multiple.

[0095] It should be noted that the first semiconductor structure may include multiple memory regions, such as a first memory region, a second memory region, and so on. Figure 10 The first storage area is shown only as an example, and the first storage area is formed in the same way as the second and third storage areas.

[0096] In some embodiments, the method further includes: forming a third transistor in a first semiconductor structure, and coupling the positive terminal of the third transistor to the gate of the first transistor.

[0097] In some embodiments, reference Figure 11 Forming the second semiconductor structure includes: providing a substrate, dividing the substrate into two regions (or even more regions) arranged in the X-axis direction. Figure 11(Only two regions are shown in the diagram). A second transistor 918 is formed in one region to form a second circuit region 917. Other circuitry is formed in the other region to form a first peripheral region 916. Here, the second circuit region 917 is located between two adjacent peripheral regions. The second transistor 918 can be a CMOS transistor, including a source (S), a drain (D), and a gate (G). The number of second transistors 918 can include one or more. Here, the first peripheral region 916 and the second circuit region 917 (or even more regions) constitute a second semiconductor structure.

[0098] In some embodiments, reference Figure 12 The method further includes: bonding a first semiconductor structure and a second semiconductor structure in the Z-axis direction to form a first semiconductor structure and a second semiconductor structure stacked in the Z-axis direction. The first semiconductor structure and the second semiconductor structure are bonded together at a bonding interface 919 via bonding contacts 920. Here, the bonding method includes, but is not limited to, hybrid bonding.

[0099] In some embodiments, the method further includes: during the bonding process between the first semiconductor structure and the second semiconductor structure, connecting one end of a dummy channel structure connected to the drain of the first transistor to a contact structure, and connecting one end of a dummy channel structure connected to the gate or source of the first transistor to the second transistor. Alternatively, connecting one end of a dummy channel structure connected to the drain of the first transistor to a contact structure; and connecting one end of a dummy channel structure connected to the gate or source of the first transistor to a circuit in the peripheral region.

[0100] Based on the above-described memory device, this disclosure also provides a memory system 1300, see reference. Figure 13 The storage system 1300 includes: a memory device 1200 as described in the above embodiments of the present disclosure; and a memory controller 1400 connected to the memory device 1200 and used to control the memory device 1200.

[0101] The scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory device, characterized in that, include: A first semiconductor structure and a second semiconductor structure are stacked and disposed in a first direction; The first semiconductor structure includes a connection region and a first circuit region stacked in the first direction; The second semiconductor structure includes a second circuit region; The memory device includes a first transistor and a second transistor, wherein the first transistor is located in the first circuit region and the second transistor is located in the second circuit region.

2. The memory device according to claim 1, characterized in that, The connection area is located between the first circuit area and the second circuit area.

3. The memory device according to claim 2, characterized in that, The first circuit region overlaps with the connection region and the second circuit region in the first direction.

4. The memory device according to claim 3, characterized in that, The connection area, the first circuit area, and the second circuit area have the same width in the second direction; the second direction is perpendicular to the first direction.

5. The memory device according to claim 4, characterized in that, The first semiconductor structure further includes: a plurality of memory regions arranged in the second direction; the connection region and the first circuit region are located between two adjacent memory regions; the second semiconductor structure further includes: a plurality of peripheral regions arranged in the second direction; the second circuit region is located between two adjacent peripheral regions; The storage region includes a storage channel structure, and the connection region includes a dummy channel structure and a contact structure. The storage channel structure is coupled to the contact structure, and different dummy channel structures are respectively connected to the gate, source, or drain of the first transistor.

6. The memory device according to claim 5, characterized in that, The other end of the dummy channel structure, connected to the drain of the first transistor, is connected to the contact structure; and The other end of the dummy channel structure, which is connected to the gate or source of the first transistor, is connected to the second transistor. Alternatively, the other end of the dummy channel structure connected to the gate or source of the first transistor is connected to the circuitry in the peripheral region.

7. The memory device according to claim 1, characterized in that, The first semiconductor structure further includes a third transistor; the positive electrode of the third transistor is coupled to the gate of the first transistor.

8. The memory device according to claim 1, characterized in that, The number of first transistors disposed in the first circuit area is multiple, and the multiple first transistors are independent of each other.

9. The memory device according to claim 1, characterized in that, The memory device includes a word line driver circuit, which includes the first transistor and the second transistor.

10. A storage system, characterized in that, include: The memory device as described in any one of claims 1-9; And a memory controller, connected to the memory device and used to control the memory device.

11. A method for manufacturing a memory device, characterized in that, The method includes: A first semiconductor structure and a second semiconductor structure are formed and stacked in a first direction; The first semiconductor structure includes a connection region and a first circuit region stacked in the first direction; the second semiconductor structure includes a second circuit region. The memory device includes a first transistor and a second transistor, wherein the first transistor is located in the first circuit region and the second transistor is located in the second circuit region.

12. The manufacturing method according to claim 11, characterized in that, The method further includes: In the first semiconductor structure, a plurality of memory regions arranged in a second direction are formed, such that the connection region and the first circuit region are located between two adjacent memory regions; and in the second semiconductor structure, a plurality of peripheral regions arranged in the second direction are formed, such that the second circuit region is located between two adjacent peripheral regions; the second direction is perpendicular to the first direction; and A storage channel structure is formed in the storage region, a dummy channel structure and a contact structure are formed in the connection region, and the storage channel structure is coupled to the contact structure. Different dummy channel structures are respectively connected to the gate, source or drain of the first transistor.

13. The manufacturing method according to claim 12, characterized in that, The method further includes: The other end of the dummy channel structure, which is connected to the drain of the first transistor, is connected to the contact structure; and The other end of the dummy channel structure connected to the gate or source of the first transistor is connected to the second transistor; or, the other end of the dummy channel structure connected to the gate or source of the first transistor is connected to the circuit in the peripheral region.

14. The manufacturing method according to claim 13, characterized in that, The method further includes: A third transistor is formed in the first semiconductor structure, and the positive terminal of the third transistor is coupled to the gate of the first transistor.

15. The manufacturing method according to claim 14, characterized in that, The method further includes: A plurality of the first transistors are formed in the first circuit region, and the plurality of the first transistors are made independent of each other.

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