Semiconductor device and method of manufacturing semiconductor device

Abstract

This application relates to a semiconductor device and a method of manufacturing a semiconductor device. A semiconductor device includes: a gate structure including a source select line, a drain select line, and a word line stacked between the source select line and the drain select line; a second channel layer penetrating the source select line and including polysilicon; a third channel layer penetrating the drain select line and including polysilicon; a first channel layer penetrating the word line, connecting the second channel layer and the third channel layer, and including molybdenum disulfide (MoS2); and an insulating core disposed within the first channel layer.

Description

Technical Field

[0001] Embodiments of this disclosure relate to electronic devices, and more specifically, to a semiconductor device and a method of manufacturing the semiconductor device. Background Technology

[0002] The integration density of semiconductor devices is primarily determined by the area occupied by a single memory cell. Recently, as improvements in the integration density of semiconductor devices for forming memory cells in a single layer on a substrate have reached their limits, three-dimensional semiconductor devices for stacking memory cells on a substrate have been proposed. Furthermore, various structures and manufacturing methods have been developed to improve the operational reliability of such semiconductor devices. Summary of the Invention

[0003] In embodiments of this disclosure, a semiconductor device may include: a gate structure including a source select line, a drain select line, and a word line stacked between the source select line and the drain select line; a first channel layer, a second channel layer, and a third channel layer; and an insulating core disposed within the first channel layer, wherein the second channel layer penetrates the source select line and includes polysilicon; wherein the third channel layer penetrates the drain select line and includes polysilicon; and wherein the first channel layer penetrates the word line, connects between the second channel layer and the third channel layer, and includes molybdenum disulfide (MoS2).

[0004] In embodiments of this disclosure, a semiconductor device may include: a gate structure including alternating conductive and insulating layers; an insulating core extending through the gate structure; a first channel layer surrounding the insulating core, disposed between the insulating core and the gate structure, and including molybdenum disulfide (MoS2); and a second channel layer including a source portion extending along a surface of the gate structure and a channel portion extending into the gate structure and connected to the first channel layer, and including polysilicon.

[0005] In embodiments of this disclosure, a method of manufacturing a semiconductor device may include the steps of: forming a stack comprising alternating layers of a first material layer and a second material layer; forming a first channel layer extending through the stack and comprising molybdenum disulfide (MoS2); forming an insulating core in the first channel layer; exposing the sidewalls of the insulating core by etching the first channel layer; and forming a third channel layer over the first channel layer and the insulating core.

[0006] In embodiments of this disclosure, a method of manufacturing a semiconductor device may include the steps of: forming a stack comprising alternating layers of a first material layer and a second material layer; forming a first channel layer extending through the stack and comprising molybdenum disulfide (MoS2); forming an insulating core in the first channel layer; and forming a second channel layer comprising a source portion extending along a surface of the stack and a channel portion protruding from the source portion and connected to the first channel layer.

[0007] In embodiments of this disclosure, a method of manufacturing a semiconductor device may include the following steps: forming a first wafer including a substrate, a gate structure disposed on the substrate, a first channel layer extending through the gate structure into the substrate and including molybdenum disulfide (MoS2), and an insulating core disposed within the first channel layer; forming a second wafer including peripheral circuitry; bonding the first wafer and the second wafer to each other; removing the substrate such that the first channel layer protrudes from the surface of the gate structure; forming an opening by etching the first channel layer; and forming a second channel layer on the insulating core and the first channel layer, the second channel layer being connected to the first channel layer and including polysilicon. Attached Figure Description

[0008] Figure 1A and Figure 1B This is a simplified diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 2A and Figure 2B This is a simplified diagram used to describe the characteristics of a semiconductor device according to embodiments of the present disclosure.

[0010] Figures 3A to 3E This is a simplified diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 4A and Figure 4B This is a simplified diagram used to describe the characteristics of a semiconductor device according to embodiments of the present disclosure.

[0012] Figure 5 This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 6 This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figures 7A to 7D This is a simplified diagram illustrating a method for manufacturing a semiconductor device according to embodiments of the present disclosure.

[0015] Figures 8A to 8F This is a simplified diagram illustrating a method for manufacturing a semiconductor device according to embodiments of the present disclosure.

[0016] Figures 9A to 9D This is a simplified diagram illustrating a method for manufacturing a semiconductor device according to embodiments of the present disclosure.

[0017] Figures 10A to 10D This is a simplified diagram illustrating a method for manufacturing a semiconductor device according to embodiments of the present disclosure.

[0018] Figures 11A to 11C This is a simplified diagram illustrating a method for manufacturing a semiconductor device according to embodiments of the present disclosure.

[0019] Figures 12A to 12C This is a simplified diagram illustrating a method for manufacturing a semiconductor device according to embodiments of the present disclosure.

[0020] Figure 13 This is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0021] Figure 14 This is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0022] Various embodiments of this disclosure relate to a semiconductor device having a stable structure and improved properties, as well as a method of manufacturing the semiconductor device.

[0023] By using three-dimensional stacked memory cells, the integration density of semiconductor devices can be improved. It also provides a semiconductor device with a stable structure and improved reliability.

[0024] Hereinafter, embodiments based on the technical spirit of this disclosure will be described with reference to the accompanying drawings.

[0025] Figure 1A and Figure 1B This is a simplified diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0026] Reference Figure 1A and Figure 1B The semiconductor device may include a gate structure GST, a first channel layer 14, an insulating core 17, and a channel pad 18. The semiconductor device may also include a source structure 10 and a memory layer 13.

[0027] The gate structure GST may include alternating layers of conductive layers 11 and insulating layers 12. At least one conductive layer 11 disposed at the bottom may be a source select line SSL, at least one conductive layer 11 disposed at the top may be a drain select line DSL, and the remaining conductive layers 11 may be word lines WL. Word lines WL may be stacked between the source select line SSL and the drain select line DSL. For reference, the terms "top" and "bottom" are relative concepts, and it is possible for the source select line SSL to be disposed at the top and the drain select line DSL at the bottom.

[0028] The first channel layer 14 may extend through the gate structure GST and also at least partially extend into the source structure 10. The first channel layer 14 may comprise a two-dimensional semiconductor material. As an example, the first channel layer 14 may comprise molybdenum disulfide (MoS2). The first channel layer 14 may comprise a monolayer of MoS2 formed as an atomic thickness. Alternatively, the first channel layer 14 may comprise a bulk state of monolayer stacked MoS2.

[0029] The memory layer 13 may surround the sidewall of the first channel layer 14. The memory layer 13 may be disposed between the first channel layer 14 and the gate structure GST. The memory layer 13 may also be disposed above the first channel layer 14 and the source structure 10 (e.g., as shown in the image). Figure 1A The memory layer 13 may include at least one of a barrier layer 13A, a data storage layer 13B, and a tunneling layer 13C. The data storage layer 13B may be disposed between the barrier layer 13A and the tunneling layer 13C. The tunneling layer 13C may contact the first channel layer 14. The barrier layer 13A may contact the sides of the conductive layer 11 and the insulating layer 12 of the gate structure GST. The data storage layer 13B may include a floating gate, polysilicon, a charge trapping material, a nitride, a variable resistance material, etc.

[0030] The insulating core 17 may include an insulating material such as an oxide. The insulating core 17 may be disposed inside the first channel layer 14. The insulating core 17 may extend through the gate structure GST into the source structure 10. The upper surface of the insulating core 17 may be configured to be higher than the upper surface of the uppermost conductive layer 11. The upper surface of the insulating core 17 may be configured to be lower than the upper surface of the uppermost insulating layer 12.

[0031] The channel pad 18 may be disposed above the insulating core 17. The channel pad 18 may be disposed inside the first channel layer 14 and may contact the inner wall of the first channel layer 14. The lower surface of the channel pad 18 may be configured to be higher than the upper surface of the uppermost conductive layer 11. As an example, the channel pad 18 may not overlap with the drain select line DSL. For example, the channel pad 18 may comprise polysilicon.

[0032] The source structure 10 may be disposed below the gate structure GST. The first channel layer 14 and the insulating core 17 may extend through the gate structure GST into the source structure 10. The source structure 10 may have a single-layer structure or a multi-layer structure. (Refer to...) Figure 1A The source structure 10 may include a first source layer 10A, a second source layer 10B, and a third source layer 10C disposed between the first source layer 10A and the second source layer 10B. The third source layer 10C may penetrate the memory layer 13 and connect to the first channel layer 14. The third source layer 10C may contact the first channel layer 14. The first source layer 10A and the second source layer 10B may not contact the first channel layer 14. The first source layer 10A, the second source layer 10B, and the third source layer 10C may each include polysilicon. (Refer to...) Figure 1B The source structure 10 may surround the first channel layer 14 and may be a polycrystalline silicon layer.

[0033] According to the above structure, the selection transistor or memory cell can be disposed in the region where the first channel layer 14 and the conductive layer 11 intersect. The source selection transistor can be disposed in the region where the first channel layer 14 and the source selection line SSL intersect. The drain selection transistor can be disposed in the region where the first channel layer 14 and the drain selection line DSL intersect. The memory cell can be disposed in the region where the first channel layer 14 and the word line WL intersect. The source selection transistor, drain selection transistor, and memory cell that share the first channel layer 14 can be connected in series and can form a memory string. Because the first channel layer 14 includes MoS2, the electron mobility can be increased and the cell current can be improved.

[0034] Because the channel pad 18 is formed inside the first channel layer 14, the first channel layer 14 has a structure surrounding the sidewalls of the channel pad 18. When the channel pad 18 is disposed above the first channel layer 14 and the lower surface of the channel pad 18 and the upper surface of the first channel layer 14 are in contact with each other, the channel pad 18 is included in the main current path. The channel pad 18 comprising polysilicon has a lower electron mobility than the first channel layer 14 comprising MoS2. In addition, the current path has high resistance due to scattering caused by the crystal structure of polysilicon. Therefore, the channel pad 18 is formed to contact the inner wall of the first channel layer 14, so that the channel pad 18 does not directly participate in the current path, and the first channel layer 14 can be used as the main current path. Therefore, the cell current can be improved, and the operating characteristics of the semiconductor device can be improved.

[0035] Figure 2A and Figure 2B This is a simplified diagram used to describe the characteristics of a semiconductor device according to embodiments of the present disclosure. Figure 2A This is a diagram showing the atomic structure of MoS2. Figure 2BThis is a diagram showing the variation of the band gap based on the stacking of MoS2.

[0036] Reference Figure 2A MoS2 has a two-dimensional structure. Due to its crystal structure, MoS2 does not exhibit electron scattering, thus favoring electron mobility. Therefore, by forming the first channel layer 14 with MoS2, electron mobility and unit cell current can be improved. Because MoS2 can be formed as a single-atom-thick layer, the thickness of the first channel layer 14 can be reduced to improve the integration density of semiconductor devices. MoS2 has high electron affinity and a large band gap, thus facilitating the doping of N-type impurities.

[0037] Figure 2B (a) is a graph showing the characteristics of MoS2 in a monolayer state. Figure 2B (b) is a graph showing the characteristics of MoS2 in its bulk state. The x-axis of each graph is the wave vector (k), representing the movement of electrons within the periodic lattice. The y-axis of each graph represents the energy levels.

[0038] In the graph, each curve represents the energy of an electron along a specific path, and indicates the energy change of the electron. Arrows indicate the lowest energy transition between the conduction band and the valence band, and shaded areas indicate the band gap.

[0039] Reference Figure 2A and Figure 2B In (a), in the monolayer state of MoS2, electrons and holes move only in the plane, and the quantum confinement effect is strong. The lowest point of the conduction band is located directly above the highest point of the valence band, and the gap between electronic energy levels becomes very large. Therefore, monolayer MoS2 has a relatively large band gap of about 1.8 eV and a direct band gap. Because monolayer MoS2 has a wider band gap than silicon, it can have a smaller leakage current and maintain stable performance even at high temperatures.

[0040] Reference Figure 2A and Figure 2B In (b), in the bulk state of monolayer MoS2, electrons and holes move freely within the three-dimensional structure, and band rearrangement occurs due to interlayer interactions. As the lowest point of the conduction band moves, the band gap decreases. Therefore, the bulk state of MoS2 has a relatively small band gap of 1.2 eV and an indirect band gap.

[0041] Therefore, the state of MoS2 included in the first channel layer 14 can be determined by considering the electron mobility, electron affinity, band gap, etc. of MoS2. Taking into account the operating characteristics of source-select transistors, drain-select transistors, or memory cells, the first channel layer 14 can have a monolayer state or a block state. As an example, the first channel layer 14 can be entirely monolayer or entirely block state. Alternatively, the first channel layer 14 corresponding to a memory cell can have a monolayer state, and the first channel layer 14 corresponding to a source / drain select transistor can have a block state.

[0042] Figures 3A to 3E This is a simplified diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. In the following text, any content repeated from the previously described content may be omitted.

[0043] Reference Figures 3A to 3E The semiconductor device may include a gate structure GST, a first channel layer 34, a second channel layer 35, a third channel layer 36, a memory layer 33, and an insulating core 37. The gate structure GST may include alternately stacked conductive layers 31 and insulating layers 32. The memory layer 33 may surround the first channel layer 34, the second channel layer 35, and the third channel layer 36. The memory layer 33 may include at least one of a barrier layer 33A, a data storage layer 33B, and a tunneling layer 33C.

[0044] The first channel layer 34 can penetrate the word line WL. The first channel layer 34 can surround the insulating core 37 and can be disposed between the insulating core 37 and the gate structure GST. The second channel layer 35 can penetrate the source select line SSL, and the third channel layer 36 can penetrate the drain select line DSL. The first channel layer 34 can be connected between the second channel layer 35 and the third channel layer 36. The second channel layer 35 can be disposed at the bottom and the third channel layer 36 can be disposed at the top, or the second channel layer 35 can be disposed at the top and the third channel layer 36 can be disposed at the bottom.

[0045] The second channel layer 35 and the third channel layer 36 may each comprise a material different from the first channel layer 34. The first channel layer 34 may comprise a material with a higher electron mobility than the second channel layer 35 and the third channel layer 36. The first channel layer 34 may comprise a material with a larger band gap than the second channel layer 35 and the third channel layer 36, or a material with a similar band gap to the second channel layer 35 and the third channel layer 36. The first channel layer 34 may comprise a material with a higher electron affinity than the second channel layer 35 and the third channel layer 36. As an example, the first channel layer 34 may comprise MoS2, and the second channel layer 35 and the third channel layer 36 may each comprise polycrystalline silicon.

[0046] For reference, the semiconductor device may further include a first channel layer 34 and a second channel layer 35, but not a third channel layer 36. In this case, the first channel layer 34 can penetrate the word line WL and the drain select line DSL. Alternatively, the semiconductor device may further include a first channel layer 34 and a third channel layer 36, but not a second channel layer 35. In this case, the first channel layer 34 can penetrate the word line WL and the source select line SSL.

[0047] Reference Figure 3A The third channel layer 36 may include a channel portion 36A and a pad portion 36B. The pad portion 36B may be disposed above the insulating core 37. The channel portion 36A may be connected to the pad portion 36B and may protrude from the lower surface of the pad portion 36B. The insulating core 37 may extend into the interior of the third channel layer 36, and the channel portion 36A may extend along the sidewall of the insulating core 37. The channel portion 36A may penetrate the drain select line DSL and may be directly connected to the first channel layer 34.

[0048] Reference Figure 3B The third channel layer 36 may include a channel portion 36C and a protrusion portion 36D. The channel portion 36C may be disposed above the insulating core 37 and the first channel layer 34, and may penetrate the drain select line DSL. The protrusion portion 36D may protrude from the lower surface of the channel portion 36C into the interior of the first channel layer 34. The protrusion portion 36D may contact the inner wall of the first channel layer 34. Through the protrusion portion 36D, the contact area between the third channel layer 36 and the first channel layer 34 may be increased, and the contact resistance between the third channel layer 36 and the first channel layer 34 may be reduced.

[0049] Reference Figure 3C The second channel layer 35 may include a channel portion 35A and a source portion 35B. An insulating core 37 may extend into the interior of the second channel layer 35. The channel portion 35A may surround the insulating core 37 and extend between the insulating core 37 and the gate structure GST. The channel portion 35A may protrude from the source portion 35B and penetrate the source select line SSL. The channel portion 35A may extend into the gate structure GST and connect to the first channel layer 34. The source portion 35B may extend along the surface of the gate structure GST. The source portion 35B may connect to the channel portion 35A and may be disposed below the gate structure GST.

[0050] A first source layer 30A may be disposed below a source portion 35B, and a second source layer 30B may be disposed between the source portion 35B and the gate structure GST. The first source layer 30A and the second source layer 30B may be disposed below the gate structure GST, and the source portion 35B may be disposed between the first source layer 30A and the second source layer 30B. The source portion 35B may be used together with the first source layer 30A and the second source layer 30B as a source structure. Therefore, the second channel layer 35 may be used as both a channel layer and a source layer.

[0051] Reference Figure 3D The second channel layer 35 may include a channel portion 35C and a source portion 35D. An insulating core 37 may extend into the interior of the second channel layer 35. The channel portion 35C may surround the insulating core 37 and extend between the insulating core 37 and the gate structure GST. The channel portion 35C may protrude from the lower surface of the source portion 35D. The channel portion 35C may penetrate the source select line SSL and may be connected to the first channel layer 34. The source portion 35D may extend along the surface of the gate structure GST. The source portion 35D may be connected to the channel portion 35C and may be disposed above the gate structure GST. The second channel layer 35 may serve as both a channel layer and a source layer.

[0052] Reference Figure 3E The second channel layer 35 may include a channel portion 35E and a source portion 35F. The source portion 35F may be disposed above the gate structure GST and may extend along the surface of the gate structure GST. The channel portion 35E may protrude from the lower surface of the source portion 35F. The channel portion 35E may extend through the gate structure GST and may penetrate the source select line SSL. The channel portion 35E may contact the inner wall of the first channel layer 34. The second channel layer 35 may serve as both a channel layer and a source layer.

[0053] According to the above structure, the semiconductor device may include: a first channel layer 34 comprising MoS2, a second channel layer 35 comprising polysilicon, and a third channel layer 36 comprising polysilicon, or a combination thereof. Therefore, the cell current and the characteristics of the erase operation can be improved.

[0054] For reference, a semiconductor device may also include, according to reference... Figure 1A and Figure 1B The first channel layer 14 of the described implementation and reference Figures 3A to 3E At least one or a combination of the first trench layer 34, the second trench layer 35 and the third trench layer 36 described.

[0055] Figure 4A and Figure 4B This is a simplified diagram used to describe the characteristics of a semiconductor device according to embodiments of the present disclosure. Figure 4AThis is a graph used to describe the gate-induced drain leakage (GIDL) characteristics of a select transistor including a MoS2 channel layer. Figure 4B This is a diagram used to describe the GIDL characteristics of a select transistor that includes a polysilicon channel layer.

[0056] Semiconductor devices can perform erase operations using the GIDL method. According to the GIDL method, the erase operation is performed by generating GIDL current in the source selection transistor and / or drain selection transistor via interband tunneling (BTBT) and supplying holes to the memory cell. Therefore, by supplying a sufficient amount of holes, the characteristics of the erase operation can be improved.

[0057] Reference Figure 4A The monolayer MoS2 channel layer has a relatively large bandgap energy of approximately 1.8 eV, resulting in a relatively large BTBT length. In this case, the GIDL current decreases, and a relatively small number of holes are supplied.

[0058] Reference Figure 4B The polycrystalline silicon channel layer has a relatively small bandgap energy of about 1.1 eV, therefore the length of the BTBT is relatively small. Consequently, the GIDL current can be increased, and a large number of holes can be supplied. For reference, the bulk MoS2 channel layer also has a relatively small bandgap energy of about 1.2 eV, therefore, the GIDL current can be relatively large, and a large number of holes can be supplied.

[0059] With this in mind, the erase operation characteristics of semiconductor devices can be improved by using polysilicon channel layers or bulk MoS2 channel layers to form selection transistors. Furthermore, both cell current and erase characteristics can be improved by using polysilicon channel layers or bulk MoS2 channel layers to form source selection transistors and / or drain selection transistors and using a single-layer MoS2 channel layer to form memory cells.

[0060] Figure 5 This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. In the following text, any content repeated from the previously described content may be omitted.

[0061] Reference Figure 5 The semiconductor device may include a first semiconductor structure S1 and a second semiconductor structure S2. The second semiconductor structure S2 may be disposed above the first semiconductor structure S1, or the first semiconductor structure S1 may be disposed above the second semiconductor structure S2.

[0062] The first semiconductor structure S1 may include peripheral circuitry PC. The peripheral circuitry PC may include a line decoder, page buffer, input / output circuitry, logic circuitry, etc. As an example, the first semiconductor structure S1 may include a substrate SUB, a transistor TR, a first interconnect structure IC1, and a first interlayer insulating layer IL1. The transistor TR may be part of the peripheral circuitry PC. The first interconnect structure IC1 may be formed in the first interlayer insulating layer IL1 and may be electrically connected to the peripheral circuitry PC. The first interconnect structure IC1 may include vias, wiring, etc.

[0063] The second semiconductor structure S2 may include a memory cell array CA, which includes stacked memory cells. As an example, the second semiconductor structure S2 may include a source structure 50, a gate structure GST, a channel layer CH, a memory layer 53, an insulating core 57, a slit structure 59, a second interconnect structure IC2, and a second interlayer insulating layer IL2.

[0064] The gate structure GST may include alternately stacked conductive layers 51 and insulating layers 52. The channel layer CH may include reference... Figure 1A and Figure 1B The first channel layer 14 described may include references Figures 3A to 3E The first channel layer 34, the second channel layer 35, and the third channel layer 36 are described, or combinations thereof may be included. A slit structure 59 may pass through the gate structure GST and extend into the source structure 50. The slit structure 59 may include insulating material, semiconductor material, and / or conductive material. As an example, the slit structure 59 may include a source contact 59B and an insulating spacer 59A. The insulating spacer 59A may extend around the source contact 59B through the sidewall of the gate structure GST. A second interconnect structure IC2 may be disposed in the second interlayer insulating layer IL2 and may be electrically connected to the memory cell array CA. The second interconnect structure IC2 may include vias, wiring, etc.

[0065] According to the above structure, the integration density of the semiconductor device can be increased by stacking the first semiconductor structure S1 and the second semiconductor structure S2. By forming a channel layer CH including at least one of a polysilicon channel layer, a bulk MoS2 channel layer, or a monolayer MoS2 channel layer, the operating characteristics of the semiconductor device can be improved.

[0066] Figure 6 This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. In the following text, any content repeated from the previously described content may be omitted.

[0067] Reference Figure 6 The semiconductor device may include a first semiconductor structure S1, a second semiconductor structure S2, and a bonding structure BS. The first semiconductor structure S1 may include peripheral circuitry PC, and the second semiconductor structure S2 may include a memory cell array CA.

[0068] The first semiconductor structure S1 may include a substrate SUB, a transistor TR, a first interlayer insulating layer IL1, and a first interconnect structure IC1. The transistor TR may belong to the peripheral circuit PC. The first interconnect structure IC1 may be disposed in the first interlayer insulating layer IL1 and may include vias, wiring, etc. The first interconnect structure IC1 may be electrically connected to the peripheral circuit PC.

[0069] The second semiconductor structure S2 may include a source layer 60, a gate structure GST, a channel layer CH, a memory layer 63, an insulating core 67, a slit structure 69, a second interlayer insulating layer IL2, and a second interconnect structure IC2.

[0070] The gate structure GST may include alternately stacked conductive layers 61 and insulating layers 62. The channel layer CH may include reference... Figure 1A and Figure 1B The first channel layer 14 described may include references Figures 3A to 3E The first channel layer 34, the second channel layer 35, and the third channel layer 36 are described, or combinations thereof may be included. The source layer 60 may be disposed above the gate structure GST. The source layer 60 may be a layer formed separately from the channel layer CH, or it may be the source portion of the second channel layer.

[0071] The slit structure 69 can pass through the gate structure GST and extend into the source layer 60. The slit structure 69 may include insulating material, semiconductor material, and / or conductive material. The second interconnect structure IC2 may be disposed in the second interlayer insulating layer IL2 and may be electrically connected to the memory cell array CA. The second interconnect structure IC2 may include vias, wiring, etc.

[0072] A bonding structure BS can be disposed between the first semiconductor structure S1 and the second semiconductor structure S2. The first semiconductor structure S1 and the second semiconductor structure S2 can be manufactured separately and can be electrically connected to each other through the bonding structure BS. The memory cell array CA, including the gate structure GST and the peripheral circuit PC, can be electrically connected to each other through the bonding structure BS.

[0073] The bonding structure BS may include a first bonding layer BL1, a second bonding layer BL2, a first bonding pad BP1, and a second bonding pad BP2. The first bonding layer BL1 and the second bonding layer BL2 may be in contact with each other. Additionally, the first bonding pad BP1 and the second bonding pad BP2 may be in contact with each other. For example, the first bonding layer BL1 and the second bonding layer BL2 may each include SiCN, tetraethyl orthosilicate (TEOS), etc. The first bonding pad BP1 may be electrically connected to the first interconnect structure IC1, and the second bonding pad BP2 may be electrically connected to the second interconnect structure IC2. The memory cell array CA and the peripheral circuit PC may be electrically connected to each other via the first bonding pad BP1 and the second bonding pad BP2.

[0074] According to the above structure, the first semiconductor structure S1 and the second semiconductor structure S2 can be bonded to each other in the vertical direction. This increases the integration density of the semiconductor device. The channel layer CH may include at least one of a polysilicon channel layer, a bulk MoS2 channel layer, or a monolayer MoS2 channel layer, thus improving the operating characteristics of the semiconductor device.

[0075] Figures 7A to 7D This is a simplified diagram illustrating a method of manufacturing a semiconductor device according to embodiments of the present disclosure. In the following text, any content repeated from the previously described content may be omitted.

[0076] Reference Figure 7A A source structure 70 is formed. The source structure 70 may include a first source layer 70A, a second source layer 70B, and a source sacrificial layer 70C. The source sacrificial layer 70C may be formed between the first source layer 70A and the second source layer 70B. The source structure 70 may also include a first protective layer 70D and a second protective layer 70E. As an example, the first source layer 70A, the first protective layer 70D, the source sacrificial layer 70C, the second protective layer 70E, and the second source layer 70B may be formed sequentially. The first source layer 70A, the second source layer 70B, and the source sacrificial layer 70C may each comprise polysilicon. The first protective layer 70D and the second protective layer 70E may each comprise oxide.

[0077] Subsequently, a stack ST is formed on the source structure 70. The stack ST may include alternating layers of first material 71 and second material 72. The first material layer 71 may be used to form the stacked gate lines, and the second material layer 72 may be used to form an insulating layer. As an example, the first material layer 71 may each include a sacrificial material such as a nitride, and the second material layer 72 may each include an insulating material such as an oxide. As an example, the first material layer 71 may each include a conductive material such as polysilicon or metal, and the second material layer 72 may each include an insulating material such as an oxide.

[0078] Subsequently, a first opening OP1 is formed in the laminate ST. The first opening OP1 can penetrate the laminate ST and extend into the source structure 70. As an example, the first opening OP1 can penetrate the laminate ST, the second source layer 70B, the second protective layer 70E, the source sacrificial layer 70C, and the first protective layer 70D, and can extend into the first source layer 70A.

[0079] Subsequently, a memory layer 73 may be formed in the first opening OP1. As an example, a barrier layer 73A, a data storage layer 73B, and / or a tunneling layer 73C may be formed in the first opening OP1. Subsequently, a first channel layer 74 may be formed in the memory layer 73. The first channel layer 74 may include a monolayer of MoS2 and / or bulk MoS2. Subsequently, an insulating core 77 may be formed in the first channel layer 74.

[0080] Reference Figure 7B The second opening OP2 can be formed by etching the insulating core 77. The insulating core 77 can be etched such that the upper surface of the insulating core 77 is set higher than the upper surface of the uppermost first material layer 71. As an example, a dry cleaning process can be used to etch the insulating core 77. In this case, the insulating core 77 can be selectively etched without etching the first trench layer 74, and the inner wall of the first trench layer 74 can be exposed.

[0081] Reference Figure 7C A channel pad 78 may be formed in the second opening OP2 above the insulating core 77. The channel pad 78 may contact the inner wall of the first channel layer 74. For example, the channel pad 78 may comprise polysilicon.

[0082] Reference Figure 7D A slit (not shown) can be formed in the laminate ST, through which the source sacrificial layer 70C can be removed. After removing the source sacrificial layer 70C, the memory layer 73 can be etched to expose the first channel layer 74. In the process of etching the memory layer 73, the first protective layer 70D and the second protective layer 70E can be etched together. Subsequently, a third source layer 70F connected to the first channel layer 74 can be formed. Thus, a source structure 70 including the first source layer 70A, the second source layer 70B, and the third source layer 70F can be formed.

[0083] Subsequently, the first material layer 71 can be replaced with a third material layer 79. As an example, the third material layer 79 can be formed after the first material layer 71 is removed through a slit. The third material layer 79 is used to form gate lines such as source select lines, drain select lines, and word lines, and may each comprise a metal such as tungsten or molybdenum. Thus, a gate structure GST comprising alternately stacked second material layers 72 and third material layers 79 can be formed.

[0084] For reference, when each of the first material layers 71 comprises a conductive material, the replacement process can be omitted. In this case, the first material layer 71 can be used as a gate line, and the stacked layer ST can be used as a gate structure GST.

[0085] According to the above method, a first channel layer 74 comprising a single layer of MoS2 and / or a bulk state of MoS2 can be formed. A channel pad 78 comprising polysilicon can be formed within the first channel layer 74. Because the first channel layer 74 surrounds the sidewalls of the channel pad 78, the first channel layer 74 can form the main current path, and the cell current can be improved.

[0086] Figures 8A to 8F This is a simplified diagram illustrating a method of manufacturing a semiconductor device according to embodiments of the present disclosure. In the following text, any content repeated from the previously described content may be omitted.

[0087] Reference Figure 8A A source structure 80 is formed. The source structure 80 may include a first source layer 80A, a second source layer 80B, a source sacrificial layer 80C, a first protective layer 80D, and a second protective layer 80E. Subsequently, a laminate ST is formed on the source structure 80. The laminate ST may include alternating layers of first material layer 81 and second material layer 82.

[0088] Subsequently, a first opening OP1 is formed in the laminate ST, and a memory layer 83 is formed in the first opening OP1. The memory layer 83 may include a barrier layer 83A, a data storage layer 83B, and / or a tunneling layer 83C. Subsequently, a first channel layer 84 may be formed in the first opening OP1. The first channel layer 84 may include a monolayer of MoS2 and / or bulk MoS2. Subsequently, an insulating core 87 may be formed in the first channel layer 84, and a second opening OP2 exposing the inner wall of the first channel layer 84 may be formed by etching the insulating core 87.

[0089] Reference Figure 8B The first channel layer 84 exposed through the second opening OP2 can be etched. Thus, the second opening OP2 can extend downwards, and the sidewalls of the insulating core 87 can be exposed through the extended second opening OP2A. As an example, the portion of the first channel layer 84 corresponding to the drain select line can be etched, and the second opening OP2A can extend to the height corresponding to the drain select line.

[0090] Reference Figure 8C A third channel layer 86 may be formed in the second opening OP2A. The third channel layer 86 may be disposed above the insulating core 87 and the first channel layer 84. The third channel layer 86 may include a channel portion 86A extending along the sidewall of the insulating core 87 and a pad portion 86B disposed above the insulating core 87. For example, the third channel layer 86 may include polysilicon.

[0091] Reference Figure 8DA slit (not shown) can be formed in the stack ST, and a third opening OP3 can be formed by removing the source sacrificial layer 80C through the slit. Subsequently, the first channel layer 84 can be exposed by etching the memory layer 83 through the third opening OP3.

[0092] Reference Figure 8E A fourth opening OP4 extending along the sidewall of the insulating core 87 can be formed by etching the first channel layer 84. The sidewall of the insulating core 87 and the inner wall of the memory layer 83 can be exposed through the fourth opening OP4. As an example, the portion of the first channel layer 84 corresponding to the source select line can be etched, and the fourth opening OP4 can be formed at a height corresponding to the source select line.

[0093] Reference Figure 8F A second channel layer 85 may be formed in the third opening OP3 and the fourth opening OP4. For example, the second channel layer 85 may include polysilicon. The second channel layer 85 may include a channel portion 85A and a source portion 85B connected to the channel portion 85A. The channel portion 85A may be disposed in the fourth opening OP4, and the source portion 85B may be disposed in the third opening OP3. The channel portion 85A may surround the sidewall of the insulating core 87 and may extend between the insulating core 87 and the memory layer 83. The source portion 85B may be disposed between the first source layer 80A and the second source layer 80B. The source portion 85B may be used together with the first source layer 80A and the second source layer 80B as a source structure.

[0094] Subsequently, the first material layer 81 can be replaced by the third material layer 89, and a gate structure GST can be formed.

[0095] According to the above method, a first channel layer 84 comprising a monolayer of MoS2 and / or a bulk state of MoS2 can be formed, and a second channel layer 85 and a third channel layer 86 each comprising polysilicon can be formed. Therefore, not only the cell current can be improved, but also the operating characteristics of the semiconductor device can be improved.

[0096] Figures 9A to 9D This is a simplified diagram illustrating a method of manufacturing a semiconductor device according to embodiments of the present disclosure. In the following text, any content repeated from the previously described content may be omitted.

[0097] Reference Figure 9A A laminate ST comprising alternating layers of first material layer 91 and second material layer 92 is formed. Subsequently, a first opening OP1 is formed in the laminate ST, and a memory layer 93 and a first channel layer 94 may be sequentially formed in the first opening OP1. The memory layer 93 may include at least one of a barrier layer 93A, a data storage layer 93B, and a tunneling layer 93C. The first channel layer 94 may include a monolayer of MoS2 and / or bulk MoS2.

[0098] Subsequently, an insulating core 97 can be formed in the first channel layer 94, and a second opening OP2 exposing the inner wall of the first channel layer 94 can be formed by etching the insulating core 97.

[0099] Reference Figure 9B The first trench layer 94 exposed through the second opening OP2 can be etched. Thus, the second opening OP2 can extend downward and the sidewalls of the insulating core 97 can be exposed through the extended second opening OP2A.

[0100] Reference Figure 9C The insulating core 97 exposed through the second opening OP2A can be etched. Thus, the second opening OP2A can extend downwards, and the inner wall of the first channel layer 94 can be exposed through the extended second opening OP2B. The first channel layer 94 can protrude beyond the upper surface of the insulating core 97.

[0101] Reference Figure 9D A third channel layer 96 may be formed in the second opening OP2B. The third channel layer 96 may be disposed above the insulating core 97 and the first channel layer 94. The third channel layer 96 may include a channel portion 96A and a protrusion portion 96B protruding from the lower surface of the channel portion 96A. The channel portion 96A may be disposed above the insulating core 97 and the first channel layer 94, and may penetrate the drain selection line. The protrusion portion 96B may be disposed above the insulating core 97, and may protrude into the interior of the first channel layer 94 to contact the inner wall of the first channel layer 94.

[0102] According to the above method, a first channel layer 94 comprising a monolayer of MoS2 and / or a bulk state of MoS2 can be formed, and a third channel layer 96 comprising polysilicon can be formed. Therefore, not only the cell current can be improved, but also the operating characteristics of the semiconductor device can be improved.

[0103] Figures 10A to 10D This is a simplified diagram illustrating a method of manufacturing a semiconductor device according to embodiments of the present disclosure. In the following text, any content repeated from the previously described content may be omitted.

[0104] Reference Figure 10A A first wafer WF1 can be formed. The first wafer WF1 may include a substrate 100, a gate structure GST above the substrate, a first channel layer 140, a memory layer 130, an insulating core 170, a channel pad 180, a slot structure 190, a second interconnect structure IC2, a second interlayer insulating layer IL2, a second bonding layer BL2, and a second bonding pad BP2. The gate structure GST may include alternately stacked conductive layers 110 and insulating layers 120. The first channel layer 140 and the insulating core 170 may be formed to extend into the substrate 100.

[0105] The first channel layer 140 and the channel pad 180 can respectively correspond to the above reference. Figure 1A and Figure 1B The first channel layer 14 and channel pad 18 are described. For reference, the semiconductor device may also exclude the channel pad 180, but include the above-described... Figure 3A and Figure 3B The first trench layer 34 and the third trench layer 36 are described.

[0106] Reference Figure 10B A second wafer WF2 can be formed. The second wafer WF2 may include a substrate 101, a transistor TR, a first interconnect structure IC1, a first interlayer insulating layer IL1, a first bonding layer BL1, and a first bonding pad BP1. The first interconnect structure IC1 may be electrically connected to the transistor TR.

[0107] Reference Figure 10C The first wafer WF1 can be flipped so that the substrate 100 is disposed above the gate structure GST, and then the first wafer WF1 and the second wafer WF2 can be bonded to each other. The first bonding layer BL1 and the second bonding layer BL2 can be bonded to each other, and the first bonding pad BP1 and the second bonding pad BP2 can be electrically connected to each other.

[0108] Subsequently, the substrate 100 can be removed, for example, by using a polishing process, an etch-back process, a planarization process, an etching process, etc. With the substrate 100 removed, the memory layer 130 can be exposed. The first channel layer 140 can then be exposed by etching the memory layer 130. The first channel layer 140 and the slit structure 190 can protrude from the surface of the gate structure GST.

[0109] Reference Figure 10D A source layer 102 may be formed on the gate structure GST. For example, the source layer 102 may include polysilicon.

[0110] According to the above method, a first wafer WF1 including a first channel layer 140 can be formed, the first channel layer 140 including a monolayer of MoS2 and / or bulk MoS2. By separately fabricating the first wafer WF1 and the second wafer WF2, and then bonding the first wafer WF1 and the second wafer WF2 together to form a semiconductor device, the manufacturing process of the semiconductor device can be improved.

[0111] Figures 11A to 11C This is a simplified diagram illustrating a method of manufacturing a semiconductor device according to embodiments of the present disclosure. In the following text, any content repeated from the previously described content may be omitted.

[0112] Reference Figure 11AA first wafer WF1 and a second wafer WF2 can be formed. The first wafer WF1 may include a substrate 200, a gate structure GST, a first channel layer 240, a third channel layer 260, a memory layer 230, an insulating core 270, a slot structure 290, a second interconnect structure IC2, a second interlayer insulating layer IL2, a second bonding layer BL2, and a second bonding pad BP2. The gate structure GST may include alternately stacked conductive layers 210 and insulating layers 220.

[0113] The second wafer WF2 may include a substrate 201, a transistor TR, a first interconnect structure IC1, a first interlayer insulating layer IL1, a first bonding layer BL1, and a first bonding pad BP1.

[0114] Subsequently, the first wafer WF1 and the second wafer WF2 are bonded together. The substrate 200 may be disposed above the gate structure GST, and the rear surface of the substrate 200 may be exposed.

[0115] Reference Figure 11B The memory layer 230 can be exposed by removing the substrate 200. Subsequently, the first channel layer 240 can be exposed by etching the memory layer 230. Then, an opening OP can be formed by etching the first channel layer 240. The opening OP can extend between the insulating core 270 and the memory layer 230 and can be configured to correspond to the source select line.

[0116] Reference Figure 11C A second channel layer 250 may be formed on the gate structure GST. The second channel layer 250 may include a source portion 250B and a channel portion 250A connected to the source portion 250B. The source portion 250B may be disposed above the gate structure GST and may extend along the surface of the gate structure GST. The channel portion 250A may be disposed in the opening OP and may extend along the sidewall of the insulating core 270 and be connected to the first channel layer 240. For example, the second channel layer 250 may include polysilicon.

[0117] According to the above method, a first wafer WF1 comprising a first channel layer 240 and a third channel layer 260 can be formed. The first channel layer 240 comprises a monolayer of MoS2 and / or bulk MoS2, and the third channel layer 260 comprises polysilicon. After the first wafer WF1 and the second wafer WF2 are bonded together, a second channel layer 250 comprising polysilicon can be formed. Therefore, the manufacturing process of the semiconductor device can be improved, and the operating characteristics of the semiconductor device can be improved.

[0118] Figures 12A to 12C This is a simplified diagram illustrating a method of manufacturing a semiconductor device according to embodiments of the present disclosure. In the following text, any content repeated from the previously described content may be omitted.

[0119] Figure 12A This can correspond to the above. Figure 11B The gate structure GST may include alternating layers of conductive layer 310 and insulating layer 320. The memory layer 330 may include a barrier layer 330A, a data storage layer 330B, and a tunneling layer 330C. The sidewalls of the insulating core 370 and the inner walls of the memory layer 330 may be exposed through openings OP.

[0120] Reference Figure 12B The opening OP can be enlarged by etching the insulating core 370. The enlarged opening OPA can expose the inner wall of the first channel layer 340. The upper surface of the insulating core 370 can be set to be lower than the upper surface of the first channel layer 340.

[0121] Reference Figure 12C A second channel layer 350 may be formed. The second channel layer 350 may include a source portion 350B and a channel portion 350A connected to the source portion 350B. The source portion 350B may be disposed above the gate structure GST and may extend along the surface of the gate structure GST. The channel portion 350A may extend into the gate structure GST and may contact the inner wall of the first channel layer 340.

[0122] According to the above method, the second channel layer 350 can protrude into the interior of the first channel layer 340, and the sidewall of the second channel layer 350 and the inner wall of the first channel layer 340 can contact each other. Therefore, the contact area between the second channel layer 350 and the first channel layer 340 can be increased, and the contact resistance between the second channel layer 350 and the first channel layer 340 can be reduced.

[0123] The structure and method described above can be applied to semiconductor devices with various structures. Figure 13 and Figure 14 A schematic configuration of a semiconductor device to which the above embodiments are applicable is shown.

[0124] Figure 13 This is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0125] Reference Figure 13 The semiconductor device may include a substrate SUB, peripheral circuitry PC, and memory cell array CA. For example, the peripheral circuitry PC and the memory cell array CA may be formed on the same substrate.

[0126] The substrate SUB may include a semiconductor material. As an example, the semiconductor material may include at least one of group IV semiconductors, group III-V compound semiconductors, and group II-VI compound semiconductors. For example, group IV semiconductors may include single-crystal silicon (Si), polycrystalline silicon, germanium (Ge), or silicon-germanium (SiGe). Group III-V compound semiconductors may include GaAs, GaN, GaP, GaAsP, GaInAsP, AlAs, AlGa, InP, InSb, or InGaAs. Group II-VI compound semiconductors may include ZnS, ZnO, or CdS.

[0127] The substrate SUB may include a dielectric layer. The substrate SUB may be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, or a glass substrate. The substrate SUB may include organic materials. As an example, the substrate SUB may include graphene.

[0128] The substrate SUB can be a bulk wafer or an epitaxial layer grown using a selective epitaxial growth (SEG) method. The substrate SUB can be a layer formed using a metal-induced lateral crystallization (MILC) method and may partially comprise a metal. The substrate SUB can be monocrystalline, polycrystalline, or amorphous. The substrate SUB may include Group II, III, IV, V, or VI impurities. As an example, the substrate SUB may include an n-well region doped with n-type impurities and / or a p-well region doped with p-type impurities.

[0129] The peripheral circuitry PC can be disposed between the substrate SUB and the memory cell array CA. The peripheral circuitry PC may include row decoders, column decoders, page buffers, logic circuits, control circuits, sense amplifiers, input / output circuits, etc. As an example, the peripheral circuitry PC may include N-channel metal-oxide-semiconductor (NMOS) transistors, P-channel metal-oxide-semiconductor (PMOS) transistors, resistors, capacitors, etc. The peripheral circuitry PC may also include interconnect structures. These interconnect structures can serve as paths for transmitting operating voltages and may include contact plugs, wiring, etc.

[0130] A memory cell array (CA) may include memory cells. As an example, the memory cell array (CA) may include memory strings connected between source lines and bit lines, and each memory string may include stacked memory cells. As an example, the memory cell array (CA) may include memory cells connected between word lines and bit lines. The memory cell array (CA) may also include interconnect structures.

[0131] Figure 14 This is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0132] Reference Figure 14The semiconductor device may include a substrate SUB, peripheral circuitry PC, bonding structure BS, and memory cell array CA. For example, the peripheral circuitry PC and the memory cell array CA may be formed on separate substrates and then bonded to each other. The semiconductor device may also include a support base SP_B.

[0133] The substrate SUB can be used as a support in the process of forming the peripheral circuit PC. The support base SP_B can be used as a support in the process of forming the memory cell array CA. As an example, a first wafer including the memory cell array CA and a second wafer including the peripheral circuit PC can be fabricated separately and then electrically connected to each other via a bonding structure BS. After the first wafer and the second wafer are bonded together, the support base SP_B of the first wafer can be at least partially removed. The support base SP_B can be completely removed or can be partially retained on the memory cell array CA.

[0134] The support substrate SP_B can be a semiconductor substrate, an insulating substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. The support substrate SP_B can be a bulk wafer, an epitaxial layer grown by selective epitaxial growth (SEG), or a layer formed by metal-induced lateral crystallization (MILC). The support substrate SP_B can be single-crystal, polycrystalline, or amorphous. The support substrate SP_B can include Group II, III, IV, V, or VI impurities.

[0135] A bonding structure BS can be used to connect a memory cell array (CA) and peripheral circuitry (PC) to each other. As an example, the bonding structure BS can bond the memory cell array (CA) and peripheral circuitry (PC) to each other using wafer-to-wafer bonding, chip-to-wafer bonding, chip-to-chip bonding, etc. The bonding structure BS may include bonding pads, bonding layers, bonding interfaces, etc. Bonding pads may include metals such as copper or aluminum and / or alloys thereof. Bonding interfaces may include non-metal-to-non-metal interfaces, metal-to-metal interfaces, etc. The memory cell array (CA) and peripheral circuitry (PC) can be electrically connected to each other through the bonding structure BS.

[0136] For reference, interconnect structures included in the memory cell array (CA) and / or peripheral circuitry (PC) can also be directly connected to each other without bonding pads. As an example, bonding layers included in the memory cell array (CA) and bonding layers included in the peripheral circuitry (PC) can be bonded to each other to form a bonding interface, and interconnect structures included in the memory cell array (CA) and interconnect structures included in the peripheral circuitry (PC) can be directly connected to each other. Thus, contact plugs, wiring, etc., formed on different wafers can be electrically connected to each other without separate bonding pads.

[0137] Other configurations can be referenced above. Figure 13 The configurations described are the same or similar.

[0138] In addition, semiconductor devices may also have the above reference. Figure 13 and Figure 14 The described embodiments are structures that are combined with each other or structures with partial modifications. (Refer to...) Figure 13 and Figure 14 In the described implementation, the positions of the memory cell array CA and the peripheral circuitry PC can be changed. (Refer to...) Figure 13 and Figure 14 In the described implementation, at least one memory cell array CA and / or at least one peripheral circuit PC may be additionally coupled. As an example, a portion of the peripheral circuit PC may be disposed within the memory cell array CA.

[0139] Although embodiments based on the technical concept of this disclosure have been described above with reference to the accompanying drawings, this is merely for illustrating embodiments according to the concept of this disclosure, and this disclosure is not limited to the embodiments described above. Various substitutions, modifications, alterations, and combinations of various types can be made to the embodiments by those skilled in the art to which this disclosure pertains without departing from the technical concept of this disclosure as defined in the following claims, and such substitutions, modifications, alterations, and combinations should be interpreted as falling within the scope of this disclosure. Furthermore, these embodiments can be combined to form additional embodiments.

[0140] Cross-reference to related applications

[0141] This application claims priority to Korean Patent Application No. 10-2024-0196055, filed on December 24, 2024, the entirety of which is incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: A gate structure including a source select line, a drain select line, and a word line stacked between the source select line and the drain select line; First trench layer, second trench layer and third trench layer; as well as An insulating core, which is disposed inside the first channel layer, The second channel layer penetrates the source selection line and includes polysilicon; The third channel layer penetrates the drain selection line and includes polysilicon; and The first channel layer penetrates the word line, connects between the second channel layer and the third channel layer, and includes molybdenum disulfide (MoS2).

2. The semiconductor device according to claim 1, wherein, The third channel layer includes: The pad portion is disposed above the insulating core; and The channel portion extends along the sidewall of the insulating core.

3. The semiconductor device according to claim 2, wherein, The insulating core extends into the channel portion.

4. The semiconductor device according to claim 1, wherein, The third channel layer includes: The channel portion is disposed above the insulating core and the first channel layer; and A protruding portion that protrudes from the channel portion into the interior of the first channel layer.

5. The semiconductor device according to claim 1, wherein, The second channel layer includes: A channel portion that surrounds the insulating core and extends between the insulating core and the gate structure; and The source portion extends along the surface of the gate structure.

6. The semiconductor device according to claim 5, wherein, The insulating core extends into the second channel layer.

7. The semiconductor device according to claim 5, further comprising: A first source layer is disposed below the source portion; as well as A second source layer is disposed between the source portion and the gate structure.

8. The semiconductor device according to claim 5, wherein, The source portion is disposed above the gate structure, and the channel portion protrudes from the lower surface of the source portion.

9. The semiconductor device according to claim 1, wherein, The second channel layer includes: The source portion extends along the surface of the gate structure; and The channel portion protrudes from the source portion and contacts the inner wall of the first channel layer.

10. The semiconductor device of claim 1, further comprising a memory layer surrounding the first channel layer, the second channel layer, and the third channel layer.

11. The semiconductor device of claim 1, further comprising peripheral circuitry disposed below the gate structure.

12. The semiconductor device of claim 11, further comprising a bonding structure that electrically connects the memory cell array including the gate structure, the first channel layer, the second channel layer, the third channel layer and the insulating core to the peripheral circuit.

13. A semiconductor device comprising: A gate structure comprising alternating layers of conductive and insulating layers; An insulating core that extends through the gate structure; A first channel layer, which surrounds the insulating core, is disposed between the insulating core and the gate structure, and comprises molybdenum disulfide (MoS2); as well as The second channel layer includes a source portion extending along the surface of the gate structure and a channel portion extending into the gate structure and connected to the first channel layer, and the second channel layer includes polysilicon.

14. The semiconductor device of claim 13, further comprising a channel pad disposed above the insulating core and comprising polysilicon. in, The first channel layer surrounds the sidewall of the channel pad.

15. The semiconductor device of claim 13, further comprising a third channel layer including a pad portion disposed above the insulating core and a channel portion extending along a sidewall of the insulating core and connected to the first channel layer.

16. The semiconductor device of claim 13, further comprising a third channel layer including a channel portion disposed above the insulating core and the first channel layer and a protrusion portion protruding from the channel portion and contacting the inner wall of the first channel layer.

17. The semiconductor device according to claim 13, wherein, The channel portion of the second channel layer surrounds the insulating core and extends between the insulating core and the gate structure.

18. The semiconductor device of claim 17, further comprising: A first source layer is disposed below the source portion; as well as A second source layer is disposed between the source portion and the gate structure.

19. The semiconductor device according to claim 17, wherein, The source portion is disposed above the gate structure, and the channel portion protrudes from the lower surface of the source portion.

20. The semiconductor device according to claim 13, wherein, The source portion is disposed above the gate structure, and the channel portion is in contact with the inner wall of the first channel layer.

21. A method for manufacturing a semiconductor device, the method comprising the following steps: A laminate is formed, comprising alternating layers of first and second materials; A first channel layer is formed, which extends through the laminate and includes molybdenum disulfide (MoS2). An insulating core is formed in the first channel layer; The sidewalls of the insulating core are exposed by etching the first trench layer; as well as A third channel layer is formed above the first channel layer and the insulating core.

22. The method according to claim 21, wherein, The third channel layer comprises polycrystalline silicon.

23. The method according to claim 21, wherein, The third channel layer includes: The pad portion is disposed on the insulating core; and The channel portion extends along the sidewall of the insulating core.

24. The method of claim 21, further comprising the step of: The insulating core is etched so that the first channel layer protrudes.

25. The method according to claim 24, wherein, The third channel layer includes: The channel portion is disposed above the insulating core and the first channel layer; and A protruding portion that protrudes from the channel portion and contacts the inner wall of the first channel layer.

26. The method of claim 21, further comprising the step of: Forming a source pole sacrificial layer; The first opening is formed by removing the source sacrificial layer; The second opening is formed by etching the first trench layer through the first opening; as well as A second channel layer is formed, the second channel layer including a channel portion disposed in the second opening and a source portion disposed in the first opening.

27. The method according to claim 21, wherein, The laminate is formed on a substrate, and the first channel layer is formed to extend into the substrate.

28. The method of claim 27, further comprising the step of: Remove the substrate so that the first trench layer protrudes from the laminate; The first trench layer is etched to expose the sidewalls of the insulating core; as well as A second channel layer is formed, which includes a source portion disposed above the laminate and a channel portion extending along the sidewall of the insulating core.

29. The method of claim 27, further comprising the step of: Remove the substrate so that the first trench layer protrudes from the laminate; The first trench layer is etched to expose the sidewalls of the insulating core; The insulating core is etched so that the first channel layer protrudes; as well as A second channel layer is formed, the second channel layer including a source portion disposed above the laminate and a channel portion extending through the laminate and contacting the inner wall of the first channel layer.

30. A method for manufacturing a semiconductor device, the method comprising the following steps: A laminate is formed, comprising alternating layers of first and second materials; A first channel layer is formed, which extends through the laminate and includes molybdenum disulfide (MoS2). An insulating core is formed in the first channel layer; as well as A second channel layer is formed, the second channel layer including a source portion extending along the surface of the laminate and a channel portion protruding from the source portion and connected to the first channel layer.

31. The method according to claim 30, wherein, The second channel layer comprises polycrystalline silicon.

32. The method of claim 30, further comprising the step of: Etching the insulating core to expose the inner wall of the first channel layer; and A channel pad is formed, which is disposed above the insulating core and in contact with the inner wall of the first channel layer.

33. The method of claim 30, further comprising the step of: The sidewalls of the insulating core are exposed by etching the first trench layer; as well as A third channel layer is formed, the third channel layer including pad portions disposed above the first channel layer and the insulating core, and channel portions extending along the sidewall of the insulating core and connected to the first channel layer.

34. The method of claim 30, further comprising the step of: The sidewalls of the insulating core are exposed by etching the first trench layer; The insulating core is etched so that the first channel layer protrudes; as well as A third channel layer is formed, which includes a channel portion disposed above the insulating core and the first channel layer, and a protrusion portion protruding into the interior of the first channel layer and connected to the first channel layer.

35. The method according to claim 30, wherein, The stack is formed on the source sacrificial layer, and the first channel layer is formed to extend into the source sacrificial layer.

36. The method according to claim 35, wherein, The steps for forming the second channel layer include the following: The first opening is formed by removing the source sacrificial layer; The second opening is formed by etching the first trench layer through the first opening; and A second channel layer is formed, the second channel layer including the channel portion disposed in the second opening and the source portion disposed in the first opening.

37. The method of claim 30, wherein, The laminate is formed on a substrate, and the first channel layer is formed to extend into the substrate.

38. The method according to claim 37, wherein, The steps for forming the second channel layer include the following: Remove the substrate so that the first trench layer protrudes from the laminate; Etching the first trench layer to expose the sidewalls of the insulating core; and A second channel layer is formed, the second channel layer including the source portion disposed above the laminate and the channel portion extending along the sidewall of the insulating core.

39. The method according to claim 37, wherein, The steps for forming the second channel layer include the following: Remove the substrate so that the first trench layer protrudes from the laminate; The first trench layer is etched to expose the sidewalls of the insulating core; Etch the insulating core to make the first channel layer protrude; and A second channel layer is formed, the second channel layer including the source portion disposed above the laminate and the channel portion extending through the laminate and contacting the inner wall of the first channel layer.

40. A method for manufacturing a semiconductor device, the method comprising the following steps: A first wafer is formed, the first wafer including a substrate, a gate structure disposed on the substrate, a first channel layer extending through the gate structure into the substrate and including molybdenum disulfide (MoS2), and an insulating core disposed inside the first channel layer. Forming a second wafer including peripheral circuitry; The first wafer and the second wafer are joined together; Remove the substrate so that the first channel layer protrudes from the surface of the gate structure; An opening is formed by etching the first trench layer; as well as A second channel layer is formed on the insulating core and the first channel layer, the second channel layer being connected to the first channel layer and comprising polycrystalline silicon.

41. The method according to claim 40, wherein, The first wafer also includes a trench pad disposed above the insulating core, in contact with the inner wall of the first trench layer, and comprising polysilicon.

42. The method according to claim 40, wherein, The first wafer also includes a third channel layer, which includes a pad portion disposed above the insulating core and a channel portion extending along the sidewall of the insulating core and connected to the first channel layer.

43. The method according to claim 40, wherein, The first wafer also includes a third channel layer, which includes a channel portion disposed above the insulating core and the first channel layer, and a protrusion portion protruding from the channel portion and contacting the inner wall of the first channel layer.

44. The method of claim 40, wherein, The second channel layer includes a source portion disposed above the gate structure and a channel portion extending into the gate structure and connected to the first channel layer.

45. The method of claim 40, further comprising the step of: The insulating core is etched so that the first channel layer protrudes.

46. ​​The method according to claim 45, wherein, The second channel layer includes a source portion disposed above the gate structure and a channel portion extending through the gate structure and contacting the inner wall of the first channel layer.

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