Interface treatment method for reducing defect density of selective epitaxy of hbt germanium silicon base region

Abstract

This invention discloses an interface treatment method for reducing the defect density of selective epitaxial growth in the germanium-silicon base region of an HBT (Hardware-to-Bit) device. The method includes: providing a patterned substrate; performing wet cleaning on the patterned substrate to remove intrinsic oxides, and drying the wet-cleaned patterned substrate; performing in-situ plasma cleaning on the patterned substrate; performing in-situ H2 baking on the patterned substrate; and forming a germanium-silicon base region in the base region growth window through selective germanium-silicon epitaxy. In this invention, due to the strict thermal budget constraints of the SiGe BiCMOS process, three surface pretreatment methods—wet cleaning, in-situ plasma cleaning, and in-situ H2 baking—are specifically combined to treat the growth interface before SiGe epitaxy, thereby obtaining a high-quality SiGe epitaxial layer and improving the electrical performance of the SiGe HBT device.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit chip manufacturing, and in particular relates to an interface treatment method for reducing the density of selective epitaxial defects in the HBT germanium-silicon base region. Background Technology

[0002] The key to achieving high-speed performance in SiGe HBTs lies in the bandgap engineering and steep doping of the SiGe base region. Therefore, the crystal quality of the SiGe base region is crucial for improving the performance of SIGE HBTs. In the fabrication process of SiGe heterojunction bipolar transistors, interface treatment before selective epitaxy is a critical step that determines the final performance and reliability of the device.

[0003] Interface treatment directly determines the electrical characteristics of heterojunctions. The core advantage of HBTs lies in utilizing the bandgap engineering provided by the SiGe base region to improve carrier injection efficiency. If oxides or contaminants are present on the silicon surface before epitaxy, they will disrupt the formation of an ideal abrupt heterojunction. This leads to bandgap disorder, introduces interface states, which become scattering and recombination centers for carriers, severely degrading current gain and cutoff frequency (f). T ) and the highest oscillation frequency (f max This process can lead to increased device noise. An atomically clean interface is a prerequisite for achieving excellent high-frequency and high-speed performance. Furthermore, interface treatment before epitaxy is crucial to the crystal quality of the epitaxial layer. Selective epitaxy requires the growth of a perfect single crystal on a single-crystal silicon window, with no polycrystalline deposition in the dielectric layer (such as SiO2 or SiN). Residual oxides or organic matter can cause defects such as stacking faults and dislocations in the epitaxial layer. These defects can persist throughout the entire epitaxial layer, not only reducing carrier mobility but also becoming channels for leakage current, breaking down the collector and causing complete device failure. Proper interface cleaning and high-temperature baking can thoroughly remove contaminants, ensuring high-quality epitaxial growth only in the designated area. An unclean interface can alter surface energy, affecting the epitaxial reaction and gas-phase chemical equilibrium, potentially disrupting the dynamic balance of growth / etching and leading to loss of selectivity.

[0004] In summary, the interface treatment before epitaxy is crucial for obtaining an atomically-level single-crystal surface for SiGe HBTs. It ensures a steep, atomically-level interface in the heterojunction, high crystal integrity of the epitaxial material, and precise process control, forming the cornerstone of SiGe HBT's high performance. However, traditional wet cleaning techniques always suffer from air exposure, leading to oxide layer formation. Furthermore, the overall thermal budget of SiGe HBTs limits the pre-epitaxy H2bake temperature to no higher than 1000℃. Therefore, traditional interface treatment methods struggle to achieve a perfect single-crystal silicon interface. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide an interface treatment method for reducing the density of selective epitaxial defects in the germanium-silicon base region of HBT.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution: An interface treatment method for reducing the selective epitaxial defect density in the germanium-silicon based region of an HBT includes the following steps: S100. A patterned substrate is provided, the patterned substrate having a base region growth window; S200: Perform wet cleaning on the patterned substrate to remove intrinsic oxides, and then dry the patterned substrate after wet cleaning. S300, In-situ plasma cleaning of patterned substrates; S400, In-situ H2 baking of the patterned substrate; S500: A germanium-silicon base region is formed in the base region growth window through selective germanium-silicon epitaxy.

[0007] Furthermore, the patterned substrate is fabricated using the following steps: S110. A silicon substrate is provided, and an oxide layer is formed on the silicon substrate; S120, A silicon nitride layer is formed on the oxide layer; S130, the oxide layer and silicon nitride layer are etched sequentially to form a base region growth window exposed on the surface of the silicon substrate.

[0008] Furthermore, in step S200, the wet cleaning of the patterned substrate includes the following sub-steps: S210. Clean the patterned substrate with a mixed solution of ammonia and hydrogen peroxide for 10-20 minutes. S220. Clean the patterned substrate with hydrofluoric acid solution for 10-20 minutes. S230. Rinse the patterned substrate with deionized water.

[0009] Furthermore, in step S210, the mixed solution is a solution with NH4OH:H2O2:H2O in a ratio of 1:2:8.

[0010] Furthermore, in step S220, the hydrofluoric acid solution is a solution with an HF:H2O ratio of 1:100.

[0011] Furthermore, when drying the patterned substrate after wet cleaning, isopropanol pure vapor is used to dry the patterned substrate.

[0012] Furthermore, step S300 includes the following sub-steps: S310. NF3 and NH3 are used in the reaction chamber of the epitaxial growth equipment to generate NH4F and / or NH4F·HF plasma etching gas under radio frequency action. The plasma etching gas reacts with silicon dioxide on the patterned substrate to generate (NH4F·HF) plasma etching gas. 4）2 SiF6 solid; S320, by heating (NH) 4）2 SiF6 solid sublimates into SiF4, NH3, and HF gases, which are then carried out of the reaction chamber by the carrier gas.

[0013] Furthermore, argon gas is used as the carrier gas in the reaction chamber of the epitaxial growth equipment.

[0014] Furthermore, in step S400, during in-situ H2 baking, the epitaxial growth equipment is used to bake in situ at 925–1000°C for 1–3 minutes, with an H2 flow rate of 25–35 SLM / min.

[0015] Furthermore, in step S500, the growth source gas used is DCS and GeH4, the selective etching gas used is HCl, and the epitaxial growth temperature is 600-700℃.

[0016] In this invention, to meet the stringent thermal budget constraints of the SiGe BiCMOS process, a combined surface pretreatment scheme was specifically designed. This scheme employs three sequential steps: wet cleaning, in-situ plasma cleaning, and in-situ H2 baking, to systematically treat the growth interface before selective SiGe epitaxy. This comprehensive pretreatment method ensures atomic-level cleanliness of the interface while effectively suppressing impurity redistribution and material damage caused by the thermal process. This provides an ideal surface foundation for the controllable growth of high-quality SiGe epitaxial layers, ultimately significantly optimizing the electrical performance of SiGe HBT devices, particularly achieving reliable improvements in key indicators such as current gain, cutoff frequency, and noise characteristics. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a flowchart of an embodiment of the interface treatment method for reducing the selective epitaxial defect density in the HBT germanium-silicon based region according to the present invention.

[0018] Figure 2 This is a schematic diagram of the patterned substrate structure.

[0019] Figure 3 This is a schematic diagram of the structure after a germanium-silicon base region is formed in the base region growth window of a patterned substrate.

[0020] Figure 4 The image shows a SiGe TEM image grown without using the interface processing method of this embodiment.

[0021] Figure 5 This is a SiGe TEM image grown using the interface processing method of this embodiment.

[0022] The diagrams in the instruction manual are labeled as follows: 1. Silicon substrate; 2. Oxide layer; 3. Silicon nitride layer; 4. Base region growth window; 5. Germanium-silicon base region. Detailed Implementation

[0023] The following specific examples illustrate the implementation of the present invention. The illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0024] Please see Figure 1 , Figure 1 This is a flowchart of an embodiment of the interface treatment method for reducing the selective epitaxial defect density in the HBT germanium-silicon-based region according to the present invention. The interface treatment method for reducing the selective epitaxial defect density in the HBT germanium-silicon-based region of this embodiment includes the following steps: S100, please refer to Figure 2 A patterned substrate is provided, the patterned substrate having a base region growth window 4. The patterned substrate in this step can be fabricated using the following steps: S110. A silicon substrate 1 is provided, and an oxide layer 2 is formed on the silicon substrate 1 by depositing silicon oxide (SiO2).

[0025] S120. A silicon nitride layer 3 is formed on the oxide layer 2 by depositing silicon nitride (SiN). The silicon nitride layer 3 not only covers the surface of the silicon substrate 1, but also generally covers the sidewalls of the silicon substrate 1.

[0026] S130: The oxide layer 2 and the silicon nitride layer 3 are etched sequentially to form a base region growth window 4 exposed on the surface of the silicon substrate 1, thereby obtaining a patterned substrate. In this step, the area where the base region growth window 4 is located can be defined by photolithography, and then the base region growth window 4 can be formed by dry etching and wet etching. The specific process is existing technology and will not be described in detail here.

[0027] S200. The patterned substrate is wet-cleaned to remove intrinsic oxides, and then dried. Intrinsic oxides, or intrinsic OX, refer to oxide layers 2 that are not intentionally grown through processes such as thermal oxidation or chemical vapor deposition. Instead, they are unavoidable natural oxide layers formed spontaneously by the surface atoms of silicon material reacting with oxygen when exposed to air or an oxygen-containing atmosphere. Its chemical formula is primarily silicon dioxide, but its structure may not be as dense or uniform as that formed by thermal oxidation.

[0028] Selective SiGe epitaxy requires direct growth on a clean, intact silicon crystal surface. This native oxide layer disrupts the crystal structure of the silicon substrate 1, preventing the epitaxial layer from perfectly "continuing" the substrate's lattice in a single-crystal form, thus causing defects or even preventing growth. Furthermore, the residual native oxide layer introduces interface states and impurities, severely impacting the electrical performance and reliability of the final device. Therefore, to improve device performance, this native oxide layer needs to be removed.

[0029] This step, wet cleaning of the patterned substrate, may include the following sub-steps: S210. Clean the patterned substrate with a mixed solution of ammonia and hydrogen peroxide for 10-20 minutes, preferably 15 minutes. The mixed solution is preferably a solution of NH4OH:H2O2:H2O in a ratio of 1:2:8; the temperature of the mixed solution is generally 80-90℃, preferably 85℃. Ammonia solution, through oxidation and complexation, can effectively remove photoresist residue, grease, and other organic impurities from the patterned substrate, and can also remove some metals such as Au, Ag, Cu, Ni, and Zn. The corrosion of the silicon substrate 1 by ammonia is slight and isotropic. Under the action of hydrogen peroxide, the silicon surface is oxidized, forming a thin layer of silicon dioxide, making it hydrophilic. This layer of silicon dioxide plays a crucial protective role before finally entering the DHF cleaning bath.

[0030] S220. Clean the patterned substrate with a hydrofluoric acid solution for 10–20 minutes, preferably 15 minutes. The hydrofluoric acid solution is an HF:H₂O solution of 1:100; the temperature of the hydrofluoric acid solution is generally 20–30°C, preferably 25°C. DHF (Diluted Hydrofluoric Acid) can dissolve the intrinsic oxide without corroding the single-crystal silicon itself. After the intrinsic oxide is removed, the exposed silicon atoms will combine with hydrogen atoms in HF or water to form Si-H bonds, forming a hydrogen-terminated surface, which can effectively inhibit the rapid formation of a native oxide layer on silicon in air.

[0031] S230. Rinse the patterned substrate with deionized water. The purpose of rinsing with deionized water is to quickly terminate the chemical reaction of HF and wash away residual HF and reaction products (H2SiF6).

[0032] When drying the patterned substrate after wet cleaning, pure IPA (isopropyl alcohol) vapor is used to dry the patterned substrate to avoid water residue. The surface tension gradient generated by the IPA vapor pulls away the water, achieving contactless and particulate-free drying.

[0033] S300. Perform in-situ plasma cleaning on the patterned substrate. This step includes the following sub-steps: S310. NH4F and / or NH4F·HF plasma etching gases are generated in the reaction chamber of the epitaxial growth equipment using NF3 and NH3 under radio frequency action; subsequently, the plasma etching gases react with silicon dioxide on the patterned substrate to generate easily sublimated (NH4F·HF) plasma etching gases. 4）2 SiF6 solid is used to etch the interface oxide layer 2. The reaction temperature for etching the interface oxide layer 2 in this step is generally 30-45℃.

[0034] Plasma etching gas generation principle: NF3 + NH3 → NH4F + NH4F.HF Etching principle of interface oxide layer 2: NH4F or NH4F.HF + SiO2 — (NH4)2SiF6(solid) + H2O S320. Heating causes the (NH4)2SiF6 solid to sublimate into SiF4, NH3, and HF gases, which are then carried out of the reaction chamber by the carrier gas, thereby removing the silicon oxide formed in the air and cleaning the growth interface. The heating temperature in this step is typically 150–200°C; argon (Ar) is generally used as the carrier gas in the reaction chamber of the epitaxial growth equipment. Using Ar as the carrier gas maintains plasma stability and allows for the removal of reaction waste, ensuring a clean environment after each process and preparing for subsequent epitaxial growth.

[0035] (NH4)2SiF6 sublimation: (NH4)2SiF6(solid) → SiF4(g) + NH3(g) + HF(g) The plasma etching gas in this step exhibits high reactivity and removal rate towards silicon dioxide, while showing extremely low etching rates towards the single-crystal silicon substrate 1 and the silicon nitride mask, achieving selective cleaning and perfectly protecting the patterned structure. Compared to the traditional high-temperature hydrogen reduction method, this process can be performed at a lower temperature, avoiding increased thermal costs and material thermal damage. The reactants and byproducts are both gaseous or sublimable solids, avoiding pattern collapse or residue caused by liquid surface tension in wet cleaning, making it particularly suitable for cleaning high aspect ratio nanostructures. Furthermore, this cleaning step can be completed directly within the reaction chamber of the epitaxial growth equipment, enabling in-situ cleaning and growth throughout the entire process. This avoids the risk of re-oxidation of the wafer after removal from the atmospheric environment, resulting in an atomically clean growth interface.

[0036] S400. In-situ H2 baking is performed on the patterned substrate. In this step, in-situ H2 baking is conducted in the reaction chamber of the epitaxial growth equipment at 925–1000°C for 1–3 minutes, with an H2 flow rate of 25–35 SLM / min, preferably 30 SLM / min. In-situ H2 baking desorbs surface contaminants, reconstructs and planarizes the Si surface, thereby reducing interface defects. This step, under absolutely clean conditions and without contact with the atmosphere, utilizes the combined effects of high temperature and hydrogen to perform ultimate purification and perfection treatment on the silicon surface. Thus, before the start of epitaxial growth, a perfect silicon single crystal surface with atomically cleanliness, accurate stoichiometry, complete crystal structure, and atomically smoothness is obtained on the silicon substrate 1, serving as a seed template for subsequent high-quality SiGe epitaxial growth.

[0037] S500, please refer to Figure 3 In this step, a germanium-silicon base region 5 is precisely formed within a predefined base region growth window 4 using selective germanium-silicon epitaxy. The growth source gases used are DCS and GeH4; DCS provides the silicon component, and GeH4 provides the germanium component. Simultaneously, HCl is introduced as a selective etching gas. By adjusting its flow rate ratio in real time, the formation of amorphous or polycrystalline nuclei on the surface of the dielectric layer (such as SiO2 and SiN) is precisely suppressed, ensuring that the SiGe material achieves high-quality epitaxial growth only on the exposed single-crystal silicon window. The entire epitaxial process can be carried out in the medium-low temperature range of 600–700℃. This temperature range ensures sufficient surface reaction and migration rates to obtain good crystal quality while effectively controlling germanium diffusion and maintaining the steepness of the heterojunction interface. Ultimately, a SiGe base region structure with precise germanium composition, steep impurity distribution, and excellent interface characteristics is achieved, laying a crucial foundation for the subsequent fabrication of high-performance SiGe HBT devices.

[0038] Please see Figure 4 , Figure 4The SiGe TEM image was grown using conventional methods of the prior art, without employing the interface processing method of this embodiment. (The text abruptly ends here.) Figure 4 Numerous bit faults can be observed due to improper interface handling. Please refer to [link / reference]. Figure 5 This is a TEM image of SiGe grown using the interface processing method of this embodiment. Figure 5 It can be seen that the grown SiGe is a fully strained SiGe single crystal. (Comparison) Figure 4 and Figure 5 It can be seen that the interface processing method of this embodiment can effectively reduce the defect density of selective epitaxy in the SiGe HBT germanium-silicon base region 5.

[0039] In this embodiment, to meet the stringent thermal budget constraints of the SiGe BiCMOS process, a combined surface pretreatment scheme was specifically designed. This scheme employs three sequential steps: wet cleaning, in-situ plasma cleaning, and in-situ H2 baking, to systematically treat the growth interface before selective SiGe epitaxy. This comprehensive pretreatment method ensures atomic-level cleanliness of the interface while effectively suppressing impurity redistribution and material damage caused by the thermal process. This provides an ideal surface foundation for the controllable growth of high-quality SiGe epitaxial layers, ultimately significantly optimizing the electrical performance of SiGe HBT devices, particularly achieving reliable improvements in key indicators such as current gain, cutoff frequency, and noise characteristics.

[0040] The above embodiments merely illustrate preferred implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention should be determined by the appended claims.

Claims

1. An interface treatment method for reducing the selective epitaxial defect density in the germanium-silicon-based region of an HBT, characterized in that, Includes the following steps: S100. A patterned substrate is provided, the patterned substrate having a base region growth window; S200. Perform wet cleaning on the patterned substrate to remove intrinsic oxides, and then dry the patterned substrate after wet cleaning. S300, In-situ plasma cleaning of patterned substrates; S400, In-situ H2 baking of the patterned substrate; S500: A germanium-silicon base region is formed in the base region growth window through selective germanium-silicon epitaxy.

2. The interface treatment method for reducing the selective epitaxial defect density in the HBT germanium-silicon based region as described in claim 1, characterized in that, The patterned substrate is prepared using the following steps: S110. A silicon substrate is provided, and an oxide layer is formed on the silicon substrate; S120, A silicon nitride layer is formed on the oxide layer; S130, the oxide layer and silicon nitride layer are etched sequentially to form a base region growth window exposed on the surface of the silicon substrate.

3. The interface treatment method for reducing the selective epitaxial defect density in the HBT germanium-silicon based region as described in claim 1, characterized in that, In step S200, the wet cleaning of the patterned substrate includes the following sub-steps: S210. Clean the patterned substrate with a mixed solution of ammonia and hydrogen peroxide for 10-20 minutes. S220. Clean the patterned substrate with hydrofluoric acid solution for 10-20 minutes. S230. Rinse the patterned substrate with deionized water.

4. The interface treatment method for reducing the selective epitaxial defect density in the HBT germanium-silicon based region as described in claim 3, characterized in that, In step S210, the mixed solution is a solution with NH4OH:H2O2:H2O in a ratio of 1:2:

8.

5. The interface treatment method for reducing the selective epitaxial defect density in the HBT germanium-silicon based region as described in claim 3, characterized in that, In step S220, the hydrofluoric acid solution is a solution with an HF:H2O ratio of 1:

100.

6. The interface treatment method for reducing the selective epitaxial defect density in the HBT germanium-silicon based region as described in any one of claims 1 to 5, characterized in that, When drying the patterned substrate after wet cleaning, isopropanol pure vapor is used to dry the patterned substrate.

7. The interface treatment method for reducing the selective epitaxial defect density in the HBT germanium-silicon based region as described in claim 1, characterized in that, The S300 step includes the following sub-steps: S310. NF3 and NH3 are used in the reaction chamber of the epitaxial growth equipment to generate NH4F and / or NH4F·HF plasma etching gas under radio frequency action. The plasma etching gas reacts with silicon dioxide on the patterned substrate to generate (NH4F·HF) plasma etching gas. 4）2 SiF6 solid; S320, by heating (NH) 4）2 SiF6 solid sublimates into SiF4, NH3, and HF gases, which are then carried out of the reaction chamber by the carrier gas.

8. The interface treatment method for reducing the selective epitaxial defect density in the HBT germanium-silicon based region as described in claim 7, characterized in that, Argon gas is used as the carrier gas in the reaction chamber of the epitaxial growth equipment.

9. The interface treatment method for reducing the selective epitaxial defect density in the HBT germanium-silicon based region as described in claim 7, characterized in that: In step S400, the in-situ H2 baking is performed in the reaction chamber of the epitaxial growth equipment at 925–1000°C for 1–3 min, with an H2 flow rate of 25–35 SLM / min.

10. The interface treatment method for reducing the selective epitaxial defect density in the HBT germanium-silicon based region as described in claim 1, characterized in that: In step S500, the growth source gases used are DCS and GeH4, the selective etching gas used is HCl, and the epitaxial growth temperature is 600-700℃.

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