Semiconductor device

Abstract

A semiconductor device includes: a substrate including a first surface and a second surface; a first conductivity type semiconductor layer on the first surface; a second conductivity type doped well region within the first conductivity type semiconductor layer; a gate electrode on the first conductivity type semiconductor layer; a gate insulating layer between the first conductivity type semiconductor layer and the gate electrode; a first conductivity type doped pattern within the second conductivity type doped well region and including a first portion overlapping and electrically connected to a contact portion of a source electrode, a second portion adjacent to the gate electrode, and a third portion connecting the first portion and the second portion; and a drain electrode on the second surface, wherein the width of the first portion is less than the length of the contact portion, or the width of the second portion is less than the length of the gate electrode.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] In modern society, semiconductor devices are closely related to our daily lives. In particular, the importance of power semiconductor devices is increasing in various fields such as transportation (e.g., electric vehicles, railways, and electric trams), renewable energy systems (e.g., solar power, wind power), and mobile devices. Power semiconductor devices are semiconductor devices used to handle high voltages or high currents and perform functions such as power conversion and control in large power systems or high-power electronic devices. Power semiconductor devices have the ability to handle high power and durability, allowing them to handle large currents and withstand high voltages. For example, power semiconductor devices can handle voltages of hundreds to thousands of volts and currents of tens to thousands of amperes. Power semiconductor devices can improve the efficiency of electrical energy by minimizing power losses. Furthermore, power semiconductor devices can operate stably even in environments such as high temperatures.

[0003] These power semiconductor devices can be classified by material; for example, there are SiC power semiconductor devices and GaN power semiconductor devices. By using SiC or GaN instead of existing silicon wafers (Si wafers) to manufacture power semiconductor devices, the drawbacks of silicon, such as its instability at high temperatures, can be overcome. SiC power semiconductor devices are heat-resistant and have low power loss, making them suitable for electric vehicles and renewable energy systems. GaN power semiconductor devices are expensive but highly efficient in terms of speed, making them suitable for fast charging of mobile devices. Summary of the Invention

[0004] The disclosed embodiments provide a semiconductor device with stable electrical characteristics and improved reliability.

[0005] According to an embodiment, a semiconductor device includes: a substrate including a first surface and a second surface opposite to each other; a first conductivity type semiconductor layer positioned on the first surface of the substrate; a second conductivity type doped well region positioned within the first conductivity type semiconductor layer; a gate electrode positioned on the first conductivity type semiconductor layer; a gate insulating layer positioned between the first conductivity type semiconductor layer and the gate electrode; a first conductivity type doped pattern positioned within the second conductivity type doped well region; a source electrode positioned on the second conductivity type doped well region and including a contact portion electrically connected to the first conductivity type doped pattern; and a drain electrode positioned on the second surface of the substrate, wherein the first conductivity type doped pattern includes: a first portion extending in a first direction and overlapping the contact portion of the source electrode; a second portion extending in the first direction and positioned adjacent to the gate electrode; and a third portion connecting the first portion and the second portion, and wherein the width of the first portion in the second direction is less than the length of the contact portion in the second direction, or the width of the second portion in the second direction is less than the length of the gate electrode in the second direction, the second direction being perpendicular to the first direction.

[0006] According to an embodiment, a semiconductor device includes: a substrate including a first surface and a second surface opposite to each other; a first conductivity type semiconductor layer positioned on the first surface of the substrate; a second conductivity type doped well region positioned within the first conductivity type semiconductor layer; a first conductivity type doped pattern positioned within the second conductivity type doped well region; a gate electrode positioned on the first conductivity type semiconductor layer; a gate insulating layer positioned between the first conductivity type semiconductor layer and the gate electrode; a source electrode including a contact portion positioned on the second conductivity type doped well region; and a drain electrode positioned on the second surface of the substrate, wherein the first conductivity type doped pattern includes: a first portion overlapping the contact portion of the source electrode and extending in a first direction; a second portion overlapping the gate electrode and extending in the first direction; and a third portion connecting the first portion and the second portion and extending in a second direction intersecting the first direction, and wherein the sum of the length of the first portion in the first direction, the length of the second portion in the first direction, and the length of the third portion in the second direction is greater than the length of the source electrode in the second direction.

[0007] According to an embodiment, a semiconductor device includes: a substrate including a first surface and a second surface opposite to each other; a first conductivity type semiconductor layer positioned on the first surface of the substrate and including a gate trench; a second conductivity type doped well region positioned within the first conductivity type semiconductor layer; a first conductivity type doped pattern positioned within the second conductivity type doped well region; a dummy pattern positioned within the first conductivity type doped pattern; a gate electrode positioned within the gate trench; an interlayer insulating layer positioned between the first conductivity type semiconductor layer and the gate electrode; a source electrode including a contact portion positioned on the second conductivity type doped well region; and a drain electrode positioned on the second surface of the substrate, wherein the first conductivity type doped pattern includes: a first vertical portion overlapping the contact portion; a second vertical portion positioned on one side of the gate electrode and not overlapping the contact portion; and a horizontal portion connecting the first vertical portion and the second vertical portion, and wherein the dummy pattern is positioned between the first vertical portion and the second vertical portion.

[0008] According to the implementation method, the reliability of semiconductor devices can be improved. Attached Figure Description

[0009] Figure 1 This is a plan view illustrating a semiconductor device according to an example embodiment.

[0010] Figure 2 It is along Figure 1 A sectional view taken by line A-A'.

[0011] Figure 3 It is along Figure 1 The sectional view taken by line B-B'.

[0012] Figure 4 It is along Figure 1 A sectional view taken by line C-C'.

[0013] Figure 5 This is a plan view showing the arrangement of a first conductivity type doped pattern of a semiconductor device according to an example embodiment.

[0014] Figure 6 This is a plan view illustrating the flow of drive current in a semiconductor device according to an example embodiment.

[0015] Figure 7 This is a plan view showing the arrangement of a first conductivity type doped pattern of a semiconductor device according to some example embodiments.

[0016] Figures 8 to 12 This is a plan view illustrating a semiconductor device according to some example embodiments.

[0017] Figures 13 to 17This is a cross-sectional view showing a semiconductor device according to some example embodiments. Detailed Implementation

[0018] In the following, various embodiments will be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily implement the inventive concept. The inventive concept can be implemented in many different forms and is not limited to the embodiments described herein.

[0019] For clarity of this disclosure, parts not related to the description have been omitted, and the same reference numerals are used for the same or similar parts throughout the specification.

[0020] Furthermore, the dimensions and thicknesses of each component shown in the accompanying drawings are arbitrarily illustrated for ease of explanation, and therefore the embodiments are not necessarily limited to those shown. Thicknesses are shown enlarged to clearly illustrate the layers and regions in the drawings. In the drawings, the thicknesses of some layers and regions are exaggerated for ease of explanation.

[0021] Furthermore, when we say that a part of a layer, membrane, region, or plate is "above" or "on" another part, this includes not only the case where it is "directly above" the other part, but also the case where there are other parts in between. Conversely, when we say that a part is "directly above" another part, we mean that there are no other parts in between. Also, "above" or "on" a reference part means located above or below the reference part, and does not necessarily mean located "above" or "on" in the opposite direction of gravity.

[0022] It will be understood that when an element is referred to as being “connected” or “attached” to or “on” another element, it can be directly connected to or attached to the other element or on the other element, or there may be an intermediate element present. Conversely, when an element is referred to as being “directly connected” or “directly attached” to another element, or as being “in contact” with or “on” another element (or using any form of the word “in contact”), there is no intermediate element at the point of contact.

[0023] Furthermore, throughout the specification, whenever a section is referred to as "including" a component, it does not mean that it excludes other components, but rather that it may include other components, unless otherwise specifically stated.

[0024] Furthermore, throughout the instruction manual, when we say "in a plane," we mean when viewing the target portion from above, and when we say "in a section," we mean when viewing the target portion from the side in a vertically cut section.

[0025] In the following text, reference will be made to Figures 1 to 4 Describe a semiconductor device according to an example implementation.

[0026] Figure 1 This is a plan view illustrating a semiconductor device according to an example embodiment. Figure 2 It is along Figure 1 A sectional view taken by line A-A'. Figure 3 It is along Figure 1 The sectional view taken by line B-B'. Figure 4 It is along Figure 1 A sectional view taken by line C-C'.

[0027] refer to Figures 1 to 4 The semiconductor device according to the embodiment may include a substrate 110, a first conductivity type semiconductor layer 131 positioned on a first surface of the substrate 110, a second conductivity type doped well region 133 positioned in the first conductivity type semiconductor layer 131, a gate electrode 150 positioned on the first conductivity type semiconductor layer 131, a gate insulating layer 151 positioned between the first conductivity type semiconductor layer 131 and the gate electrode 150, a first conductivity type doped pattern 300 positioned in the second conductivity type doped well region 133, a source electrode 173 positioned on the second conductivity type doped well region 133, and a drain electrode 175 positioned on a second surface of the substrate 110.

[0028] The substrate 110 can be a semiconductor substrate including SiC. For example, the substrate 110 can be made of a 4H SiC substrate. In some cases, the substrate 110 can be made of a 3C SiC substrate, a 6H SiC substrate, etc. The substrate 110 can be doped with impurities of a first conductivity type. For example, the impurities of the first conductivity type can be n-type. In other words, the substrate 110 can be doped with n-type impurities. The substrate 110 can be heavily doped with n-type impurities. The resistivity of the substrate 110 can be about 0.005 Ωcm or greater and about 0.035 Ωcm or less. The thickness of the substrate 110 can be about 10 μm or greater and about 700 μm or less. The material, doping type, doping concentration, resistivity, thickness, etc. of the substrate 110 are not limited thereto and can be varied in various ways.

[0029] The substrate 110 may include a first surface and a second surface that are opposite to each other. For example, the first side of the substrate 110 may refer to the upper side of the substrate 110, and the second side of the substrate 110 may refer to the lower side of the substrate 110.

[0030] A first conductivity type semiconductor layer 131 may be positioned on a first surface (i.e., the upper surface) of the substrate 110. The lower surface of the first conductivity type semiconductor layer 131 may contact the upper surface of the substrate 110. However, the exemplary embodiment is not limited thereto, and another layer may be additionally positioned between the substrate 110 and the first conductivity type semiconductor layer 131. The first conductivity type semiconductor layer 131 may be an epitaxial layer formed from the substrate 110 using an epitaxial growth method. The first conductivity type semiconductor layer 131 may be formed of or comprise SiC. For example, the first conductivity type semiconductor layer 131 may be formed of or comprise 4H SiC. The first conductivity type semiconductor layer 131 may be doped with an n-type impurity. The first conductivity type semiconductor layer 131 may be lightly doped with an n-type impurity. The doping concentration of the first conductivity type semiconductor layer 131 may be lower than the doping concentration of the substrate 110. The doping concentration of the first conductivity type semiconductor layer 131 may be approximately 1 × 10⁻⁶. 15 cm -3 Or larger and approximately 1×10 17 cm -3 Or even smaller. The thickness of the first conductivity type semiconductor layer 131 can be about 1 μm or more and about 13 μm or less.

[0031] The second conductivity type doped well region 133 may be located within the first conductivity type semiconductor layer 131. The second conductivity type doped well region 133 may be located in the upper portion of the first conductivity type semiconductor layer 131. The second conductivity type doped well region 133 may contact the lower surface of the second conductivity type doped layer 135, which will be described later. The second conductivity type doped well region 133 may surround the lower and side surfaces of the first conductivity type doped pattern 300, which will be described later. The upper surface of the second conductivity type doped well region 133 may be coplanar with the upper surface of the first conductivity type semiconductor layer 131. In an embodiment, at least a portion of the upper surface of the second conductivity type doped well region 133 may overlap with at least a portion of the gate electrode 150, which will be described later, and at least a portion of the gate insulating layer 151, which will be described later, in a third direction (Z direction). Here, the third direction (Z direction) may refer to the thickness direction of the substrate 110 and / or the direction perpendicular to the first surface of the substrate 110.

[0032] In an embodiment, the second conductivity type doped well region 133 can be used as a channel for a transistor constituting a semiconductor device. For example, the portion of the second conductivity type doped well region 133 adjacent to the gate electrode 150, which will be described later, can be used as a channel for the transistor. The second conductivity type doped well region 133 used as a channel for the transistor can be located between the first conductivity type semiconductor layer 131 and the first conductivity type doped pattern 300, which will be described later. In other words, a current path from the source electrode 173 to the drain electrode 175 can be formed in at least a portion of the second conductivity type doped well region 133. For ease of explanation, the portion of the second conductivity type doped well region 133 adjacent to the gate electrode 150 that serves as a channel for the transistor is referred to as the channel region.

[0033] In one embodiment, the second conductivity type doped well region 133 can extend from the upper surface of the first conductivity type semiconductor layer 131 toward the lower surface of the first conductivity type semiconductor layer 131. That is, the second conductivity type doped well region 133 can extend from the upper surface of the first conductivity type semiconductor layer 131 in a third direction (Z direction). The second conductivity type doped well region 133 can be formed in at least a portion of the first conductivity type semiconductor layer 131 by ion implantation, but the example embodiment is not limited thereto.

[0034] In one embodiment, the second conductivity type doped well region 133 may include a patterned portion 133PP positioned between the second conductivity type doped layer 135 (described later) and the second portion 320 and the third portion 330 of the first conductivity type doped pattern 300 (described later). The patterned portion 133PP may refer to the portion of the second conductivity type doped well region 133 positioned between the second conductivity type doped layer 135 (described later) and the second portion 320 and the third portion 330 of the first conductivity type doped pattern 300 (described later). Further reference will be made later. Figure 5 A detailed description of this is provided in the description of the first conductivity type doped pattern 300.

[0035] The second conductivity type doped well region 133 can be formed of or comprise SiC. For example, the second conductivity type doped well region 133 can comprise 4H SiC. The second conductivity type doped well region 133 can be doped with p-type impurities. The second conductivity type doped well region 133 can be lightly doped with p-type impurities. The doping concentration of the second conductivity type doped well region 133 can be approximately 1 × 10⁻⁶. 17 cm -3 Or larger and approximately 1×10 19 cm -3 Or even smaller. The material, doping type, doping concentration, etc. of the second conductivity type doped well region 133 are not limited to this, and can be changed in various ways.

[0036] The gate electrode 150 can be positioned on the first conductivity type semiconductor layer 131. The gate electrode 150 can be spaced apart from the first conductivity type semiconductor layer 131. For example, the gate electrode 150 can be spaced apart from the first conductivity type semiconductor layer 131 in a third direction (Z direction) via the gate insulating layer 151. The semiconductor device according to the embodiment can have a planar gate structure. That is, in the semiconductor device according to the embodiment, the gate electrode 150 has a plate shape with an upper surface and a lower surface, and the lower surface of the gate electrode 150 can be positioned at a level higher than the uppermost surface of the first conductivity type semiconductor layer 131. However, the example embodiment is not limited to this, and the semiconductor device according to the embodiment can have a trench-shaped gate structure. For example, in the semiconductor device according to the embodiment, a trench of a predetermined depth can be formed in the first conductivity type semiconductor layer 131, and the gate electrode 150 can be positioned spaced apart from the first conductivity type semiconductor layer 131 in a third direction (Z direction) within the trench. Furthermore, the gate electrode 150 can be positioned to be spaced apart from the first conductivity type semiconductor layer 131 in a first direction (X direction). Please refer to later Figures 15 to 17 An explanation is provided for this.

[0037] The semiconductor device according to the embodiments may include a plurality of gate electrodes 150 arranged spaced apart in a first direction (X direction). For example, the plurality of gate electrodes 150 may be arranged to extend longitudinally in a second direction (Y direction) and be spaced apart in the first direction (X direction).

[0038] In one embodiment, the gate electrode 150 may overlap with at least a portion of the second conductivity type doped well region 133 and the first conductivity type doped pattern 300, which will be described later, in the third direction (Z direction). For example, the gate electrode 150 may overlap with a second portion 320 of the first conductivity type doped pattern 300, which will be described later, in the third direction (Z direction), and may not overlap with the first portion 310 and the third portion 330 of the first conductivity type doped pattern 300 in the third direction (Z direction), but the example embodiment is not limited thereto.

[0039] The gate electrode 150 may include a conductive material. For example, the gate electrode 150 may include polycrystalline silicon doped with impurities. As another example, the gate electrode 150 may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, a conductive metal oxynitride, or a combination thereof. The gate electrode 150 may be formed of a single layer or multiple layers.

[0040] A gate insulating layer 151 may be positioned between a first conductivity type semiconductor layer 131 and a gate electrode 150. That is, the gate insulating layer 151 may be positioned below the gate electrode 150 and may cover the lower surface of the gate electrode 150. In an example embodiment, the side surfaces of the gate insulating layer 151 and the gate electrode 150 may be aligned in the third direction (Z direction). The gate electrode 150 may be insulated from the first conductivity type semiconductor layer 131 by the gate insulating layer 151. The thickness of the gate insulating layer 151 may be nearly constant. For example, the gate insulating layer 151 may have a uniform thickness in the third direction (Z direction). In an embodiment, the gate insulating layer 151 may overlap with the second conductivity type doped well region 133 and the first conductivity type doped pattern 300, which will be described later, in the third direction (Z direction). The lower surface of the gate insulating layer 151 may be in direct contact with the second conductivity type doped well region 133 and the first conductivity type doped pattern 300, which will be described later, but the example embodiment is not limited to this. The upper surface of the gate insulating layer 151 can be in direct contact with the lower surface of the gate electrode 150.

[0041] The gate insulating layer 151 may include an insulating material. For example, the gate insulating layer 151 may include SiO2. However, other materials may also be used, and the material of the gate insulating layer 151 may be varied in various ways. As another example, the gate insulating layer 151 may include SiN, SiON, SiC, SiCN, or combinations thereof. The gate insulating layer 151 may be formed as a single layer or multiple layers.

[0042] A first conductivity type doped pattern 300 may be positioned within a second conductivity type doped well region 133. The first conductivity type doped pattern 300 may be positioned in the upper portion of a first conductivity type semiconductor layer 131. At least a portion of the first conductivity type doped pattern 300 may be surrounded by the second conductivity type doped well region 133. For example, the second conductivity type doped well region 133 may be positioned on opposite sides of at least a portion of the first conductivity type doped pattern 300 in a first direction (X direction). At least a portion of the first conductivity type doped pattern 300 may overlap with at least a portion of the gate electrode 150 and at least a portion of the gate insulating layer 151 in a third direction (Z direction). Furthermore, at least a portion of the first conductivity type doped pattern 300 may overlap with at least a portion of the source electrode 173, which will be described later, in a third direction (Z direction). For example, at least a portion of the first conductivity type doped pattern 300 may overlap with the contact portion 173C of the source electrode 173, which will be described later, in a third direction (Z direction). The upper surface of the first conductivity type doped pattern 300 can contact the gate insulating layer 151 and the silicide layer 190, which will be described later.

[0043] In one embodiment, a first conductivity type doped pattern 300 can extend from the upper surface of the first conductivity type semiconductor layer 131 in the third direction (Z direction). The first conductivity type doped pattern 300 can be embedded within the second conductivity type doped well region 133. In this case, the thickness of the first conductivity type doped pattern 300 in the third direction (Z direction) can be less than the thickness of the second conductivity type doped well region 133 in the third direction (Z direction). Therefore, the lower surface and side surface of the first conductivity type doped pattern 300 can be surrounded by the second conductivity type doped well region 133.

[0044] In one embodiment, at least a portion of the gate electrode 150 may overlap with the first conductivity type doped pattern 300 in the third direction (Z direction). For example, a portion of the gate electrode 150 may overlap with the first conductivity type doped pattern 300 in the third direction (Z direction), and the remaining portion may overlap with the second conductivity type doped well region 133 in the third direction (Z direction). Therefore, the overlap area between the gate electrode 150 and the first conductivity type doped pattern 300 can be reduced, and the resistance value between the gate electrode 150 and the first conductivity type doped pattern 300 can be increased.

[0045] According to an embodiment, a first conductivity type doped pattern 300 of the semiconductor device can be electrically connected to a source electrode 173. The first conductivity type doped pattern 300 can provide an electrical connection path between the source electrode 173 and a second conductivity type doped well region 133. For example, the first conductivity type doped pattern 300 of the semiconductor device according to an embodiment may include a first portion 310 overlapping with a contact portion 173C of the source electrode 173 (described later) in a third direction (Z direction), a second portion 320 positioned adjacent to the gate electrode 150, and a third portion 330 connecting the first portion 310 and the second portion 320. When a conduction signal is applied to the gate electrode 150, a drive current can flow from the source electrode 173 sequentially through the first portion 310, the third portion 330, and the second portion 320 to the second conductivity type doped well region 133. In this case, the first portion 310, the second portion 320, and the third portion 330 of the first conductivity type doped pattern 300 may have a predetermined resistance component, and the first conductivity type doped pattern 300 can be used as a resistive element. For example, the first conductivity type doped pattern 300 can be used as a ballast resistor. Therefore, the first conductivity type doped pattern 300 can be patterned to have a predetermined resistance value. Further reference will follow later. Figure 5 Provide a detailed explanation of this.

[0046] In one embodiment, for the first conductivity type doped pattern 300 to function as a resistive element electrically connecting the contact portion 173C of the source electrode 173 (described later) to the second conductivity type doped well region 133, the first conductivity type doped pattern 300 may include at least one curved portion in a plan view. In one embodiment, the extension length DD of the first conductivity type doped pattern 300 may be greater than the length of the contact portion 173C in the second direction (Y direction). In one embodiment, the width of at least a portion of the first conductivity type doped pattern 300 in the second direction (Y direction) may be less than the length of the contact portion 173C in the second direction (Y direction) (described later). In one embodiment, the width of at least a portion of the first conductivity type doped pattern 300 in the first direction (X direction) may be less than the distance between the contact portion 173C and the gate electrode 150 in the first direction (X direction). Further reference will be made later. Figure 5 Provide a detailed explanation of this.

[0047] The first conductivity type doped pattern 300 may be a doped region formed within the first conductivity type semiconductor layer 131 using an ion implantation process. The first conductivity type doped pattern 300 may be formed of or comprise SiC. For example, the first conductivity type doped pattern 300 may comprise 4H SiC. The first conductivity type doped pattern 300 may be doped with n-type impurities. The first conductivity type doped pattern 300 may be highly doped with n-type impurities. The doping concentration of the first conductivity type doped pattern 300 may be approximately 1 × 10⁻⁶. 18 cm -3 Or larger and approximately 5×10 20 cm -3 Or smaller. The material, doping type, doping concentration, etc. of the first conductivity type doped pattern 300 are not limited to this, and can be changed in various ways.

[0048] The semiconductor device according to the embodiment may further include a second conductivity type doped layer 135 located within a second conductivity type doped well region 133.

[0049] A second conductivity type doped layer 135 may be positioned within a second conductivity type doped well region 133. The second conductivity type doped layer 135 is positioned on top of a first conductivity type semiconductor layer 131 and may have an upper surface in contact with the lower surface of a silicide layer 190 connected to a source electrode 173, which will be described later. In one embodiment, at least a portion of the upper surface of the second conductivity type doped layer 135 may be in contact with the lower surface of the silicide layer 190, but the example embodiment is not limited thereto. As another example, at least a portion of the upper surface of the second conductivity type doped layer 135 may be in contact with the lower surface of the source electrode 173. The second conductivity type doped layer 135 may be buried within the second conductivity type doped well region 133.

[0050] In one embodiment, the second conductivity type doped layer 135 can extend from the upper surface of the first conductivity type semiconductor layer 131 in the third direction (Z direction). In this case, the thickness of the second conductivity type doped layer 135 in the third direction (Z direction) can be less than the thickness of the second conductivity type doped well region 133 in the third direction (Z direction). In another embodiment, the thickness of the second conductivity type doped layer 135 in the third direction (Z direction) can be greater than or equal to the thickness of the first conductivity type doped pattern 300 in the third direction (Z direction), but the example embodiment is not limited thereto. The second conductivity type doped layer 135 can be formed in at least a portion of the second conductivity type doped well region 133 by ion implantation.

[0051] The second conductivity type doped layer 135 may be formed of or comprise SiC. For example, the second conductivity type doped layer 135 may comprise 4H SiC. The second conductivity type doped layer 135 may be doped with p-type impurities. The second conductivity type doped layer 135 may form an ohmic contact with the source electrode 173. For this purpose, the second conductivity type doped layer 135 may be doped with p-type impurities at a high concentration. In an embodiment, the doping concentration of the second conductivity type doped layer 135 may be higher than the doping concentration of the second conductivity type doped well region 133. The doping concentration of the second conductivity type doped layer 135 may be approximately 1 × 10⁻⁶. 18 cm -3 Or larger and approximately 5×10 20 cm -3 Or even smaller. The material, doping type, doping concentration, etc. of the second conductivity type doped layer 135 are not limited to this, and can be changed in various ways.

[0052] The semiconductor device according to the embodiments may further include an interlayer insulating layer 140 positioned on the gate electrode 150.

[0053] An interlayer insulating layer 140 may be positioned on a first conductivity type semiconductor layer 131. The interlayer insulating layer 140 may be positioned on a gate electrode 150. Specifically, the interlayer insulating layer 140 may cover the upper and side surfaces of the gate electrode 150. The interlayer insulating layer 140 may cover the side surface of the gate insulating layer 151. For example, the interlayer insulating layer 140 may contact the upper and side surfaces of the gate electrode 150 and the side surface of the gate insulating layer 151. In an embodiment, the interlayer insulating layer 140 may also be positioned on at least a portion of the first conductivity type doped pattern 300 and at least a portion of the second conductivity type doped well region 133. The interlayer insulating layer 140 may have a lower surface that contacts at least a portion of the upper surface of the first conductivity type doped pattern 300 and the upper surface of the second conductivity type doped well region 133. The gate electrode 150 may be insulated from the source electrode 173 by the interlayer insulating layer 140.

[0054] Interlayer insulating layer 140 may include an insulating material. In some embodiments, interlayer insulating layer 140 may include the same insulating material as gate insulating layer 151. For example, interlayer insulating layer 140 may include SiO2. However, the example embodiments are not limited to this, and interlayer insulating layer 140 may include various types of insulating materials to insulate gate electrode 150 from source electrode 173. For example, interlayer insulating layer 140 may include SiOP, SiN, SiON, or combinations thereof. Interlayer insulating layer 140 may be composed of a single layer or multiple layers. When interlayer insulating layer 140 is made of the same material as gate insulating layer 151, the boundary between interlayer insulating layer 140 and gate insulating layer 151 may not be clearly distinguishable at the contact points.

[0055] The source electrode 173 can be positioned on the second conductivity type doped well region 133. The second conductivity type doped layer 135 and the first conductivity type doped pattern 300 can be positioned between the source electrode 173 and the second conductivity type doped well region 133. The source electrode 173 can be electrically connected to the second conductivity type doped well region 133 through the second conductivity type doped layer 135. The source electrode 173 can also be electrically connected to the first conductivity type doped pattern 300.

[0056] According to an embodiment, the source electrode 173 of the semiconductor device may include a contact portion 173C positioned between a plurality of gate electrodes 150 spaced apart from each other along a first direction (X direction).

[0057] Contact portion 173C can be positioned between a plurality of gate electrodes 150 spaced apart along a first direction (X direction). Contact portion 173C can refer to the portion of source electrode 173 positioned between the plurality of gate electrodes 150 spaced apart along the first direction (X direction). Contact portion 173C can extend longitudinally in a second direction (Y direction). Contact portion 173C can extend in a direction parallel to the gate electrodes 150. Contact portion 173C can be positioned on the side surface of the gate electrode 150. Interlayer insulating layer 140 can be positioned between contact portion 173C and gate electrode 150. Contact portion 173C can be separated from gate electrode 150 through interlayer insulating layer 140. Contact portion 173C can contact the side surface of interlayer insulating layer 140.

[0058] Contact portion 173C may overlap with the second conductivity type doped well region 133 and the first conductivity type doped pattern 300 in the third direction (Z direction). For example, contact portion 173C may overlap with a portion of the second conductivity type doped well region 133 in the third direction (Z direction). Furthermore, contact portion 173C may overlap with a first portion 310 of the first conductivity type doped pattern 300 in the third direction (Z direction), but may not overlap with the second portion 320 and the third portion 330 in the third direction (Z direction). However, the example embodiment is not limited to this, and as another example, contact portion 173C may not overlap with the first conductivity type doped pattern 300 in the third direction (Z direction). In this case, the upper surface of the first conductivity type doped pattern 300 may be covered by the gate insulating layer 151. Contact portion 173C may overlap with the second conductivity type doped layer 135 in the third direction (Z direction).

[0059] In one embodiment, at least a portion of the contact portion 173C may overlap with the first conductivity type doped pattern 300 in the third direction (Z direction). For example, a portion of the contact portion 173C may overlap with the first conductivity type doped pattern 300 in the third direction (Z direction), and the remaining portion may overlap with the second conductivity type doped well region 133 in the third direction (Z direction). Therefore, the overlap area between the contact portion 173C and the first conductivity type doped pattern 300 can be reduced, and the resistance value between the contact portion 173C and the first conductivity type doped pattern 300 can be increased.

[0060] The source electrode 173 may include a conductive material. For example, the source electrode 173 may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal oxide nitride. For example, the source electrode 173 may be formed from the following: titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), silicon titanium nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride. The source electrode 173 may be formed from a single layer or multiple layers. The components include: molybdenum (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof.

[0061] The semiconductor device according to the embodiment may further include a silicide layer 190 positioned between the source electrode 173 and the second conductivity type doped layer 135 and between the source electrode 173 and the first conductivity type doped pattern 300.

[0062] The silicide layer 190 can be conformally positioned along the interface between the source electrode 173 and the second conductivity type doped layer 135, and between the source electrode 173 and the first conductivity type doped pattern 300. The silicide layer 190 can be positioned between the contact portion 173C of the source electrode 173 and the second conductivity type doped well region 133. The silicide layer 190 can be positioned between the contact portion 173C and the first conductivity type doped pattern 300, and between the contact portion 173C and the second conductivity type doped layer 135. The lower surface of the silicide layer 190 can contact the second conductivity type doped layer 135 and the first conductivity type doped pattern 300. In an embodiment, the lower surface of the silicide layer 190 can contact the second conductivity type doped well region 133. The upper surface of the silicide layer 190 can contact the source electrode 173.

[0063] The silicide layer 190 may comprise a metal silicide material. For example, the silicide layer 190 may comprise tungsten silicide (WSi), titanium silicide (TiSi), cobalt silicide (CoSi), nickel silicide (NiSi), or combinations thereof. In the manufacturing process of the semiconductor device according to an embodiment, a silicide process may be performed on the upper surfaces of the second conductivity type doped layer 135 and the first conductivity type doped pattern 300 exposed by trenches between adjacent gate electrodes 150 along a first direction (X direction) to form the silicide layer 190. However, the example embodiment is not limited thereto, and after the source electrode 173 is formed, an annealing process may subsequently be performed to reduce the contact resistance between the second conductivity type doped layer 135 and the contact portion 173C, and between the first conductivity type doped pattern 300 and the contact portion 173C. Therefore, the silicide layer 190 may be formed along the interfaces between the contact portion 173C and the second conductivity type doped layer 135, and between the contact portion 173C and the first conductivity type doped pattern 300.

[0064] Drain electrode 175 may be positioned on a second surface (i.e., lower surface) of substrate 110. The upper surface of drain electrode 175 may contact the lower surface of substrate 110. Drain electrode 175 may have an ohmic contact with substrate 110. The region within substrate 110 in contact with drain electrode 175 may be doped at a relatively high concentration compared to other regions. However, the exemplary embodiment is not limited to this, and another layer may be additionally positioned between drain electrode 175 and substrate 110. For example, a silicide layer may be positioned between drain electrode 175 and substrate 110. The silicide layer may include a metal silicide material. The metal silicide layer may facilitate electrical connection between drain electrode 175 and substrate 110.

[0065] The drain electrode 175 may include a conductive material. For example, the drain electrode 175 may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal oxynitride. The drain electrode 175 may be made of the same material as the source electrode 173, or it may be made of a different material. The drain electrode 175 may be formed as a single layer or multiple layers.

[0066] According to an embodiment, when a conduction signal is applied to the gate electrode 150, the semiconductor device can cause a drive current to flow from the drain electrode 175 toward the source electrode 173 in the third direction (Z direction). In this case, the drive current can flow from the drain electrode 175 through the substrate 110, the first conductivity type semiconductor layer 131, the portion of the second conductivity type doped well region 133 adjacent to the gate electrode 150, and the first conductivity type doped pattern 300 to the source electrode 173.

[0067] Further references are provided below. Figure 5The first conductivity type doping pattern 300 of the semiconductor device according to the embodiment will be described in detail.

[0068] Figure 5 This is a plan view illustrating the arrangement of a first conductivity type doped pattern in a semiconductor device according to an example embodiment. For clarity, in Figure 5 The diagram shows a first conductivity type doped pattern 300, a second conductivity type doped well region 133, a second conductivity type doped layer 135, a contact portion 173C, and a gate electrode 150, with the remaining components omitted from the illustration.

[0069] Further reference Figure 5 According to the embodiment, the first conductivity type doped pattern 300 of the semiconductor device can provide an electrical connection path between the contact portion 173C and the second conductivity type doped well region 133. In this case, the first conductivity type doped pattern 300 can have a predetermined resistance component and can be used as a resistive element. For example, the first conductivity type doped pattern 300 can be used as a ballast resistor.

[0070] The first conductivity type doped pattern 300 of the semiconductor device according to the embodiment may include a first portion 310 overlapping the contact portion 173C in the third direction (Z direction), a second portion 320 positioned adjacent to the gate electrode 150, and a third portion 330 connecting the first portion 310 and the second portion 320.

[0071] The first portion 310 may extend in a first direction (X direction). The first portion 310 may overlap with the contact portion 173C in a third direction (Z direction). The first portion 310 may refer to a first conductivity type doped pattern 300 that extends in the first direction (X direction) and overlaps with the contact portion 173C in the third direction (Z direction). The first portion 310 does not overlap with the gate electrode 150 in the third direction (Z direction). Figure 2 As shown, at least a portion of the first portion 310 may overlap with the interlayer insulating layer 140 in the third direction (Z direction), but the example embodiment is not limited to this. In the embodiment, the first width W1 of the first portion 310 in the second direction (Y direction) may be less than the first length D1 of the contact portion 173C in the second direction (Y direction) (that is, the length of the source electrode 173 in the second direction), but the example embodiment is not limited to this. Therefore, the resistance value of the first portion 310 can be increased. Furthermore, the length of the first portion 310 in the first direction (X direction) may be less than the length between the contact portion 173C and the gate electrode 150 in the first direction (X direction), but the example embodiment is not limited to this.

[0072] The second portion 320 may extend in the first direction (X direction). The second portion 320 may extend in a direction parallel to the first portion 310, but the example embodiment is not limited thereto. The second portion 320 may overlap with the gate electrode 150 in the third direction (Z direction), but the example embodiment is not limited thereto. In the embodiment, the second portion 320 may refer to the portion of the first conductivity type doped pattern 300 that extends in the first direction (X direction) and overlaps with the gate electrode 150 in the third direction (Z direction). The second portion 320 does not overlap with the contact portion 173C in the third direction (Z direction). Figure 3 As shown, at least a portion of the second portion 320 may overlap with the interlayer insulating layer 140 in the third direction (Z direction), but the exemplary embodiment is not limited thereto. In the embodiment, the second width W2 of the second portion 320 in the second direction (Y direction) may be smaller than the second length D2 of the gate electrode 150 in the second direction (Y direction), but the exemplary embodiment is not limited thereto. Therefore, the resistance value of the second portion 320 can be increased. The second width W2 of the second portion 320 in the second direction (Y direction) may be substantially the same as the first width W1 of the first portion 310 in the second direction (Y direction), but the exemplary embodiment is not limited thereto. Reference will be made later. Figure 12 A description of this is provided. Furthermore, the length of the second portion 320 in the first direction (X direction) may be less than the length between the contact portion 173C and the gate electrode 150 in the first direction (X direction), but the example implementation is not limited thereto.

[0073] The third portion 330 may be positioned between the first portion 310 and the second portion 320. The third portion 330 may extend in a second direction (Y direction) to connect the first portion 310 and the second portion 320. The third portion 330 does not overlap with the source electrode 173 and the gate electrode 150 in the third third direction (Z direction). In embodiments, the third portion 330 may refer to the portion of the first conductivity type doped pattern 300 that connects the first portion 310 and the second portion 320 and does not overlap with the source electrode 173 and the gate electrode 150 in the third third direction (Z direction). The third portion 330 may extend in a direction parallel to the gate electrode 150, but the exemplary embodiments are not limited thereto. The third portion 330 may extend in a direction parallel to the contact portion 173C, but the exemplary embodiments are not limited thereto. Figure 4 As shown, the third portion 330 may overlap with the interlayer insulating layer 140 in the third direction (Z direction), but the example embodiment is not limited to this. The third width W3 of the third portion 330 in the first direction (X direction) may be less than the length between the contact portion 173C and the gate electrode 150 in the first direction (X direction). In this case, the resistance value of the third portion 330 may be increased.

[0074] In this embodiment, the first portion 310 to the third portion 330 may have a predetermined resistance value. Therefore, the first conductivity type doped pattern 300 can be used as a resistive element with a predetermined resistance value. That is, the first conductivity type doped pattern 300 can be used as a resistive element that electrically connects the contact portion 173C of the source electrode 173 and the second conductivity type doped well region 133.

[0075] In this embodiment, the first conductivity type doped pattern 300 can have various shapes to achieve a predetermined resistance value. For example, the first width W1 of the first portion 310 in the second direction (Y direction) can be smaller than the first length D1 of the contact portion 173C in the second direction (Y direction), or the second width W2 of the second portion 320 in the second direction (Y direction) can be smaller than the second length D2 of the gate electrode 150 in the second direction (Y direction), or the third width W3 of the third portion 330 in the first direction (X direction) can be smaller than the length between the contact portion 173C and the gate electrode 150 in the first direction (X direction). In this case, current can flow from the contact portion 173C sequentially through the first portion 310, the third portion 330, and the second portion 320 to the second conductivity type doped well region 133, thereby reducing the drive current of the semiconductor device according to the embodiment (see [link]). Figure 6 (C1).

[0076] In an embodiment, the first conductivity type doped pattern 300 may include at least one curved portion in a plan view. For example, the first conductivity type doped pattern 300 may include curved portions positioned between the first portion 310 and the third portion 330 and between the second portion 320 and the third portion 330. The curved portions may be located at the points where the first portion 310 and the third portion 330 intersect, and at the points where the second portion 320 and the third portion 330 intersect. Since the first conductivity type doped pattern 300 of the semiconductor device according to the embodiment includes at least one curved portion, the extension length of the first conductivity type doped pattern 300 can be increased, and the resistance value of the first conductivity type doped pattern 300 can be increased, thereby reducing the drive current of the semiconductor device according to the embodiment (see [link]). Figure 6 (C1).

[0077] In an embodiment, the extension length DD of the first conductivity type doped pattern 300 can be greater than the first length D1 of the contact portion 173C in the second direction (Y direction). For example, the sum of the lengths of the first portion 310, the second portion 320, and the third portion 330 in the second direction (Y direction) can be greater than the first length D1 of the contact portion 173C in the second direction (Y direction). Here, the extension length DD of the first conductivity type doped pattern 300 can refer to the sum of the lengths of each of the first portion 310 to the third portion 330 of the first conductivity type doped pattern 300 in the extension direction. For example, the extension length DD of the first conductivity type doped pattern 300 can be the sum of the lengths of the first portion 310 in the first direction (X direction), the second portion 320 in the first direction (X direction), and the third portion 330 in the second direction (Y direction). Furthermore, the sum of the lengths of the first portion 310 in the first direction (X direction), the second portion 320 in the first direction (X direction), and the third portion 330 in the second direction (Y direction) can be greater than the second length D2 of the gate electrode 150 in the second direction (Y direction). In this case, the resistance value of the first conductivity type doped pattern 300 increases, thereby reducing the drive current of the semiconductor device according to the embodiment (see [link]). Figure 6 (C1).

[0078] exist Figures 1 to 5 In this embodiment, the first conductivity type doped pattern 300 is described as including a portion extending in a first direction (X direction) and / or a second direction (Y direction), but the example implementation is not limited to this, and the shape of the first conductivity type doped pattern 300 can be changed in various ways.

[0079] According to an embodiment, the second conductivity type doped well region 133 of the semiconductor device may include a patterned portion 133PP positioned between the second conductivity type doped layer 135 and the third portion 330.

[0080] like Figures 3 to 5As shown, the patterned portion 133PP can be positioned between the second conductivity type doped layer 135 and the first conductivity type doped pattern 300. For example, the patterned portion 133PP can be positioned between the second conductivity type doped layer 135 and the third portion 330, but the exemplary embodiment is not limited thereto. The patterned portion 133PP can designate a second conductivity type doped well region 133 located between the second conductivity type doped layer 135 and the third portion 330. The patterned portion 133PP can extend in a second direction (Y direction). The patterned portion 133PP can extend parallel to the third portion 330. At least a portion of the first conductivity type doped pattern 300 can be defined by the patterned portion 133PP. One end of the patterned portion 133PP can contact the first portion 310, and one side of the patterned portion 133PP can contact the third portion 330. In an embodiment, the patterned portion 133PP can be positioned on one side of the third portion 330 in a first direction (X direction), but the exemplary embodiment is not limited thereto. Therefore, the second conductivity type doped well region 133 can be positioned on opposite sides of the third portion 330 in the first direction (X direction).

[0081] In one embodiment, the length of the patterned portion 133PP in the second direction (Y direction) may be less than the first length D1 of the contact portion 173C in the second direction (Y direction). In this case, a portion of the contact portion 173C and the first conductivity type doped pattern 300 may overlap in the third direction (Z direction).

[0082] In one embodiment, the patterned portion 133PP may overlap with a portion of the contact portion 173C in the third direction (Z direction). For example, a portion of the contact portion 173C may overlap with the first conductivity type doped pattern 300 in the third direction (Z direction), and the remaining portion of the contact portion 173C may overlap with the patterned portion 133PP in the third direction (Z direction). The upper surface of the patterned portion 133PP may be in contact with the silicide layer 190.

[0083] Further references will be made below. Figure 6 Describe the effects of the semiconductor device according to the implementation method.

[0084] Figure 6 This is a plan view illustrating the flow of drive current in a semiconductor device according to an example embodiment.

[0085] Further reference Figure 6According to the embodiment, the source electrode 173, drain electrode 175, and gate electrode 150 of the semiconductor device can constitute a transistor. In this case, a portion of the second conductivity type doped well region 133 can be used as the channel of the transistor. According to the embodiment, when a conduction signal is applied to the gate electrode 150, the semiconductor device can allow a drive current C1 to flow sequentially from the contact portion 173C of the source electrode 173 through the first portion 310, the third portion 330, and the second portion 320 to the second conductivity type doped well region 133.

[0086] According to embodiments, the first conductivity type doped pattern 300 of the semiconductor device can have various shapes, thereby having a predetermined resistance value. For example, the first width W1 of the first portion 310 in the second direction (Y direction) can be less than the first length D1 of the contact portion 173C in the second direction (Y direction), or the second width W2 of the second portion 320 in the second direction (Y direction) can be less than the second length D2 of the gate electrode 150 in the second direction (Y direction), or the third width W3 of the third portion 330 in the first direction (X direction) can be less than the length between the contact portion 173C and the gate electrode 150 in the first direction (X direction). As another example, the first conductivity type doped pattern 300 may include at least one curved portion in a planar view. As another example, the extension length DD of the first conductivity type doped pattern 300 can be greater than the first length D1 of the contact portion 173C in the second direction (Y direction). Therefore, within a range where the distance between the gate electrode 150 and the contact portion 173C remains unchanged, the resistance value of the first conductivity type doped pattern 300 can be increased, and the magnitude of the drive current C1 flowing through the first conductivity type doped pattern 300 can be decreased. Thus, the reliability of the semiconductor device according to the embodiment can be improved by reducing the magnitude of the drive current C1 without changing the size of the transistor device.

[0087] In the following text, reference will be made to Figures 7 to 14 Describes the blocking pattern of a semiconductor device according to some embodiments.

[0088] Figure 7 This is a plan view showing the arrangement of a first conductivity type doped pattern of a semiconductor device according to some embodiments. Figures 8 to 12 This is a plan view illustrating a semiconductor device according to some embodiments. Figure 13 and Figure 14 This is a cross-sectional view showing a semiconductor device according to some embodiments.

[0089] Figures 7 to 14 It shows according to Figures 1 to 6 Examples of various modifications to the semiconductor device of the embodiments shown. Figures 7 to 14 The implementation methods shown are the same as Figures 1 to 6The embodiments shown are essentially the same, so their description will not be repeated, and the differences will be explained primarily. Furthermore, the same reference numerals are used for the same components as in the previous embodiments.

[0090] refer to Figure 7 According to some embodiments, the first conductivity type doped pattern 300 of the semiconductor device may also include a fourth portion 340 connected to the second portion 320.

[0091] In some embodiments, the fourth portion 340 may extend longitudinally in the second direction (Y direction). The fourth portion 340 may extend parallel to the gate electrode 150. The fourth portion 340 may extend parallel to the third portion 330, but the exemplary embodiments are not limited thereto. The fourth portion 340 may overlap with the gate electrode 150 in the third direction (Z direction) and may not overlap with the contact portion 173C in the third direction (Z direction). The fourth portion 340 may completely overlap with the gate electrode 150 in the third direction (Z direction), but the exemplary embodiments are not limited thereto. At least a portion of the fourth portion 340 may be surrounded by a second conductivity type doped well region 133.

[0092] In some embodiments, the second conductivity type doped well region 133 may be positioned between the fourth portion 340 and the second portion 320. The fourth portion 340 may be defined by the second conductivity type doped well region 133. Opposite sides of the fourth portion 340 in the first direction (X direction) may contact the second conductivity type doped well region 133, but are not limited thereto.

[0093] refer to Figure 8 The first conductivity type doped pattern 300 of the semiconductor device according to some embodiments can have various shapes. For example, the semiconductor device according to some embodiments may include a first gate electrode 150a and a second gate electrode 150b positioned on opposite sides of the contact portion 173C. Furthermore, the semiconductor device according to some embodiments may include a first doped pattern 300a positioned between the contact portion 173C and the first gate electrode 150a, and a second doped pattern 300b positioned between the contact portion 173C and the second gate electrode 150b. The first doped pattern 300a and the second doped pattern 300b may have the same shape as... Figures 1 to 6 The configuration is substantially the same as that of the first conductivity type doped pattern 300 in the implementation.

[0094] exist Figure 8In the diagram, the first doped pattern 300a and the second doped pattern 300b are shown as having a symmetrical structure relative to each other; however, this is not a limitation. As another example, the first doped pattern 300a and the second doped pattern 300b may have asymmetrical shapes. For example, the first doped pattern 300a may be asymmetrical with respect to the second doped pattern 300b about a reference axis extending in a second direction (Y direction). The first doped pattern 300a and the second doped pattern 300b have the same shape and may be arranged spaced apart from each other in a first direction (X direction). In some embodiments, at least one of the first doped pattern 300a and the second doped pattern 300b may have a symmetrical structure with respect to each other. Figures 1 to 6 The first conductivity type doped pattern 300 of the embodiment has the same shape.

[0095] refer to Figure 9 and Figure 10 The first conductivity type doped pattern 300 of the semiconductor device according to some embodiments may have various shapes. In some embodiments, the third portion 330 of the first conductivity type doped pattern 300 may include a plurality of extension portions 331, 332, 333 extending in different directions.

[0096] For example, such as Figure 9 As shown, the third part 330 may include a first extension 331 connected to the first part 310 and extending in a second direction (Y direction), a second extension 332 connected to the first extension 331 and extending in a first direction (X direction), and a third extension 333 connected to the second extension 332 and the second part 320 and extending in a second direction (Y direction).

[0097] The first extension portion 331 and the third extension portion 333 may extend in a parallel direction, and the second extension portion 332 may extend in a direction parallel to the first portion 310 and the second portion 320, but the exemplary embodiments are not limited thereto. In some embodiments, the lengths of the first extension portion 331 and the third extension portion 333 in the second direction (Y direction) may be less than or equal to the length of the contact portion 173C in the second direction (Y direction), but are not limited thereto. In some embodiments, the length of the second extension portion 332 in the first direction (X direction) may be less than the length between the gate electrode 150 and the contact portion 173C in the first direction (X direction), but the exemplary embodiments are not limited thereto.

[0098] In some embodiments, the first extension 331 to the third extension 333 may be defined by a second conductivity type doped well region 133. For example, the second conductivity type doped well region 133 may further include a protrusion 133_P positioned between the first extension 331 and the third extension 333. The protrusion 133_P may be positioned between the first extension 331 and the third extension 333. One side of the protrusion 133_P may contact the first extension 331, the other side may contact the third extension 333, and one end of the protrusion 133_P may contact the second extension 332. The length of the protrusion 133_P in the second direction (Y direction) may be less than the length of the contact portion 173C in the second direction (Y direction).

[0099] In some embodiments, since the third portion 330 includes multiple extension portions 331, 332, 333, the extension length of the first conductivity type doped pattern 300 can be further increased, and the resistance value of the first conductivity type doped pattern 300 can be further increased, thereby reducing the drive current of the semiconductor device according to some embodiments (see...). Figure 6 (C1). Therefore, the reliability of semiconductor devices can be improved.

[0100] exist Figure 9 In the example, the third part 330 is shown as including three extensions 331, 332, and 333, but the example implementation is not limited thereto. As another example, such as... Figure 10 As shown, the third portion 330 of a semiconductor device according to some embodiments may include four extensions extending in a second direction (Y direction) and a portion extending in a first direction (X direction) to connect the extensions. In some embodiments, the second conductivity type doped well region 133 may include a plurality of protrusions 133_P1, 133_P2 positioned between the extensions extending in the second direction (Y direction). As another example, the third portion 330 may extend in a direction different from the first direction (X direction) and the second direction (Y direction). As another example, the third portion 330 may have a shape having a predetermined curvature.

[0101] refer to Figure 11According to some embodiments, a first conductivity type doped pattern 300 of a semiconductor device may include a plurality of first portions 310 overlapping the contact portion 173C in a third third direction (Z direction). In some embodiments, the plurality of first portions 310 may be provided to overlap the contact portion 173C in a third third direction (Z direction). The plurality of first portions 310 may be defined by a second conductivity type doped well region 133. At least a portion of the plurality of first portions 310 may be surrounded by the second conductivity type doped well region 133. For example, a patterned portion 133PP of the second conductivity type doped well region 133 may be positioned between the plurality of first portions 310, and the plurality of first portions 310 may be spaced apart in a second direction (Y direction) by the patterned portion 133PP.

[0102] Furthermore, the first conductivity type doped pattern 300 of the semiconductor device according to some embodiments may include a plurality of second portions 320 overlapping the gate electrode 150 in the third direction (Z direction). In some embodiments, the second portions 320 may be provided as a plurality to overlap the gate electrode 150 in the third direction (Z direction). The plurality of second portions 320 may be defined by a second conductivity type doped well region 133. For example, at least a portion of the plurality of second portions 320 may be surrounded by the second conductivity type doped well region 133.

[0103] In some embodiments, the third portion 330 may be connected between the plurality of first portions 310 and the plurality of second portions 320. In some embodiments, the first conductivity type doped pattern 300 may have an approximate "H" shape in a plane, but the example embodiments are not limited thereto.

[0104] refer to Figure 12According to some embodiments, the first conductivity type doped pattern 300 of a semiconductor device may include portions with different widths. For example, the first width W1 of the first portion 310 in the second direction (Y direction), the second width W2 of the second portion 320 in the second direction (Y direction), and the fifth width W5 of the second extension portion 332 in the second direction (Y direction) may be different. For example, the first width W1 of the first portion 310 in the second direction (Y direction) may be different from the second width W2 of the second portion 320 in the second direction (Y direction). The first width W1 of the first portion 310 in the second direction (Y direction) may be greater than the second width W2 of the second portion 320 in the second direction (Y direction), but the example embodiment is not limited thereto. Furthermore, the fourth width W4 of the first extension portion 331 in the first direction (X direction) and the sixth width W6 of the third extension portion 333 in the first direction (X direction) may be different. The fourth width W4 of the first extension portion 331 in the first direction (X direction) may be greater than the sixth width W6 of the third extension portion 333 in the first direction (X direction), but the example embodiment is not limited thereto.

[0105] In some embodiments, the first width W1 of the first portion 310 in the second direction (Y direction), the fourth width W4 of the first extension portion 331 in the first direction (X direction), the fifth width W5 of the second extension portion 332 in the second direction (Y direction), the sixth width W6 of the third extension portion 333 in the first direction (X direction), and the second width W2 of the second portion 320 in the second direction (Y direction) can decrease sequentially. That is, the first width W1 of the first portion 310 in the second direction (Y direction) can be the largest, and the second width W2 of the second portion 320 in the second direction (Y direction) can be the smallest, but the example embodiments are not limited thereto. In some embodiments, since the first conductivity type doped pattern 300 includes portions with different widths, the first conductivity type doped pattern 300 with a desired resistance value can be easily designed.

[0106] refer to Figure 13 and Figure 14 The semiconductor device according to some example embodiments may also include a dummy pattern 139 located within a first conductivity type doped pattern 300_1.

[0107] The dummy pattern 139 can be positioned in the upper portion of the first conductivity type semiconductor layer 131. The upper surface of the dummy pattern 139 can be coplanar with the upper surface of the first conductivity type doped pattern 300_1. The dummy pattern 139 can be surrounded by the first conductivity type doped pattern 300_1. For example, the first conductivity type doped pattern 300_1 can be positioned on the lower and side surfaces of the dummy pattern 139. Therefore, the dummy pattern 139 can be positioned separately from the second conductivity type doped well region 133.

[0108] In some embodiments, the dummy pattern 139 can extend from the upper surface of the first conductivity type semiconductor layer 131 in the third direction (Z direction). The dummy pattern 139 can be embedded within the first conductivity type doped pattern 300_1. In this case, the thickness of the dummy pattern 139 in the third direction (Z direction) can be less than the thickness of the first conductivity type doped pattern 300_1 in the third direction (Z direction). Therefore, the lower surface and side surfaces of the dummy pattern 139 can be surrounded by the first conductivity type doped pattern 300_1.

[0109] In some implementations, such as Figure 13 As shown, the thickness of the dummy pattern 139 in the third direction (Z direction) can be less than the thickness of the second conductivity type doped layer 135 in the third direction (Z direction). In this case, the thickness of the first conductivity type doped pattern 300_1 in the third direction (Z direction) can be less than the thickness of the second conductivity type doped layer 135 in the third direction (Z direction). However, the example implementation is not limited to this, and as... Figure 14 As shown, the thickness of the dummy pattern 139 in the third direction (Z direction) can be substantially the same as the thickness of the second conductivity type doped layer 135 in the third direction (Z direction). In this case, the thickness of the first conductivity type doped pattern 300_1 in the third direction (Z direction) can be greater than the thickness of the second conductivity type doped layer 135 in the third direction (Z direction).

[0110] In some embodiments, the dummy pattern 139 may be a doped region formed within the dummy pattern 139 using an ion implantation process. The dummy pattern 139 may include SiC. For example, the dummy pattern 139 may include 4H SiC. The dummy pattern 139 may have a second conductivity type. The dummy pattern 139 may be doped with p-type impurities. The doping concentration of the dummy pattern 139 may be substantially the same as the doping concentration of the second conductivity type doped layer 135, but the example embodiments are not limited thereto. As another example, the doping concentration of the dummy pattern 139 may be substantially the same as the doping concentration of the second conductivity type doped well region 133. The material, doping type, doping concentration, etc., of the dummy pattern 139 are not limited thereto and may be varied in various ways.

[0111] According to some embodiments, a first conductivity type doped pattern 300_1 of a semiconductor device may include a first vertical portion 300_V1 electrically connected to a contact portion 173C, a second vertical portion 300_V2 positioned adjacent to a gate electrode 150, and a horizontal portion 300_H connecting the first vertical portion 300_V1 and the second vertical portion 300_V2.

[0112] In some embodiments, the first vertical portion 300_V1 may overlap with the contact portion 173C in the third direction (Z direction) and may not overlap with the gate electrode 150 in the third direction (Z direction). The first vertical portion 300_V1 may be positioned between the second conductivity type doped layer 135 and the dummy pattern 139. The first vertical portion 300_V1 may contact the second conductivity type doped layer 135 and the dummy pattern 139, but the example embodiments are not limited thereto.

[0113] In some embodiments, the second vertical portion 300_V2 may overlap with the gate electrode 150 in the third direction (Z direction) and may not overlap with the contact portion 173C in the third direction (Z direction). The second vertical portion 300_V2 may be positioned between the second conductivity type doped well region 133 and the dummy pattern 139. The second vertical portion 300_V2 may contact the second conductivity type doped well region 133 and the dummy pattern 139, but the exemplary embodiments are not limited thereto. In some embodiments, the dummy pattern 139 may be positioned between the first vertical portion 300_V1 and the second vertical portion 300_V2. That is, the first vertical portion 300_V1 and the second vertical portion 300_V2 may be spaced apart in the first direction (X direction) by the dummy pattern 139.

[0114] The horizontal portion 300_H can be positioned between the first vertical portion 300_V1 and the second vertical portion 300_V2. The horizontal portion 300_H can connect the first vertical portion 300_V1 and the second vertical portion 300_V2. The horizontal portion 300_H can be positioned between the second conductivity type doped well region 133 and the dummy pattern 139. The horizontal portion 300_H can be positioned on the lower surface of the dummy pattern 139. The horizontal portion 300_H can contact the lower surface of the dummy pattern 139.

[0115] A semiconductor device according to some embodiments may include a dummy pattern 139 positioned within a first conductivity type doped pattern 300_1. Therefore, a path for the drive current can be formed from the contact portion 173C, sequentially through the first vertical portion 300_V1, the horizontal portion 300_H, and the second vertical portion 300_V2 of the first conductivity type doped pattern 300_1, to the channel region of the second conductivity type doped well region 133. Therefore, within a range where the distance between the gate electrode 150 and the contact portion 173C remains unchanged, the resistance value of the first conductivity type doped pattern 300_1 can be increased, and the magnitude of the drive current flowing through the first conductivity type doped pattern 300_1 can be decreased. Therefore, the reliability of the semiconductor device can be improved by reducing the magnitude of the drive current C1 without changing the size of the transistor device.

[0116] In the following text, reference will be made to Figures 15 to 17 Describes a semiconductor device according to some implementation methods.

[0117] Figures 15 to 17 This is a cross-sectional view showing a semiconductor device according to some example embodiments.

[0118] Figures 15 to 17 It shows according to Figure 13 and Figure 14 Examples of various modifications to the semiconductor device of the embodiments shown. Figures 15 to 17 The implementation methods shown are the same as Figure 13 and Figure 14 The embodiments shown are substantially the same, therefore repeated descriptions will be omitted, and the differences will be mainly described. Furthermore, the same reference numerals are used for the same components as in the previous embodiments.

[0119] refer to Figures 15 to 17 According to some embodiments, the first conductivity type semiconductor layer 131 of the semiconductor device may include a gate trench 160.

[0120] In some embodiments, the gate trench 160 may be formed to have a predetermined depth in the upper surface of the first conductivity type semiconductor layer 131. For example... Figures 15 to 17 As shown, the gate trench 160 can be formed with an approximately U-shaped cross-section. The gate trench 160 may include a bottom surface and sidewalls extending from the bottom surface. Figures 15 to 17 In this example, the angle of the sidewall relative to the bottom surface of the gate trench 160 is depicted as vertical (e.g., right angle), but the example implementation is not limited to this. For example, the angle of the sidewall relative to the bottom surface of the gate trench 160 may be an angle.

[0121] The gate trench 160 may extend in a second direction (Y direction). A semiconductor device according to an embodiment may include a plurality of gate trenches 160 extending longitudinally in the second direction (Y direction). That is, a plurality of gate trenches 160 may be provided and may extend longitudinally in the second direction (Y direction). Each of the plurality of gate trenches 160 may extend in a direction parallel to each other. The plurality of gate trenches 160 may be arranged spaced apart from each other in a first direction (X direction).

[0122] In some embodiments, each of the plurality of gate trenches 160 may include a bottom surface and sidewalls extending from the bottom surface. The bottom surface of each of the plurality of gate trenches 160 may be defined by a first conductivity type semiconductor layer 131. The sidewalls of each of the plurality of gate trenches 160 may be defined by the first conductivity type semiconductor layer 131, a second conductivity type doped well region 133, and a first conductivity type doped pattern 300_2.

[0123] In some embodiments, gate electrode 150_1 may be positioned within a gate trench 160 of a first conductivity type semiconductor layer 131. Gate electrode 150_1 may be spaced apart from the first conductivity type semiconductor layer 131. Gate electrode 150_1 may be spaced apart from the first conductivity type semiconductor layer 131 at a substantially constant interval. However, the example embodiments are not limited thereto, and the distance between gate electrode 150_1 and the first conductivity type semiconductor layer 131 may vary depending on the location. Gate electrode 150_1 may have a cross-sectional shape similar to the cross-sectional shape of gate trench 160. Gate electrode 150_1 may include a lower surface and a side surface extending from the lower surface, and the lower surface and side surface of gate electrode 150_1 may be formed in a cross-section with an approximately U-shaped shape along the gate trench 160. Gate electrode 150_1 may also include an upper surface facing the lower surface, and the side surface may be connected between the lower surface and the upper surface. The lower surface of gate electrode 150_1 may face the bottom surface of gate trench 160. The side surface of the gate electrode 150_1 may face the sidewall of the gate trench 160.

[0124] In some embodiments, the interlayer insulating layer 140_1 may be positioned on the bottom surface and sidewalls of the gate trench 160. The interlayer insulating layer 140_1 may be positioned on the bottom surface and sidewalls of the gate trench 160 with a substantially uniform thickness. Therefore, the distance between the gate electrode 150_1 and the first conductivity type semiconductor layer 131 may be almost constant.

[0125] According to some embodiments, the semiconductor device may also include a dummy pattern 139 positioned within a first conductivity type doped pattern 300_2.

[0126] In some embodiments, the dummy pattern 139 can extend from the upper surface of the first conductivity type semiconductor layer 131 in a third direction (Z direction). For example, as Figure 15 and Figure 16 As shown, the thickness of the dummy pattern 139 in the third direction (Z direction) can be less than the thickness of the second conductivity type doped layer 135 in the third direction (Z direction). In this case, the thickness of the first conductivity type doped pattern 300_2 in the third direction (Z direction) can be less than or equal to the thickness of the second conductivity type doped layer 135 in the third direction (Z direction). However, the example implementation is not limited to this, and as... Figure 17 As shown, the thickness of the dummy pattern 139 in the third direction (Z direction) can be substantially the same as the thickness of the second conductivity type doped layer 135 in the third direction (Z direction). In this case, the thickness of the first conductivity type doped pattern 300_2 in the third direction (Z direction) can be greater than the thickness of the second conductivity type doped layer 135 in the third direction (Z direction). The remaining description of the dummy pattern 139 is as follows... Figure 13 and Figure 14 The description of the dummy pattern 139 in the implementation method is basically the same, so it will be omitted.

[0127] In some embodiments, a first conductivity type doped pattern 300_2 may be connected between the contact portion 173C and the second conductivity type doped well region 133. The first conductivity type doped pattern 300_2 may overlap with the gate electrode 150_1 in a first direction (X direction). The first conductivity type doped pattern 300_2 may not overlap with the gate electrode 150_1 in a third direction (Z direction).

[0128] In some implementations, such as Figure 15 As shown, the first conductivity type doped pattern 300_2 may include a first vertical portion 300_V1 overlapping the contact portion 173C in the third direction (Z direction), a second vertical portion 300_V2 positioned adjacent to the gate electrode 150_1, and a horizontal portion 300_H connecting the first vertical portion 300_V1 and the second vertical portion 300_V2. The second vertical portion 300_V2 may be positioned between the dummy pattern 139 and the interlayer insulating layer 140_1. The first vertical portion 300_V1 may be electrically connected to the contact portion 173C. The second vertical portion 300_V2 may be positioned on one side of the gate electrode 150_1. The second vertical portion 300_V2 does not overlap with the contact portion 173C in the third direction (Z direction). In some embodiments, the dummy pattern 139 may be positioned between the first vertical portion 300_V1 and the second vertical portion 300_V2.

[0129] In some implementations, such as Figure 16As shown, the first conductivity type doped pattern 300_2 may include a first horizontal portion 300_H1 connecting the first vertical portion 300_V1 and the second vertical portion 300_V2, and a second horizontal portion 300_H2 positioned between the second vertical portion 300_V2 and the interlayer insulating layer 140_1. The first horizontal portion 300_H1 may be positioned between the dummy pattern 139 and the second conductivity type doped well region 133, and the first vertical portion 300_V1 may be positioned between the capping layer 142 and the second conductivity type doped well region 133.

[0130] According to some embodiments, the semiconductor device may have a path for driving current formed sequentially from the contact portion 173C through a first vertical portion 300_V1, a horizontal portion 300_H, and a second vertical portion 300_V2 of the first conductivity type doped pattern 300_2 to a channel region of the second conductivity type doped well region 133. Therefore, within a range where the distance between the gate electrode 150_1 and the contact portion 173C remains unchanged, the resistance value of the first conductivity type doped pattern 300_2 can be increased, and the magnitude of the driving current flowing through the first conductivity type doped pattern 300_2 can be decreased. Therefore, the reliability of the semiconductor device can be improved by reducing the magnitude of the driving current without changing the size of the transistor device.

[0131] Although the embodiments have been described in detail above, the scope of this disclosure is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of this disclosure as defined in the appended claims also fall within the scope of this disclosure.

[0132] <Description of Symbols>

[0133] 110: Substrate

[0134] 131: First conductivity type semiconductor layer

[0135] 133: Second conductivity type doped well region

[0136] 140: Interlayer insulation layer

[0137] 150: Gate electrode

[0138] 173: Source Electrode

[0139] 175: Drain electrode

[0140] 300: First conductivity type doped pattern

[0141] This application claims priority and benefit to Korean Patent Application No. 10-2024-0197472, filed with the Korean Intellectual Property Office on December 26, 2024, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: The substrate includes a first surface and a second surface that are opposite to each other; A first conductivity type semiconductor layer is positioned on the first surface of the substrate; The second conductivity type doped well region is located within the first conductivity type semiconductor layer; The gate electrode is positioned on the semiconductor layer of the first conductivity type; A gate insulating layer is positioned between the first conductivity type semiconductor layer and the gate electrode; A first conductivity type doped pattern is positioned within the second conductivity type doped well region; The source electrode is positioned on the second conductivity type doped well region and includes a contact portion electrically connected to the first conductivity type doped pattern; as well as The drain electrode is positioned on the second surface of the substrate. The first conductivity type doped pattern includes: The first portion extends in a first direction and overlaps with the contact portion of the source electrode. The second part extends in the first direction and is positioned adjacent to the gate electrode, and The third part connects the first part and the second part, and The width of the first portion in the second direction is less than the length of the contact portion in the second direction, or the width of the second portion in the second direction is less than the length of the gate electrode in the second direction, and the second direction is perpendicular to the first direction.

2. The semiconductor device as described in claim 1, The second portion overlaps with the gate electrode in a third direction perpendicular to both the first and second directions. The first part and the third part do not overlap with the gate electrode in the third direction.

3. The semiconductor device as described in claim 2, The second part and the third part do not overlap with the contact part in the third direction.

4. The semiconductor device as described in claim 1, Wherein the extension length of the first conductivity type doped pattern is greater than the length of the contact portion, and The extension length of the first conductivity type doped pattern includes the length of the first portion in the first direction, the length of the second portion in the first direction, and the length of the third portion in the second direction.

5. The semiconductor device as described in claim 4, The first conductivity type doped pattern includes at least one curved portion in the planar view.

6. The semiconductor device as claimed in claim 1, The third portion extends in the second direction, which intersects with the first direction.

7. The semiconductor device as claimed in claim 6, The width of the third portion in the first direction is less than the distance between the contact portion and the gate electrode.

8. The semiconductor device as claimed in claim 1, The contact portion extends in the first direction, and The width of the first portion in the second direction is less than the length of the contact portion in the second direction.

9. The semiconductor device as claimed in claim 1, The gate electrode extends in the second direction, and The width of the second portion in the second direction is less than the length of the gate electrode in the second direction.

10. The semiconductor device as claimed in claim 1, The width of the first portion in the second direction is different from the width of the second portion in the second direction.

11. The semiconductor device of claim 1, further comprising: A second conductivity type doped layer is positioned between the second conductivity type doped well region and the contact portion. The second conductivity type doped well region includes a patterned portion located between the second conductivity type doped layer and the third portion.

12. The semiconductor device as claimed in claim 11, The patterned portion and the contact portion extend in the second direction, and The length of the patterned portion in the second direction is less than the length of the contact portion in the second direction.

13. The semiconductor device of claim 11, further comprising: A silicide layer is positioned between the contact portion and the first portion. The upper surface of the patterned portion is in contact with the silicide layer.

14. The semiconductor device as claimed in claim 1, The second conductivity type doped well region is located on opposite sides of the third part.

15. The semiconductor device as claimed in claim 1, The third portion extends in a direction parallel to the gate electrode.

16. A semiconductor device, comprising: The substrate includes a first surface and a second surface that are opposite to each other; A first conductivity type semiconductor layer is positioned on the first surface of the substrate; The second conductivity type doped well region is located within the first conductivity type semiconductor layer; A first conductivity type doped pattern is positioned within the second conductivity type doped well region; The gate electrode is positioned on the semiconductor layer of the first conductivity type; A gate insulating layer is positioned between the first conductivity type semiconductor layer and the gate electrode; The source electrode includes a contact portion positioned on a doped well region of the second conductivity type; as well as The drain electrode is positioned on the second surface of the substrate. The first conductivity type doped pattern includes: The first portion overlaps with the contact portion of the source electrode and extends in a first direction. The second part overlaps with the gate electrode and extends in the first direction, and The third part connects the first part and the second part and extends in a second direction intersecting the first direction, and The sum of the length of the first part in the first direction, the length of the second part in the first direction, and the length of the third part in the second direction is greater than the length of the source electrode in the second direction.

17. The semiconductor device as claimed in claim 16, The width of the first portion in the second direction is less than the length of the source electrode in the second direction.

18. The semiconductor device as claimed in claim 16, The width of the second portion in the second direction is less than the length of the gate electrode in the second direction.

19. The semiconductor device as claimed in claim 16, The third portion does not overlap with the gate electrode and the contact portion in a third direction perpendicular to the first and second directions.

20. A semiconductor device, comprising: The substrate includes a first surface and a second surface that are opposite to each other; A first conductivity type semiconductor layer is positioned on the first surface of the substrate and includes a gate trench. The second conductivity type doped well region is located within the first conductivity type semiconductor layer; A first conductivity type doped pattern is positioned within the second conductivity type doped well region; A dummy pattern is positioned within the first conductivity type doped pattern; The gate electrode is positioned within the gate trench; An interlayer insulating layer is positioned between the first conductivity type semiconductor layer and the gate electrode; The source electrode includes a contact portion positioned on a doped well region of the second conductivity type; as well as The drain electrode is positioned on the second surface of the substrate. The first conductivity type doped pattern includes: The first vertical portion overlaps with the contact portion. The second vertical portion is positioned on one side of the gate electrode and does not overlap with the contact portion. The horizontal portion connects the first vertical portion and the second vertical portion, and The dummy pattern is positioned between the first vertical portion and the second vertical portion.

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