A semiconductor gate structure and a method of fabricating the same
By etching the wafer edge after depositing gate metal to remove metal particle defects, the problem of wafer surface scratches is solved, and the yield of semiconductor devices is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI INTEGRATED CIRCUIT EQUIPMENT & MATERIALS INDUSTRY INNOVATION CENTER CO LTD
- Filing Date
- 2024-12-24
- Publication Date
- 2026-06-26
AI Technical Summary
In existing technologies, gate bending and bridging problems caused by wafer surface scratches during the fabrication process of semiconductor devices affect yield.
After depositing the gate metal, edge etching is performed on the wafer edge to remove metal particle defects, followed by polishing.
By removing metal particle defects at the wafer edge, scratch defects during the grinding process are reduced, thereby improving the yield of semiconductor devices.
Smart Images
Figure CN122294558A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor process technology, and in particular to a method for fabricating a semiconductor gate structure and a semiconductor gate structure. Background Technology
[0002] High-k Metal Gate (HKMG) technology is one of the key technologies in modern semiconductor manufacturing and is widely used in logic chips. In the HKMG process, fabricating the gate requires depositing a metal material on the wafer surface as the gate, followed by polishing the wafer surface in subsequent processes.
[0003] However, in existing technologies, scratches often remain on the wafer surface after polishing. These scratches can cause problems such as bent gates and bridging between the gate and other structures, leading to chip failure. These scratches are currently the most significant factor affecting the yield of semiconductor device fabrication. Therefore, how to improve the scratches in the HKMG process is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0004] The purpose of this invention is to provide a method for fabricating a semiconductor gate structure and a semiconductor gate structure that can improve scratch defects.
[0005] To solve the above-mentioned technical problems, the present invention provides a method for fabricating a semiconductor gate structure, comprising:
[0006] Obtain the wafer to be prepared;
[0007] A gate metal is deposited on the surface of the wafer to be prepared; metal particle defects are formed at the edge of the wafer based on the deposited gate metal;
[0008] The wafer is etched at the crystal edge to remove the metal particle defects.
[0009] Grinding is performed on the wafers that have undergone edge etching.
[0010] Optionally, depositing gate metal on the surface of the wafer to be prepared includes:
[0011] Aluminum metal is deposited on the surface of the wafer to be prepared.
[0012] Optionally, edge etching of the wafer includes:
[0013] The wafer is wet-etched using an etching solution.
[0014] Optionally, the etching solution includes a dilute hydrofluoric acid solution.
[0015] Optionally, edge etching of the wafer includes:
[0016] The wafer is etched in a region at a predetermined distance from the edge inwards; the predetermined distance is no greater than 1.8 mm.
[0017] Optionally, the preset distance is not less than 0.6 mm.
[0018] Optionally, edge etching of the wafer includes:
[0019] The wafer is etched at the edge for a preset time; the preset time ranges from 100s to 200s, including the endpoint value.
[0020] Optionally, grinding the wafer after edge etching includes:
[0021] Chemical mechanical polishing is performed on wafers that have undergone edge etching.
[0022] Optionally, the metal particle defects include metal protrusions formed in the stepped structure.
[0023] The present invention also provides a semiconductor gate structure, which is a semiconductor gate structure prepared by any of the above-described semiconductor gate structure preparation methods.
[0024] The present invention provides a method for fabricating a semiconductor gate structure, comprising: obtaining a wafer to be fabricated; depositing gate metal on the surface of the wafer to be fabricated; forming metal particle defects at the edge of the wafer based on the deposited gate metal; performing edge etching on the wafer to remove the metal particle defects; and grinding the wafer after edge etching.
[0025] During the deposition of gate metal, the wafer edges are prone to defects, which can easily lead to the formation of metal particle defects. By etching the wafer edges, these metal particle defects can be removed, thus preventing scratch defects during the grinding and polishing process and improving the yield of semiconductor device fabrication.
[0026] The present invention also provides a semiconductor gate structure, which has the same beneficial effects as described above, and will not be described in detail here. Attached Figure Description
[0027] To more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0028] Figure 1 This is a flowchart of a semiconductor gate structure fabrication method provided in an embodiment of the present invention;
[0029] Figure 2 for Figure 1 Schematic diagram of the structure etched at the mid-grain edge;
[0030] Figure 3 A flowchart illustrating a specific method for fabricating a semiconductor gate structure provided in an embodiment of the present invention;
[0031] Figure 4 and Figure 5 This is a comparison of electron microscopy scans of the wafer edge before and after edge etching. Detailed Implementation
[0032] The core of this invention is to provide a method for fabricating a semiconductor gate structure. In existing technologies, scratches often remain on the wafer surface after polishing. These scratches can cause problems such as gate bending and bridging with other structures, leading to chip failure. While existing technologies typically improve the grinding and polishing process, these improvements have yielded minimal results.
[0033] The present invention provides a method for fabricating a semiconductor gate structure, comprising: obtaining a wafer to be fabricated; depositing gate metal on the surface of the wafer to be fabricated, wherein metal particle defects are formed at the edge of the wafer based on the deposited gate metal; performing edge etching on the wafer to remove the metal particle defects; and grinding the wafer after edge etching.
[0034] During the deposition of gate metal, the wafer edges are prone to defects, which can easily lead to the formation of metal particle defects. By etching the wafer edges, these metal particle defects can be removed, thus preventing scratch defects during the grinding and polishing process and improving the yield of semiconductor device fabrication.
[0035] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0036] Example 1
[0037] Please refer to Figure 1 as well as Figure 2 , Figure 1 This is a flowchart of a semiconductor gate structure fabrication method provided in an embodiment of the present invention; Figure 2 for Figure 1 A schematic diagram of the structure etched at the middle crystal edge.
[0038] See Figure 1In this embodiment of the invention, the method for fabricating a semiconductor gate structure includes:
[0039] S101: Obtain the wafer to be prepared.
[0040] The wafer to be prepared in this step is typically one that has completed part of the gate process, specifically the wafer before the gate metal deposition process in the HKMG process. The remaining steps in the gate process, and the specific structure of the wafer surface, can be set according to the actual situation and are not specifically limited here. Typically, the key processes completed before this step include, but are not limited to, the fabrication of the pseudo-polysilicon gate and the removal of pseudo-polysilicon within the pseudo-polysilicon gate, in order to facilitate subsequent gate metal deposition.
[0041] S102: Deposit gate metal on the surface of the wafer to be prepared.
[0042] This step involves depositing gate metal on the surface of the wafer to be fabricated. Following this step, metal particle defects form at the wafer edges based on the deposited gate metal. The symmetry of the wafer's edges is less than that of the central region; therefore, the edges of the wafer will have more defects compared to the center. This process of depositing gate metal on the wafer surface not only forms the gate metal but also creates metal particle defects based on the defects at the wafer edges. These metal particle defects typically include metal protrusions formed in step structures.
[0043] If metal particle defects are not removed in time, they may detach from the wafer during subsequent polishing and scratch other areas of the wafer, forming scratch defects. These scratch defects typically manifest as problems such as the gate being bent or the gate bridging with other structures.
[0044] S103: Etch the wafer edge to remove metal particle defects.
[0045] See Figure 2 In this step, after depositing the gate metal on the wafer surface and before polishing, the wafer undergoes bevel etch, which involves etching a predetermined area at the wafer edge. This bevel etch can remove at least some of the aforementioned metal particle defects, thereby reducing scratches caused by these defects during subsequent polishing.
[0046] In this embodiment, this step may specifically include: etching a region within a predetermined distance from the edge of the wafer; the predetermined distance is no greater than 1.8 mm. That is, in this embodiment, the width of the edge etching is typically no greater than 1.8 mm. This step of etching the region within 1.8 mm of the wafer edge ensures that, in addition to removing metal particle defects present at the wafer edge, the edge etching process will not affect the various functional structures inside the wafer. Furthermore, in this embodiment, the predetermined distance is no less than 0.6 mm. Since the aforementioned metal particle defects typically exist in the range of 0.3 mm to 0.6 mm from the wafer edge, the width of the edge etching typically needs to be no less than 0.6 mm to ensure the removal of most of the metal particle defects generated by the deposition of gate metal on the wafer surface.
[0047] In this embodiment, this step may further include: performing edge etching on the wafer for a preset time; the preset time ranges from 100s to 200s, including the endpoint value. That is, the duration of the above edge etching is usually between 100s and 200s.
[0048] S104: Grinding the wafer after edge etching.
[0049] This step specifically involves polishing the wafer using the polishing process in the gate fabrication, followed by subsequent processes until the semiconductor gate structure is fabricated. Since edge etching in the preceding steps removes at least some metal particle defects, the polishing process in this step reduces scratch defects and improves the yield of semiconductor device fabrication.
[0050] The semiconductor gate structure fabrication method provided in this invention addresses the issue that, during gate metal deposition, numerous edge defects on the wafer can easily lead to the formation of metal particle defects at these edges. By etching the wafer edges, these metal particle defects can be removed, thereby preventing scratch defects during the polishing process and improving the yield of the semiconductor device.
[0051] The specific details of the semiconductor gate structure fabrication method provided by this invention will be described in detail in the following embodiments.
[0052] Example 2
[0053] Please refer to Figures 3 to 5 , Figure 3 A flowchart illustrating a specific method for fabricating a semiconductor gate structure provided in an embodiment of the present invention; Figure 4 and Figure 5 This is a comparison of electron microscopy scans of the wafer edge before and after edge etching.
[0054] See Figure 3 In this embodiment of the invention, the method for fabricating a semiconductor gate structure includes:
[0055] S201: Obtain the wafer to be prepared.
[0056] This step is basically the same as S101 in the above embodiment. For details, please refer to the above embodiment. It will not be repeated here.
[0057] S202: Deposit aluminum metal on the surface of the wafer to be prepared.
[0058] In this step, aluminum is deposited on the wafer surface as the gate metal. Specifically, the metal particle defects generated at the wafer edge based on this aluminum metal deposition (Al DEP) are aluminum metal particle defects. For example... Figure 4 As shown, the metal particle defect includes metal protrusions formed on the wafer edge step structure.
[0059] S203: Wet edge etching of the wafer is performed using an etching solution.
[0060] This step specifically involves wet edge etching of the wafer edges to remove the aforementioned metal particle defects. The etching solution used in this step typically includes a dilute hydrofluoric acid solution (DHF), which is effective in removing metal particles such as aluminum. The duration of this edge etching step is typically around 150 seconds. Figure 5 As shown, in this embodiment, metal particle defects can be removed by edge etching.
[0061] S204: Chemical mechanical polishing of wafers that have undergone edge etching.
[0062] This step involves chemical mechanical polishing (CMP) of the wafer after edge etching to complete the fabrication of the semiconductor gate structure. Specific details regarding CMP can be found in existing technologies and will not be elaborated upon here.
[0063] In this embodiment, Product 1 and Product 2 were tested respectively. For each product, the same wafer was selected and the corresponding product was prepared by a semiconductor gate structure fabrication process excluding the above-mentioned edge etching, and the corresponding product was prepared by a semiconductor gate structure fabrication process including the above-mentioned edge etching. The results are shown in Table 1 below:
[0064] Table 1. Comparison of Crystal Edge Etching Effects
[0065] Product 1 Product 2 Metal gate scratch count 35→8 22→12.5 Defect improvement level 77% 43%
[0066] As can be seen from Table 1 above, increasing the edge etching process can effectively reduce the generation of scratch defects, increase the yield of semiconductor device production, and thus reduce costs.
[0067] The semiconductor gate structure fabrication method provided in this embodiment of the invention can remove metal particle defects generated by gate metal deposition by etching the wafer edge after depositing gate metal. This can avoid the generation of scratch defects during the grinding and polishing process and improve the yield of semiconductor device fabrication.
[0068] Example 3
[0069] The following describes a semiconductor gate structure provided by an embodiment of the present invention. The semiconductor gate structure described below can be referred to in correspondence with the semiconductor gate structure preparation method described above.
[0070] In this embodiment, the semiconductor gate structure is the semiconductor gate structure fabricated by the semiconductor gate structure fabrication method described in any of the above embodiments. The specific details of the semiconductor gate structure fabrication method have been described in detail in the above embodiments and will not be repeated here. Other aspects of the semiconductor gate structure can be found in the prior art and will not be described further here.
[0071] Since the semiconductor gate structure provided in this embodiment is specifically prepared using the semiconductor gate structure preparation method provided in the above embodiment, it can have a higher yield and correspondingly a lower cost.
[0072] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.
[0073] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.
[0074] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.
[0075] Finally, it should be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0076] The semiconductor gate structure and its fabrication method provided by this invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this invention.
Claims
1. A method for fabricating a semiconductor gate structure, characterized in that, include: Obtain the wafer to be prepared; A gate metal is deposited on the surface of the wafer to be prepared; metal particle defects are formed at the edge of the wafer based on the deposited gate metal; The wafer is etched at the crystal edge to remove the metal particle defects. Grinding is performed on the wafers that have undergone edge etching.
2. The method according to claim 1, characterized in that, Depositing gate metal on the surface of the wafer to be prepared includes: Aluminum metal is deposited on the surface of the wafer to be prepared.
3. The method according to claim 1, characterized in that, Edge etching of the wafer includes: The wafer is wet-etched using an etching solution.
4. The method according to claim 3, characterized in that, The etching solution includes a dilute hydrofluoric acid solution.
5. The method according to claim 1, characterized in that, Edge etching of the wafer includes: The wafer is etched in a region at a predetermined distance from the edge inwards; the predetermined distance is no greater than 1.8 mm.
6. The method according to claim 5, characterized in that, The preset distance is not less than 0.6mm.
7. The method according to claim 1, characterized in that, Edge etching of the wafer includes: The wafer is etched at the edge for a preset time; the preset time ranges from 100s to 200s, including the endpoint value.
8. The method according to claim 1, characterized in that, Grinding of wafers that have undergone edge etching includes: Chemical mechanical polishing is performed on wafers that have undergone edge etching.
9. The method according to claim 1, characterized in that, The metal particle defects include metal protrusions formed in stepped structures.
10. A semiconductor gate structure, characterized in that, The semiconductor gate structure is prepared by the semiconductor gate structure preparation method according to any one of claims 1 to 9.