Semiconductor device, method of manufacturing the same, and electronic apparatus including the same

Abstract

This invention provides a semiconductor device, a method of manufacturing the semiconductor device, and an electronic device including the semiconductor device. The semiconductor device may include an active semiconductor layer, a gate insulating film surrounding at least three surfaces of the active semiconductor layer, and a gate electrode extending in a first direction and surrounding at least three surfaces of the gate insulating film. The gate electrode may be separated from another gate electrode or another electronic device by a gate notch having a trench shape to electrically isolate the gate electrode from the other gate electrode or another electronic device. The gate notch may face the gate electrode in a second direction. The second direction may be perpendicular to the first direction. The gate insulating film may extend along the lower surface of the gate electrode to the sidewall of the gate notch.

Description

Technical Field

[0001] This invention relates to semiconductor devices, methods for manufacturing semiconductor devices, and / or electronic devices including semiconductor devices. Background Technology

[0002] Field-effect transistors (FETs) are semiconductor devices that perform electrical switching functions and can be used in various integrated circuit devices, including memory, driver integrated circuits (ICs), and logic devices. As the integration density of integrated circuit devices increases, the size of FETs within these devices is rapidly shrinking. With the reduction in FET size, technologies such as FinFETs and Gate-All-Around FETs (GAAFETs) have been developed to address the issue of reduced channel area. These FinFETs and GAAFETs can each include gate structures with relatively high aspect ratios, thus their manufacturing processes can be quite complex. Summary of the Invention

[0003] Semiconductor devices, methods for manufacturing semiconductor devices, and / or electronic devices including semiconductor devices are provided.

[0004] Other aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practicing the embodiments presented in this disclosure.

[0005] According to embodiments of this disclosure, a semiconductor device may include: an active semiconductor layer; a gate insulating film surrounding at least three surfaces of the active semiconductor layer; and a gate electrode extending in a first direction and surrounding at least three surfaces of the gate insulating film. The gate electrode may be separated from another gate electrode or another electronic device by a gate notch having a trench shape, thereby electrically isolating the gate electrode from the other gate electrode or another electronic device. The gate notch may face the gate electrode in a second direction. The second direction may be perpendicular to the first direction. The gate insulating film may extend along the lower surface of the gate electrode to the sidewall of the gate notch.

[0006] In some embodiments, the semiconductor device may further include an isolation film comprising an insulating dielectric material. An active semiconductor layer may extend in a first direction to protrude over the isolation film in that direction.

[0007] In some embodiments, a first portion of the gate electrode may extend from the upper surface of the isolation film along the surface of the active semiconductor layer to surround the active semiconductor layer, a second portion of the gate electrode may extend on the upper surface of the isolation film in a second direction, a first portion of the gate insulating film may be between the active semiconductor layer and the first portion of the gate electrode, and a second portion of the gate insulating film may be between the upper surface of the isolation film and the second portion of the gate electrode.

[0008] In some embodiments, a third portion of the gate insulating film may extend through the sidewalls of the gate notch to the outer surface of the gate electrode opposite to the active semiconductor layer. The first, second, and third portions of the gate insulating film may extend continuously.

[0009] In some implementations, the end portion of the second part of the gate electrode may be matched with the position of the gate cutout.

[0010] In some embodiments, the gate cutout may have the shape of a groove provided in the upper surface of the isolation membrane, and the bottom surface of the gate cutout may protrude further in a first direction from the upper surface of the isolation membrane adjacent to the gate cutout in a third direction, the third direction being perpendicular to the first and second directions.

[0011] In some embodiments, the semiconductor device may further include a gate connection portion. The active semiconductor layers may include a first active semiconductor layer and a second active semiconductor layer adjacent to each other in a second direction. The gate electrodes may include a first gate electrode surrounding at least three surfaces of the first active semiconductor layer and a second gate electrode surrounding at least three surfaces of the second active semiconductor layer. The gate connection portion may be located between the first gate electrode and the second gate electrode.

[0012] In some embodiments, the first gate electrode, the second gate electrode, and the gate connection portion may be integrally formed from a single conductive material.

[0013] In some embodiments, the gate connection portion may include a conductive material having a higher conductivity than the materials of the first gate electrode and the second gate electrode.

[0014] In some embodiments, a gate insulating film may surround at least three surfaces of the first active semiconductor layer between the first active semiconductor layer and the first gate electrode, and a gate insulating film may surround at least three surfaces of the second active semiconductor layer between the second active semiconductor layer and the second gate electrode.

[0015] In some embodiments, the gate insulating film may extend along the first gate electrode, the gate connection portion, and the second gate electrode.

[0016] In some embodiments, the gate insulating film may surround the lower surface of the gate connection portion, the upper surface of the gate connection portion, and the two side surfaces of the gate connection portion in a third direction, which may be perpendicular to the first direction and the second direction.

[0017] In some embodiments, the gate connection portion may include a first gate connection portion adjacent to the first gate electrode and a second gate connection portion adjacent to the second gate electrode. The thickness of the first gate connection portion in the first direction may be different from the thickness of the second gate connection portion in the first direction.

[0018] In some embodiments, each of the first gate electrode and the second gate electrode may include a first gate layer and a second gate layer surrounded by the first gate layer. The first gate connection portion and the second gate connection portion may each include a first connection layer and a second connection layer surrounded by the first connection layer. The first gate layer of the first gate electrode, the first gate layer of the second gate electrode, the first connection layer of the first gate connection portion, and the first connection layer of the second gate connection portion may each include a first conductive material. The second gate layer of the first gate electrode, the second gate layer of the second gate electrode, the second connection layer of the first gate connection portion, and the second connection layer of the second gate connection portion may each include a second conductive material. The second conductive material may be different from the first conductive material. The thickness of the first connection layer of the first gate connection portion may be equal to the thickness of the first connection layer of the second gate connection portion. The thickness of the second connection layer of the first gate connection portion in a first direction may be different from the thickness of the second connection layer of the second gate connection portion in the first direction.

[0019] In some embodiments, the semiconductor device may further include: an insulating filler covering the gate connection portion between the first gate electrode and the second gate electrode; a conductive filler on the insulating filler between the first gate electrode and the second gate electrode; and a gate contact contacting the upper surface of the conductive filler.

[0020] In some embodiments, the semiconductor device may further include: a conductive filler covering the gate connection portion between the first gate electrode and the second gate electrode; and a gate contact contacting the upper surface of the conductive filler.

[0021] In some embodiments, a first portion of the gate insulating film may surround the four surfaces of the active semiconductor layer, and a second portion of the gate insulating film may extend along the lower surface of the gate electrode to the sidewall of the gate notch in a second direction. The first portion of the gate insulating film may be separable from the second portion of the gate insulating film, and the gate electrode may surround the four surfaces of the first portion of the gate insulating film.

[0022] In some implementations, the active semiconductor layer may include a plurality of channel elements spaced apart from each other in a first direction. A first portion of the gate insulating film may surround the surface of each of the plurality of channel elements.

[0023] According to an exemplary embodiment of this disclosure, a method of manufacturing a semiconductor device may include: forming an active semiconductor layer that protrudes from and extends from a substrate in a first direction; forming an isolation film covering an upper surface of the substrate and a side surface of the active semiconductor layer; conformally forming a dummy gate along the surface of the isolation film; forming a trench adjacent to the active semiconductor layer in a second direction, perpendicular to the first direction, by partially etching the isolation film; forming a dummy block that covers the trench and the active semiconductor layer; removing the isolation film from the side surface of the dummy gate and the side surface of the active semiconductor layer to expose the active semiconductor layer and form empty spaces in the dummy block; conformally forming a gate insulating film along the inner surface of the dummy block and the side surface of the active semiconductor layer; forming a gate electrode by filling the remaining portion of the empty spaces in the dummy block after forming the gate insulating film with a conductive material; and removing the dummy block.

[0024] According to an exemplary embodiment of this disclosure, an electronic device may include a memory and a memory controller configured to control the memory to read data from the memory and / or write data to the memory. At least one of the memory and the memory controller may include the aforementioned semiconductor device. Attached Figure Description

[0025] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, wherein:

[0026] Figure 1 The structure of a semiconductor device according to an embodiment is schematically shown;

[0027] Figure 2 Show along Figure 1 The vertical cross-sectional structure of the semiconductor device intercepted by line A1-A1';

[0028] Figure 3 Show along Figure 1 The vertical cross-sectional structure of the semiconductor device intercepted by line A2-A2';

[0029] Figure 4 Show along Figure 1 The horizontal cross-sectional structure of the semiconductor device intercepted by line A3-A3';

[0030] Figure 5 The structure of a semiconductor device according to another embodiment is schematically shown;

[0031] Figure 6 The structure of a semiconductor device according to another embodiment is schematically shown;

[0032] Figure 7 Show along Figure 6 The vertical cross-sectional structure of the semiconductor device intercepted by line B1-B1';

[0033] Figure 8 The structure of a semiconductor device according to another embodiment is schematically shown;

[0034] Figure 9 The structure of a semiconductor device according to another embodiment is schematically shown;

[0035] Figures 10A to 10S A method for manufacturing a semiconductor device according to an embodiment is illustrated schematically;

[0036] Figure 11 The structure of a semiconductor device according to another embodiment is schematically shown;

[0037] Figure 12 The structure of a semiconductor device according to another embodiment is schematically shown;

[0038] Figure 13 The structure of a semiconductor device according to another embodiment is schematically shown;

[0039] Figure 14 The structure of a semiconductor device according to another embodiment is schematically shown;

[0040] Figure 15 The structure of a semiconductor device according to another embodiment is schematically shown;

[0041] Figures 16A to 16C A method for forming a gate connection portion comprising a conductive material different from that of the first gate electrode and the second gate electrode is schematically illustrated;

[0042] Figure 17 A circuit diagram of a complementary metal-oxide-semiconductor (CMOS) inverter according to an embodiment is shown;

[0043] Figure 18 A circuit diagram of a CMOS static random access memory (SRAM) device according to an embodiment is shown;

[0044] Figure 19 A block diagram showing an electronic device according to an embodiment is shown; and

[0045] Figure 20 This is a block diagram of an electronic device according to an embodiment. Detailed Implementation

[0046] Reference will now be made in detail to embodiments, examples of which are shown in the accompanying drawings, wherein the same reference numerals always denote the same elements. In this respect, the presented embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, embodiments are described below only by reference to the accompanying drawings to illustrate various aspects. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of…” modify the entire column of elements when following a column of elements, but not individual elements within that column.

[0047] In the following description, with reference to the accompanying drawings, a semiconductor device, a method of manufacturing a semiconductor device, and an electronic device including a semiconductor device are described in detail. In the drawings, the same reference numerals indicate the same parts, and the dimensions of each part in the drawings may be exaggerated for clarity and convenience. Furthermore, the various embodiments described below are merely examples, and various modifications can be made to the embodiments.

[0048] In the following text, the terms “above,” “below,” “left,” or “right” can include not only being above / below / left / right while in direct contact, but also being above / below / left / right without contact. Unless the context clearly indicates otherwise, the singular expression includes the plural expression. Furthermore, when a part is described as “including” a component, this does not mean that the part excludes other components, but rather that the part may further include other components, unless otherwise specifically described.

[0049] The article "the" and similar referential terms are used to indicate that the referent can refer to both singular and plural referents. Unless the operations of a method are explicitly described in a particular order or vice versa, these operations can be performed in any suitable order, and are not necessarily limited to the order described.

[0050] In addition, terms such as “unit” and “module” described in the specification refer to a unit that performs at least one function or operation, which can be implemented by hardware or software, or a combination of hardware and software.

[0051] The lines connecting the components or connecting elements depicted in the accompanying drawings are merely illustrations of functional and / or physical or electrical connections. In actual installations, they may be represented as various alternative or additional functional, physical, or electrical connections.

[0052] Any example or use of its terminology is intended to illustrate technical ideas only and is not intended to limit the scope of the invention, unless otherwise defined by the claims.

[0053] Figure 1 The structure of a semiconductor device according to an embodiment is schematically shown. (Refer to...) Figure 1The semiconductor device 100 may include a substrate 101, an active semiconductor layer 103 projecting from the upper surface of the substrate 101 in a vertical direction (e.g., in a first direction or in the Z-axis direction), a gate insulating film 104 surrounding the surface of the active semiconductor layer 103, and a gate electrode 105 surrounding the surface of the gate insulating film 104. The gate insulating film 104 and the gate electrode 105 may be provided to extend along the surface of the active semiconductor layer 103 to surround the first and second surfaces of the active semiconductor layer 103 and the upper surface of the active semiconductor layer 103, wherein the first and second surfaces of the active semiconductor layer 103 face each other in a horizontal direction (i.e., in a second direction or in the X-axis direction). The gate insulating film 104 may be provided between the active semiconductor layer 103 and the gate electrode 105 such that the active semiconductor layer 103 does not directly contact the gate electrode 105. Therefore, the gate insulating film 104 may surround the three surfaces of the active semiconductor layer 103, and the gate electrode 105 may surround the three surfaces of the gate insulating film 104.

[0054] Substrate 101 may include a semiconductor substrate. For example, substrate 101 may include at least one semiconductor material selected from group IV semiconductors (such as silicon (Si) or germanium (Ge)), group III-V compound semiconductors (such as GaAs or GaP), and oxide semiconductors. Substrate 101 may include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.

[0055] Additionally, the semiconductor device 100 may further include a first passivation layer 106 provided to cover the gate insulating film 104 and the gate electrode 105. The first passivation layer 106 may be provided to fill the space surrounding the gate insulating film 104 and the gate electrode 105 in a second direction. The first passivation layer 106 may include an insulating dielectric material.

[0056] Figure 2 Show along Figure 1 The vertical cross-sectional structure of semiconductor device 100 is shown by line A1-A1'. In other words, Figure 2 The diagram shows a cross-section taken by cutting a portion of the active semiconductor layer 103 of the semiconductor device 100. (Refer to...) Figure 2 The semiconductor device 100 may further include a source region 107 and a drain region 108 respectively provided on a first side and a second side of the active semiconductor layer 103, wherein the first side and the second side face each other in a third direction perpendicular to the first and second directions (e.g., in the Y-axis direction). Additionally, the semiconductor device 100 may further include a second passivation layer 109 provided to cover the source region 107 and the drain region 108. The second passivation layer 109 may be provided to fill the space above the source region 107 and the drain region 108 in a second direction. The second passivation layer 109 may include an insulating dielectric material.

[0057] The active semiconductor layer 103 may be located between the source region 107 and the drain region 108 in a third-direction orientation. The active semiconductor layer 103, source region 107, and drain region 108 may have a rod shape protruding from the substrate 101 in a first direction and extending in a third-direction orientation. The active semiconductor layer 103, source region 107, and drain region 108 may comprise at least one semiconductor material selected from, for example, group IV semiconductors (such as Si or Ge), group III-V compound semiconductors (such as GaAs or GaP), oxide semiconductors, and two-dimensional material semiconductors. The active semiconductor layer 103 may be doped with a first conductivity type impurity, and the source region 107 and drain region 108 may be doped with a second conductivity type impurity electrically opposite to the first conductivity type impurity. For example, the active semiconductor layer 103 may comprise a p-type semiconductor, and the source region 107 and drain region 108 may comprise an n-type semiconductor. As another example, the active semiconductor layer 103 may comprise an n-type semiconductor, and the source region 107 and drain region 108 may comprise a p-type semiconductor. The active semiconductor layer 103 can be approximately 10 16 / cm 3 To about 10 17 / cm 3 With relatively low doping concentrations, source region 107 and drain region 108 can be doped at approximately 10⁻⁶. 19 / cm 3 To about 10 21 / cm 3 The relatively high concentration of doping.

[0058] The active semiconductor layer 103, source region 107, drain region 108, gate insulating film 104, and gate electrode 105 can form a field-effect transistor TR. Specifically, Figure 1 and Figure 2 The field-effect transistor TR shown can be a FinFET. Therefore, semiconductor device 100 may include a field-effect transistor TR. Figure 1 and Figure 2 In the diagram, semiconductor device 100 is shown to include one field-effect transistor TR, but semiconductor device 100 may include two or more field-effect transistors TR.

[0059] Refer again Figure 1 The semiconductor device 100 may further include an isolation film 102 that electrically isolates adjacent field-effect transistors TR from each other. The isolation film 102 may include an insulating dielectric material and may be provided on the upper surface of the substrate 101. An active semiconductor layer 103 may extend from the substrate 101 in a first direction to penetrate the isolation film 102 and protrude above the isolation film 102. Figure 2The source region 107 and drain region 108 shown may also extend from the substrate 101 in the first direction to penetrate the isolation film 102 and protrude above the isolation film 102.

[0060] A gate insulating film 104 and a gate electrode 105 may be provided on the upper surface of the isolation film 102. The gate insulating film 104 may include a first portion protruding from the upper surface of the isolation film 102 in a first direction and a second portion extending on the upper surface of the isolation film 102 in a second direction. The gate electrode 105 may also include a first portion protruding from the upper surface of the isolation film 102 in a first direction and a second portion extending on the upper surface of the isolation film 102 in a second direction. The first portion of the gate insulating film 104 and the first portion of the gate electrode 105 may extend from the upper surface of the isolation film 102 along the surface of the active semiconductor layer 103 in the first direction to surround the active semiconductor layer 103 protruding from the isolation film 102 in the first direction. The first portion of the gate insulating film 104 may be provided between the active semiconductor layer 103 and the first portion of the gate electrode 105, and the second portion of the gate insulating film 104 may be provided between the upper surface of the isolation film 102 and the second portion of the gate electrode 105.

[0061] The semiconductor device 100 may further include a gate notch GC to electrically or signal-isolate the gate electrode 105 of the field-effect transistor TR from the gate electrodes of other adjacent field-effect transistors or from other adjacent electronic devices. The gate notch GC may have a shape, for example, a recessed groove or trench formed by partially etching the upper surface of the isolation film 102. The gate notch GC may be provided to face and be adjacent to the gate electrode 105 in a second direction. Figure 1 In the diagram, the gate cutout GC is shown having inclined sidewalls provided within the isolation membrane 102, but is not limited thereto; the gate cutout GC may also have vertical sidewalls. Furthermore, Figure 1 The diagram shows a gate cutout GC provided on both sides of the field-effect transistor TR in a second direction, but is not limited thereto. Depending on electrical or signal requirements, the gate cutout GC may be provided only on one side of the field-effect transistor TR in the second direction, or the gate cutout GC may not be present on both sides of the field-effect transistor TR.

[0062] Figure 3 Show along Figure 1 The vertical cross-sectional structure of semiconductor device 100 is shown by line A2-A2'. In other words, Figure 3 A cross-section of a portion of the gate cutout GC of the semiconductor device 100 is shown by cutting the gate cutout GC into planes parallel to the first and third directions. (Refer to...) Figure 3The gate notch GC can be filled with a first passivation layer 106 provided to cover the gate insulating film 104 and the gate electrode 105. A second passivation layer 109 covering the source region 107 and the drain region 108 can be provided on both sides of the first passivation layer 106 in the third direction. A portion of the first passivation layer 106 can extend in the third direction to the periphery of the gate notch GC. Therefore, the second passivation layer 109 can not directly contact the isolation film 102, and the first passivation layer 106 can be disposed between the isolation film 102 and the second passivation layer 109. On the other hand, in Figure 3 In this diagram, for convenience, the first passivation layer 106 and the second passivation layer 109 are shown as being distinguishable from each other, but when the first passivation layer 106 and the second passivation layer 109 comprise the same material, the first passivation layer 106 and the second passivation layer 109 may not be distinguishable.

[0063] As described in more detail with respect to the method of manufacturing a semiconductor device described below, a gate notch GC can be formed before forming the gate insulating film 104 and the gate electrode 105. During the formation of the gate notch GC, since a trench extending in the third-party direction can be formed by etching the isolation film 102 to a uniform depth in the third-party direction, the isolation film 102 can have a flat surface with almost no curvature around the gate notch GC in the third-party direction. In other words, the bottom surface of the gate notch GC can be no lower than the surface of the isolation film 102 around the gate notch GC in the third-party direction, and the bottom surface of the gate notch GC and the surface of the isolation film 102 around the gate notch GC can be formed into a plane with almost the same height in the third-party direction. Optionally, in the method of manufacturing a semiconductor device described below, the source region 107 and the drain region 108 are formed... Figure 10I and Figure 10J In the process shown, the area around the gate notch (GC) can be further etched along the first direction in a third-direction upward direction. Thus, as... Figure 3 As shown, the gate cutout GC can protrude further in the first direction than in the third direction on the surface of the isolation membrane 102 surrounding the gate cutout GC.

[0064] Refer again Figure 1 The second portion of the gate electrode 105 can extend along the upper surface of the isolation film 102 in the second direction to the location of the gate cutout GC. In other words, the end portion of the second portion of the gate electrode 105 can be matched with the location of the gate cutout GC. Therefore, the gate electrode 105 of the field-effect transistor TR can be separated from the gate electrode 105 of another field-effect transistor TR or the electrical ground or signal ground of another electronic device through the gate cutout GC.

[0065] On the other hand, the gate insulating film 104 (e.g., the second portion of the gate insulating film 104) may extend along the lower surface of the second portion of the gate electrode 105 and the upper surface of the isolation film 102 toward the gate notch GC. The gate insulating film 104 may extend continuously along the sidewall of the gate notch GC and the outer surface of the gate electrode 105 without being interrupted by the gate notch GC. Therefore, the gate insulating film 104 may further include a third portion extending along the side surface of the second portion of the gate electrode 105 adjacent to the gate notch GC, the upper surface of the second portion of the gate electrode 105, and the outer sidewall surface of the first portion of the gate electrode 105 opposite to the active semiconductor layer 103. In other words, the gate insulating film 104 may include a first portion between the active semiconductor layer 103 and the first portion of the gate electrode 105, a second portion between the isolation film 102 and the second portion of the gate electrode 105, and a third portion extending along the outer surface of the gate electrode 105 through the sidewall of the gate notch GC. The first, second, and third portions of the gate insulating film 104 may extend continuously without being interrupted.

[0066] exist Figure 1 In the cross-section shown, a third portion of the gate insulating film 104 can be provided between the gate electrode 105 and the first passivation layer 106. For example, the third portion of the gate insulating film 104 can extend continuously between the side surface of the end portion of the second portion of the gate electrode 105 and the first passivation layer 106, between the upper surface of the second portion of the gate electrode 105 and the first passivation layer 106, and between the first portion of the gate electrode 105 and the first passivation layer 106. The portion of the third portion of the gate insulating film 104 provided on the side surface of the end portion of the second portion of the gate electrode 105 can extend continuously from the gate cutout GC without any step difference. Therefore, the portion of the third portion of the gate insulating film 104 provided on the side surface of the end portion of the second portion of the gate electrode 105 can form the same plane as the gate cutout GC.

[0067] Therefore, the remaining surface of the gate electrode 105, except for the upper surface, can be completely surrounded by the gate insulating film 104. Although in Figure 1 Not shown, but the gate insulating film 104 may also be provided on the surface of the gate electrode 105 as viewed from a third party. For example, see reference... Figure 2 The gate insulating film 104 may extend in a third-party direction from between the active semiconductor layer 103 and the gate electrode 105 to the side surface of the gate electrode 105. In other words, the gate insulating film 104 may also be provided in a third-party direction between the side surface of the gate electrode 105 and the first passivation layer 106 or in a third-party direction between the side surface of the gate electrode 105 and the second passivation layer 109.

[0068] Figure 4 It shows along Figure 1The horizontal cross-sectional structure of semiconductor device 100 is shown by line A3-A3'. In other words, Figure 4 A cross-section of a portion of the active semiconductor layer 103 of the semiconductor device 100 is shown, obtained by cutting the active semiconductor layer 103 into planes parallel to the second and third directions. (Refer to...) Figure 4 The active semiconductor layer 103 may be provided in a third-direction orientation between the source region 107 and the drain region 108. A gate electrode 105 may be provided on both sides of the active semiconductor layer 103 in a second direction. The surface of the gate electrode 105 may be surrounded by a gate insulating film 104. For example, the gate insulating film 104 may be provided between the gate electrode 105 and the active semiconductor layer 103, between the gate electrode 105 and the source region 107, between the gate electrode 105 and the drain region 108, and between the gate electrode 105 and the first passivation layer 106. Figure 4 It is shown that the widths of the source region 107 and drain region 108 in the second direction are greater than the width of the active semiconductor layer 103 in the second direction, and the source region 107 and drain region 108 extend to the outer wall surface of the gate electrode 105 in the second direction, but this is not a limitation. The widths of the source region 107 and drain region 108 in the second direction may be greater than or less than [the width of the gate electrode 105]. Figure 4 The width shown.

[0069] The first passivation layer 106 may be provided in the third-party upward region in the same region as the active semiconductor layer 103 and the gate electrode 105, and may extend in the second direction. The second passivation layer 109 may be provided in the third-party upward region in the same region as the source region 107 and the drain region 108, and may extend in the second direction. The gate notch GC may be located below the first passivation layer 106, as indicated by the dashed line.

[0070] Figure 5 The structure of a semiconductor device according to another embodiment is schematically shown. Specifically, Figure 5 It shows that in relation to Figure 4 The structure of a semiconductor device according to another embodiment in the same cross-section. (Refer to...) Figure 5The semiconductor device 100 may further include spacers 110 provided on both sides of the gate electrode 105 in a third-direction orientation. The spacers 110 may extend in a second direction. Therefore, the spacers 110 may be provided in the third-direction orientation between the gate electrode 105 and the source region 107, between the gate electrode 105 and the drain region 108, and between the first passivation layer 106 and the second passivation layer 109. The spacers 110 may serve to limit the position of the active semiconductor layer 103, the gate insulating film 104, and the gate electrode 105 in the method of manufacturing the semiconductor device described below. The source region 107 and the drain region 108 may be separated from the gate insulating film 104 and the gate electrode 105 by the spacers 110. The active semiconductor layer 103 may penetrate the spacers 110 in the third-direction orientation and be electrically connected to the source region 107 and the drain region 108. The spacers 110 may include, for example, silicon nitride (SiN), but are not limited thereto.

[0071] Figure 6 The structure of a semiconductor device according to another embodiment is schematically illustrated. The semiconductor device 100 described so far includes a field-effect transistor TR between two adjacent gate cutouts GC, but is not limited thereto. For example, two or more field-effect transistors sharing a gate signal may be provided between two adjacent gate cutouts GC. (Refer to...) Figure 6 The semiconductor device 100a may include a first field-effect transistor TR1 and a second field-effect transistor TR2 provided between two adjacent gate cutouts GC. Figure 6 This is just one example; in other embodiments, three or more field-effect transistors may be provided between two adjacent gate cutouts GC. The first field-effect transistor TR1 and the second field-effect transistor TR2 may be arranged adjacent to each other in a second direction. Depending on the application of the semiconductor device 100a, the first field-effect transistor TR1 and the second field-effect transistor TR2 may comprise different types of field-effect transistors. For example, the first field-effect transistor TR1 may comprise an n-channel metal-oxide-semiconductor (NMOS) transistor, and the second field-effect transistor TR2 may comprise a p-channel metal-oxide-semiconductor (PMOS) transistor.

[0072] The structure of each of the first field-effect transistor TR1 and the second field-effect transistor TR2 can be compared with... Figure 1 The field-effect transistors TR shown have the same structure. For example, the first field-effect transistor TR1 may include a first active semiconductor layer 103a, a gate insulating film 104, and a first gate electrode 105a. Although Figure 6 Not shown in the image, but in relation to Figure 2In the same cross-section, the first field-effect transistor TR1 may further include a first source region and a first drain region. The second field-effect transistor TR2 may include a second active semiconductor layer 103b, a gate insulating film 104, and a second gate electrode 105b. Although Figure 6 Not shown in the image, but in relation to Figure 2 The second field-effect transistor TR2 in the same cross section may further include a second source region and a second drain region.

[0073] The first gate electrode 105a may be provided as three surfaces surrounding the first active semiconductor layer 103a. The second gate electrode 105b may be provided as three surfaces surrounding the second active semiconductor layer 103b. The gate insulating film 104 may be provided as three surfaces surrounding the first active semiconductor layer 103a between the first active semiconductor layer 103a and the first gate electrode 105a, and as three surfaces surrounding the second active semiconductor layer 103b between the second active semiconductor layer 103b and the second gate electrode 105b.

[0074] The first gate electrode 105a of the first field-effect transistor TR1 and the second gate electrode 105b of the second field-effect transistor TR2 can be integrally formed, such that the first field-effect transistor TR1 and the second field-effect transistor TR2 can share the same gate signal. In other words, the first gate electrode 105a and the second gate electrode 105b can be considered as a single gate electrode, and this single gate electrode can be considered as extending between the first active semiconductor layer 103a of the first field-effect transistor TR1 and the second active semiconductor layer 103b of the second field-effect transistor TR2. Similarly, gate insulating films 104 can be integrally formed around the surfaces of the first gate electrode 105a and the second gate electrode 105b, respectively. In other words, it can be seen that a gate insulating film 104 extends from the first field-effect transistor TR1 to the second field-effect transistor TR2.

[0075] In other words, the semiconductor device 100a may further include a gate connection portion 111 provided between the first gate electrode 105a of the first field-effect transistor TR1 and the second gate electrode 105b of the second field-effect transistor TR2. The first gate electrode 105a of the first field-effect transistor TR1 and the second gate electrode 105b of the second field-effect transistor TR2 may be electrically connected to each other via the gate connection portion 111. The first gate electrode 105a of the first field-effect transistor TR1, the second gate electrode 105b of the second field-effect transistor TR2, and the gate connection portion 111 may be integrally formed from a single conductive material. The gate connection portion 111 may be provided on the upper surface of the isolation film 102 between the first field-effect transistor TR1 and the second field-effect transistor TR2, and may extend in a second direction.

[0076] The gate insulating film 104 can be provided as a surface surrounding the gate connection portion 111. The gate insulating film 104 can extend along the surface of the first gate electrode 105a of the first field-effect transistor TR1, the surface of the second gate electrode 105b of the second field-effect transistor TR2, and the surface of the gate connection portion 111. For example, the gate insulating film 104 can be provided as a surface surrounding the first gate electrode 105a of the first field-effect transistor TR1, the second gate electrode 105b of the second field-effect transistor TR2, and all surfaces of the gate connection portion 111 except for the upper surface of the first gate electrode 105a of the first field-effect transistor TR1 and the upper surface of the second gate electrode 105b of the second field-effect transistor TR2.

[0077] Figure 7 Show along Figure 6 The vertical cross-sectional structure of semiconductor device 100a is taken by line B-B'. In other words, Figure 7 The cross-section of the gate connection portion 111 of the semiconductor device 100a is shown by cutting the gate connection portion 111 into planes parallel to the first and third directions. (Refer to...) Figure 7 The two side surfaces of the gate connection portion 111 in the third direction, the lower surface of the gate connection portion 111, and the upper surface of the gate connection portion 111 may be surrounded by the gate insulating film 104. The gate connection portion 111 and the gate insulating film 104 may be covered by the first passivation layer 106.

[0078] Figure 8 The structure of a semiconductor device according to another embodiment is schematically shown. The semiconductor device 100b may include a first field-effect transistor TR1 and a second field-effect transistor TR2 having different threshold voltages. (Refer to...) Figure 8 In order to adjust the threshold voltage of the first field-effect transistor TR1 and the threshold voltage of the second field-effect transistor TR2 independently and differently, the thickness of the first gate electrode 105a of the first field-effect transistor TR1 may be different from the thickness of the second gate electrode 105b of the second field-effect transistor TR2. As described in more detail with respect to the method of manufacturing the semiconductor device described below, the first gate electrode 105a of the first field-effect transistor TR1, the second gate electrode 105b of the second field-effect transistor TR2, and the gate connection portion 111 may be conformally integrally formed. Therefore, a step difference may exist between the first gate electrode 105a of the first field-effect transistor TR1 and the second gate electrode 105b of the second field-effect transistor TR2.

[0079] The gate connection portion 111 may include a first gate connection portion 111a closer to the first gate electrode 105a of the first field-effect transistor TR1 and a second gate connection portion 111b closer to the second gate electrode 105b of the second field-effect transistor TR2. The first-direction thickness t1 of the first gate connection portion 111a may be equal to the second-direction thickness of the first gate electrode 105a of the first field-effect transistor TR1. The first-direction thickness t2 of the second gate connection portion 111b may be equal to the second-direction thickness of the second gate electrode 105b of the second field-effect transistor TR2. When the second-direction thickness of the first gate electrode 105a of the first field-effect transistor TR1 differs from the second-direction thickness of the second gate electrode 105b of the second field-effect transistor TR2, the first-direction thickness t1 of the first gate connection portion 111a may differ from the first-direction thickness t2 of the second gate connection portion 111b. Therefore, a step difference may be formed at the boundary where the first gate connection portion 111a and the second gate connection portion 111b contact. In this specification, the first-direction thickness refers to the thickness measured in a first direction, and the second-direction thickness refers to the thickness measured in a second direction.

[0080] On the other hand, the gate insulating film 104 can have a uniform thickness that is independent of the thickness of the first gate electrode 105a and the thickness of the second gate electrode 105b. In other words, the thickness of the gate insulating film 104 in the first field-effect transistor TR1, the thickness of the gate insulating film 104 in the second field-effect transistor TR2, and the thickness of the gate insulating film 104 surrounding the gate connection portion 111 can be substantially the same.

[0081] Figure 9 The structure of a semiconductor device according to another embodiment is schematically shown. (Refer to...) Figure 9The semiconductor device 100c may further include a gate contact 114. The first field-effect transistor TR1 and the second field-effect transistor TR2 can receive gate signals through the gate contact 114. For this purpose, the gate contact 114 may be provided as electrically connected to a first gate electrode 105a of the first field-effect transistor TR1 and / or a second gate electrode 105b of the second field-effect transistor TR2. For example, the gate contact 114 may be electrically connected between the first gate electrode 105a of the first field-effect transistor TR1 and the second gate electrode 105b of the second field-effect transistor TR2. The gate insulating film 104 provided on the surface of the first gate electrode 105a of the first field-effect transistor TR1 facing the second field-effect transistor TR2, the surface of the second gate electrode 105b of the second field-effect transistor TR2 facing the first field-effect transistor TR1, and the upper surface of the gate connection portion 111 can be removed, so that the first gate electrode 105a of the first field-effect transistor TR1 and / or the second gate electrode 105b of the second field-effect transistor TR2 can be electrically connected to the gate contact 114.

[0082] Semiconductor device 100c may further include an insulating filler 112 to reduce parasitic capacitance. The insulating filler 112 may include an insulating dielectric material. For example, the insulating filler 112 may include, but is not limited to, silicon oxide (SiO2) having a relatively low dielectric constant. The insulating filler 112 may fill the upper surface of the gate connection portion 111 between the first gate electrode 105a of the first field-effect transistor TR1 and the second gate electrode 105b of the second field-effect transistor TR2. Semiconductor device 100c may further include a conductive filler 113 filled on the insulating filler 112 between the first gate electrode 105a of the first field-effect transistor TR1 and the second gate electrode 105b of the second field-effect transistor TR2. The conductive filler 113 may include a conductive metallic material. The gate contact 114 may be provided to penetrate the first passivation layer 106 and contact the upper surface of the conductive filler 113. According to an embodiment, the parasitic capacitance caused by the conductive filler 113 and the gate contact 114 can be reduced by using the insulating filler 112 to reduce the area occupied by the conductive filler 113 and the gate contact 114.

[0083] Figures 10A to 10S A method for manufacturing a semiconductor device according to an embodiment is illustrated schematically. For example, Figures 10A to 10S The manufacturing process was shown in [the diagram]. Figure 8 and Figure 9 The methods for semiconductor devices 100b and 100c shown in the figure, but with Figures 10A to 10SThe same principle as the method shown can also be applied to the manufacturing of other semiconductor devices 100 and 100a.

[0084] First, refer to Figure 10A A first active semiconductor layer 103a and a second active semiconductor layer 103b can be formed protruding and extending from the substrate 101 in a first direction. The first active semiconductor layer 103a and the second active semiconductor layer 103b can be provided adjacent to each other in a second direction. The substrate 101 can include, for example, a silicon bulk substrate, and the first active semiconductor layer 103a and the second active semiconductor layer 103b can be formed by partially etching the silicon bulk substrate. In another example, the substrate 101 can include an SOI substrate, on which the first active semiconductor layer 103a and the second active semiconductor layer 103b can be grown. In addition to silicon, the substrate 101 can also include other types of semiconductor substrates, such as III-V compound semiconductor substrates, such as GaAs and GaP.

[0085] The first active semiconductor layer 103a and the second active semiconductor layer 103b may comprise a semiconductor material, for example, Si, Ge, and compound semiconductors. The first active semiconductor layer 103a and the second active semiconductor layer 103b may be doped with impurities of a first conductivity type. Although Figure 10A The diagram shows only two active semiconductor layers formed on a substrate 101, but the number of active semiconductor layers is not limited to this, and a much larger number of active semiconductor layers can be formed on the substrate 101 at once. In the following, for convenience, only the process of forming a field-effect transistor sharing a single gate signal will be shown as an example.

[0086] Next, an insulating dielectric material can be deposited on the upper surface of the substrate 101 to form an isolation film 102. The material of the isolation film 102 can also be deposited on the surfaces of the first active semiconductor layer 103a and the second active semiconductor layer 103b. For example, a portion of the isolation film 102 can extend along the two side surfaces of the first active semiconductor layer 103a in the second direction, the two side surfaces of the second active semiconductor layer 103b in the second direction, the upper surface of the first active semiconductor layer 103a, and the upper surface of the second active semiconductor layer 103b. Therefore, the first active semiconductor layer 103a and the second active semiconductor layer 103b can be covered by the isolation film 102.

[0087] Reference Figure 10BA dummy gate 121 can be conformally formed along the surface of the isolation film 102. The dummy gate 121 may include, for example, polysilicon germanium (poly-SiGe), but is not limited thereto. The dummy gate 121 can be formed with a constant thickness. For example, the thickness of the dummy gate 121 in a first direction in the region facing the upper surface of the substrate 101 can be approximately the same as the thickness of the dummy gate 121 in a second direction in the regions facing the side surfaces of the first active semiconductor layer 103a and the second active semiconductor layer 103b.

[0088] Reference Figure 10C A mask 122 can be formed on the dummy gate 121 to completely cover the first active semiconductor layer 103a and the second active semiconductor layer 103b. For example, the height of the mask 122 can be greater than the height of the first active semiconductor layer 103a and the second active semiconductor layer 103b. Next, the portion of the mask 122 covering the first active semiconductor layer 103a can be removed to expose the dummy gate 121 surrounding the first active semiconductor layer 103a. The mask 122 can remain only around the second active semiconductor layer 103b. Then, the dummy gate 121 exposed around the first active semiconductor layer 103a can be removed by an etching process. Therefore, the isolation film 102 surrounding the first active semiconductor layer 103a can be exposed. As a result, the dummy gate 121 can remain only around the second active semiconductor layer 103b.

[0089] Reference Figure 10D After completely removing the mask 122, dummy gate material can be further conformally deposited on the substrate 101. Therefore, the dummy gate material can be deposited around the first active semiconductor layer 103a to form a first dummy gate 121a. Additionally, dummy gate material can be further added around the dummy gate 121a around the second active semiconductor layer 103b to form a second dummy gate 121b with an increased thickness.

[0090] The thickness of the first dummy gate 121a can be uniform. For example, the first directional thickness of the first dummy gate 121a in the region facing the upper surface of the substrate 101 can be approximately the same as the second directional thickness of the first dummy gate 121a in the region facing the side surface of the first active semiconductor layer 103a. The thickness of the second dummy gate 121b can be uniform. For example, the first directional thickness of the second dummy gate 121b in the region facing the upper surface of the substrate 101 can be approximately the same as the second directional thickness of the second dummy gate 121b in the region facing the side surface of the second active semiconductor layer 103b. The thickness of the first dummy gate 121a can be different from that of the second dummy gate 121b. For example, the thickness of the first dummy gate 121a can be less than the thickness of the second dummy gate 121b. Therefore, a step difference can be formed at the boundary where the first dummy gate 121a and the second dummy gate 121b contact.

[0091] After forming the first dummy gate 121a and the second dummy gate 121b, a dielectric layer 123 may be conformally formed to cover the surfaces of the first dummy gate 121a and the second dummy gate 121b. The dielectric layer 123 may be used as an etch stop layer in the process described below. The dielectric layer 123 may include, for example, SiO2 or SiN, but is not limited thereto.

[0092] Reference Figure 10E A mask 124 can be formed to completely cover the dielectric layer 123. For example, the mask 124 can be formed to completely cover the thickness of the dielectric layer 123 on the first dummy gate 121a and the second dummy gate 121b. The mask 124 can be formed to have a flat upper surface. Next, the mask 124 can be patterned to expose the dielectric layer 123 in the region where the gate notch GC will later be formed. Next, the isolation film 102 can be partially etched to form a concave trench 130, which is adjacent to the first active semiconductor layer 103a and the second active semiconductor layer 103b in a second direction and extends upward in a third direction. For example, the dielectric layer 123 in the exposed region of the patterned mask 124 can be removed by an etching process. The etching process can be performed such that the dielectric layer 123, the first dummy gate 121a and the second dummy gate 121b in the exposed region are completely removed and the isolation film 102 is partially removed. Therefore, grooves 130 with concave shapes can be formed in the isolation membrane 102.

[0093] Figure 10F From Figure 10E A plan view of the structure as seen from above. (Refer to...) Figure 10FThe first active semiconductor layer 103a and the second active semiconductor layer 103b can extend upward in a third direction. Additionally, trenches 130 extending upward in a third direction parallel to the first active semiconductor layer 103a and the second active semiconductor layer 103b can be formed in the isolation film 102. For example, two trenches 130 can be formed adjacent to the first active semiconductor layer 103a and the second active semiconductor layer 103b in a second direction, such that the first active semiconductor layer 103a and the second active semiconductor layer 103b are positioned between the two trenches 130 in the second direction.

[0094] Reference Figure 10G The mask 124 can be completely removed, and a dummy block 125 can be formed. The dummy block 125 can be formed to fill the trench 130 and completely cover the first active semiconductor layer 103a, the second active semiconductor layer 103b, and the dielectric layer 123. For example, the dummy block 125 can be formed to completely cover the thickness of the dielectric layer 123 on the first dummy gate 121a and the second dummy gate 121b. The dummy pad 125 can be formed to have a flat upper surface. The dummy block 125 can include, for example, polysilicon (poly-Si), but is not limited thereto.

[0095] Figure 10H It is used for explanation Figure 10G A top-down plan view of the subsequent process. (Refer to...) Figure 10H The system can define a first region R1 in which the source and drain regions are to be formed, and a second region R2 in which the gate insulating film and gate electrode are to be formed. For example, the first active semiconductor layer 103a and the second active semiconductor layer 103b can be exposed in the first region R1 by patterning. The dummy block 125 in the second region R2 can remain unchanged. Next, spacers 110 can be formed on both sides of the second region R2 in the third direction. A plurality of first regions R1 and a plurality of second regions R2 can be arranged alternately in the third direction. The first region R1, the second region R2 and the spacers 110 can extend in a second direction.

[0096] Figure 10I Show along Figure 10H The vertical cross-sectional structure of line C1-C1' in the first region R1 is shown. (Refer to...) Figure 10I The first active semiconductor layer 103a and the second active semiconductor layer 103b can be exposed to the outside within the first region R1 by an etching process. For example, a portion of the dielectric layer 123 around the first active semiconductor layer 103a and the second active semiconductor layer 103b, a portion of the first dummy gate 121a, a portion of the second dummy gate 121b, and a portion of the dummy block 125 can be removed.

[0097] Reference Figure 10JThe dielectric layer 123, the first dummy gate 121a, the second dummy gate 121b, and the dummy block 125 remaining in the first region R1 can be completely removed. The upper regions of the first active semiconductor layer 103a and the second active semiconductor layer 103b can also be partially removed. Additionally, an insulating layer 126 can be formed along the side surfaces of the remaining first active semiconductor layer 103a and the remaining second active semiconductor layer 103b and along the upper surface of the isolation film 102. The insulating layer 126 may include components related to… Figure 1 and Figure 2 The first passivation layer 106 or the second passivation layer 109 shown are made of the same material. Thereafter, a semiconductor doped with impurities of the second conductivity type can be grown from the upper portions of the remaining first active semiconductor layer 103a and the remaining second active semiconductor layer 103b to form the first drain region 108a and the second drain region 108b. Although in Figure 10J Although not shown, in another adjacent first region R1, a first source region and a second source region can be formed in the same manner as the first drain region 108a and the second drain region 108b. Although not shown, after forming the source and drain regions, the first source region and the second source region can be... Figure 2 The second passivation layer 109 shown is filled into the first region R1.

[0098] Subsequently, as described later, a gate insulating film and a gate electrode can be formed in the second region R2. Optionally, the process of forming the gate insulating film and the gate electrode in the second region R2 can be performed first, and then the process can be performed... Figure 10I and Figure 10J The process for forming the source and drain regions is shown.

[0099] Reference Figure 10K The dummy block 125 can be etched anisotropically, so that the dielectric layer 123 is exposed in the second region R2. Figure 10K Shown along after exposing dielectric layer 123 Figure 10H The second region R2 shown is a vertical cross-sectional structure cut by line C2-C2'. For example, the upper portion of the dummy block 125 can be removed using a dry etching method. The dielectric layer 123 can be used as... Figure 10K The etch stop layer is shown.

[0100] On the other hand, the trench 130 in the second region R2 can separate the gate insulating film and gate electrode of the field-effect transistor to be formed in the process described later from the gate insulating film and gate electrode of another field-effect transistor that does not share a signal therebetween. In this respect, the trench 130 in the second region R2 can be referred to as the gate cutout GC.

[0101] Reference Figure 10LThe dielectric layer 123, the first dummy gate 121a, and the second dummy gate 121b can be removed within the second region R2. Additionally, the material of the isolation film 102 on the side surfaces of the first active semiconductor layer 103a and the second active semiconductor layer 103b within the second region R2 can also be removed. For example, the first active semiconductor layer 103a and the second active semiconductor layer 103b can be exposed by isotropically removing the material inside the dummy block 125 using a wet etching method. Therefore, an empty space can be formed within the dummy block 125.

[0102] Reference Figure 10M A gate insulating film 104, a first gate electrode 105a, a gate connection portion 111, and a second gate electrode 105b can be formed in the empty space within the dummy block 125. For example, the gate insulating film 104 can be formed first using an atomic layer deposition (ALD) method. Therefore, the gate insulating film 104 can be conformally formed along the surface inside the dummy block 125. For example, the gate insulating film 104 can be conformally formed within the dummy block 125 along the surface of the first active semiconductor layer 103a, the surface of the second active semiconductor layer 103b, the upper surface of the isolation film 102, and the inner surface of the dummy block 125. The gate insulating film 104 may include a dielectric material having a relatively high dielectric constant. The gate insulating film 104 may include, for example, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO4), tantalum oxide (Ta2O5), titanium oxide (TiO2), aluminum oxide (Al2O3), etc.

[0103] Next, after forming the gate insulating film 104, the remaining empty spaces within the dummy block 125 can be conformally filled with a conductive material. For example, by conformally depositing conductive material in the remaining empty spaces within the dummy block 125 after forming the gate insulating film 104 using the ALD method, the first gate electrode 105a, the gate connection portion 111, and the second gate electrode 105b can be formed simultaneously. In this respect, the first gate electrode 105a, the gate connection portion 111, and the second gate electrode 105b can be considered as a monolayer integrally formed from the same material. The conductive material can include at least one of, for example, metals, metal nitrides, metal carbides, and polysilicon. Metals can include, for example, aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), etc. Metal nitrides can include, for example, titanium nitride (TiN), tantalum nitride (TaN), etc. Metal carbides can include, for example, TiAlC, TaAlC, TiSiC, TaSiC, etc.

[0104] The gate insulating film 104, the first gate electrode 105a, the gate connection portion 111, and the second gate electrode 105b formed in this manner can be separated from the gate insulating film and gate electrode of another field-effect transistor that does not share a signal through the gate cutout GC. The gate cutout GC can define the end portions of the first gate electrode 105a and the second gate electrode 105b within the second region R2.

[0105] On the other hand, during the formation of the gate insulating film 104, gate insulating film material 104' can also be deposited on the upper surface of the dummy block 125. Additionally, during the formation of the first gate electrode 105a, the gate connection portion 111, and the second gate electrode 105b, gate electrode material 105' can also be deposited above the upper surface of the dummy block 125. (Refer to...) Figure 10N The gate electrode material 105' and gate insulating film material 104' retained on the dummy block 125 can be removed by using an etching process or a chemical mechanical planarization (CMP) process. Through these processes, the first field-effect transistor TR1 and the second field-effect transistor TR2 can be formed.

[0106] Reference Figure 10O A mask 127 can be formed to cover the entire upper surface of the dummy block 125, the upper surface of the first gate electrode 105a, and the upper surface of the second gate electrode 105b. Then, after patterning the mask 127 to expose the dummy block 125 between the first gate electrode 105a and the second gate electrode 105b, the dummy block 125 between the first gate electrode 105a and the second gate electrode 105b can be removed by an etching process. Additionally, the gate insulating film 104 between the first gate electrode 105a and the second gate electrode 105b can also be removed. Therefore, an empty space can be formed between the first gate electrode 105a and the second gate electrode 105b.

[0107] Reference Figure 10P The space between the first gate electrode 105a and the second gate electrode 105b can be filled with insulating filler 112. For example, after the material of insulating filler 112 has been deposited until it covers the upper surface of dummy block 125, the material of insulating filler 112 above dummy block 125 can be removed by a planarization process, thereby exposing dummy block 125.

[0108] Reference Figure 10Q A portion of the insulating filler 112 between the first gate electrode 105a and the second gate electrode 105b can be removed. Then, an empty space can be formed between the first gate electrode 105a and the second gate electrode 105b and above the insulating filler 112.

[0109] Reference Figure 10RConductive filler 113 can be filled in the empty space between the first gate electrode 105a and the second gate electrode 105b and above the insulating filler 112. For example, after the material of conductive filler 113 has been deposited until it covers the upper surface of the dummy block 125, the material of conductive filler 113 above the dummy block 125 can be removed by a planarization process, thereby exposing the dummy block 125.

[0110] Reference Figure 10S The remaining dummy block 125 can be completely removed, and the first passivation layer 106 can be filled in the second region R2. Then, after forming a hole in the first passivation layer 106 to expose the conductive filler 113, the hole can be filled with a conductive material to form a gate contact 114.

[0111] Optionally, if the gate contact 114 is not formed, this step may not be performed. Figures 100 to 10S The process shown, and in Figure 10N In the process shown, after the dummy block 125 is completely removed, the first passivation layer 106 can be filled into the second region R2. Additionally, as described above, Figures 10K to 10S The process shown can be performed in Figure 10I and Figure 10J The process shown is performed beforehand.

[0112] As described above, in the manufacturing process of the semiconductor device according to the embodiment, the gate cleavage (GC) can be formed before the gate electrode is formed. Therefore, compared to the case where a gate electrode with a relatively high aspect ratio is formed first and then the gate cleavage is formed later, the manufacturing process difficulty may be reduced and the possibility of defects occurring in the manufacturing process may also be reduced according to the embodiment.

[0113] Figure 11 The structure of a semiconductor device according to another embodiment is schematically shown. So far, the case where the field-effect transistor of the semiconductor device is a FinFET has been described, but it is not limited to this. The field-effect transistor can also be a GAAFET. See reference... Figure 11 The first active semiconductor layer 103a and the second active semiconductor layer 103b of the semiconductor device 100d can be physically separated from the substrate 101 and the isolation film 102 below them. In other words, the first active semiconductor layer 103a and the second active semiconductor layer 103b can be spaced apart from the substrate 101 and the isolation film 102 in a first direction, and can extend in the first direction.

[0114] The gate insulating film 104 may surround the four surfaces of the first active semiconductor layer 103a and the four surfaces of the second active semiconductor layer 103b. Specifically, a first portion of the gate insulating film 104 may completely surround all surfaces of the first active semiconductor layer 103a and the second active semiconductor layer 103b, that is, their lower surface, upper surface, and two side surfaces in the second direction. Between the end portions of the second portions of the first gate electrode 105a and the second portions of the second gate electrode 105b, or between the two gate cutouts, the second portion of the gate insulating film 104 may extend continuously in the second direction along the upper surface of the isolation film 102. For example, the second portion of the gate insulating film 104 may extend continuously in the second direction along the lower surfaces of the second portions of the first gate electrode 105a and the second portions of the second gate electrode 105b to the sidewall of the gate cutout GC or the outer surface of the gate electrode 105, such as... Figure 1 and Figure 6 As shown, the first portion of the gate insulating film 104 surrounding the first active semiconductor layer 103a and the second active semiconductor layer 103b can be physically separated from the second portion of the gate insulating film 104 provided on the upper surface of the isolation film 102.

[0115] The first gate electrode 105a may surround the four surfaces of the gate insulating film 104 surrounding the first active semiconductor layer 103a, particularly the four surfaces of the first portion of the gate insulating film 104. The second gate electrode 105b may surround the four surfaces of the gate insulating film 104 surrounding the second active semiconductor layer 103b, particularly the four surfaces of the first portion of the gate insulating film 104. Furthermore, the first gate electrode 105a, the gate connection portion 111, and the second gate electrode 105b may extend continuously in a second direction on the second portion of the gate insulating film 104.

[0116] Figure 12 The structure of a semiconductor device according to another embodiment is schematically shown. (Refer to...) Figure 12Each of the first active semiconductor layer 103a and the second active semiconductor layer 103b of the semiconductor device 100e may include a plurality of channel elements spaced apart from each other in a first direction. For example, the first active semiconductor layer 103a may include a first channel element 103a1, a second channel element 103a2, and a third channel element 103a3 arranged sequentially and spaced apart from each other in a first direction, and the second active semiconductor layer 103b may include a first channel element 103b1, a second channel element 103b2, and a third channel element 103b3 arranged sequentially and spaced apart from each other in a first direction. A first gate electrode 105a may surround each of the first channel elements 103a1, the second channel element 103a2, and the third channel element 103a3 of the first active semiconductor layer 103a, and a second gate electrode 105b may surround each of the first channel elements 103b1, the second channel element 103b2, and the third channel element 103b3 of the second active semiconductor layer 103b.

[0117] Furthermore, a first portion of the gate insulating film 104 may completely surround all surfaces (e.g., its two side surfaces in the second direction, its lower surface, and its upper surface) of the first channel elements 103a1, 103a2, and 103a3 of the first active semiconductor layer 103a and the first channel elements 103b1, 103b2, and 103b3 of the second active semiconductor layer 103b. In other words, the gate insulating film 104 may be between each of the first channel elements 103a1, 103a2, and 103a3 of the first active semiconductor layer 103a and the first gate electrode 105a, and the gate insulating film 104 may be between each of the first channel elements 103b1, 103b2, and 103b3 of the second active semiconductor layer 103b and the second gate electrode 105b. Although Figure 12 The diagram shows that each of the first active semiconductor layer 103a and the second active semiconductor layer 103b includes three channel elements, but this is only an example, and the number of channel elements is not limited to this. Figure 12 The quantities shown in the figure.

[0118] Figure 13 The structure of a semiconductor device according to another embodiment is schematically shown. (Refer to...) Figure 13The first gate electrode 105a and the second gate electrode 105b of the semiconductor device 100f may each include a plurality of gate layers for controlling the threshold voltage of the field-effect transistor. For example, the first gate electrode 105a may include a first gate layer 105a1 and a second gate layer 105a2. The second gate electrode 105b may include a first gate layer 105b1 and a second gate layer 105b2. In addition, the first gate connection portion 111a may include a first connection layer 111a1 and a second connection layer 111a2, and the second gate connection portion 111b may include a first connection layer 111b1 and a second connection layer 111b2. The first gate layer 105a1 of the first gate electrode 105a, the first gate layer 105b1 of the second gate electrode 105b, the first connection layer 111a1 of the first gate connection portion 111a, and the first connection layer 111b1 of the second gate connection portion 111b may be integrally formed of a first conductive material. The second gate layer 105a2 of the first gate electrode 105a, the second gate layer 105b2 of the second gate electrode 105b, the second connection layer 111a2 of the first gate connection portion 111a, and the second connection layer 111b2 of the second gate connection portion 111b can be integrally formed from a second conductive material different from the first conductive material.

[0119] For example, in Figure 10M In the process shown, after the gate insulating film 104 is conformally formed, a first conductive material is conformally deposited to integrally form the first gate layer 105a1 of the first gate electrode 105a, the first gate layer 105b1 of the second gate electrode 105b, the first connection layer 111a1 of the first gate connection portion 111a, and the first connection layer 111b1 of the second gate connection portion 111b. Subsequently, the first gate layer 105a1 of the first gate electrode 105a, the first gate layer 105b1 of the second gate electrode 105b, the first connection layer 111a1 of the first gate connection portion 111a, and the first connection layer 111b1 of the second gate connection portion 111b can be formed, and the remaining space can be filled with a second conductive material to integrally form the second gate layer 105a2 of the first gate electrode 105a, the second gate layer 105b2 of the second gate electrode 105b, the second connection layer 111a2 of the first gate connection portion 111a, and the second connection layer 111b2 of the second gate connection portion 111b.

[0120] Therefore, the second gate layer 105a2 of the first gate electrode 105a can be surrounded by the first gate layer 105a1 of the first gate electrode 105a. Similarly, the second gate layer 105b2 of the second gate electrode 105b can also be surrounded by the first gate layer 105b1 of the second gate electrode 105b. Furthermore, the second connection layer 111a2 of the first gate connection portion 111a can be surrounded by the first connection layer 111a1 of the first gate connection portion 111a. The second connection layer 111b2 of the second gate connection portion 111b can be surrounded by the first connection layer 111b1 of the second gate connection portion 111b. Additionally, the first gate layer 105a1 of the first gate electrode 105a, the first gate layer 105b1 of the second gate electrode 105b, the first connection layer 111a1 of the first gate connection portion 111a, and the first connection layer 111b1 of the second gate connection portion 111b can all be surrounded by the gate insulating film 104.

[0121] In this configuration, the first gate layer 105a1 of the first gate electrode 105a and the first connection layer 111a1 of the first gate connection portion 111a can have the same thickness t1. The first gate layer 105b1 of the second gate electrode 105b and the first connection layer 111b1 of the second gate connection portion 111b can have the same thickness t2. Furthermore, the thickness t1 of the first gate layer 105a1 of the first gate electrode 105a and the first connection layer 111a1 of the first gate connection portion 111a can be the same as the thickness t2 of the first gate layer 105b1 of the second gate electrode 105b and the first connection layer 111b1 of the second gate connection portion 111b. In other words, the first gate layer 105a1 of the first gate electrode 105a, the first gate layer 105b1 of the second gate electrode 105b, the first connection layer 111a1 of the first gate connection portion 111a, and the first connection layer 111b1 of the second gate connection portion 111b can all have the same thickness.

[0122] The second gate layer 105a2 of the first gate electrode 105a and the second connection layer 111a2 of the first gate connection portion 111a can have the same thickness t3. The second gate layer 105b2 of the second gate electrode 105b and the second connection layer 111b2 of the second gate connection portion 111b can have the same thickness t4. On the other hand, the thickness t3 of the second gate layer 105a2 of the first gate electrode 105a and the second connection layer 111a2 of the first gate connection portion 111a can be different from the thickness t4 of the second gate layer 105b2 of the second gate electrode 105b and the second connection layer 111b2 of the second gate connection portion 111b.

[0123] Figure 14 The structure of a semiconductor device according to another embodiment is schematically shown. (Refer to...) Figure 14 ,and Figure 9 Unlike the semiconductor device 100c shown, the semiconductor device 100g may not include the insulating filler 112. In other words, the semiconductor device 100g may further include a conductive filler 113 provided to fill the space surrounded by the first gate electrode 105a, the second gate electrode 105b and the gate connection portion 111.

[0124] Figure 15 The structure of a semiconductor device according to another embodiment is schematically illustrated. Up to this point, it has been described that the first gate electrode 105a, the second gate electrode 105b, and the gate connection portion 111 can be integrally formed from the same conductive material. The threshold voltage of the first field-effect transistor TR1 can be affected by the material of the first gate electrode 105a, and the threshold voltage of the second field-effect transistor TR2 can be affected by the material of the second gate electrode 105b. However, the material of the gate connection portion 111 can have almost no effect on the threshold voltages of the first field-effect transistor TR1 and the second field-effect transistor TR2. With this in mind, the semiconductor device 100h may include the gate connection portion 111, which comprises a conductive material different from the materials of the first gate electrode 105a and the second gate electrode 105b. For example, the gate connection portion 111 may comprise a conductive material having a higher conductivity than the materials of the first gate electrode 105a and the second gate electrode 105b.

[0125] Figures 16A to 16C A method for forming a gate connection portion 111 comprising a conductive material different from that of the first gate electrode 105a and the second gate electrode 105b is schematically illustrated. (Refer to...) Figure 16A ,exist Figure 10L Following the process shown, a gate insulating film 104 can be conformally formed along the surface inside the dummy block 125. Next, a conductive material 111' can be deposited to completely fill the internal space of the dummy block 125. At this time, a conductive material 111' can also be deposited on the upper surface of the dummy block 125.

[0126] Reference Figure 16B The gate connection portion 111 can be formed by removing the conductive material 111' exposed between the dummy blocks 125 via an etching process, leaving the conductive material 111' below the dummy blocks 125. Alternatively, the conductive material 111' can be removed. (See reference...) Figure 16C The remaining space can be filled with gate electrode material to form the first gate electrode 105a and the second gate electrode 105b. Next, the following can be performed: Figures 100 to 10S The process shown may remove the dummy block 125 and form the first passivation layer 106.

[0127] The aforementioned semiconductor devices can be used, for example, in display driver integrated circuits, complementary metal-oxide-semiconductor (CMOS) inverters, CMOS static random access memory (SRAM) devices, CMOS NAND circuits, neural network devices, and / or various other electronic devices.

[0128] Figure 17 This is a circuit diagram of a CMOS inverter 400 according to an embodiment. (Refer to...) Figure 17 The CMOS inverter 400 may include a CMOS transistor 410. The CMOS transistor 410 may include a PMOS transistor 420 and an NMOS transistor 430 connected between a power supply terminal Vdd and a ground terminal. The CMOS transistor 410 may include a semiconductor device according to any of the above embodiments.

[0129] Figure 18 This is a circuit diagram of a CMOS SRAM device 500 according to an embodiment. (Refer to...) Figure 18 The CMOS SRAM device 500 may include a pair of driving transistors 510. Each of the pair of driving transistors 510 may include a PMOS transistor 520 and an NMOS transistor 530 connected between a power supply terminal Vdd and a ground terminal. The CMOS SRAM device 500 may further include a pair of transfer transistors 540. The source of the transfer transistor 540 may be cross-connected to a common node of the PMOS transistor 520 and the NMOS transistor 530 constituting the driving transistor 510. The source of the PMOS transistor 520 may be connected to the power supply terminal Vdd, and the source of the NMOS transistor 530 may be connected to the ground terminal. A word line WL may be connected to the gate of the pair of transfer transistors 540, and a bit line BL and an anti-phase line may be connected to the drain of the pair of transfer transistors 540, respectively. At least one of the driving transistors 510 and the transfer transistors 540 of the CMOS SRAM device 500 may include a semiconductor device according to any of the above embodiments.

[0130] Figure 19 This is a block diagram illustrating an electronic device 700 according to an embodiment. (Refer to...) Figure 19 The electronic device 700 may include a memory 710 and a memory controller 720. The memory controller 720 may control the memory 710 to read data from and / or write data to the memory 710 in response to a request from the host 730. At least one of the memory 710 and the memory controller 720 may include a semiconductor device according to any of the above embodiments.

[0131] Figure 20 This is a block diagram of an electronic device 800 according to an embodiment. (Refer to...) Figure 20The electronic device 800 can be configured as a wired / wireless communication device, or as a device for transmitting and / or receiving information in a wired or wireless environment. The electronic device 800 may include a controller 810, an input / output (I / O) device 820, a memory 830, and a wireless interface 840, each interconnected via a bus 850.

[0132] The controller 810 may include at least one of a microprocessor, a digital signal processor, or a similar processing device. The I / O device 820 may include at least one of a keypad, a keyboard, or a display. The memory 830 may be used to store commands executed by the controller 810. For example, the memory 830 may be used to store user data. The electronic device 800 may use a wireless interface 840 to send / receive data via a wireless communication network. The wireless interface 840 may include an antenna and / or a wireless transceiver. In some embodiments, the electronic device 800 may be used with communication interface protocols of third-generation communication systems, such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), North American Digital Cellular (NADC), Extended Time Division Multiple Access (E-TDMA), and / or Wideband Code Division Multiple Access (WCDMA). At least one of the controller 810, I / O device 820, memory 830, and wireless interface 840 of the electronic device 800 may include a semiconductor device according to any of the above embodiments.

[0133] The implementation methods described so far can be summarized as follows.

[0134] (1) The semiconductor device according to the embodiment may include an active semiconductor layer, a gate insulating film provided to surround at least three surfaces of the active semiconductor layer, a gate electrode extending in a first direction to surround at least three surfaces of the gate insulating film, and a gate cut having a trench shape to electrically isolate the gate electrode from another gate electrode or another electronic device and being provided to face the gate electrode in a second direction perpendicular to the first direction, wherein the gate insulating film may extend along the lower surface of the gate electrode to the sidewall of the gate cut.

[0135] (2) The semiconductor device may further include an isolation film comprising an insulating dielectric material, and an active semiconductor layer may extend to protrude over the isolation film in a first direction.

[0136] (3) The gate electrode may include a first portion and a second portion, the first portion extending from the upper surface of the isolation film along the surface of the active semiconductor layer to surround the active semiconductor layer, and the second portion extending in a second direction on the upper surface of the isolation film.

[0137] (4) The gate insulating film may include a first portion provided between the active semiconductor layer and a first portion of the gate electrode and a second portion provided between the upper surface of the insulating film and a second portion of the gate electrode.

[0138] (5) The gate insulating film may further include a third portion extending through the sidewall of the gate cut to the outer surface of the gate electrode opposite to the active semiconductor layer, and the first, second and third portions of the gate insulating film may extend continuously.

[0139] (6) The end portion of the second part of the gate electrode can be matched with the position of the gate cutout.

[0140] (7) The gate cutout may have the shape of a groove provided in the upper surface of the isolation membrane, and the bottom surface of the gate cutout may protrude further in the first direction than the upper surface of the isolation membrane adjacent to the gate cutout in a third direction perpendicular to the first and second directions.

[0141] (8) The active semiconductor layer may include a first active semiconductor layer and a second active semiconductor layer that are adjacent in the second direction, the gate electrode may include a first gate electrode surrounding at least three surfaces of the first active semiconductor layer and a second gate electrode surrounding at least three surfaces of the second active semiconductor layer, and the semiconductor device may further include a gate connection portion provided between the first gate electrode and the second gate electrode.

[0142] (9) In an embodiment, the first gate electrode, the second gate electrode and the gate connection portion may be integrally formed from a single conductive material.

[0143] (10) In another embodiment, the gate connection portion may include a conductive material having a higher conductivity than the materials of the first gate electrode and the second gate electrode.

[0144] (11) The gate insulating film may be provided to surround at least three surfaces of the first active semiconductor layer between the first active semiconductor layer and the first gate electrode, and to surround at least three surfaces of the second active semiconductor layer between the second active semiconductor layer and the second gate electrode.

[0145] (12) The gate insulating film may extend along the surface of the first gate electrode, the gate connection portion and the second gate electrode.

[0146] (13) The gate insulating film may surround the lower surface of the gate connection portion, the upper surface of the gate connection portion, and the two side surfaces of the gate connection portion in a third direction perpendicular to the first direction and the second direction.

[0147] (14) The gate connection portion may include a first gate connection portion adjacent to the first gate electrode and a second gate connection portion adjacent to the second gate electrode, and the first direction thickness of the first gate connection portion may be different from the first direction thickness of the second gate connection portion.

[0148] (15) Each of the first gate electrode and the second gate electrode may include a first gate layer and a second gate layer surrounded by the first gate layer, and each of the first gate connection portion and the second gate connection portion may include a first connection layer and a second connection layer surrounded by the first connection layer.

[0149] (16) The first gate layer of the first gate electrode, the first gate layer of the second gate electrode, the first connection layer of the first gate connection portion and the first connection layer of the second gate connection portion may include a first conductive material.

[0150] (17) The second gate layer of the first gate electrode, the second gate layer of the second gate electrode, the second connection layer of the first gate connection portion and the second connection layer of the second gate connection portion may include a second conductive material different from the first conductive material.

[0151] (18) The first connection layer of the first gate connection portion and the first connection layer of the second gate connection portion may have the same thickness, and the first direction thickness of the second connection layer of the first gate connection portion may be different from the first direction thickness of the second connection layer of the second gate connection portion.

[0152] (19) In an embodiment, the semiconductor device may further include an insulating filler provided to cover a gate connection portion between the first gate electrode and the second gate electrode, a conductive filler provided on the insulating filler between the first gate electrode and the second gate electrode, and a gate contact contacting the upper surface of the conductive filler.

[0153] (20) In another embodiment, the semiconductor device may further include a conductive filler provided to cover a gate connection portion between the first gate electrode and the second gate electrode, and a gate contact that contacts the upper surface of the conductive filler.

[0154] (21) The gate insulating film may include a first portion surrounding the four surfaces of the active semiconductor layer and a second portion extending along the lower surface of the gate electrode in a second direction to the sidewall of the gate cutout, the first portion of the gate insulating film being separate from the second portion of the gate insulating film, and the gate electrode being surrounding the four surfaces of the first portion of the gate insulating film.

[0155] (22) The active semiconductor layer may include a plurality of channel elements spaced apart from each other in a first direction, and a first portion of the gate insulating film may surround the surface of each of the plurality of channel elements.

[0156] (23) A method of manufacturing a semiconductor device, the method comprising: forming an active semiconductor layer protruding from and extending from a substrate in a first direction; forming an isolation film covering an upper surface of the substrate and a side surface of the active semiconductor layer; conformally forming a dummy gate along the surface of the isolation film; forming a trench adjacent to the active semiconductor layer in a second direction perpendicular to the first direction and extending upward in a third direction perpendicular to the first and second directions by partially etching the isolation film; forming a dummy block to cover the trench and the active semiconductor layer; removing the isolation film on the side surface of the dummy gate and the active semiconductor layer to expose the active semiconductor layer and forming an empty space within the dummy block; conformally forming a gate insulating film along the inner surface of the dummy block and the surface of the active semiconductor layer; forming a gate electrode by filling the empty space remaining after the formation of the gate insulating film within the dummy block with a conductive material; and removing the dummy block.

[0157] (24) An electronic device may include a memory and a memory controller for controlling the memory to read data from the memory and / or write data to the memory, wherein at least one of the memory and the memory controller includes a semiconductor device, the semiconductor device including an active semiconductor layer, a gate insulating film provided for surrounding at least three surfaces of the active semiconductor layer, a gate electrode extending in a first direction to surround at least three surfaces of the gate insulating film, and a gate cutout having a trench shape to electrically isolate the gate electrode from another gate electrode or another electronic device and provided as a gate cutout facing the gate electrode in a second direction perpendicular to the first direction, wherein the gate insulating film extends along the lower surface of the gate electrode to the sidewall of the gate cutout.

[0158] According to the embodiments disclosed herein, the gate slit can be formed first in the semiconductor device manufacturing process before the gate electrode is formed. Therefore, compared to the case where a gate electrode with a relatively high aspect ratio is formed first and then the gate slit is formed later, the manufacturing process difficulty can be reduced and the possibility of defects occurring in the manufacturing process can also be reduced according to the embodiments.

[0159] Although the above-described semiconductor device, method of manufacturing semiconductor device, and electronic device including semiconductor device have been described with reference to embodiments shown in the accompanying drawings, these are merely examples, and those skilled in the art will understand that various modifications and equivalent embodiments are possible from them. Therefore, the embodiments disclosed herein should be considered illustrative rather than restrictive. The scope of the claims is indicated in the claims, not in the foregoing description, and all differences within the scope of equivalents may be construed as being included within the scope of the claims.

[0160] The concept of "substantially identical" elements can indicate that elements can be completely identical, and can also indicate that elements can be determined to be identical, taking into account errors or deviations that occur during the process.

[0161] Although the term "equal to" is used in the description of the example implementation, it should be understood that some imprecision may exist. Therefore, when an element is said to be "equal to" another element, it should be understood that the element or value may be "equal to" the other element within a range of expected manufacturing or operational tolerances (e.g., ±10%).

[0162] One or more of the elements disclosed herein may include or be implemented in processing circuitry, which is hardware such as including logic circuitry; hardware / software combinations such as a processor executing software; or combinations thereof. For example, processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0163] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

[0164] Cross-references to related applications

[0165] This application is based on and claims priority to Korean Patent Application No. 10-2024-0196098, filed on December 24, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: Active semiconductor layer; A gate insulating film surrounds at least three surfaces of the active semiconductor layer; as well as A gate electrode, extending in a first direction and surrounding at least three surfaces of the gate insulating film, wherein The gate electrode is separated from another gate electrode or another electronic device by a gate cutout with a trench shape, so as to electrically isolate the gate electrode from the other gate electrode or the other electronic device. The gate notch faces the gate electrode in the second direction. The second direction is perpendicular to the first direction, and The gate insulating film extends along the lower surface of the gate electrode to the sidewall of the gate notch.

2. The semiconductor device according to claim 1, further comprising: The insulating membrane includes an insulating dielectric material, wherein The active semiconductor layer extends in the first direction and protrudes from the isolation membrane in the first direction.

3. The semiconductor device according to claim 2, wherein The first portion of the gate electrode extends from the upper surface of the isolation film along the surface of the active semiconductor layer to surround the active semiconductor layer. The second portion of the gate electrode extends in the second direction on the upper surface of the insulating membrane. The first portion of the gate insulating film lies between the active semiconductor layer and the first portion of the gate electrode, and The second portion of the gate insulating film is between the upper surface of the isolation film and the second portion of the gate electrode.

4. The semiconductor device according to claim 3, wherein The third portion of the gate insulating film extends through the sidewall of the gate notch to the outer surface of the gate electrode opposite to the active semiconductor layer, and The first portion, the second portion, and the third portion of the gate insulating film extend continuously.

5. The semiconductor device according to claim 3, wherein The end portion of the second part of the gate electrode is matched with the position of the gate cutout.

6. The semiconductor device according to claim 2, wherein The gate notch has the shape of the trench provided in the upper surface of the isolation membrane. The bottom surface of the gate notch protrudes further in the first direction from the upper surface of the isolation film adjacent to the gate notch in the third direction, and The third direction is perpendicular to the first direction and the second direction.

7. The semiconductor device according to claim 1, further comprising: Gate connection portion, wherein The active semiconductor layer includes a first active semiconductor layer and a second active semiconductor layer that are adjacent to each other in the second direction. The gate electrode includes a first gate electrode surrounding at least three surfaces of the first active semiconductor layer and a second gate electrode surrounding at least three surfaces of the second active semiconductor layer, and The gate connection portion is located between the first gate electrode and the second gate electrode.

8. The semiconductor device according to claim 7, wherein The first gate electrode, the second gate electrode, and the gate connection portion are integrally formed from a single conductive material.

9. The semiconductor device according to claim 7, wherein The gate connection portion includes a conductive material having a higher conductivity than the materials of the first gate electrode and the second gate electrode.

10. The semiconductor device according to claim 7, wherein The gate insulating film surrounds at least three surfaces of the first active semiconductor layer between the first active semiconductor layer and the first gate electrode, and The gate insulating film surrounds at least three surfaces of the second active semiconductor layer between the second active semiconductor layer and the second gate electrode.

11. The semiconductor device of claim 10, wherein... The gate insulating film extends along the first gate electrode, the gate connection portion, and the second gate electrode.

12. The semiconductor device of claim 11, wherein... The gate insulating film surrounds the lower surface of the gate connection portion, the upper surface of the gate connection portion, and the two side surfaces of the gate connection portion in the third direction. The third direction is perpendicular to the first direction and the second direction.

13. The semiconductor device according to claim 7, wherein The gate connection portion includes a first gate connection portion adjacent to the first gate electrode and a second gate connection portion adjacent to the second gate electrode, and The thickness of the first gate connection portion in the first direction is different from the thickness of the second gate connection portion in the first direction.

14. The semiconductor device of claim 13, wherein The first gate electrode and the second gate electrode each include a first gate layer and a second gate layer surrounded by the first gate layer. The first gate connection portion and the second gate connection portion each include a first connection layer and a second connection layer surrounded by the first connection layer. The first gate layer of the first gate electrode, the first gate layer of the second gate electrode, the first connection layer of the first gate connection portion, and the first connection layer of the second gate connection portion each include a first conductive material. The second gate layer of the first gate electrode, the second gate layer of the second gate electrode, the second connection layer of the first gate connection portion, and the second connection layer of the second gate connection portion each include a second conductive material. The second conductive material is different from the first conductive material. The thickness of the first connection layer in the first gate connection portion is equal to the thickness of the first connection layer in the second gate connection portion, and The thickness of the second connection layer of the first gate connection portion in the first direction is different from the thickness of the second connection layer of the second gate connection portion in the first direction.

15. The semiconductor device according to claim 7, further comprising: An insulating filler covers the gate connection portion between the first gate electrode and the second gate electrode; A conductive filler is provided on the insulating filler between the first gate electrode and the second gate electrode; as well as The gate contact contacts the upper surface of the conductive filler.

16. The semiconductor device of claim 7, further comprising: A conductive filler covers the gate connection portion between the first gate electrode and the second gate electrode; as well as The gate contact contacts the upper surface of the conductive filler.

17. The semiconductor device according to claim 1, wherein The first portion of the gate insulating film surrounds the four surfaces of the active semiconductor layer. A second portion of the gate insulating film extends along the lower surface of the gate electrode in the second direction to the sidewall of the gate notch. The first portion of the gate insulating film is separated from the second portion of the gate insulating film, and The gate electrode surrounds the four surfaces of the first portion of the gate insulating film.

18. The semiconductor device of claim 17, wherein The active semiconductor layer includes a plurality of channel elements spaced apart from each other in the first direction, and The first portion of the gate insulating film surrounds the surface of each of the plurality of channel elements.

19. A method for manufacturing a semiconductor device, the method comprising: An active semiconductor layer is formed, the active semiconductor layer protruding and extending from the substrate in a first direction; An isolation film is formed covering the upper surface of the substrate and the side surface of the active semiconductor layer; A dummy gate is conformally formed along the surface of the isolation membrane; By partially etching the isolation film, a trench is formed adjacent to the active semiconductor layer in a second direction, which is perpendicular to the first direction. The trench extends upward in a third direction, which is perpendicular to both the first and second directions. A dummy block is formed, which covers the trench and the active semiconductor layer; Remove the isolation film from the side surface of the dummy gate and the side surface of the active semiconductor layer to expose the active semiconductor layer and form an empty space in the dummy block; A gate insulating film is conformally formed along the inner surface of the dummy block and the side surface of the active semiconductor layer; The gate electrode is formed by filling the empty spaces in the dummy block with a conductive material in the remaining portion after the gate insulating film is formed. as well as Remove the dummy block.

20. An electronic device, comprising: Memory; and A memory controller is configured to control the memory to read data from the memory and / or write data to the memory. At least one of the memory and the memory controller comprises a semiconductor device according to any one of claims 1 to 18.

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