Solar cell and photovoltaic module

Abstract

This application provides a solar cell and a photovoltaic module. The solar cell includes a silicon substrate and a doped layer, a main grid, and a sub-grid disposed on the surface of the silicon substrate. The surface of the silicon substrate includes alternating first and second regions. The first region is a region for disposing of the sub-grid and is provided with a doped layer. The second region is a region without a doped layer. An overlapping structure is provided at the intersection of the main grid and the sub-grid. The width of the first region increases from the middle of the first region to the end of the first region, thereby ensuring the printing alignment of the sub-grid and the increase of the Polytech region.

Description

Technical Field

[0001] This application relates to the field of solar cells, and more particularly to a solar cell and a photovoltaic module. Background Technology

[0002] Polytech technology is a technique that removes a doped layer (also known as a poly layer) from some non-grid-line regions of a solar cell, resulting in areas with doped layers and areas without. Polytech technology allows the poly layer to be formed into a finger-like structure, where the areas without a poly layer are called non-grid-line regions, and the areas with a poly layer are called grid-line regions. However, currently, during the printing of sub-grids, it is not easy to align the sub-grids with the grid-line overlap areas, affecting the passivation contact performance of the cell. Summary of the Invention

[0003] To address the aforementioned technical problems, this application discloses a solar cell and photovoltaic module that makes it easier to align the printed sub-grids with the grid line overlap area.

[0004] In a first aspect, this application provides a solar cell, comprising: A silicon substrate, and a doped layer, a main gate, and a sub-gate disposed on the surface of the silicon substrate. The surface of the silicon substrate includes alternating first and second regions. The first region is a region for disposing of the sub-gate, and the first region is provided with the doped layer. The second region is a region without the doped layer. An overlapping structure is provided at the intersection of the main gate and the sub-gate. The width of the first region increases from the middle to the end of the first region.

[0005] In some embodiments of this application, the width of the end of the first region is W1, where 280μm≤W1≤350μm.

[0006] In some embodiments of this application, the overlapping structure includes an overlapping body and extensions connected to both ends of the overlapping body, wherein the boundary line between the overlapping body and the extensions corresponds to the end position of the width gradient of the first region.

[0007] In some embodiments of this application, the overlapping body includes a first segment and a second segment located at both ends of the first segment. The boundary line between the first segment and the second segment corresponds to the widest position of the first region. The width of the second segment is less than the width of the first segment, and the second segment is connected to the extension.

[0008] In some embodiments of this application, the length of the overlapping body is L1, where 1mm ≤ L1 ≤ 4mm.

[0009] In some embodiments of this application, the width of the extension is W2, where 70μm≤W2≤300μm.

[0010] In some embodiments of this application, the length of the first segment is L2, where 1μm≤L2≤1000μm; And / or, the width of the first segment is W3, 150μm≤W3≤400μm.

[0011] In some embodiments of this application, the length extension direction of the overlapping structure is the same as the length extension direction of the first region.

[0012] In some embodiments of this application, the widths of the first segment, the second segment, and the extension gradually narrow in the overlapping structure.

[0013] In some embodiments of this application, for any second region, the width of the second region decreases from the middle to the end of the second region.

[0014] In some embodiments of this application, the end of the second region has at least one recessed structure.

[0015] In some embodiments of this application, the width of the sub-gate is W4, where 10μm≤W4≤40μm; And / or, the width of the main gate is W5, 40μm≤W5≤60μm.

[0016] In some embodiments of this application, the second region accounts for 55% to 85% of the total area on the back of the solar cell.

[0017] Secondly, this application provides a photovoltaic module, which includes solar cells as described in the first aspect.

[0018] Compared with the prior art, this application has at least the following beneficial effects: This application provides a solar cell and a photovoltaic module, wherein the solar cell includes a silicon substrate and a doped layer, a main grid, and a sub-grid disposed on the surface of the silicon substrate. The surface of the silicon substrate includes alternating first and second regions, and an overlap structure is provided at the intersection of the main grid and the sub-grid. In this application, since the first region is used to house the sub-grid, as the width of the first region increases from its center to its ends, the second region adjacent to the first region correspondingly becomes larger as it approaches the center, resulting in a larger second region. Furthermore, the structure of the first region being wider at both ends and narrower in the middle, compared to the existing equal-width structure of the first region, not only increases the size of the second region but also provides a larger offset redundancy when the sub-grid is aligned with the grid line overlap area. This makes it easier to align the sub-grid with the grid line overlap area during grid overlap, preventing misalignment problems caused by printing errors. These two factors work together to ensure the printing alignment of the sub-grid and increase the Polytech area. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a partial schematic diagram of a solar cell in one embodiment of this application; Figure 2 This is a schematic diagram of the overlapping structure in one embodiment of this application; Figure 3 This is a partial schematic diagram of a solar cell according to another embodiment of this application; Figure 4 This is a partial schematic diagram of a solar cell in another embodiment of this application; Figure 5 This is a schematic diagram of the overlapping structure, main grid, and sub-grid in one embodiment of this application; Figure 6 This is a schematic diagram of the structure of a battery cell sample according to one embodiment of this application; Figure 7 This is a schematic diagram illustrating the preparation of patterned photoresist in one embodiment of this application; Figure 8 This is a schematic diagram of the battery cell structure in one embodiment of the HF etching process of this application; Figure 9 This is a schematic diagram of a solar cell structure with photoresist removed according to one embodiment of this application; Figure 10This is a schematic diagram of the battery cell structure during the etching process in one embodiment of this application; Figure 11 This is a schematic diagram of the battery cell structure in the HF cleaning process of one embodiment of this application; Figure 12 This is a schematic diagram of the battery cell structure in one embodiment of the present application, showing the process of preparing the passivation layer. Figure 13 This is a schematic diagram of the battery cell structure during the metallization process in one embodiment of this application; Figure 14 This is a partial scanning electron microscope image of a solar cell in one embodiment of this application.

[0021] Explanation of reference numerals in the attached figures: 1-Silicon substrate, 2-Front-side silicon oxide layer, 3-Overlap structure, 4-N-type doped layer, 5-Dielectric layer, 6-Inner extension layer, 7-Back-side coating, 9-Photoresist, 11-First region, 12-Second region, 13-Third region, 31-Overlap body, 32-Extension, 81-First side-side coating, 82-Second side-side coating, 91-Passivation layer, 92-Electrode, 121-Recessed structure, 311-First segment, 312-Second segment, 921-Main gate, 922-Sub-gate. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0024] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0025] Furthermore, the terms "installation," "setup," "equipped with," "connection," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0026] Furthermore, the terms "first," "second," etc., are primarily used to distinguish different devices, components, or parts (which may be the same or different in specific type and construction), and are not intended to indicate or imply the relative importance or quantity of the indicated devices, components, or parts. Unless otherwise stated, "a plurality of" means two or more.

[0027] The technical solution of this application will be further described below with reference to the embodiments and accompanying drawings.

[0028] In a first aspect, this application provides a solar cell comprising a silicon substrate and a doped layer, a main gate, and a sub-gate disposed on the surface of the silicon substrate, wherein the doped layer may be an N-type doped polycrystalline silicon layer. Figure 1 This is a partial schematic diagram of a solar cell according to one embodiment of this application, see reference. Figure 1 The surface of the silicon substrate includes alternating first regions 11 and second regions 12. The first region 11 is a region for setting the sub-gate, and the first region 11 is provided with the doped layer; the second region 12 is a region without the doped layer. (Reference) Figures 1-5 An overlapping structure 3 is provided at the intersection of the main gate 921 and the secondary gate 922. The width of the first region 11 increases from its center to its end. The width of the first region can gradually increase, and the edge of the first region can be a smooth curve or an irregular curve. Figure 1 Taking one of the first regions, 11, as an example, Figure 1The direction indicated by the dashed arrow in the first region 11 is from the middle to the end of the first region 11. The opening (i.e., the end) of the first region 11 is wider than its middle, meaning the middle of the first region 11 is narrower than its end. The first region of this application can be disposed on the back side of the solar cell, allowing for the formation of more second regions on the back side, thus reducing the relative area of ​​the poly layer and facilitating the reduction of parasitic absorption on the back side of the cell; alternatively, the first region can also be disposed on the front side of the solar cell, thereby forming heavily doped and lightly doped regions; or, the first region can be disposed on both the front and back sides of the solar cell. Furthermore, the solar cell also includes a third region 13, which is the region for setting the main grid, and the third region 13 also has a doped layer. It is understood that the length extension direction of the third region 13 is perpendicular to the length extension directions of the first region 11 and the second region 12.

[0029] The solar cells and photovoltaic modules provided in this application, since the first region is used to set the sub-grid, in this application, as the width of the first region increases from the middle to both ends, the corresponding second region next to the first region is larger as it gets closer to the middle. Furthermore, the structure of the first region being wider at both ends and narrower in the middle, compared to the existing equal-width structure of the first region, not only increases the size of the second region but also allows for a larger offset redundancy when the sub-grid is aligned with the grid line overlap area. This makes it easier to align the sub-grid with the grid line overlap area during grid overlap, preventing loose connections caused by misregistration. The combined effect of these two factors ensures accurate printing alignment of the sub-grid and increases the size of the Polytech area. Furthermore, the widened overlap structure can extend the flow window of the electrode paste (e.g., silver paste) during high-temperature sintering, avoiding mechanical overlap between the sub-grid silver paste and the main grid. The widened overlap structure also increases the robustness and stability of the connection between the sub-grid and the main grid, reducing the risk of breakage or poor contact at the connection point under stress, thereby improving the reliability and lifespan of the solar cell. Additionally, the centipede-like overlap structure increases the light-receiving area of ​​the solar cell, reduces the electrode's shading of light, increases lateral current collection, reduces contact resistance, disperses mechanical stress during main grid welding, and reduces the risk of microcracks in the solar cell. Therefore, the main-sub-grid overlap gradient structure design provided in this application solves the problem of misalignment during printing and increases the open area of ​​the Polytech region, ensuring double-sidedness, significantly extending the lifespan of the screen printing stencil, and reducing production costs. Moreover, this application greatly reduces parasitic absorption in the N-poly layer, improving the photoelectric conversion efficiency of the solar cell, and features low cost and simple process, significantly improving the yield of solar cells.

[0030] In one alternative implementation, refer to Figure 1The width of the end of the first region 11 is W1, where 280μm ≤ W1 ≤ 350μm. For example, W1 can be 280μm, 290μm, 300μm, 310μm, 320μm, or 350μm. In this application, the end of the first region refers to the point where the opening of the first region is at its maximum. W1 being within the above range allows for a larger offset redundancy when the sub-gate is aligned to the gate line overlap area, thus facilitating the printing alignment of the sub-gate.

[0031] In one alternative implementation, refer to Figure 2 and Figure 3 The overlapping structure 3 includes an overlapping body 31 and extensions 32 connected to both ends of the overlapping body 31. The width of the overlapping body is generally greater than the width of the extensions. The shape of the overlapping parts is adapted to the shape of the first region. That is, when the width of the first region increases from the middle to the two ends, the width of the overlapping structure decreases from the middle to the two ends. The overlapping structure is a conductive structure used to overlap the sub-busbar and the main busbar. Because its arrangement shape on the surface of the battery cell resembles centipede legs, it is also called a centipede leg structure. In one implementation, the width of the middle of the first region can be uniform until the width begins to change at the boundary line between the overlapping body and the extension. The boundary line between the overlapping body 31 and the extension 32 of the first region corresponds to the end position of the gradual width change of the first region 11, which is beneficial to forming more second regions. In another implementation, the width of the middle of the first region can be non-uniform, and its width begins to increase further at the boundary line between the extension and the overlapping body.

[0032] In one alternative implementation, refer to Figure 2 and Figure 3 The overlapping body 31 includes a first segment 311 and a second segment 312 located at both ends of the first segment 311. The boundary line between the first segment 311 and the second segment 312 corresponds to the widest position of the first region 11. The width of the second segment 312 is smaller than the width of the first segment 311, and the second segment 312 is connected to the extension 32. This facilitates the formation of more Polytech regions, thereby reducing parasitic absorption on the back of the solar cell.

[0033] In one alternative implementation, refer to Figure 2 The length of the overlapping body 31 is L1, where 1mm ≤ L1 ≤ 4mm. For example, L1 can be 1mm, 1.5mm, 2mm, 2.5mm, 3mm, or 4mm. A L1 within this range facilitates the formation of a tapered shape at both ends of the overlapping structure, allowing for complete printing within the L1 range, as the centipede-leg-shaped overlapping structure can be printed entirely.

[0034] In one alternative implementation, refer to Figure 2 The width of the extension 32 is W2, which is 70μm ≤ W2 ≤ 300μm. For example, W2 can be 70μm, 100μm, 150μm, 200μm, 250μm, or 300μm. Within the above range, W2 can reserve sufficient width redundancy for printing the sub-grid, avoiding misalignment of the sub-grid or ink flow into non-grid areas, thus ensuring the printing accuracy of the sub-grid.

[0035] In one alternative implementation, refer to Figure 2 The length of the first segment 311 is L2, where 1μm ≤ L2 ≤ 1000μm; and / or the width of the first segment 311 is W3, where 150μm ≤ W3 ≤ 400μm. For example, L2 can be 1μm, 10μm, 100μm, 500μm, or 1000μm. W3 can be 150μm, 200μm, 250μm, 300μm, 350μm, or 400μm. L2 is within the above range, thus providing sufficient width for main grid printing, preventing the main grid paste from flowing into the area where the second segment 312 is located, ensuring good overlap between the main and auxiliary grids, and facilitating main grid printing alignment. Within the above width range, the requirement that even if the main grid has a slight offset, it can still remain within the area where the first segment 311 is located can be met. Within the aforementioned range, W3 can retain sufficient width redundancy for the overlap of the main gate and the sub-gate, avoiding poor overlap due to excessive width, which could lead to poor soldering and broken gates, thus affecting current collection. Furthermore, the sub-gate still has a large offset redundancy when aligned with the gate line overlap area.

[0036] In one alternative implementation, refer to Figure 3 The length extension direction of the overlapping structure 3 is the same as the length extension direction of the first region 11. In this way, the overall shape of the overlapping part is more compatible with the shape of the first region, which is conducive to forming more second regions.

[0037] In one alternative implementation, refer to Figure 2 In the overlapping structure 3, the widths of the first segment 311, the second segment 312, and the extension 32 gradually narrow, so that the overall shape of the overlapping part is more compatible with the shape of the first region.

[0038] In one alternative implementation, refer to Figure 1 For any one of the second regions 12, the width of the second region 12 decreases from its center to its end. Figure 1 Taking one of the second regions, 12, as an example, Figure 1The direction indicated by the dashed arrow in the second region 12 is the direction from the middle to the end of the second region 12. The end of the second region 12 is narrower than the middle, so as to match the shape of the first region. That is, the middle of the second region 12 is wider. Compared with the existing equal-width structure of the second region, the second region is enlarged.

[0039] In one alternative implementation, refer to Figure 4 The end of the second region 12 has at least one recessed structure 121, which can be an irregularly shaped recessed structure, such as a recessed triangular structure, a recessed arc-shaped structure, etc.

[0040] In one alternative implementation, refer to Figure 5 The width of the sub-gate 922 is W4, 10μm≤W4≤40μm, and the height is 3μm~6μm; and / or, the width of the main gate 921 is W5, 40μm≤W5≤60μm. For example, W4 is 10μm, 15μm, 20μm, 25μm, 30μm, or 40μm. W5 is 40μm, 45μm, 50μm, 55μm, or 60μm. The width of the sub-gate is smaller than the width of the overlapping body and the extension in the overlapping structure, ensuring sufficient width for printing the sub-gate and avoiding misalignment of the sub-gate or ink flow into the non-gate area. In this application, the width of the sub-gate can be obtained by measuring the sub-gate located outside the overlapping area; the width of the main gate can be obtained by measuring the main gate located outside the overlapping area.

[0041] In one optional embodiment, the second region occupies 55% to 85% of the total area of ​​the back surface of the solar cell. For example, the second region occupies 55%, 60%, 65%, 70%, 75%, 80%, or 85% of the total area of ​​the back surface of the solar cell. Since the second region is the region without the doped layer, i.e., the Polytech region, a larger area of ​​the second region indicates the formation of more Polytech regions on the back surface, which is beneficial for reducing parasitic absorption on the back surface of the cell, thereby improving the photoelectric conversion efficiency of the solar cell.

[0042] Because the overlap between the main and sub-gates is widened, and the Polytech region is widened by removing as much polysilicon as possible, the gate line area becomes narrower. This often leads to increased alignment difficulties during sub-gate printing, making the sub-gate prone to misalignment. Furthermore, a centipede-like structure is printed at the overlap. If the sub-gate is designed based on the width of the middle of this structure, the gate line area will be too wide, resulting in an increased area of ​​the poly layer on the back side. This leads to a higher minority carrier recombination rate, limiting bifacial power generation performance and causing parasitic absorption, reducing weak light response. In this application, when the first region is formed on the back side of the solar cell, more Polytech regions can be formed on the back side, which helps reduce parasitic absorption on the back side of the cell and also improves the printing alignment accuracy of the sub-gate.

[0043] The material of the overlapping structure in this application can be the same as the material of the sub-gate, including but not limited to silver.

[0044] In this application, the percentage of the second region in the total area of ​​the back of the solar cell can be measured in the following way: the back of the solar cell after removing the main grid and the sub-grid is photographed to obtain an image of the back of the solar cell. Since there is a height difference between the open film area and the non-open film area, different colors can be displayed after scanning and processing with a zeta-3D microscope, and the first and third regions (i.e., the main grid and fine grid line area) and the second region (i.e., the Polytech area) can be identified. The area of ​​the open film and the non-open film area is obtained by software analysis, thereby determining the percentage of the second region in the total area of ​​the back of the solar cell.

[0045] This application does not impose any particular limitation on the formation method of the first and second regions mentioned above, as long as the purpose of this invention can be achieved. In one optional implementation, taking the TOPCon solar cell as an example, the fabrication method of the solar cell includes the following steps: Step A, Reference Figure 6 A solar cell sample with an N-type doped layer (N-poly) and after annealing / phosphorus diffusion is provided. The solar cell sample includes a silicon substrate 1. On the back side of the silicon substrate 1, an inner diffusion layer 6, a dielectric layer 5, an N-type doped layer 4, a back side coating layer 7 (PSG), a first side coating layer 81 (PSG), and a second side coating layer 82 (poly / tunneling silicon oxide / inner diffusion layer composition) are formed sequentially. On the front side of the silicon substrate 1, a front side silicon oxide layer 2 (PSG) is formed. Step B, Reference Figure 7 A patterned photoresist 9 corresponding to the pattern formed during metallization is coated around the surface of the coating layer 7 on the back side of the battery cell sample. The shape of the patterned photoresist can be: a pattern with a gradient width is formed at the designed overlap position, that is, a shape designed to form the first region of this application, and then cured. Step C, Reference Figure 8 The oxide layer of the unpatterned photoresist-masked area, including the PSG in the non-photoresist area on the back, the PSG on the side, and the BSG of partial thickness on the front, is etched by hydrofluoric acid (HF) to form a patterned back-side coating 7, i.e., a patterned PSG area, on the N-type doped layer 4. Step D, Reference Figure 9 Clean the photoresist with an alkaline solution to expose the patterned back-side coating 7; Step E, Reference Figure 10 The regions without silicon oxide (BSG or PSG) are etched using an alkaline solution to remove the corresponding N-type doped layer, dielectric layer, and inner extension layer. Step F, Reference Figure 11Hydrofluoric acid is used to clean and remove all oxide layers from the surface of the battery cell sample, in preparation for the deposition of a passivation film. Step G, Reference Figure 12 A passivation layer 91 is prepared on the sample surface. The material of the passivation layer includes, but is not limited to, at least one of aluminum oxide, silicon nitride, silicon oxynitride, and silicon oxide. The passivation layer may have a multilayer structure. Step H, Reference Figure 13 Metallization: Electrode 92 is fabricated, including the fabrication of a front electrode and a back electrode, wherein the sub-gate of the back electrode is fabricated in a patterned N-type doped layer region to obtain a solar cell.

[0046] The above fabrication process uses photoresist as a mask. Specifically, the photoresist is used to mask the areas where the first region (i.e., the metal patterned area) is formed, and then wet etching is used to remove the areas not masked by photoresist, thereby removing the unwanted poly layer in one step. In this fabrication process, photoresist is printed on the metal patterned area, and HF etching is performed on the entire non-photoresist area. This effectively removes the poly layer at the edges and sides of the cell, improving edge passivation and leakage current reduction. Furthermore, cleaning can be integrated into the RCA (Removal of PSG) cleaning process, eliminating the need for the traditional single-sided HF cleaning in the PSG removal process, thus simplifying the process and reducing manufacturing costs.

[0047] Figure 14 This is a partial microscope image of a solar cell in one embodiment of this application, where the dark black area is the first region and the gray-white area is the second region.

[0048] The dielectric layer of this application may include at least one of various dielectric materials, such as silicon oxide, magnesium fluoride, amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide. Specifically, the dielectric layer may be composed of a silicon oxide layer containing silicon oxide. This is because the silicon oxide layer has excellent passivation properties, can minimize the recombination loss of minority carriers on the semiconductor substrate surface, and is a thin film with excellent durability for subsequent high-temperature processes. To better provide interface passivation for the substrate, the thickness of the dielectric layer can be 0.1 nm to 5 nm. For example, the thickness of the dielectric layer can be 0.1 nm, 0.5 nm, 1 nm, 1.5 nm, 2 nm, 3 nm, 4 nm, or 5 nm, etc.; however, this application is not limited to these values, and the thickness of the dielectric layer can have various values. The dielectric layer acts as a barrier for electrons and holes and can be combined with the polycrystalline silicon layer to prevent minority carriers from passing through. The dielectric layer can also act as a pinhole channel, allowing charge carriers in the solar cell to move freely. The selective passage of majority charge carriers is generated by the heavily doped polycrystalline silicon, which helps to reduce the recombination loss of minority charge carriers.

[0049] In the fabrication of the front and back electrodes, electrode pastes are screen-printed onto the front and back sides of the solar cell, respectively, and then sintered to obtain the front and back electrodes. This application does not impose any particular limitations on the materials used for the front and back electrodes, including but not limited to silver.

[0050] Secondly, this application provides a photovoltaic module, which includes solar cells as described in the first aspect.

[0051] This application also provides a photovoltaic module for converting received light energy into electrical energy and transmitting it to an external load. The photovoltaic module includes: at least one cell string, which is composed of multiple solar cells connected together; an encapsulating film for covering the surface of the cell string; and a cover plate for covering the surface of the encapsulating film facing away from the cell string.

[0052] The above provides a detailed description of a solar cell and photovoltaic module disclosed in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core inventive points of the embodiments of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A solar cell, characterized in that, include: A silicon substrate, and a doped layer, a main gate, and a sub-gate disposed on the surface of the silicon substrate. The surface of the silicon substrate includes alternating first and second regions. The first region is a region for disposing of the sub-gate, and the first region is provided with the doped layer. The second region is a region without the doped layer. An overlapping structure is provided at the intersection of the main gate and the sub-gate, wherein: The width of the first region increases from the middle to the end of the first region.

2. The solar cell according to claim 1, characterized in that, The width of the end of the first region is W1, where 280μm≤W1≤350μm.

3. The solar cell according to claim 1, characterized in that, The overlapping structure includes an overlapping body and extensions connected to both ends of the overlapping body. The boundary line between the overlapping body and the extensions corresponds to the end position of the width gradient of the first region.

4. The solar cell according to claim 3, characterized in that, The overlapping body includes a first segment and a second segment located at both ends of the first segment. The dividing line between the first segment and the second segment corresponds to the widest position of the first region. The width of the second segment is less than the width of the first segment, and the second segment is connected to the extension.

5. The solar cell according to claim 3, characterized in that, The length of the overlapping body is L1, where 1mm ≤ L1 ≤ 4mm.

6. The solar cell according to claim 3, characterized in that, The width of the extension is W2, where 70μm≤W2≤300μm.

7. The solar cell according to claim 4, characterized in that, The length of the first segment is L2, where 1μm≤L2≤1000μm; And / or, the width of the first segment is W3, 150μm≤W3≤400μm.

8. The solar cell according to claim 3, characterized in that, The length extension direction of the overlapping structure is the same as the length extension direction of the first region.

9. The solar cell according to claim 4, characterized in that, In the overlapping structure, the widths of the first segment, the second segment, and the extension gradually narrow.

10. The solar cell according to claim 1, characterized in that, For any of the second regions, the width of the second region decreases from the middle to the end of the second region.

11. The solar cell according to claim 1, characterized in that, The end of the second region has at least one recessed structure.

12. The solar cell according to claim 1, characterized in that, The width of the sub-gate is W4, where 10μm≤W4≤40μm; And / or, the width of the main gate is W5, 40μm≤W5≤60μm.

13. The solar cell according to claim 1, characterized in that, The second region accounts for 55% to 85% of the total area on the back of the solar cell.

14. A photovoltaic module, characterized in that, The photovoltaic module includes the solar cell according to any one of claims 1 to 13.

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