Light emitting display device

Abstract

A light-emitting display device according to one or more embodiments of the present invention may include: a substrate comprising a plurality of sub-pixels, the plurality of sub-pixels having light-emitting regions and non-light-emitting regions; data lines and gate lines disposed in the non-light-emitting regions on the substrate and intersecting each other; at least one insulating layer disposed on the data lines and the gate lines; and a color filter disposed on the at least one insulating layer and corresponding to at least one sub-pixel of the plurality of sub-pixels, wherein one or more of the plurality of sub-pixels may include a low-reflectivity pattern overlapping the light-emitting regions.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit and priority of Korean Patent Application No. 10-2024-0197782, filed on December 26, 2024, which is incorporated herein by reference in its entirety for all purposes. Technical Field

[0003] This invention relates to a light-emitting display device. Background Technology

[0004] With the advancement of the information age, the demand for display devices for displaying images has increased in various forms. As a result, various types of display devices have recently been used, such as liquid crystal display (LCD) devices, organic light-emitting diode (OLED) devices, LED display devices, and quantum dot (QD) display devices.

[0005] Among display devices, organic light-emitting display devices are self-emissive. In an organic light-emitting display device, holes and electrons are injected into the light-emitting layer from an anode for hole injection and a cathode for electron injection, and the injected holes and electrons combine with each other. Here, when the excitons formed by the holes and electrons fall from the excited state to the ground state, the organic light-emitting display device can emit light and display an image.

[0006] This type of organic light-emitting display device primarily uses polarizers on the display surface of the panel to reduce external light reflection. However, when an organic light-emitting display device uses polarizers, the transmittance decreases, thereby reducing panel efficiency and increasing power consumption. Summary of the Invention

[0007] One or more embodiments of the present invention may provide a light-emitting display device that can reduce reflectivity and improve light efficiency with a polarizer-less structure that does not use a polarizer.

[0008] One or more embodiments of the present invention may provide a light-emitting display device that can reduce reflectivity, improve light efficiency, and improve display image quality by optimizing the cell reflectance of the light-emitting portion to suit a polarizer-free structure while maintaining the area of ​​the light-emitting portion.

[0009] Additional advantages and features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon studying the following, or may be learned from practice of the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures specifically pointed out in the written description, its claims, and the accompanying drawings.

[0010] A light-emitting display device according to one or more embodiments of the present invention may include: a substrate comprising a plurality of sub-pixels, the plurality of sub-pixels having light-emitting regions and non-light-emitting regions; data lines and gate lines disposed in the non-light-emitting regions on the substrate and intersecting each other; at least one insulating layer disposed on the data lines and the gate lines; and a color filter disposed on the at least one insulating layer and corresponding to at least one sub-pixel of the plurality of sub-pixels, the plurality of sub-pixels comprising a low-reflectivity pattern overlapping the light-emitting regions.

[0011] According to one or more embodiments of the present invention, a light-emitting display device can be provided that can reduce reflectivity and improve light efficiency with a polarizer-free structure that does not use a polarizer.

[0012] According to one or more embodiments of the present invention, a light-emitting display device can be provided that can reduce reflectivity, improve light efficiency, and improve the quality of the displayed image by optimizing the unit reflectivity of the light-emitting portion to suit a polarizer-free structure while maintaining the area of ​​the light-emitting portion.

[0013] According to one or more embodiments of the present invention, a light-emitting display device can optimize the reflectivity of the unit while maintaining the area of ​​the light-emitting portion, even with a polarizer-free structure that does not use a polarizer. Thus, the light-emitting display device can reduce reflectivity, increase light efficiency, and improve the quality of the displayed image. Furthermore, by standardizing the materials used in the light-emitting display device, costs can be reduced, power consumption can be reduced, and reliability and display quality can be improved, thereby reducing production energy and realizing environmental, social, and governance (ESG) benefits.

[0014] The effects of the present invention are not limited to those described herein, but other effects not described herein will be clearly understood by those skilled in the art from the following description.

[0015] The details of the invention described in the technical problems, technical solutions and beneficial effects do not specify the essential features of the claims; therefore, the scope of the claims is not limited by the details described in the detailed description of the invention. Attached Figure Description

[0016] The accompanying drawings, which provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate various aspects and embodiments of the invention and, together with the description, serve to explain the principles and examples of the invention.

[0017] Figure 1 A light-emitting display device according to an embodiment of the present invention is shown.

[0018] Figure 2This is a circuit diagram showing a sub-pixel of a light-emitting display device according to an embodiment of the present invention.

[0019] Figure 3 This illustrates a plurality of sub-pixels in a display panel according to an embodiment of the present invention.

[0020] Figure 4 It is along the embodiment of the present invention Figure 3 The cross-sectional view taken from line I-I'.

[0021] Figure 5 This illustrates a plurality of sub-pixels in a display panel according to an embodiment of the present invention.

[0022] Figure 6 It is according to one embodiment of the present invention. Figure 5 The cross-sectional view taken from line II-II'.

[0023] Figure 7 A plurality of sub-pixels in a display panel according to another embodiment of the present invention are shown.

[0024] Figure 8 It is along another embodiment of the present invention Figure 7 The cross-sectional view taken from line III-III'.

[0025] Figure 9 A plurality of sub-pixels in a display panel according to another embodiment of the present invention are shown.

[0026] Figure 10 It is along another embodiment of the present invention Figure 9 A cross-sectional view taken from line IV-IV'.

[0027] Figure 11 A plurality of sub-pixels in a display panel according to another embodiment of the present invention are shown.

[0028] Figure 12 It is along another embodiment of the present invention Figure 11 A cross-sectional view taken from line V-V'.

[0029] Figure 13 A plurality of sub-pixels in a display panel according to another embodiment of the present invention are shown.

[0030] Figure 14 It is along another embodiment of the present invention Figure 13 The cross-sectional view taken from line VI-VI'.

[0031] Figure 15 A plurality of sub-pixels in a display panel according to another embodiment of the present invention are shown.

[0032] Figure 16 It is along another embodiment of the present invention Figure 15 The cross-sectional view taken from line VII-VII'.

[0033] Throughout the accompanying drawings and detailed description, unless otherwise described, the same reference numerals shall be understood to refer to the same elements, features, and structures. For purposes of clarity, illustration, and / or convenience, the dimensions, lengths, and thicknesses of layers, regions, and elements, and their depictions, may be exaggerated. Detailed Implementation

[0034] The advantages and features of this invention, as well as its implementation methods, will be explained by referring to the embodiments described in the accompanying drawings. However, this invention may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are examples provided so that the disclosure of this invention will be thorough and complete, and to assist those skilled in the art in understanding the inventive concept, rather than limiting the scope of protection of this invention.

[0035] The shapes (e.g., size, length, width, height, thickness, position, radius, diameter, and area), dimensions, ratios, angles, quantities, etc., disclosed herein (including those shown in the accompanying drawings) are merely examples, and therefore the invention is not limited to the details shown. Any embodiment described herein as "examples" should not be construed as superior or advantageous over other embodiments. However, it should be noted that the relative sizes of the components shown in the accompanying drawings are part of the invention.

[0036] When terms such as "comprising," "having," "including," "containing," or "constituting" are used to refer to one or more elements, one or more other elements may be added unless terms such as "only" are used. The terminology used in this invention is for describing exemplary embodiments only and is not intended to limit the scope of the invention. Singular terms may include plural forms unless the context clearly indicates otherwise.

[0037] When interpreting elements, they are interpreted as including error regions, even though they are not explicitly described.

[0038] When describing positional relationships, for example, when the positional order is described as "on," "above," "below," "lower," and "next to," situations in which there is no contact between them can be included, unless "exactly" or "directly" is used.

[0039] When it is mentioned that the first element is "above" the second element, it does not mean that the first element is actually located above the second element in the drawing. The upper and lower parts of the object in question can change depending on the orientation of the object. Therefore, the case of the first element being "above" the second element in the drawing or in the actual configuration includes both the case of the first element being "below" the second element and the case of the first element being "above" the second element.

[0040] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous situations may be included unless “exactly” or “directly” is used.

[0041] It should be understood that although the terms "first," "second," etc., may be used in this document to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0042] In describing the elements of the present invention, the terms “first,” “second,” “A,” “B,” “(a),” “(b),” etc., may be used. These terms are intended to identify the corresponding element from the other elements and are not intended to limit the nature, basis, order, or number of the elements.

[0043] For expressions such as “connecting,” “joining,” “attaching,” “adhering,” etc., of one element, the element may be directly connected, joined, attached, adhered, etc., to another element, or indirectly connected, joined, attached, adhered, etc., provided that one or more intermediate elements are provided or inserted between the elements, unless otherwise specified.

[0044] The expression "overlapping" of one element with another element can mean that the element can not only directly contact or overlap with the other element, but also indirectly overlap with the other element when one or more intermediate elements are set or inserted between the elements, unless otherwise specified.

[0045] The term “at least one” should be understood to include any and all combinations of one or more of the associated listed items. For example, “at least one of the first element, the second element, and the third element” may include all combinations of two or more elements selected from the first element, the second element, and the third element, as well as each of the first element, the second element, and the third element.

[0046] Features of various embodiments of the present invention may be combined or integrated with each other in part or in whole, may be technically related to each other, and may be interoperable, connected, or driven together in different ways. Embodiments of the present invention may be implemented or carried out independently of each other, or may be implemented or carried out together in a mutually dependent or related relationship. In one or more aspects, components of each device according to various embodiments of the present invention are operatively engaged and configured.

[0047] In the following description, various exemplary embodiments of the invention are described in detail with reference to the accompanying drawings. Regarding the reference numerals for elements in each drawing, the same elements may be shown in other drawings, and similar reference numerals may refer to similar elements, unless otherwise stated. The same or similar elements may be represented by the same reference numerals, even if they are shown in different drawings. Furthermore, for ease of description, the dimensions, sizes, dimensions, and thicknesses of each element shown in the drawings may differ from the actual dimensions, sizes, dimensions, and thicknesses; therefore, embodiments of the invention are not limited to the dimensions, sizes, dimensions, and thicknesses shown in the drawings.

[0048] Figure 1 A light-emitting display device according to an embodiment of the present invention is shown.

[0049] In the following text, the X-axis represents the direction parallel to the scan lines, the Y-axis represents the direction parallel to the data lines, and the Z-axis represents the height direction of the light-emitting display device.

[0050] The light-emitting display device according to an embodiment of the present invention is implemented as an organic light-emitting display device, but it can also be implemented as a liquid crystal display device, a quantum dot light-emitting diode display device, or an electrophoretic display device.

[0051] Reference Figure 1 According to an embodiment of the present invention, a light-emitting display device may include a display panel 110, a scan driver 120 (or gate driver) built into the display panel 110, a data driver 130 connected to the display panel 110, a timing controller 160 for controlling the scan driver 120 and the data driver 130, and a power supply circuit 170.

[0052] Display panel 110 includes a display area DA and a non-display area NDA surrounding the display area DA. Display panel 110 includes pixels P disposed in the display area DA to display images. Each pixel P may include multiple subpixels SP. The structure of the subpixels SP can vary depending on the type of light-emitting display device. For example, subpixels SP can be formed as top-emitting, bottom-emitting, or double-sided-emitting types, depending on their structure. Subpixels SP represent units capable of forming a specific type of color filter or capable of emitting light of a color without forming a color filter. Depending on the light-emitting characteristics, subpixels SP may have one or more different light-emitting areas. For example, multiple subpixels SP can be arranged in a stripe type or a quadrilateral type, but embodiments of the present invention are not limited thereto. The color type, arrangement type, and order of the subpixels SP can be configured in various forms depending on the light-emitting characteristics, device lifespan, device specifications, etc.

[0053] Display panel 110 may include data lines DL and scan lines SL (or gate lines) connected to sub-pixels SP. Data lines DL may be arranged to intersect with scan lines SL. Each sub-pixel SP of display panel 110 may be connected to any one of the data lines DL and any one of the scan lines SL. Data lines DL may provide data voltage from data driver 130 to each sub-pixel SP. Scan lines SL may provide scan signals from scan driver 120 to each sub-pixel SP.

[0054] Each sub-pixel SP is turned on by a scan signal. When the data voltage of the data line DL is supplied to the gate of the driving transistor, the light-emitting element can emit light according to the drain-source current of the driving transistor. The scan driver 120 can receive a scan control signal GCS from the timing controller 160. The scan driver 120 can provide a scan signal or a light emission control signal to the scan line SL by using the scan control signal GCS.

[0055] The scan driver 120 can be configured as an in-panel gate driver (GIP) in a non-display area NDA located outside one or both sides of the display area DA. Alternatively, the scan driver 120 can be manufactured as a driver chip, mounted on a flexible film, and attached to the non-display area NDA located outside one or both sides of the display area DA via a tape auto-bonding (TAB) method.

[0056] Data driver 130 receives digital video data DATA and data control signal DCS from timing controller 160. Data driver 130 converts digital video data DATA into analog positive / negative data voltages using data control signal DCS and provides the analog positive / negative data voltages to data line DL.

[0057] The timing controller 160 receives digital video data DATA and timing signals from the host system. Timing signals may include a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock. The vertical sync signal defines one frame period. The horizontal sync signal defines a horizontal time period required to supply data voltage to the pixels of a horizontal row of the display panel 110. The data enable signal defines the time period for valid input data. The dot clock is a signal that repeats for a predetermined short period.

[0058] The timing controller 160 can generate a data control signal DCS for controlling the operating timing of the data driver 130 and a scan control signal GCS for controlling the operating timing of the scan driver 120 based on the timing signals. The timing controller 160 can output the scan control signal GCS to the scan driver 120 to control the scan driver 120, and output digital video data DATA and the data control signal DCS to the data driver 130 to control the data driver 130.

[0059] The power supply circuit 170 can generate and provide multiple drive voltages required for the operation of all circuit configurations of the light-emitting display device by using an input voltage. The power supply circuit 170 can generate a first power supply voltage EVDD (or pixel power supply voltage), a second power supply voltage EVSS (or common power supply voltage), and an initialization voltage Vref (or reference voltage, see...). Figure 2 The generated voltage is supplied to the display panel 110. The power supply circuit 170 can generate and provide various drive voltages required for the operation of the scan driver 120, the data driver 130, and the timing controller 160.

[0060] Figure 2 This is a circuit diagram showing a sub-pixel of a light-emitting display device according to an embodiment of the present invention.

[0061] Reference Figure 2 Each pixel P comprises multiple sub-pixels SP that make up the unit pixel. Each of the multiple sub-pixels SP contains a pixel circuit with a 3T (transistor) 1C (capacitor) and a light-emitting device ED. The 3T (transistor) 1C (capacitor) includes, but is not limited to, a driving transistor DR, a first switching transistor TR1, a second switching transistor TR2, and a storage capacitor Cst. Each sub-pixel SP may also include a compensation circuit. In this case, the sub-pixel SP can have various structures, such as 3T2C, 4T1C, 4T2C, 5T1C, 5T2C, 6T1C, 6T2C, 7T1C, and 7T2C.

[0062] At least one thin-film transistor DR, TR1, and TR2 in each sub-pixel SP may include a gate, a source, and a drain. Since the source and drain can change rather than be fixed depending on the direction of the voltage and current applied to the gate, either the source or the drain may be represented as a first electrode, and the other as a second electrode. At least one transistor DR, TR1, and TR2 may be made of at least one of polycrystalline silicon semiconductor, amorphous silicon semiconductor, and oxide semiconductor. Transistors DR, TR1, and TR2 may be P-type or N-type, or P-type and N-type may be used interchangeably.

[0063] The driving transistor DR corresponds to a transistor used to drive a light-emitting device ED, and the driving transistor DR includes: a first node N1 to which a data voltage Vdata is applied; a second node N2 connected to the pixel electrode (first electrode or anode) of the light-emitting device ED; and a third node N3 connected to the first power supply voltage line VDDL (or pixel power supply voltage line) and supplied with the first power supply voltage EVDD (or pixel power supply voltage). For example, the driving transistor DR can generate a data current based on the first power supply voltage EVDD provided from the first power supply voltage line VDDL, and can provide the data current to the first electrode of the light-emitting device ED.

[0064] The first switching transistor TR1 can be used to supply the data voltage Vdata provided from the data line DL to the first node N1 of the driving transistor DR. The second switching transistor TR2 can be used to supply the reference voltage Vref provided from the reference line REFL to the second node N2 of the driving transistor DR, or can output the voltage of the second node N2 of the driving transistor DR. A storage capacitor Cst can be connected between the first node N1 and the second node N2 of the driving transistor DR. The storage capacitor Cst can be used to hold the data voltage Vdata provided to the driving transistor DR for one frame, but embodiments of the present invention are not limited thereto.

[0065] The light-emitting device (ED) may include: a pixel electrode (first electrode or anode) connected to a second node N2 of the driving transistor DR; and a common electrode (second electrode or cathode) connected to a second power supply voltage line VSSL. The ED emits light through a light-emitting layer (or organic light-emitting layer) between the first and second electrodes in response to a driving current generated by the driving transistor DR. The pixel electrode of the ED may be an independent electrode for each light-emitting device, and the common electrode and light-emitting layer may be a common layer shared by the entire light-emitting device; however, embodiments of the present invention are not limited thereto.

[0066] Figure 3 This illustrates a plurality of sub-pixels in a display panel according to an embodiment of the present invention. Figure 4 It is along the embodiment of the present invention Figure 3The cross-sectional view taken from line I-I'.

[0067] Reference Figure 3 and Figure 4 The display panel 110 according to an embodiment of the present invention can be configured as a top-emitting type, a bottom-emitting type, or a dual-sided-emitting type. For example, the display panel 110 can be implemented as a bottom-emitting type.

[0068] The display panel 110 according to an embodiment of the present invention may include: a plurality of sub-pixels SP1, SP2, SP3 and SP4; a plurality of data lines DL1, DL2, DL3 and DL4; at least one scan line SL (or gate line); a first power supply voltage line VDDL; pixel circuits CA1, CA2, CA3 and CA4; and at least one color filter CF1, CF3 and CF4.

[0069] Multiple subpixels SP1, SP2, SP3, and SP4 can be unit pixels of different colors. These subpixels can be arranged in a stripe pattern along a first direction (or the X-axis direction) or a second direction (or the Y-axis direction). For example, multiple subpixels SP1, SP2, SP3, and SP4 can be arranged along the first direction (or the X-axis direction), but are not limited to this. The arrangement order or type of the multiple subpixels can be varied.

[0070] Multiple sub-pixels SP1, SP2, SP3, and SP4 may include light-emitting areas EA1, EA2, EA3, and EA4 in which light-emitting devices ED for emitting light are disposed, and a non-light-emitting area NEA. For example, the non-light-emitting area NEA may include: a first non-light-emitting area NEA1 in which pixel circuits CA1, CA2, CA3, and CA4 are disposed; and a second non-light-emitting area NEA2 between adjacent sub-pixels SP1, SP2, SP3, and SP4. For example, at least one scan line SL extending in a first direction (or the X-axis direction) may be disposed in the first non-light-emitting area NEA1, and multiple data lines DL1, DL2, DL3, and DL4 extending in a second direction (or the Y-axis direction) and a first power supply voltage line VDDL may be disposed in the second non-light-emitting area NEA2.

[0071] The light-emitting regions EA1, EA2, EA3, and EA4 may correspond to the light-emitting areas in each sub-pixel SP1, SP2, SP3, and SP4. For example, each sub-pixel SP1, SP2, SP3, and SP4 may include a light-emitting device ED, which includes a pixel electrode AE, a light-emitting layer EL, and a common electrode CE, and the light-emitting regions EA1, EA2, EA3, and EA4 may overlap with the light-emitting device ED of each sub-pixel SP1, SP2, SP3, and SP4. The light-emitting regions EA1, EA2, EA3, and EA4 may include first to fourth light-emitting regions EA1, EA2, EA3, and EA4 that emit light of different colors. For example, the first to fourth light-emitting regions EA1, EA2, EA3, and EA4 may be the opening areas of the pixel electrode AE ​​defined by the embankment BA.

[0072] The first to fourth light-emitting areas EA1, EA2, EA3, and EA4 can emit light of different colors through at least one color filter CF1, CF3, and CF4. For example, at least one color filter CF1, CF3, and CF4 can transmit light of different colors. For example, at least one color filter CF1, CF3, and CF4 can be formed of organic materials that transmit light of different colors. At least one color filter CF1, CF3, and CF4 may include a first color filter CF1 that transmits red light, a third color filter CF3 that transmits blue light, and a fourth color filter CF4 that transmits green light. For example, the first light-emitting area EA1 of the first sub-pixel SP1 can emit red light through the first color filter CF1, the second light-emitting area EA2 of the second sub-pixel SP2 can emit white light without using a color filter or through a color filter that transmits white light, the third light-emitting area EA3 of the third sub-pixel SP3 can emit blue light through the third color filter CF3, and the fourth light-emitting area EA4 of the fourth sub-pixel SP4 can emit green light through the fourth color filter CF4, but the embodiments of the present invention are not limited thereto.

[0073] At least one scan line SL (or gate line) may be configured to overlap with a first non-light-emitting region NEA1 in which pixel circuits CA1, CA2, CA3, and CA4 are disposed. The at least one scan line SL may extend in a first direction (or the X-axis direction) to pass through the first non-light-emitting region NEA1. The at least one scan line SL may provide scan signals to at least one thin-film transistor TR1 and TR2 included in the pixel circuits CA1, CA2, CA3, and CA4. For example, the at least one scan line SL may be formed in the same layer with the gates of at least one thin-film transistor DR, TR1, and TR2 disposed in the pixel circuits CA1, CA2, CA3, and CA4 using the same material. For example, the at least one scan line SL may include a low-reflectivity material layer to reduce external light reflection.

[0074] Multiple data lines DL1, DL2, DL3, and DL4 can be configured to correspond to each sub-pixel SP1, SP2, SP3, and SP4. These data lines DL1, DL2, DL3, and DL4 can overlap with the second non-emitting area NEA2 between adjacent sub-pixels SP1, SP2, SP3, and SP4. The data lines DL1, DL2, DL3, and DL4 can extend in a second direction (or the Y-axis direction) within the second non-emitting area NEA2. The data lines DL1, DL2, DL3, and DL4 can be positioned to the left or right of each sub-pixel SP1, SP2, SP3, and SP4, but embodiments of the present invention are not limited thereto. For example, a first data line DL1 may be disposed to the left of a first sub-pixel SP1 to provide data voltage to the first sub-pixel SP1, a second data line DL2 may be disposed to the left of a second sub-pixel SP2 to provide data voltage to the second sub-pixel SP2, a third data line DL3 may be disposed to the left of a third sub-pixel SP3 to provide data voltage to the third sub-pixel SP3, and a fourth data line DL4 may be disposed to the left of a fourth sub-pixel SP4 to provide data voltage to the fourth sub-pixel SP4. For example, each data line DL1, DL2, DL3, and DL4 may be formed in the same layer using the same material as the light-blocking layer disposed in the pixel circuit. Each data line DL1, DL2, DL3, and DL4 may include a low-reflectivity material layer to reduce external light reflection.

[0075] The first power supply voltage line VDDL can be configured to correspond to multiple sub-pixels SP1, SP2, SP3, and SP4. The first power supply voltage line VDDL can be configured to overlap with the second non-emitting area NEA2 on the left or right side of the multiple sub-pixels SP1, SP2, SP3, and SP4. Optionally, the first power supply voltage line VDDL can be disposed within the multiple sub-pixels SP1, SP2, SP3, and SP4. For example, the first power supply voltage line VDDL can be configured to overlap with the second non-emitting area NEA2 between the second sub-pixel SP2 and the third sub-pixel SP3, but embodiments of the present invention are not limited thereto. The first power supply voltage line VDDL can be formed in the same layer with the multiple data lines DL1, DL2, DL3, and DL4 using the same material, but embodiments of the present invention are not limited thereto.

[0076] Reference Figure 4 The display panel 110 according to an embodiment of the present invention may include: a substrate 111; multiple data lines DL1, DL2, DL3 and DL4; a first power supply voltage line VDDL; at least one scan line SL; at least one insulating layer BF, GI and PAS; at least one color filter CF1, CF3 and CF4; a planarization layer OC; a pixel electrode AE; a light-emitting layer EL and a common electrode CE. For example, the display panel 110 may also include a dam BA disposed on the planarization layer OC and the pixel electrode AE.

[0077] At least one signal line and one power supply voltage line may be disposed on the substrate 111. For example, multiple data lines DL1, DL2, DL3, and DL4, as well as a first power supply voltage line VDDL, may be disposed on the substrate 111. For example, the multiple data lines DL1, DL2, DL3, and DL4, as well as the first power supply voltage line VDDL, may be formed in the same layer of the same material as the light-blocking layers disposed in the pixel circuits CA1, CA2, CA3, and CA4.

[0078] The multiple data lines DL1, DL2, DL3, and DL4 disposed at the lowest portion of the substrate 111, as well as the first power supply voltage line VDDL, may include a low-reflectivity material layer for reducing external light reflection, and may include a conductive metal layer M1 and a low-reflectivity material layer LM1 located below the metal layer M1. For example, the metal layer M1 may be configured as a single layer or multiple layers of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), tungsten (W), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and their alloys, but embodiments of the present invention are not limited thereto. The low-reflectivity material layer LM1 may be a metal layer with excellent low-reflectivity characteristics, and may be composed of molybdenum-titanium (MoTi) or molybdenum (Mo), or may include metal oxides or alloy oxides. For example, the low-reflectivity material layer LM1 may contain copper oxide (CuOx), nickel oxide (NiOx), molybdenum oxide (MoOx), or tungsten oxide (WOx), but embodiments of the present invention are not limited thereto. For example, multiple data lines DL1, DL2, DL3 and DL4, as well as the first power supply voltage line VDDL, can be a double-layer structure including copper Cu and molybdenum-titanium MoTi, or copper Cu and metal oxide.

[0079] At least one insulating layer BF, GI, and PAS may be disposed on substrate 111. The at least one insulating layer BF, GI, and PAS may include a buffer layer BF, a gate insulating layer GI, and a passivation layer PAS. For example, the buffer layer BF may be disposed on substrate 111. The buffer layer BF may be configured to cover at least one signal line and power supply voltage line, as well as a light-blocking layer, on substrate 111. The gate insulating layer GI, the passivation layer PAS, and at least one thin-film transistor may be disposed on the buffer layer BF. For example, the at least one insulating layer BF, GI, and PAS may be configured as a single layer or multiple layers, comprising inorganic insulating materials such as silicon oxide (SiOx), silicon nitride (SiNx), or aluminum oxide (Al2O3), but embodiments of the present invention are not limited thereto.

[0080] At least one scan line SL (or gate line) may be disposed on the gate insulating layer GI. At least one scan line SL may be disposed on the gate insulating layer GI and may be patterned together with the gate insulating layer GI. At least one scan line SL may be disposed in the same layer with the gate of at least one thin-film transistor disposed in pixel circuits CA1, CA2, CA3 and CA4, and may be made of the same material.

[0081] At least one scan line SL may include a low-reflectivity material layer for reducing external light reflection. For example, at least one scan line SL may include a conductive metal layer M2 and a low-reflectivity material layer LM2 located beneath the metal layer M2. For example, the metal layer M2 may be configured as a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), tungsten (W), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and their alloys, but embodiments of the present invention are not limited thereto. The low-reflectivity material layer LM2 may be a metal layer with excellent low-reflectivity properties and may be configured as molybdenum-titanium (MoTi) or molybdenum (Mo), or may include metal oxides or alloy oxides. For example, the low-reflectivity material layer LM2 may contain copper oxide (CuOx), nickel oxide (NiOx), molybdenum oxide (MoOx), or tungsten oxide (WOx), but embodiments of the present invention are not limited thereto. For example, at least one scan line SL may be configured as a bilayer structure including copper (Cu) and molybdenum-titanium (MoTi), or copper (Cu) and metal oxides.

[0082] A passivation layer PAS can be disposed on at least one scan line SL, and at least one color filter CF1, CF3, and CF4 can be disposed on the passivation layer PAS. At least one color filter CF1, CF3, and CF4 can be configured to correspond to the first sub-pixel SP1, the third sub-pixel SP3, and the fourth sub-pixel SP4 among the first to fourth sub-pixels SP1, SP2, SP3, and SP4. The color filter may not be disposed in the second sub-pixel SP2 among the first to fourth sub-pixels SP1, SP2, SP3, and SP4. For example, a first color filter CF1, which converts white light emitted from the light-emitting device ED to red light, can be disposed in the first light-emitting area EA1 of the first sub-pixel SP1. The second light-emitting area EA2 of the second sub-pixel SP2 can emit white light as is without the need for a color filter. A third color filter CF3, which converts white light emitted from the light-emitting device ED to blue light, can be disposed in the third light-emitting area EA3 of the third sub-pixel SP3. A fourth color filter CF4, which converts white light emitted from the light-emitting device ED to green light, can be disposed in the fourth light-emitting area EA4 of the fourth sub-pixel SP4.

[0083] A planarization layer OC (or outer coating) may be disposed on the passivation layer PAS and at least one color filter CF1, CF3, and CF4. The planarization layer OC can planarize the step difference caused by at least one signal line and power supply line disposed on the substrate 111, at least one thin-film transistor, and at least one color filter CF1, CF3, and CF4, and may be formed of an organic insulating material. For example, the planarization layer OC may be formed of organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but embodiments of the present invention are not limited thereto.

[0084] The pixel electrode AE ​​(first electrode or anode), the light-emitting layer EL (or organic light-emitting layer), and the common electrode CE (second electrode or cathode) constituting the light-emitting device ED can be disposed on the planarization layer OC. Furthermore, the embankment BA configured to define the opening region (or light-emitting region) of the pixel electrode AE ​​can be further disposed on the planarization layer OC.

[0085] Pixel electrodes AE can be disposed on the planarization layer OC. Pixel electrodes AE can be patterned and disposed on the planarization layer OC for each sub-pixel SP1, SP2, SP3, and SP4. Pixel electrodes AE can be formed of transparent or semi-transparent metallic materials. For example, pixel electrodes AE can be formed of a transparent conductive material TCO (such as indium tin oxide ITO or indium zinc oxide IZO). Pixel electrodes AE can be formed of semi-transparent conductive materials such as magnesium (Mg), silver (Ag), or alloys of magnesium (Mg) and silver (Ag). For example, pixel electrodes AE formed of semi-transparent metallic materials can improve light extraction efficiency through microcavities. Pixel electrodes AE can be the anode of a light-emitting device ED. According to embodiments of the present invention, pixel electrodes AE may also include a low-reflectivity metallic layer. For example, the low-reflectivity metallic layer may include metal oxides or alloy oxides. For example, the low-reflectivity metallic layer may include copper oxide CuOx, nickel oxide NiOx, molybdenum oxide MoOx, or tungsten oxide WOx, but embodiments of the present invention are not limited thereto.

[0086] A dam BA can be disposed on the pixel electrode AE ​​and the planarization layer OC. The dam BA can be disposed on the planarization layer OC to cover a portion of the edge of the pixel electrode AE. The dam BA can be configured to define an opening region (or light-emitting region) of the pixel electrode AE. For example, the dam BA can be disposed between the pixel electrode AE ​​and the light-emitting layer EL. The opening region of the pixel electrode AE ​​can correspond to the light-emitting regions EA1, EA2, EA3, and EA4 of each sub-pixel SP1, SP2, SP3, and SP4. For example, the pixel electrode AE ​​exposed by the dam BA can be electrically connected by direct contact with the light-emitting layer EL and the common electrode CE, thereby forming a light-emitting device ED. For example, the dam BA can be omitted.

[0087] A dam BA may be disposed within the non-light-emitting area NEA of each sub-pixel SP1, SP2, SP3, and SP4. The dam BA may overlap with pixel circuits CA1, CA2, CA3, CA4 and at least one signal line and power supply voltage line. For example, the dam BA may be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. For example, the dam BA may be a black dam comprising at least one of a light-absorbing material and a black material. For instance, the dam BA may contain an insulating light-absorbing material, such as black resin or graphite, but embodiments of the invention are not limited thereto.

[0088] An emissive layer (EL) (or organic emissive layer) may be disposed on the pixel electrode AE ​​and the embankment BA. The emissive layer EL may include a hole transport layer, a light-emitting material layer, and an electron transport layer. For example, when a voltage is applied to the pixel electrode AE ​​and the common electrode CE, holes and electrons can move to the emissive layer EL through the hole transport layer and the electron transport layer, respectively, and can combine with each other in the emissive layer EL to emit light. The emissive layer EL may be a common layer formed together on multiple sub-pixels SP1, SP2, SP3, and SP4. For example, the emissive layer EL may be a white emissive layer that emits white light.

[0089] A common electrode CE can be disposed on the light-emitting layer EL. The common electrode CE can be a common layer formed together on multiple sub-pixels SP1, SP2, SP3, and SP4. The common electrode CE can be disposed on the pixel electrodes AE and the light-emitting layer EL that are in contact with each other to constitute a light-emitting device ED. For example, the common electrode CE can be formed from a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an Ag alloy, a stacked structure of Ag alloy and ITO (ITO / Ag alloy / ITO), a MoTi alloy, and a stacked structure of MoTi alloy and ITO (ITO / MoTi alloy / ITO). The Ag alloy can be an alloy of silver (Ag), palladium (Pd), copper (Cu), etc. The MoTi alloy can be an alloy of molybdenum (Mo) and titanium (Ti). The common electrode CE can be the cathode of the light-emitting device ED. According to embodiments of the present invention, the common electrode CE may also include a low-reflectivity metal layer. For example, the low-reflectivity metal layer may include a metal oxide or an alloy oxide. For example, the low-reflectivity metal layer may include copper oxide CuOx, nickel oxide NiOx, molybdenum oxide MoOx, or tungsten oxide WOx, but the embodiments of the present invention are not limited thereto.

[0090] According to embodiments of the present invention, a transmittance control film may be further included on the rear surface of the substrate 111. For example, the transmittance control film may include at least one of a transparent film and an absorbent film, but embodiments of the present invention are not limited thereto.

[0091] Figure 5 This illustrates a plurality of sub-pixels in a display panel according to an embodiment of the present invention. Figure 6 It is according to one embodiment of the present invention. Figure 5 The cross-sectional view taken from line II-II'. Figure 5 and Figure 6 An embodiment of the invention is shown, wherein, with reference to Figures 1 to 4 The described light-emitting display device additionally incorporates a low-reflectivity pattern configuration. (Referencing...) Figure 5 and Figure 6 In the following description, except for the addition of low reflectivity patterns, the same reference numerals will be used for the same parts, and repeated descriptions will be omitted or briefly described.

[0092] Reference Figure 5 and Figure 6 According to one embodiment of the present invention, the display panel 110 may include a low reflectivity pattern LP overlapping at least one of the light-emitting areas EA1, EA2, EA3, and EA4 of a plurality of sub-pixels SP1, SP2, SP3, and SP4. The low reflectivity pattern LP may be disposed in some or all of the plurality of sub-pixels SP1, SP2, SP3, and SP4.

[0093] According to one embodiment of the invention, the low reflectivity pattern LP can be configured to optimize the unit reflectivity of the light-emitting regions EA1, EA2, EA3, and EA4 while maintaining their areas, to suit a polarizer-free structure that does not use a polarizer plate. The low reflectivity pattern LP may include a low reflectivity material layer for reducing external light reflection.

[0094] According to one embodiment of the invention, a low-reflectivity pattern LP may be configured to overlap with at least one color filter CF1, CF3, and CF4 in the light-emitting regions EA1, EA2, EA3, and EA4. Furthermore, the low-reflectivity pattern LP may be configured to overlap with the pixel electrode AE ​​in the light-emitting regions EA1, EA2, EA3, and EA4. At least one color filter CF1, CF3, and CF4 may be located between the pixel electrode AE ​​and the low-reflectivity pattern LP.

[0095] According to one embodiment of the invention, a low-reflectivity pattern LP may be formed in the same layer with at least one of the data lines DL1, DL2, DL3, and DL4 and the scan line SL, using the same material. The low-reflectivity pattern LP may be connected to or separated from the data lines DL1, DL2, DL3, and DL4. For example, the low-reflectivity pattern LP may be integrally formed with the data lines DL1, DL2, DL3, and DL4, or it may be formed as a separate pattern separate from the data lines DL1, DL2, DL3, and DL4. Furthermore, the low-reflectivity pattern LP may be connected to or separated from the scan line SL. For example, the low-reflectivity pattern LP may be integrally formed with the scan line SL, or it may be formed as a separate pattern separate from the scan line SL.

[0096] Reference Figure 5 According to one embodiment of the invention, the low reflectivity pattern LP may extend from each data line DL1, DL2, DL3 and DL4 in a first direction (or X-axis direction) and is configured to overlap with the light-emitting areas EA1, EA2, EA3 and EA4.

[0097] A low reflectivity pattern LP extending from the first data line DL1 in the first direction may be set in the first light-emitting area EA1 of the first sub-pixel SP1; a low reflectivity pattern LP extending from the second data line DL2 in the first direction may be set in the second light-emitting area EA2 of the second sub-pixel SP2; a low reflectivity pattern LP extending from the third data line DL3 in the first direction may be set in the third light-emitting area EA3 of the third sub-pixel SP3; and a low reflectivity pattern LP extending from the fourth data line DL4 in the first direction may be set in the fourth light-emitting area EA4 of the fourth sub-pixel SP4.

[0098] The low reflectivity pattern LP extending from the first data line DL1 and the third data line DL3 may be positioned above the first light-emitting area EA1 and the third light-emitting area EA3 relative to the second direction (or the Y-axis direction), and the low reflectivity pattern LP extending from the second data line DL2 and the fourth data line DL4 may be positioned below the second light-emitting area EA2 and the fourth light-emitting area EA4 relative to the second direction (or the Y-axis direction).

[0099] According to one embodiment of the present invention, a low reflectivity pattern LP may extend one or more portions from each data line DL1, DL2, DL3 and DL4, and the low reflectivity pattern LP may be disposed in one or more portions of each light-emitting area EA1, EA2, EA3 and EA4, and the low reflectivity pattern LP may be disposed only in some of the light-emitting areas EA1, EA2, EA3 and EA4, but the embodiments of the present invention are not limited thereto.

[0100] Reference Figure 6According to one embodiment of the present invention, a low-reflectivity pattern LP can be disposed on a substrate 111. The low-reflectivity pattern LP according to one embodiment of the present invention can be disposed in the same layer as the data lines DL1, DL2, DL3, and DL4 and the first power supply voltage line VDDL on the substrate 111, using the same material. The low-reflectivity pattern LP may include a low-reflectivity material layer for reducing the reflection of external light. The low-reflectivity pattern LP may include a conductive metal layer M1 and a low-reflectivity material layer LM1 located below the metal layer M1. For example, the metal layer M1 may be configured as a single layer or multiple layers formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), tungsten (W), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and their alloys, but embodiments of the present invention are not limited thereto. The low-reflectivity material layer LM1 may be a metal layer with excellent low-reflectivity characteristics and may be composed of molybdenum-titanium (MoTi) or molybdenum (Mo), or may include metal oxides or alloy oxides. For example, the low-reflectivity material layer LM1 may comprise copper oxide CuOx, nickel oxide NiOx, molybdenum oxide MoOx, or tungsten oxide WOx, but embodiments of the present invention are not limited thereto. For example, the low-reflectivity pattern LP may be a bilayer structure comprising copper Cu and molybdenum-titanium MoTi, or copper Cu and metal oxides.

[0101] One end of the low-reflectivity pattern LP can be connected to each data line DL1, DL2, DL3, and DL4, and the other end of the low-reflectivity pattern LP can be electrically floated. The low-reflectivity pattern LP can overlap with at least one color filter CF1, CF3, and CF4, and can overlap with the pixel electrode AE ​​of each sub-pixel SP1, SP2, SP3, and SP4. At least one color filter CF1, CF3, and CF4 can be disposed between the pixel electrode AE ​​and the low-reflectivity pattern LP.

[0102] The lower portion of the low-reflectivity pattern LP includes a low-reflectivity material layer LM1 with a lower reflectivity than the pixel electrode AE ​​and the common electrode CE. By reflecting or absorbing a portion of the external incident light through the lower portion of the low-reflectivity pattern LP before reaching the pixel electrode AE, the unit reflectivity of the light-emitting regions EA1, EA2, EA3, and EA4 can be reduced. Furthermore, a metal layer M1 can be disposed in the upper portion of the low-reflectivity pattern LP, and light emitted from the light-emitting device ED can be internally reflected through the upper portion of the low-reflectivity pattern LP, thereby improving light extraction efficiency.

[0103] According to one embodiment of the present invention, while maintaining the optimized area of ​​the light-emitting regions EA1, EA2, EA3, and EA4, the reflectivity of externally incident light can be reduced via a low-reflectivity pattern LP overlapping the light-emitting regions EA1, EA2, EA3, and EA4. This prevents an increase in current density and avoids degrading image quality, such as image retention. Furthermore, the low-reflectivity pattern LP can induce internal reflection of light emitted from the light-emitting device ED, thereby improving light extraction efficiency. Therefore, a light-emitting display device capable of optimizing the unit reflectivity of the light-emitting regions EA1, EA2, EA3, and EA4 to suit a polarizer-free structure and improve light efficiency can be provided.

[0104] Figure 7 A plurality of sub-pixels in a display panel according to another embodiment of the present invention are shown. Figure 8 It is along another embodiment of the present invention Figure 7 The cross-sectional view taken from line III-III'. Figure 7 and Figure 8 Another embodiment of the invention is shown, wherein, with reference to Figures 1 to 6 The low-reflectivity pattern structure in the described light-emitting display device has been modified. (Referencing...) Figure 7 and Figure 8 In the following description, except for the modified low-reflectivity pattern, the same reference numerals will be used for the same parts, and repeated descriptions will be omitted or briefly described.

[0105] Reference Figure 7 and Figure 8 According to another embodiment of the present invention, the display panel 110 may include a first low reflectivity pattern LP1 and a second low reflectivity pattern LP2, wherein the first low reflectivity pattern LP1 and the second low reflectivity pattern LP2 are configured as island-shaped patterns extending in different directions in at least one of the light-emitting areas EA1, EA2, EA3 and EA4 of a plurality of sub-pixels SP1, SP2, SP3 and SP4. The first low reflectivity pattern LP1 and the second low reflectivity pattern LP2 may be disposed in some or all of the plurality of sub-pixels SP1, SP2, SP3 and SP4.

[0106] Reference Figure 7 According to another embodiment of the present invention, the first low reflectivity pattern LP1 and the second low reflectivity pattern LP2 may be island-shaped patterns spaced apart from each of the data lines DL1, DL2, DL3 and DL4 and extending in the light-emitting areas EA1, EA2, EA3 and EA4 in a first direction (or X-axis direction) or a second direction (or Y-axis direction).

[0107] At least one first low-reflectivity pattern LP1, configured as an island-shaped pattern extending in the second direction, may be disposed in the first light-emitting area EA1 of the first sub-pixel SP1; one or more second low-reflectivity patterns LP2, configured as an island-shaped pattern extending in the first direction, may be disposed in the second light-emitting area EA2 of the second sub-pixel SP2; at least one first low-reflectivity pattern LP1, configured as an island-shaped pattern extending in the second direction, may be disposed in the third light-emitting area EA3 of the third sub-pixel SP3; and one or more second low-reflectivity patterns LP2, configured as an island-shaped pattern extending in the first direction, may be disposed in the fourth light-emitting area EA4 of the fourth sub-pixel SP4. For example, one end of the first low-reflectivity pattern LP1 and the other end of the second low-reflectivity pattern LP2 may be electrically floating.

[0108] The first low reflectivity pattern LP1, which is disposed in the first light-emitting area EA1 and the third light-emitting area EA3, can be disposed at the center of the respective light-emitting areas EA1 and EA3 relative to the first direction (or the X-axis direction), and the second low reflectivity pattern LP2, which is disposed in the second light-emitting area EA2 and the fourth light-emitting area EA4, can be disposed in multiple locations at the upper and lower parts of the respective light-emitting areas EA2 and EA4 relative to the second direction (or the Y-axis direction).

[0109] According to another embodiment of the present invention, one or more of the first low-reflectivity patterns LP1 may be disposed in each of the light-emitting regions EA1, EA2, EA3, and EA4, and one or more of the second low-reflectivity patterns LP2 may be disposed in each of the light-emitting regions EA1, EA2, EA3, and EA4. The first low-reflectivity patterns LP1 and the second low-reflectivity patterns LP2 may be disposed in some or all of the light-emitting regions EA1, EA2, EA3, and EA4, but the embodiments of the present invention are not limited thereto.

[0110] Reference Figure 8According to another embodiment of the present invention, a first low-reflectivity pattern LP1 and a second low-reflectivity pattern LP2 may be disposed on a substrate 111. The first low-reflectivity pattern LP1 and the second low-reflectivity pattern LP2 may be formed in the same layer of the same material as the data lines DL1, DL2, DL3, and DL4 and the first power supply voltage line VDDL on the substrate 111. The first low-reflectivity pattern LP1 and the second low-reflectivity pattern LP2 may be configured as electrically floating island patterns within each light-emitting region EA1, EA2, EA3, and EA4. The first low-reflectivity pattern LP1 and the second low-reflectivity pattern LP2 may overlap with at least one of color filters CF1, CF3, and CF4, and may overlap with the pixel electrode AE ​​of each of the sub-pixels SP1, SP2, SP3, and SP4. At least one color filter CF1, CF3, and CF4 may be disposed between the pixel electrode AE ​​and the first low-reflectivity pattern LP1 and the second low-reflectivity pattern LP2.

[0111] The lower portion of the first low-reflectivity pattern LP1 and the second low-reflectivity pattern LP2 may include a low-reflectivity material layer LM1 having a lower reflectivity than the pixel electrode AE ​​and the common electrode CE. This layer can reduce the unit reflectivity of the light-emitting regions EA1, EA2, EA3, and EA4 by reflecting or absorbing a portion of externally incident light via the lower portion of the first low-reflectivity pattern LP1 and the second low-reflectivity pattern LP2 before it reaches the pixel electrode AE. Furthermore, a metal layer M1 may be disposed in the upper portion of the first low-reflectivity pattern LP1 and the second low-reflectivity pattern LP2 to induce internal reflection of light emitted from the light-emitting device ED via the upper portion of the first low-reflectivity pattern LP1 and the second low-reflectivity pattern LP2, thereby improving light extraction efficiency.

[0112] According to another embodiment of the present invention, the reflectivity of externally incident light can be reduced by using a first low-reflectivity pattern LP1 and a second low-reflectivity pattern LP2 overlapping with the light-emitting regions EA1, EA2, EA3, and EA4, while maintaining the optimized area of ​​the light-emitting regions EA1, EA2, EA3, and EA4, so that the current density does not increase and the display quality does not deteriorate, such as image hold-up. Furthermore, the first low-reflectivity pattern LP1 and the second low-reflectivity pattern LP2 can induce internal reflection of light emitted from the light-emitting device ED, thereby improving light extraction efficiency. Therefore, a light-emitting display device capable of optimizing the unit reflectivity of the light-emitting regions EA1, EA2, EA3, and EA4 to suit a polarizer-free structure and improve light efficiency can be provided.

[0113] Figure 9 A plurality of sub-pixels in a display panel according to another embodiment of the present invention are shown. Figure 10 It is along another embodiment of the present invention Figure 9 A cross-sectional view taken from line IV-IV'. Figure 9 and Figure 10 Another embodiment of the invention is shown, wherein, with reference to Figures 1 to 8 The low-reflectivity pattern structure in the described light-emitting display device has been modified. (Referencing...) Figure 9 and Figure 10 In the following description, except for the modified low-reflectivity pattern, the same reference numerals will be used for the same parts, and repeated descriptions will be omitted or briefly described.

[0114] Reference Figure 9 and Figure 10 According to another embodiment of the present invention, the display panel 110 may include a first low reflectivity pattern LP1 and a second low reflectivity pattern LP2 overlapping with at least one of the light-emitting areas EA1, EA2, EA3 and EA4 of a plurality of sub-pixels SP1, SP2, SP3 and SP4. The first low reflectivity pattern LP1 and the second low reflectivity pattern LP2 may be disposed in some or all of the plurality of sub-pixels SP1, SP2, SP3 and SP4.

[0115] Reference Figure 9 According to another embodiment of the present invention, the first low reflectivity pattern LP1 and the second low reflectivity pattern LP2 may extend to both sides from each of the data lines DL1, DL2, DL3 and DL4 in a first direction (or the X-axis direction), and may be configured to overlap with the light-emitting areas EA1, EA2, EA3 and EA4.

[0116] In the first light-emitting area EA1 of the first sub-pixel SP1, a first low-reflectivity pattern LP1 extending to the right from the first data line DL1 in a first direction and a second low-reflectivity pattern LP2 extending to the left from the second data line DL2 in a first direction can be provided. In the second light-emitting area EA2 of the second sub-pixel SP2, a first low-reflectivity pattern LP1 extending to the right from the second data line DL2 in a first direction and a second low-reflectivity pattern LP2 extending to the left from the third data line DL3 in a first direction can be provided. In the third light-emitting area EA3 of the third sub-pixel SP3, a first low-reflectivity pattern LP1 extending to the right from the third data line DL3 in a first direction and a second low-reflectivity pattern LP2 extending to the left from the fourth data line DL4 in a first direction can be provided. In the fourth light-emitting area EA4 of the fourth sub-pixel SP4, a first low-reflectivity pattern LP1 extending to the right from the fourth data line DL4 in a first direction can be provided. For example, one end of the first low reflectivity pattern LP1 and the second low reflectivity pattern LP2 can be integrally connected to each of the data lines DL1, DL2, DL3 and DL4, and the other end of the first low reflectivity pattern LP1 and the second low reflectivity pattern LP2 can be electrically floating.

[0117] The first low reflectivity pattern LP1 and the second low reflectivity pattern LP2 extending from the first data line DL1 and the third data line DL3 may be disposed above each of the light-emitting areas EA1, EA2 and EA3 based on a second direction (or the Y-axis direction), and the first low reflectivity pattern LP1 and the second low reflectivity pattern LP2 extending from the second data line DL2 and the fourth data line DL4 may be disposed below each of the light-emitting areas EA1, EA2, EA3 and EA4 based on a second direction.

[0118] According to another embodiment of the present invention, one or more of the first low-reflectivity pattern LP1 and the second low-reflectivity pattern LP2 may extend from each of the data lines DL1, DL2, DL3, and DL4, and one or more of the first low-reflectivity pattern LP1 and the second low-reflectivity pattern LP2 may be disposed in each of the light-emitting areas EA1, EA2, EA3, and EA4. The first low-reflectivity pattern LP1 and the second low-reflectivity pattern LP2 may be disposed only in some of the light-emitting areas EA1, EA2, EA3, and EA4, but the embodiments of the present invention are not limited thereto.

[0119] Reference Figure 10 According to another embodiment of the present invention, a first low-reflectivity pattern LP1 and a second low-reflectivity pattern LP2 may be disposed on a substrate 111. The first low-reflectivity pattern LP1 and the second low-reflectivity pattern LP2 may be formed in the same layer of the same material as the data lines DL1, DL2, DL3, and DL4 and the first power supply voltage line VDDL on the substrate 111. One end of the first low-reflectivity pattern LP1 and the second low-reflectivity pattern LP2 may be connected to each of the data lines DL1, DL2, DL3, and DL4, and the other end of the first low-reflectivity pattern LP1 and the second low-reflectivity pattern LP2 may be electrically floated. The first low-reflectivity pattern LP1 and the second low-reflectivity pattern LP2 may overlap with at least one of the color filters CF1, CF3, and CF4, and may overlap with the pixel electrode AE ​​of each of the sub-pixels SP1, SP2, SP3, and SP4. At least one of the color filters CF1, CF3, and CF4 may be disposed between the pixel electrode AE ​​and the first low-reflectivity pattern LP1 and the second low-reflectivity pattern LP2.

[0120] The lower portion of the first low-reflectivity pattern LP1 and the second low-reflectivity pattern LP2 may include a low-reflectivity material layer LM1 having a lower reflectivity than the pixel electrode AE ​​and the common electrode CE. By reflecting or absorbing a portion of the external incident light through the lower portion of the first low-reflectivity pattern LP1 and the second low-reflectivity pattern LP2 before reaching the pixel electrode AE, the unit reflectivity of the light-emitting regions EA1, EA2, EA3, and EA4 can be reduced. Furthermore, a metal layer M1 may be disposed in the upper portion of the first low-reflectivity pattern LP1 and the second low-reflectivity pattern LP2, and the upper portion of the first low-reflectivity pattern LP1 and the second low-reflectivity pattern LP2 can induce internal reflection of light emitted from the light-emitting device ED, thereby improving light extraction efficiency.

[0121] According to another embodiment of the present invention, the reflectivity of externally incident light can be reduced by using a first low-reflectivity pattern LP1 and a second low-reflectivity pattern LP2 overlapping with the light-emitting regions EA1, EA2, EA3, and EA4, while maintaining the optimized area of ​​the light-emitting regions EA1, EA2, EA3, and EA4, so that the current density does not increase and the display quality does not deteriorate, such as image hold-up. Furthermore, the first low-reflectivity pattern LP1 and the second low-reflectivity pattern LP2 can induce internal reflection of light emitted from the light-emitting device ED, thereby improving light extraction efficiency. Therefore, a light-emitting display device capable of optimizing the unit reflectivity of the light-emitting regions EA1, EA2, EA3, and EA4 to suit a polarizer-free structure and improve light efficiency can be provided.

[0122] Figure 11 A plurality of sub-pixels in a display panel according to another embodiment of the present invention are shown. Figure 12 It is along another embodiment of the present invention Figure 11 A cross-sectional view taken from line V-V'. Figure 11 and Figure 12 Another embodiment of the invention is shown, wherein, with reference to Figures 1 to 10 The low-reflectivity pattern structure in the described light-emitting display device has been modified. (Referencing...) Figure 11 and Figure 12 In the following description, except for the modified low-reflectivity pattern, the same reference numerals will be used for the same parts, and repeated descriptions will be omitted or briefly described.

[0123] Reference Figure 11 and Figure 12 According to another embodiment of the present invention, the display panel 110 may include a low reflectivity pattern LP extending from the scan line SL in at least one of the light-emitting areas EA1, EA2, EA3 and EA4 in a plurality of sub-pixels SP1, SP2 and SP3 and SP4 in a second direction (or Y-axis direction).

[0124] Reference Figure 11According to another embodiment of the invention, the low reflectivity pattern LP may extend from at least one of the scan lines SL (or gate lines) in a second direction (or Y-axis direction) and may be configured to overlap with the light-emitting regions EA1, EA2, EA3 and EA4.

[0125] In the first light-emitting area EA1 of the first sub-pixel SP1, a low-reflectivity pattern LP extending in a second direction from at least one of the scan lines SL can be provided. In the second light-emitting area EA2 of the second sub-pixel SP2, a low-reflectivity pattern LP extending in a second direction from at least one of the scan lines SL can be provided. In the third light-emitting area EA3 of the third sub-pixel SP3, a low-reflectivity pattern LP extending in a second direction from at least one of the scan lines SL can be provided. In the fourth light-emitting area EA4 of the fourth sub-pixel SP4, a low-reflectivity pattern LP extending in a second direction from at least one of the scan lines SL can be provided.

[0126] The low reflectivity pattern LP disposed in each of the light-emitting areas EA1, EA2, EA3 and EA4 may be disposed to the left of each of the light-emitting areas EA1, EA2, EA3 and EA4 relative to the first direction.

[0127] According to another embodiment of the present invention, one or more of the low reflectivity patterns LP may be disposed in each of the light-emitting areas EA1, EA2, EA3 and EA4, and the low reflectivity patterns LP may be disposed in some or all of the light-emitting areas EA1, EA2, EA3 and EA4, but the embodiments of the present invention are not limited thereto.

[0128] Reference Figure 12According to another embodiment of the present invention, a low-reflectivity pattern LP can be disposed on a buffer layer BF. The low-reflectivity pattern LP can be disposed on the buffer layer BF in the same layer as at least one scan line SL, using the same material. The low-reflectivity pattern LP may include a low-reflectivity material layer for reducing the reflection of external light. The low-reflectivity pattern LP may include a conductive metal layer M2 and a low-reflectivity material layer LM2 located below the metal layer M2. For example, the metal layer M2 may be configured as a single layer or multiple layers formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), tungsten (W), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and their alloys, but embodiments of the present invention are not limited thereto. The low-reflectivity material layer LM2 may be a metal layer with excellent low-reflectivity properties and may be composed of molybdenum-titanium (MoTi) or molybdenum (Mo), or may include metal oxides or alloy oxides. For example, the low-reflectivity material layer LM2 may contain copper oxide (CuOx), nickel oxide (NiOx), molybdenum oxide (MoOx), or tungsten oxide (WOx), but embodiments of the present invention are not limited thereto. For example, a low-reflectivity pattern LP can be a bilayer structure consisting of copper (Cu) and molybdenum-titanium (MoTi), or copper (Cu) and metal oxides.

[0129] One end of the low-reflectivity pattern LP can be connected to at least one scan line SL, and the other end of the low-reflectivity pattern LP can be electrically floated. The low-reflectivity pattern LP can overlap with at least one color filter CF1, CF3, and CF4, and can overlap with the pixel electrode AE ​​of each sub-pixel SP1, SP2, SP3, and SP4. At least one color filter CF1, CF3, and CF4 can be disposed between the pixel electrode AE ​​and the low-reflectivity pattern LP.

[0130] The lower portion of the low-reflectivity pattern LP includes a low-reflectivity material layer LM2 with a lower reflectivity than the pixel electrode AE ​​and the common electrode CE. By reflecting or absorbing a portion of the external incident light through the lower portion of the low-reflectivity pattern LP before reaching the pixel electrode AE, the unit reflectivity of the light-emitting regions EA1, EA2, EA3, and EA4 can be reduced. Furthermore, a metal layer M2 can be disposed in the upper portion of the low-reflectivity pattern LP, and light emitted from the light-emitting device ED can be internally reflected through the upper portion of the low-reflectivity pattern LP, thereby improving light extraction efficiency.

[0131] According to another embodiment of the present invention, the reflectivity of externally incident light can be reduced by a low-reflectivity pattern LP overlapping with the light-emitting regions EA1, EA2, EA3, and EA4, while maintaining the optimized area of ​​the light-emitting regions EA1, EA2, EA3, and EA4, so that the current density does not increase and the display quality does not deteriorate, such as causing image hold-up. Furthermore, the low-reflectivity pattern LP can induce internal reflection of light emitted from the light-emitting device ED, thereby improving light extraction efficiency. Therefore, a light-emitting display device can be provided that optimizes the unit reflectivity of the light-emitting regions EA1, EA2, EA3, and EA4 to suit a polarizer-free structure and improve light efficiency.

[0132] Figure 13 A plurality of sub-pixels in a display panel according to another embodiment of the present invention are shown. Figure 14 It is along another embodiment of the present invention Figure 13 The cross-sectional view taken from line VI-VI'. Figure 13 and Figure 14 Another embodiment of the invention is shown, wherein, with reference to Figures 1 to 12 The low-reflectivity pattern structure in the described light-emitting display device has been modified. (Referencing...) Figure 13 and Figure 14 In the following description, except for the modified low-reflectivity pattern, the same reference numerals will be used for the same parts, and repeated descriptions will be omitted or briefly described.

[0133] Reference Figure 13 and Figure 14 According to another embodiment of the present invention, the display panel 110 may include a low reflectivity pattern LP, which is configured as an island-shaped pattern extending in a first direction (or the X-axis direction) in at least one of the light-emitting areas EA1, EA2, EA3, and EA4 of a plurality of sub-pixels SP1, SP2, SP3, and SP4. For example, the low reflectivity pattern LP may be configured as an island-shaped pattern extending in a second direction (or the Y-axis direction). Furthermore, the low reflectivity pattern LP may be disposed in some or all of the plurality of sub-pixels SP1, SP2, SP3, and SP4.

[0134] Reference Figure 13 According to another embodiment of the present invention, the low reflectivity pattern LP may be spaced apart from at least one scan line SL, and may be an island-shaped pattern extending in a first direction (or X-axis direction) or a second direction (or Y-axis direction) in the light-emitting areas EA1, EA2, EA3 and EA4.

[0135] In the first light-emitting area EA1 of the first sub-pixel SP1, at least one low-reflectivity pattern LP, configured as an island-shaped pattern extending in a first direction, may be provided. In the second light-emitting area EA2 of the second sub-pixel SP2, at least one low-reflectivity pattern LP, configured as an island-shaped pattern extending in a first direction, may be provided. In the third light-emitting area EA3 of the third sub-pixel SP3, at least one low-reflectivity pattern LP, configured as an island-shaped pattern extending in a first direction, may be provided. In the fourth light-emitting area EA4 of the fourth sub-pixel SP4, at least one low-reflectivity pattern LP, configured as an island-shaped pattern extending in a first direction, may be provided. For example, the two ends of the low-reflectivity pattern LP may be electrically floating.

[0136] The low-reflectivity pattern LP disposed in the first luminous region EA1 and the third luminous region EA3 may be disposed above each of the luminous regions EA1 and EA3 relative to the second direction. The low-reflectivity pattern LP disposed in the second luminous region EA2 and the fourth luminous region EA4 may be disposed below each of the luminous regions EA2 and EA4 relative to the second direction.

[0137] According to another embodiment of the present invention, one or more of the low reflectivity patterns LP may be disposed in each of the light-emitting areas EA1, EA2, EA3 and EA4, and the low reflectivity patterns LP may be disposed in some or all of the light-emitting areas EA1, EA2, EA3 and EA4, but the embodiments of the present invention are not limited thereto.

[0138] Reference Figure 14 According to another embodiment of the invention, a low-reflectivity pattern LP can be disposed on a buffer layer BF. The low-reflectivity pattern LP can be disposed in the same layer as at least one of the scan lines SL on the buffer layer BF using the same material. The low-reflectivity pattern LP can be configured as an electrically floating island pattern within each of the light-emitting regions EA1, EA2, EA3, and EA4. The low-reflectivity pattern LP can overlap with at least one of the color filters CF1, CF3, and CF4, and can overlap with the pixel electrode AE ​​of each of the sub-pixels SP1, SP2, SP3, and SP4. At least one of the color filters CF1, CF3, and CF4 can be disposed between the pixel electrode AE ​​and the low-reflectivity pattern LP.

[0139] The lower portion of the low-reflectivity pattern LP includes a low-reflectivity material layer LM2 with a lower reflectivity than the pixel electrode AE ​​and the common electrode CE. By reflecting or absorbing a portion of the external incident light through the lower portion of the low-reflectivity pattern LP before reaching the pixel electrode AE, the unit reflectivity of the light-emitting regions EA1, EA2, EA3, and EA4 can be reduced. Furthermore, a metal layer M2 can be disposed in the upper portion of the low-reflectivity pattern LP, and light emitted from the light-emitting device ED can be internally reflected through the upper portion of the low-reflectivity pattern LP, thereby improving light extraction efficiency.

[0140] According to another embodiment of the present invention, the reflectivity of externally incident light can be reduced by a low-reflectivity pattern LP overlapping with the light-emitting regions EA1, EA2, EA3, and EA4, while maintaining the optimized area of ​​the light-emitting regions EA1, EA2, EA3, and EA4, so that the current density does not increase and the display quality does not deteriorate, such as causing image hold-up. Furthermore, the low-reflectivity pattern LP can induce internal reflection of light emitted from the light-emitting device ED, thereby improving light extraction efficiency. Therefore, a light-emitting display device can be provided that optimizes the unit reflectivity of the light-emitting regions EA1, EA2, EA3, and EA4 to suit a polarizer-free structure and improve light efficiency.

[0141] Figure 15 A plurality of sub-pixels in a display panel according to another embodiment of the present invention are shown. Figure 16 It is along another embodiment of the present invention Figure 15 The cross-sectional view taken from line VII-VII'. Figure 15 and Figure 16 Another embodiment of the invention is shown, wherein, with reference to Figures 1 to 14 The low-reflectivity pattern structure in the described light-emitting display device has been modified. (Referencing...) Figure 15 and Figure 16 In the following description, except for the modified low-reflectivity pattern, the same reference numerals will be used for the same parts, and repeated descriptions will be omitted or briefly described.

[0142] Reference Figure 15 and Figure 16 According to another embodiment of the present invention, the display panel 110 may include a first low reflectivity pattern LP1 and a second low reflectivity pattern LP2 overlapping with at least one of the light-emitting areas EA1, EA2, EA3 and EA4 of a plurality of sub-pixels SP1, SP2, SP3 and SP4. The first low reflectivity pattern LP1 and the second low reflectivity pattern LP2 may be disposed in some or all of the plurality of sub-pixels SP1, SP2, SP3 and SP4.

[0143] Reference Figure 15According to another embodiment of the invention, a first low-reflectivity pattern LP1 may extend from each of the data lines DL1, DL2, DL3 and DL4 in a first direction and is configured to overlap with the light-emitting areas EA1, EA2, EA3 and EA4. A second low-reflectivity pattern LP2 may be spaced apart from at least one of the scan lines SL and may be an island-shaped pattern extending in the first direction in the light-emitting areas EA1, EA2, EA3 and EA4.

[0144] In the first light-emitting area EA1 of the first sub-pixel SP1, a first low-reflectivity pattern LP1 extending from the first data line DL1 in a first direction and a second low-reflectivity pattern LP2 extending in the first direction (like an island pattern) can be provided. In the second light-emitting area EA2 of the second sub-pixel SP2, a first low-reflectivity pattern LP1 extending from the second data line DL2 in a first direction and a second low-reflectivity pattern LP2 extending in the first direction (like an island pattern) can be provided. In the third light-emitting area EA3 of the third sub-pixel SP3, a first low-reflectivity pattern LP1 extending from the third data line DL3 in a first direction and a second low-reflectivity pattern LP2 extending in the first direction (like an island pattern) can be provided. In the fourth light-emitting area EA4 of the fourth sub-pixel SP4, a first low-reflectivity pattern LP1 extending from the fourth data line DL4 in a first direction and a second low-reflectivity pattern LP2 extending in the first direction (like an island pattern) can be provided.

[0145] A first low-reflectivity pattern LP1 extending from the first data line DL1 and the third data line DL3 may be disposed above the first light-emitting area EA1 and the third light-emitting area EA3 in a second direction. A first low-reflectivity pattern LP1 extending from the second data line DL2 and the fourth data line DL4 may be disposed below the second light-emitting area EA2 and the fourth light-emitting area EA4 in a second direction. Furthermore, a second low-reflectivity pattern LP2 disposed in the first light-emitting area EA1 and the third light-emitting area EA3 may be disposed below the first light-emitting area EA1 and the third light-emitting area EA3 in a second direction. A second low-reflectivity pattern LP2 disposed in the second light-emitting area EA2 and the fourth light-emitting area EA4 may be disposed above the second light-emitting area EA2 and the fourth light-emitting area EA4 in a second direction.

[0146] According to another embodiment of the present invention, one or more of the first low-reflectivity patterns LP1 may extend from each of the data lines DL1, DL2, DL3, and DL4, and one or more of the first low-reflectivity patterns LP1 and the second low-reflectivity patterns LP2 may be disposed in each of the light-emitting areas EA1, EA2, EA3, and EA4. The first low-reflectivity patterns LP1 and the second low-reflectivity patterns LP2 may be disposed only in some of the light-emitting areas EA1, EA2, EA3, and EA4, but the embodiments of the present invention are not limited thereto.

[0147] Reference Figure 16 According to another embodiment of the present invention, a first low-reflectivity pattern LP1 may be disposed on a substrate 111, and a second low-reflectivity pattern LP2 may be disposed on a buffer layer BF. The first low-reflectivity pattern LP1 may be disposed on the substrate 111 in the same layer as data lines DL1, DL2, DL3, and DL4 and a first power supply voltage line VDDL, and the second low-reflectivity pattern LP2 may be disposed on the buffer layer BF in the same layer as at least one of the scan lines SL, using the same material. One end of the first low-reflectivity pattern LP1 may be connected to each of the data lines DL1, DL2, DL3, and DL4, and the other end of the first low-reflectivity pattern LP1 may be electrically floating. Furthermore, the second low-reflectivity pattern LP2 may be configured as an electrically floating island-shaped pattern within each light-emitting region EA1, EA2, EA3, and EA4. The first low-reflectivity pattern LP1 and the second low-reflectivity pattern LP2 may overlap with at least one of the color filters CF1, CF3 and CF4, and may overlap with the pixel electrode AE ​​of each of the sub-pixels SP1, SP2, SP3 and SP4. At least one of the color filters CF1, CF3 and CF4 may be disposed between the pixel electrode AE ​​and the first low-reflectivity pattern LP1 and the second low-reflectivity pattern LP2.

[0148] The lower portions of the first low-reflectivity pattern LP1 and the second low-reflectivity pattern LP2 may include low-reflectivity material layers LM1 and LM2 having a lower reflectivity than the pixel electrode AE ​​and the common electrode CE. These layers can reduce the unit reflectivity of the light-emitting regions EA1, EA2, EA3, and EA4 by reflecting or absorbing a portion of externally incident light via the lower portions of the first low-reflectivity pattern LP1 and the second low-reflectivity pattern LP2 before it reaches the pixel electrode AE. Furthermore, metal layers M1 and M2 may be disposed in the upper portions of the first low-reflectivity pattern LP1 and the second low-reflectivity pattern LP2 to induce internal reflection of light emitted from the light-emitting device ED via the upper portions of the first low-reflectivity pattern LP1 and the second low-reflectivity pattern LP2, thereby improving light extraction efficiency.

[0149] According to another embodiment of the present invention, the reflectivity of externally incident light can be reduced by using a first low-reflectivity pattern LP1 and a second low-reflectivity pattern LP2 overlapping with the light-emitting regions EA1, EA2, EA3, and EA4, while maintaining the optimized area of ​​the light-emitting regions EA1, EA2, EA3, and EA4, so that the current density does not increase and the display quality does not deteriorate, such as image hold-up. Furthermore, the first low-reflectivity pattern LP1 and the second low-reflectivity pattern LP2 can induce internal reflection of light emitted from the light-emitting device ED, thereby improving light extraction efficiency. Therefore, a light-emitting display device capable of optimizing the unit reflectivity of the light-emitting regions EA1, EA2, EA3, and EA4 to suit a polarizer-free structure and improve light efficiency can be provided.

[0150] The following describes a light-emitting display device according to one or more embodiments of the present invention.

[0151] A light-emitting display device according to one or more embodiments of the present invention may include: a substrate comprising a plurality of sub-pixels, the plurality of sub-pixels having light-emitting regions and non-light-emitting regions; data lines and gate lines disposed in the non-light-emitting regions on the substrate and intersecting each other; at least one insulating layer disposed on the data lines and the gate lines; and a color filter disposed on the at least one insulating layer and corresponding to at least one sub-pixel of the plurality of sub-pixels, the plurality of sub-pixels comprising a low-reflectivity pattern overlapping the light-emitting regions.

[0152] According to one or more embodiments of the present invention, the low reflectivity pattern may include a low reflectivity material layer.

[0153] According to one or more embodiments of the present invention, the low reflectivity pattern may overlap with the color filter.

[0154] According to one or more embodiments of the present invention, the low reflectivity pattern may be formed in the same layer with at least one of the data lines and the gate lines using the same material.

[0155] According to one or more embodiments of the present invention, the low reflectivity pattern may be connected to the data line or separated from the data line.

[0156] According to one or more embodiments of the present invention, the low reflectivity pattern may be connected to the gate line or separated from the gate line.

[0157] According to one or more embodiments of the present invention, the low reflectivity pattern may include a metal layer and a low reflectivity material layer located below the metal layer.

[0158] According to one or more embodiments of the present invention, each of the plurality of sub-pixels may include a light-emitting device, the light-emitting device including a pixel electrode, a light-emitting layer and a common electrode, and the light-emitting area may overlap with the light-emitting device.

[0159] According to one or more embodiments of the present invention, the low reflectivity pattern may overlap with the pixel electrode, and the color filter may be located between the pixel electrode and the low reflectivity pattern.

[0160] According to one or more embodiments of the present invention, each of the plurality of sub-pixels may include a pixel circuit having at least one thin-film transistor and a capacitor, and the non-light-emitting area may include: a first non-light-emitting area in which the pixel circuit is disposed; and a second non-light-emitting area located between adjacent sub-pixels among the plurality of sub-pixels.

[0161] According to one or more embodiments of the present invention, the gate line may extend in a first direction in the first non-light-emitting region, and the data line may extend in a second direction intersecting the first direction in the second non-light-emitting region.

[0162] According to one or more embodiments of the present invention, the low reflectivity pattern may extend from the data line in the first direction and may be configured to overlap with the light-emitting area.

[0163] According to one or more embodiments of the present invention, one end of the low reflectivity pattern may be connected to the data line, and the other end of the low reflectivity pattern may be electrically floated.

[0164] According to one or more embodiments of the present invention, the low reflectivity pattern may be spaced apart from the data line and may be an island-shaped pattern extending in the light-emitting area in the first direction or the second direction.

[0165] According to one or more embodiments of the present invention, the low reflectivity pattern may extend from the gate line in the second direction and may be configured to overlap with the light-emitting area.

[0166] According to one or more embodiments of the present invention, one end of the low reflectivity pattern may be connected to the data line, and the other end of the low reflectivity pattern may be electrically floated.

[0167] According to one or more embodiments of the present invention, the low reflectivity pattern may be spaced apart from the gate line and may be an island-shaped pattern extending in the light-emitting region in the first direction or the second direction.

[0168] According to one or more embodiments of the present invention, the light-emitting display device may further include a dam that defines a light-emitting area for each of the plurality of sub-pixels, the dam being disposed between the pixel electrode and the light-emitting layer.

[0169] According to one or more embodiments of the present invention, the embankment may comprise at least one of a light-absorbing material and a black material.

[0170] According to one or more embodiments of the present invention, the light-emitting display device may further include a transmittance control film disposed on the rear surface of the substrate.

[0171] According to one or more embodiments of the present invention, the transmittance control film may include at least one of a transparent film and a light-absorbing film.

[0172] According to one or more embodiments of the present invention, the low reflectivity pattern may include a metal layer and a low reflectivity material layer located below the metal layer, the reflectivity of the low reflectivity material layer being lower than that of each of the pixel electrode and the common electrode.

[0173] The features, structures, and effects described above in this invention are included in at least one embodiment, but are not limited to only one embodiment. Furthermore, the features, structures, and effects described in at least one embodiment of this invention can be achieved by those skilled in the art through combinations or modifications with other embodiments. Therefore, anything associated with combinations and modifications should be interpreted as falling within the scope of this invention.

[0174] It will be apparent to those skilled in the art that various modifications and variations can be made to this invention without departing from the spirit or scope thereof. Therefore, this invention is intended to cover modifications and variations that fall within the scope of the appended claims and their equivalents.

Claims

1. A light-emitting display device, comprising: A substrate, the substrate comprising a plurality of sub-pixels, the plurality of sub-pixels having light-emitting areas and non-light-emitting areas; Data lines and gate lines are disposed in a non-light-emitting area on the substrate and intersect each other; At least one insulating layer is disposed on the data line and the gate line; as well as A color filter, wherein the color filter is disposed on the at least one insulating layer and corresponds to at least one sub-pixel among the plurality of sub-pixels. One or more of the plurality of sub-pixels include a low-reflectivity pattern that overlaps with the light-emitting area.

2. The light-emitting display device according to claim 1, wherein the low reflectivity pattern comprises a low reflectivity material layer.

3. The light-emitting display device according to claim 1, wherein the low reflectivity pattern overlaps with the color filter.

4. The light-emitting display device according to claim 1, wherein the low reflectivity pattern and at least one of the data lines and the gate lines are formed in the same layer by the same material.

5. The light-emitting display device according to claim 4, wherein the low reflectivity pattern is connected to or separated from the data line.

6. The light-emitting display device according to claim 4, wherein the low reflectivity pattern is connected to or separated from the gate line.

7. The light-emitting display device according to claim 1, wherein the low reflectivity pattern comprises a metal layer and a low reflectivity material layer located below the metal layer.

8. The light-emitting display device according to claim 1, wherein each of the plurality of sub-pixels includes a light-emitting device, the light-emitting device comprising a pixel electrode, a light-emitting layer, and a common electrode. The light-emitting area overlaps with the light-emitting device.

9. The light-emitting display device according to claim 8, wherein the low-reflectivity pattern overlaps with the pixel electrode. The color filter is located between the pixel electrode and the low reflectivity pattern.

10. The light-emitting display device according to claim 1, wherein each of the plurality of sub-pixels comprises a pixel circuit having at least one thin-film transistor and a capacitor. The non-light-emitting area includes: The first non-light-emitting area is provided with the pixel circuit; and a second non-light-emitting area located between adjacent sub-pixels among the plurality of sub-pixels.

11. The light-emitting display device according to claim 10, wherein the gate line extends in a first direction in the first non-light-emitting region. The data line extends in the second non-light-emitting area in a second direction intersecting the first direction.

12. The light-emitting display device of claim 11, wherein the low reflectivity pattern extends from the data line in the first direction and is configured to overlap with the light-emitting area.

13. The light-emitting display device according to claim 12, wherein one end of the low-reflectivity pattern is connected to the data line. The other end of the low-reflectivity pattern is electrically floating.

14. The light-emitting display device of claim 11, wherein the low reflectivity pattern is spaced apart from the data line, and the low reflectivity pattern is an island-shaped pattern extending in the light-emitting area in the first direction or the second direction.

15. The light-emitting display device of claim 11, wherein the low reflectivity pattern extends from the gate line in the second direction and is configured to overlap with the light-emitting area.

16. The light-emitting display device according to claim 15, wherein one end of the low-reflectivity pattern is connected to the data line. The other end of the low-reflectivity pattern is electrically floating.

17. The light-emitting display device of claim 11, wherein the low reflectivity pattern is spaced apart from the gate line, and the low reflectivity pattern is an island-shaped pattern extending in the light-emitting area in the first direction or the second direction.

18. The light-emitting display device of claim 8, further comprising a dam defining a light-emitting area for each of the plurality of sub-pixels. The dam is disposed between the pixel electrode and the light-emitting layer.

19. The light-emitting display device according to claim 18, wherein the embankment comprises at least one of a light-absorbing material and a black material.

20. The light-emitting display device according to claim 8 further includes a transmittance control film disposed on the rear surface of the substrate.

21. The light-emitting display device according to claim 20, wherein the transmittance control film comprises at least one of a transparent film and a light-absorbing film.

22. The light-emitting display device of claim 8, wherein the lower portion of the low-reflectivity pattern comprises a metal layer and a low-reflectivity material layer located below the metal layer, the reflectivity of the low-reflectivity material layer being lower than the reflectivity of each of the pixel electrode and the common electrode.

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