Design support system and integrated device

Abstract

The design support system includes: a design department that designs the wafer process and packaging process; a wafer process department that manages the wafer process; a packaging department that manages the packaging process for the wafer manufactured by the wafer process department; and an integration unit that obtains wafer process information measured in the wafer process from the wafer process department, obtains packaging process information measured in the packaging process from the packaging department, and provides design support information derived from the wafer process information and packaging process information to the design department.

Description

Technical Field

[0001] This invention relates to design support systems and integrated devices. Background Technology

[0002] In the past, general-purpose semiconductors were mass-produced and could be integrated into various products. Examples of general-purpose semiconductors include CPUs (Central Processing Units) used in personal computers. These traditional general-purpose semiconductors, based on the von Neumann architecture, were designed to improve performance through sequential processing.

[0003] According to Moore's Law, increasing the integration level of semiconductors is believed to reduce production costs, and the primary goal in the past was to increase the production volume of general-purpose semiconductors and reduce production costs. However, increasing the production volume of semiconductors requires huge investments in equipment. Therefore, fabless manufacturing, where operators primarily engaged in semiconductor design outsource semiconductor production to external operators, has become the mainstream approach.

[0004] Patent document 1 discloses a technique related to photolithography-based pattern optimization.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: US Patent No. 11,449,659 Summary of the Invention

[0008] With the development of AI (Artificial Intelligence) technology in recent years, semiconductors are being used in AI processing. However, due to the parallel processing involved in AI, general-purpose semiconductors are unsuitable. Therefore, the ideal is to manufacture dedicated semiconductors optimized for each AI application. However, dedicated semiconductors are semiconductors that can only be used in specific products; they will not function even if integrated into other products. Therefore, mass production of dedicated semiconductors is impractical, as it would incur enormous costs, even if it were possible.

[0009] With the miniaturization of semiconductors, not only has the TAT (Turn Around Time) of semiconductor manufacturing increased, but the design period has also lengthened due to the increasing complexity of semiconductor design rules and constraints. Therefore, when design problems are identified during semiconductor development, rework in design and manufacturing (prototype) requires enormous time and costs. Thus, there is a demand for methods to reduce semiconductor design rework.

[0010] In current semiconductor manufacturing methods, the operators who design semiconductors and those who manufacture them operate independently. Therefore, the optimal manufacturing conditions or reasons for failures that the semiconductor manufacturing operator only learns after manufacturing the semiconductor based on design information from the semiconductor design operator are not shared with the semiconductor design operator. Furthermore, even if optimal manufacturing conditions and reasons for failure are shared between operators, the semiconductor design operator does not know how to achieve optimal semiconductor design and simply repeats trial and error, thus wasting time in the design process. Additionally, even using the technology disclosed in Patent Document 1, time is still spent in the design process.

[0011] This invention was made in view of the following situation, and its purpose is to significantly reduce the time spent from semiconductor design to production.

[0012] The design support system of the present invention includes: a design unit for designing wafer processes for manufacturing wafers and packaging processes for manufacturing packages from wafers; a wafer process unit for managing wafer processes; a packaging unit for managing packaging processes for wafers manufactured using the wafer process unit; and an integration device for obtaining wafer process information measured in the wafer processes from the wafer process unit, obtaining packaging process information measured in the packaging processes from the packaging unit, and providing design support information derived from the wafer process information and the packaging process information to the design unit.

[0013] According to the present invention, design support information is provided based on information obtained through the manufacture of semiconductors, thereby significantly reducing the time spent from semiconductor design to production.

[0014] Other issues, structures, and effects not mentioned above will become clear through the following description of implementation methods. Attached Figure Description

[0015] Figure 1 This is an overall structural diagram illustrating an example of a semiconductor manufacturing process according to an embodiment of the present invention.

[0016] Figure 2 This is a diagram illustrating an example of a subsequent process in the packaging process according to one embodiment of the present invention.

[0017] Figure 3 This is a block diagram illustrating an example of the overall structure of a design support system according to one embodiment of the present invention.

[0018] Figure 4 This is a block diagram illustrating an example of the internal structure of an integrated device according to one embodiment of the present invention.

[0019] Figure 5This is a flowchart illustrating an example of an AI-supported design solution provided by a design department according to an embodiment of the present invention.

[0020] Figure 6 This is a graph illustrating the differences in data obtained in batch and single-piece processing according to an embodiment of the present invention through experiments.

[0021] Figure 7 This is a diagram illustrating the contents of data obtained in batch and single-piece processing according to an embodiment of the present invention.

[0022] Figure 8 This is a diagram showing the difference between the production cycle in the conventional manufacturing method and the production cycle in the manufacturing method involved in this embodiment.

[0023] Figure 9 This is a diagram illustrating a method of manufacturing a fully monolithic device according to one embodiment of the present invention.

[0024] Figure 10 This is a diagram illustrating an example of the operation of the guidance and management unit according to one embodiment of the present invention.

[0025] Figure 11 This is a diagram illustrating an example of a chip-based heterogeneous integration (heterogeneous) design according to one embodiment of the present invention.

[0026] Figure 12 This is a diagram illustrating an example of three processes involved in a one-in-one embodiment of the present invention that can shorten the production cycle of packaging.

[0027] Figure 13 This is a diagram illustrating an example of a variation in the production cycle during the packaging process according to one embodiment of the present invention. Detailed Implementation

[0028] Hereinafter, specific embodiments of the present invention will be described with reference to the accompanying drawings. In this specification and the accompanying drawings, repeated descriptions are omitted by using the same reference numerals to constituent elements having substantially the same function or structure.

[0029] [One implementation method]

[0030] <An example of a semiconductor manufacturing process>

[0031] Figure 1 This is an overall structural diagram illustrating an example of a semiconductor manufacturing process involved in one embodiment.

[0032] Semiconductor manufacturing processes are broadly divided into design processes, wafer processes (for manufacturing wafers), and packaging processes (for manufacturing packages from wafers). In this embodiment, the manufacturing technology used for design is referred to as MFD (Manufacturing for Design), distinguishing it from DFM (Design for Manufacturing), a conventional design technology used for manufacturing. MFD is a methodology that supports design based on data obtained in the wafer and packaging processes.

[0033] The design support system 10 involved in this embodiment (see below) Figure 3 In this embodiment, by repeatedly performing MFD and DFM, it is possible to achieve coordination and optimization of semiconductor design and manufacturing, namely DMCO (Design-Manufacturing Co-Optimization). As a result, in the design support system 10 according to this embodiment, the total cycle time from semiconductor design to packaging is halved.

[0034] In the design process, semiconductors and circuit configurations are designed. In this embodiment, a new design methodology supported by AI (Artificial Intelligence) models is provided to the applicant's customers. For example, by learning from large amounts of silicon data measured using various measuring devices in the wafer and packaging processes using an AI model, the following... Figure 4 The AI ​​models shown are trained to improve the performance of the PDK (Process Design Kit). Furthermore, in this embodiment, by using the trained AI models in the design process, the design work performed by the customer's designers is assisted, thus advancing the automation of semiconductor design.

[0035] A PDK (Product Design Kit) contains technical information required for semiconductor design, such as what kind of device models are available, what design rules should be followed, and what limiting elements should be extracted. Designers input this information into the PDK tool to design semiconductors. AI models then... Figure 1 The MFD shown is composed of a layered structure, which learns from silicon big data and assists designers in design by being guided by AI models.

[0036] (General wafer fabrication and packaging processes)

[0037] The wafer fabrication process and packaging process are divided into front-end processes and back-end processes. The front-end processes include the front-end process (FEOL) for forming components, the back-end process (BEOL) for forming wiring, and wafer characteristic inspection.

[0038] In a FEOL (Feed-Off Electrode-Laminated) process, the processes include, for example, cleaning, film deposition, photolithography, etching, ion implantation, and wafer inspection, which are repeated. In a BEOL (Beta-Off Electrode-Laminated) process, the processes include, for example, cleaning, film deposition, photolithography, etching, planarization, and wafer inspection for wafers manufactured via FEOL, which are repeated.

[0039] In the wafer inspection process, the electrical characteristics of the wafers manufactured via BEOL are checked. Once the wafer characteristic inspection is completed, the wafer is finished.

[0040] The subsequent processes include assembly and inspection. The assembly process includes dicing, die bonding, wire bonding, and molding of wafers that have passed characteristic inspections. The inspection process includes a final inspection of the semiconductor produced through molding. These assembly and inspection processes are performed in simple packaging processes based on the wire bonding of a single chip, as well as complex packaging processes that stack multiple chips. When the final inspection is completed, the packaged semiconductor (also called a chip) is finished.

[0041] (The wafer fabrication process and packaging process involved in this embodiment)

[0042] In wafer fabrication processes, there are generally two types: batch processing, where wafers within a batch have the same process, and monolithic processing, where wafers within a batch are processed one by one, allowing for changes in the process of each individual wafer. These two types are often combined. In the wafer fabrication process described in this embodiment, all processes are handled in a monolithic manner. Therefore, the time required to complete a batch can be reduced to less than the usual completion time. Furthermore, by performing prototypes by changing the conditions of each wafer, a larger amount of data can be accumulated in the same amount of time compared to batch processing processes, forming silicon big data. Silicon big data helps improve the wafer yield in the wafer fabrication process. Additionally, silicon big data is used to design AI models in the process (described later). Figure 4 The design of the AI ​​model 72) is based on learning (MFD). In addition, in the wafer fabrication process, by using a monolithic approach, the processing time (x) for a single wafer can be reduced to less than half of the previous time.

[0043] Currently, chip technology has been developed, and the packaging process has become a process of mounting multiple chips on a substrate by highly bonding multiple wafers, wafers and chips, and chips and chips to obtain multi-chip products. The combinations are very diverse and complex.

[0044] In the subsequent processing steps, conceptually, the wafer completed in the previous process is chip-based, mounted onto a substrate (such as a silicon substrate) with additional rewiring, and then mounted onto the final packaging substrate. Because the substrate with additional rewiring is mounted onto the packaging substrate, multiple chips with various functions are integrated and connected. Therefore, even if not all functions are integrated onto a single chip, equivalent functionality can be achieved by using a product with multiple packaging substrates that integrate chips with various functions.

[0045] Figure 2 This diagram illustrates an example of a downstream process in the packaging process corresponding to multi-chip packaging.

[0046] For example, a bumping process and a dicing process are performed on the wafer manufactured in the preceding processes. Additionally, a TSV (Through-Silicon Via) process, a redistribution layer formation process, and a bumping process are performed on the redistribution substrate. Next, a chip mounting process is performed to combine the monolithized chip from the dicing process with the redistribution substrate. After a sealing process and a bumping process, a substrate mounting process is performed on the packaging substrate. When the sealing process is further performed, a final inspection process is performed.

[0047] In the design process, heterogeneous (heterogeneous integration) design can be performed using chip technology based on design support information received from a chip technology platform that includes multiple IPs. In the semiconductor field, functional blocks constituting LSI (Large Scale Integration), such as CPUs, image processing circuits, and memory, are considered design assets, referred to as IP (Intellectual Property) cores or simply IP. In this specification, IP is described as a circuit element in semiconductor design. Various examples can be envisioned within this circuit element, such as simple standard cells, functional blocks of interfaces, or CPU cores. These will be discussed later. Figure 11 The core chip will be explained in detail later.

[0048] <Example of a Design Support System Structure>

[0049] Figure 3 This is a block diagram illustrating an example of the overall structure of the design support system 10 according to this embodiment. The design support system 10 includes an integration unit 1, a design unit 2, a wafer processing unit 3, and a packaging unit 4.

[0050] The integration unit 1 provides a platform that can be accessed arbitrarily from the design unit 2, the wafer process unit 3, and the packaging unit 4. Therefore, the integration unit 1 obtains wafer process information measured in the wafer manufacturing process from the wafer process unit 3, obtains packaging process information measured in the packaging process from the packaging unit 4, and provides design support information derived from the wafer process information and the packaging process information to the design unit 2.

[0051] Integrated device 1 uses wafer process information as silicon big data and packaging process information as packaging big data, and performs processing based on the following description. Figure 4 Design support information is generated based on the analysis of the design AI model 72 shown. In the analysis based on the design AI model 72, the correlations of various types of parameters based on silicon big data and packaging big data are determined. The design AI model 72 provides design support information, including optimal parameter combinations and values, to the design department 2.

[0052] Design Department 2 designs the wafer fabrication and packaging processes. By utilizing design support information provided by Integration Unit 1 and the design assistance functions of the AI ​​model, Design Department 2 can optimize semiconductor design, thus improving design convergence speed. Furthermore, Design Department 2 can access information obtained by designers while using the design assistance functions of the AI ​​model to design semiconductors, as well as information obtained by the AI ​​model itself while designing semiconductors.

[0053] The wafer process unit 3 has the function of managing the wafer process and manufactures wafers based on the design information designed by the design unit 2. The wafer process unit 3 sends the data measured by various measuring devices during the wafer process to the integration unit 1 as wafer process information.

[0054] The packaging unit 4 has the function of managing the packaging process for the wafer manufactured using the wafer processing unit 3. Based on the configuration information designed by the design unit 2, the packaging unit 4 performs a packaging process for the wafer manufactured using the wafer processing unit 3, which involves placing various chips onto the substrate and wiring between multiple chips. Furthermore, the packaging unit 4 sends data measured by various measuring devices during the packaging process to the integration unit 1 as packaging process information.

[0055] Figure 4 This is a block diagram illustrating an example of the internal structure of the integration device 1 according to this embodiment. The integration device 1 operates as a platform providing the functions of each part of the design unit 2. The integration device 1 includes a wafer process information collection unit 50, a packaging process information collection unit 60, a design process learning unit 70, and a dicing unit 75. Conventionally, relevant data is obtained from data acquired during the wafer process based on the engineer's knowledge. In this system, the design AI model 72 can extract new relevant data with high precision from a large amount of data that is beyond the capacity of engineers to handle.

[0056] The wafer process information collection unit 50 accumulates wafer process information acquired for each wafer manufactured in the wafer process and outputs the wafer process information to the design process learning unit 70. The wafer process information collection unit 50 includes a data acquisition unit 51, a feedback unit 52, and a wafer process DB (Data Base) 55.

[0057] The data acquisition unit 51 acquires a large amount of data for each wafer in the wafer process as wafer process information. The data acquired by the data acquisition unit 51 is accumulated in the wafer process DB55.

[0058] Feedback unit 52 outputs the data (wafer process information) read from wafer process DB55 to design process learning unit 70.

[0059] The packaging process information collection unit 60 accumulates packaging process information and outputs it to the design process learning unit 70. This packaging process information is acquired each time a chip cut from a wafer during the packaging process is packaged. The packaging process information collection unit 60 includes a data acquisition unit 61, a feedback unit 62, and a packaging process DB 65.

[0060] The data acquisition unit 61 acquires a large amount of data obtained from measurements of each packaged product in the packaging process as packaging process information. The data acquired by the data acquisition unit 61 is accumulated in the packaging process DB65.

[0061] Feedback unit 62 outputs the data (packaging process information) read from packaging process DB65 to design process learning unit 70.

[0062] The design process learning unit 70 has a design AI model 72, which calculates first design support information to support the design of the wafer process based on wafer process information, and calculates second design support information to support the design of the packaging process based on packaging process information. The design process learning unit 70 has a design database 71 and a design learning unit 73.

[0063] The DB71 is designed to accumulate wafer process information provided by the wafer process information collection unit 50 and packaging process information provided by the packaging process information collection unit 60.

[0064] In addition, the design database (DB71) is stored in the design AI model (72) used in the design process. The design AI model (72) has the function of supporting various designs in the design process. Therefore, the design AI model (72) provides the design department 2 with the functions of the generation department (21), the optimization department (22), the guidance department, and the management department (23).

[0065] As for the machine learning in the design of AI model 72, depending on the application of DMCO, any method among unsupervised, supervised, or reinforcement learning can be used. For example, in the optimization unit 22 and the guidance and management unit 23 described later, reward-based machine learning is more preferred when determining what wiring and design policy to use, so the possibility of using reinforcement learning is high.

[0066] For example, when the optimization unit 22 obtains the correlation between manufacturing data and electrical characteristics, supervised learning is used to provide the correct answer with the electrical characteristics as the output result. Unsupervised learning is used in processes such as the automatic classification of defect data by the optimization unit 22.

[0067] The machine learning in Design AI Model 72 is not limited to these machine learning methods.

[0068] The design learning unit 73 updates the design AI model 72 by performing machine learning and other methods based on the chip process information and packaging process information accumulated in the design DB25. The updated design AI model 72 is saved to the design DB71.

[0069] The slitting unit 75 sets the slitting range for the processes of the customer's designer and the personnel who manufacture the wafers according to their designs (e.g., the applicant's manufacturer). The slitting unit 75 can arbitrarily set and slit the slitting ranges for the designer's and the applicant's processes. In this embodiment, multiple processes included in the design process are slitted, and the design unit 2 assists the design performed by the customer's designer according to the slitting range. The slitting range will be described later. Figure 5 As shown in the image.

[0070] In the design department 2, as a function provided by the design AI model 72, there is a generator 21, an optimizer 22, a guide, and a management department 23.

[0071] The generation unit 21 has the function of generating the code required for the design based on the specifications described in natural language.

[0072] The optimization unit 22 performs the process of searching for the optimal solution of the combination of design parameters under various predetermined constraints. For example, the optimization unit 22 searches for the optimal solution of the combination by maintaining the clock frequency while reducing the leakage current, and when the optimal solution is obtained, it outputs the information to the guidance and management unit 23.

[0073] The guidance and management unit 23 provides at least one of first design support information and second design support information based on the combinatorial optimal solution, thereby guiding the designer's design and managing the design process. For example, the guidance and management unit 23 has the function of guiding the designer based on past design experience to accelerate the convergence of the current design's performance power area (PPA). PPA will be discussed later. Figure 7 The explanation is provided below.

[0074] The guidance function in the guidance and management section 23 is related to the overall design flow. To advance the various processes included in the design process, it guides the designer in a way that avoids repetitive steps, based on past experience. The management function in the guidance and management section 23 is the function of planning and managing the design itself. For example, when designing a chip of a certain specification, the guidance and management section 23 plans how to divide the System-on-Chip (SoC) into blocks to advance the design without bottlenecks.

[0075] Figure 5 This is a flowchart illustrating an example of an AI-supported design solution. The AI-supported design solution is provided to the customer using a design AI model 72 that performs actions within design unit 2.

[0076] In semiconductor design, the first step is to define the semiconductor requirements specification. Next, development planning is developed, followed by system-level design. After system-level design, front-end design (F / E design) and back-end design (B / E design) are implemented.

[0077] Front-end design encompasses everything from algorithm design to logic verification. In front-end design, after the designer creates the algorithm, for example, by rewriting it in C, high-level synthesis (High Level Synthesis) is performed, automatically generating a hardware description language (HMR) from the C-based action description as input. Additionally, after the designer performs system-level design, RTL (Register Transfer Level) design is conducted, using the HMR to implement logic circuits. Following RTL design or high-level synthesis, functional verification is performed, and after logic synthesis, logic verification is executed. After logic verification, the design returns to system-level design or proceeds to the next stage of back-end design.

[0078] In the later-stage design, based on the results of logic verification and test circuit insertion in the earlier-stage design, design planning is performed. After design planning, floor layout is designed. Following floor layout, physical verification and lithography verification are then performed.

[0079] In addition, after configuration and routing, static timing analysis and power rail analysis are performed. Signal integrity is also included in the power rail analysis. Power consumption analysis is also performed after configuration and routing. On the other hand, after inserting the aforementioned test circuits, test pattern generation is performed, and gate simulation is executed after configuration and routing. This concludes the content of each design element included in the later stages of the design.

[0080] The back-end design includes physical verification of configuration cabling, timing, and power analysis. Following the back-end design, [further steps are taken]. Figure 1The diagram illustrates the wafer fabrication and packaging processes. Specifically, after power supply resolution, samples produced through the wafer fabrication and packaging processes are shipped to verify their functionality. If the samples function correctly, mass production shipments are then made, following the wafer fabrication and packaging processes.

[0081] Figure 5 The AI-supported design solution shown is provided by Figure 4 The design AI model 72 shown is provided to the design department 2 and consists of three elements (generation department 21, optimization department 22, and guidance and management department 23).

[0082] Generation section 21 Figure 5 The area enclosed by the dashed line above indicates, for example, the system-level design, algorithm design, program description, and RTL design in the front-end design. The generation unit 21 automatically generates program-based code, etc.

[0083] Similarly, in optimization section 22... Figure 5 The area enclosed by the dashed line below indicates, for example, layout planning, configuration routing, physical verification, lithographic verification, static timing analysis, power supply analysis, power consumption analysis, test circuit insertion, test pattern generation, and gate-level simulation in the later stages of design. The optimization unit 22 uses the optimal conditions for each process to enable designers to perform designs based on these optimal conditions.

[0084] The guidance and management unit 23 enables the layered design optimization of short TAT (Turn Around Time) design involved in this embodiment. TAT refers to the time spent from the start to the completion of a certain process. There are also cases where the long period from the start of semiconductor design to the completion of manufacturing is set as TAT, and cases where the period from the start of design to the completion of design in the design process is set as TAT ​​as shown in this embodiment.

[0085] As in Figure 5 The right side shows (1) to (3) and the explanations already provided. The applicant and the client can arbitrarily divide the scope of responsibility. The division of the scope of responsibility is determined by the client's design capabilities and the client's business model. Figure 4 The shown section 75 manages the scope of the division.

[0086] For example, in Figure 5 In the segmentation shown in (1), the applicant makes full use of its manufacturing technology to undertake the overall design from development planning to front-end design and back-end design, and the applicant manufactures and ships samples or ships mass-produced products.

[0087] exist Figure 5 In the segmentation shown in (2), the client is responsible for everything from the development plan to the front-end design, while the applicant undertakes the back-end design, manufacturing and shipping of samples or mass-produced products. Clients in this situation are those who want to entrust the applicant with designs corresponding to the manufacturing technology, i.e., those with a heavy burden of back-end design.

[0088] exist Figure 5 In the segmentation shown in (3), although the customer has little design experience, but wants to manufacture products using semiconductors, the applicant undertakes the system-level design, and the applicant undertakes all subsequent processes.

[0089] In the past, various suppliers targeted Figure 5 Each block shown provides a variety of design tools. As design rules and constraints have become increasingly sophisticated in recent years, designs have become more complex and demanding, making it increasingly difficult for designers to manipulate the design tools used to implement their designs. Furthermore, in front-end design, there is a tendency to cram various functionalities into a single semiconductor in order to achieve as many functionalities as possible.

[0090] On the other hand, in the back-end design, physical design is performed. Therefore, back-end designers cram as many cells as possible into small areas of the chip, designing how to route them. As a result, back-end designers increasingly spend more time designing to implement the functions designed in the front-end.

[0091] on the other hand, Figure 5 The system-level design and algorithm design shown, and the rewriting using C language, can also be an automatic generation process of machine language generated by the design AI model 72, which parses specifications written in natural language. Furthermore, the design AI model 72 can also automatically perform various processes, including those in the later stages of design, considering various constraints to find the optimal combination of parameters and perform optimization.

[0092] Furthermore, by learning from various past designs or patterns, the design AI model 72 can judge the quality of a design. Therefore, the design AI model 72 has support functions such as suggesting the optimal combination of design tools to the designer so that the designer can make an optimal design.

[0093] according to Figure 5 The AI-supported design solution shown can halve the cycle time compared to conventional design methods. Furthermore, the AI-supported design solution in this embodiment can replicate the capabilities of skilled designers using a navigator. Therefore, even novice designers can design semiconductors in the same way as skilled designers.

[0094] In conventional design methodologies, the number of modifications (ECO: Engineering Change Order) in the final design stage increases, leading to prolonged design time. On the other hand, by using the AI-supported design solution described in this embodiment, the number of modifications can be significantly reduced, further shortening the time-to-action (TAT).

[0095] <Differences in data obtained in batch and single-chip processing>

[0096] Next, refer to Figure 6 and Figure 7 This explains the differences between the data obtained in the conventional manufacturing process and the manufacturing process involved in this embodiment, as well as the results derived from the data.

[0097] Figure 6 It is a graph that uses experiments to illustrate the differences in data obtained in batch and single-piece processing. Figure 6 The horizontal axis represents the number of parameters available during semiconductor production, and the vertical axis represents the experimental time. The parameters shown on the horizontal axis are values ​​obtained by assigning certain process conditions (such as temperature, pressure, flow rate, plasma power, etc.) (e.g., 850°C, 900°C, 950°C, etc., if it is temperature). The experimental time on the vertical axis refers to the time until a semiconductor manufactured under a certain process condition is obtained.

[0098] In batch processing, a large number of wafers are processed in the same way. Figure 6 The black dots represent the data obtained for each processing step. For example... Figure 6 The figure, denoted as "batch," shows how to create a linear curve by connecting four black dots.

[0099] On the other hand, in monolithic (in) Figure 6 In the text (referred to as "single-chip"), numerous white dots represent the data obtained for each chip during the manufacturing process.

[0100] In addition, from Figure 6 It can be seen that there is a difference between the data obtained in single-chip processing and the data obtained in batch processing. That is, in... Figure 6 In batch processing, the processing time is long, so in the same experimental time as single-chip processing, only 4 data points (black dots) are obtained. The data is arranged in a roughly linear pattern, so the curve shows a linear change. On the other hand, in single-chip processing, a large amount of data can be obtained in the same experimental time, so the curve shows a non-linear change.

[0101] Figure 7 This is a diagram showing the contents of the data obtained in batch and single-piece processing.

[0102] Figure 7 The upper illustration (1) shows a graph of PPA. The PPA graph shows the density distribution function of a certain characteristic parameter. The horizontal axis of the graph shows the characteristic variation. For example, the threshold voltage of a transistor has a characteristic variation due to manufacturing deviations. If the characteristic variation is high, the response is slow; if the characteristic variation is low, the response is fast.

[0103] The PPA is designed using various parameters of the PDK. As shown in equation (1), the PPA is represented by a function that takes multiple types of σ as variables.

[0104] PPA=f(···, σ, ···)…(1)

[0105] Here, σ represents the deviation of the most important design parameter. Design parameters are those set by the designer when designing the semiconductor. For example, σ is formed by values ​​that are directly related to the physical manufacturing of the product, such as the alignment accuracy of the device, the gas flow rate, and the furnace temperature. Ultimately, the PPA of the chip becomes a function of the manufacturing parameters. Manufacturing parameters are those set for the manufacturing device when manufacturing semiconductors. As shown in equation (2) below, σ is represented as a function of multiple manufacturing parameters m as variables.

[0106] σ=g(m1, m2,···)…(2)

[0107] Typically, designers perform various designs based on data such as σ, which introduces manufacturing parameters m1, m2, ..., and therefore do not concern themselves with physical information. Furthermore, σ represents the complex processes involved in semiconductor manufacturing, so designers may not even know how semiconductor manufacturing actually takes place.

[0108] exist Figure 7 The lower side is shown again. Figure 6 The graph shown. Figure 7 The curve (2) shows the data obtained in the batch format. Figure 7 The curve (3) shows the data obtained in a single core, i.e., a monolithic design.

[0109] As mentioned above, σ is a value determined by the correlation of manufacturing parameters. Designers aim to minimize the deviation of design parameters, and the faster the deviation is reduced, the better. The smaller the value of σ, the better. However, in batch data, this is achieved through... Figure 7 The tiny number m shown as black dots in the middle i The parameters are correlated, and a linear curve is plotted. Therefore, even if the designer uses the smallest σ for fitting, it is unclear whether σ is a local minimum. Furthermore, when oscillating around the local minimum of σ, the change in σ becomes larger, leading to instability in semiconductor manufacturing.

[0110] On the other hand, in monolithic systems, by... Figure 7 The large number of m's shown in white dots i The correlation of the parameters is plotted to create a nonlinear curve. In this curve, the minimum value of σ becomes explicit, making it easy to find the optimal solution. Therefore, Figure 4 The optimization unit 22 shown calculates the minimum value of a function that takes multiple manufacturing parameters as variables as the optimal solution for each of the wafer process information and packaging process information. The guidance and management unit 23 can guide the optimal solution to the designer.

[0111] Furthermore, the part indicated as incorrect in graph (3) is the value that was judged as the minimum of σ in graph (2) representing the data obtained in the batch process. In reality, it is not the minimum of σ, and the graph is skewed significantly. Therefore, it is easy to cause errors due to m. i A slight sway increases the change in σ. On the other hand, regarding the part represented as the optimal solution in the curve (3), since the slope of the curve is small, if that part is the minimum value of σ, then even if m i The change is not easily observed in σ.

[0112] As mentioned above, when designers fit the model at the wrong location without being aware of the optimal value of σ, the quality of the manufactured semiconductors deviates, resulting in a large number of semiconductors failing inspection in subsequent processes. In semiconductor design, finding the minimum value of σ as quickly as possible beforehand is crucial; therefore, it can be said that the advantages of using a monolithic approach to find the minimum value of σ far outweigh those of a batch approach.

[0113] Furthermore, designers can accelerate PDK validation by combining silicon big data and TCAD (Technology CAD) models. For example, firstly, designers use TCAD to predict the correlation between manufacturing and design parameters. Next, by utilizing design AI model 72 to analyze the MFD of silicon big data obtained in the all-monolithic process, designers can validate the correlation between manufacturing and design parameters using silicon big data.

[0114] Figure 8 This diagram illustrates the differences between the TAT used in conventional manufacturing methods and the TAT used in the manufacturing method described in this embodiment.

[0115] exist Figure 8 The conventional manufacturing method shown on the upper side illustrates a scenario where the front-end process (FEOL) is performed followed by the back-end process (BEOL) to complete the semiconductor manufacturing. The time from the start to the completion of such semiconductor manufacturing is referred to as the conventional TAT.

[0116] exist Figure 8In the manufacturing method of this embodiment shown on the lower side, the front-end process and the back-end process are started simultaneously to manufacture the semiconductor in parallel. That is, after both the front-end process and the back-end process are completed, the wafer generated in the front-end process and the wafer generated in the back-end process are bonded together to complete the semiconductor manufacturing.

[0117] The method of bonding wafers together in this way is called wafer bonding. Thus, in the manufacturing method according to this embodiment, the total time interval (TAT) can be drastically shortened compared to conventional methods. This reduction in TAT in the manufacturing method according to this embodiment is referred to as "TAT shortening".

[0118] Figure 9 This diagram illustrates the manufacturing method using a fully monolithic device (not shown) according to this embodiment. A fully monolithic device is a device used in both wafer fabrication and packaging processes.

[0119] exist Figure 9 The lower left corner shows the representation Figure 6 The graph shows the difference between data obtained in batch processing and monolithic processing. In the all-monolithic device according to this embodiment, a one-stop production process is performed for each wafer. In this one-stop production, the amount of silicon data obtained from the all-monolithic device is, for example, approximately 100 times the amount of data obtained previously. Therefore, the silicon data obtained from the all-monolithic device is referred to as silicon big data.

[0120] Silicon big data refers to data acquired using advanced measurement devices and sensors integrated into various systems. After extracting useful data, silicon big data is analyzed using an AI model (model 72).

[0121] In addition, packaging big data is data obtained using advanced measuring devices and sensors mounted on various devices installed in the packaging process.

[0122] The AI ​​model 72 is designed to evaluate high-precision correlations and characteristics by combining various types of data contained in silicon big data in a variety of ways, thereby achieving high-precision correlation and characterization.

[0123] In this embodiment, the following series of processes is referred to as MFD: data transfer from the manufacturing area to the design area, and the use of trends, optimal values, etc., obtained from the data obtained in the manufacturing area in the design area.

[0124] Silicon big data includes, for example, TEG (Test Element Group) data, sample data, and MP (Mass Production) data. TEG data, sample data, and MP data respectively include design data, electrical characteristic test data, and manufacturing data (measurement length, film thickness, defect information, etc.).

[0125] TEG data refers to data obtained using process verification masks from foundries that include TEG. TEG data is data obtained in device and process technologies, such as SPICE models and design rules, which are equivalent to TEG data. TEG data is used for device and process technologies within the design area.

[0126] Sample data is obtained using a motion verification mask based on the customer's design. Sample data is data obtained within the design environment, such as PDK and standard cell data.

[0127] MP data is data obtained using masks used in mass production of products. MP data is used for high-speed design convergence during the design process.

[0128] The SPICE model, design rules, PDK and standard cells in the design environment, and high-level design convergence in the design process are all interconnected and mutually influential.

[0129] exist Figure 9 The right side shows a comparison example of a PDK without MFD and a PDK with MFD. The PDK without MFD is used for designing using conventional silicon data, and the processing window as a PDK without MFD is shown.

[0130] In conventional silicon data processing, the small processing window size prevented high-precision data parsing. In contrast, PDKs with MFD (Mean Fiber Deposition) provide abundant silicon data (large silicon data), allowing for a larger processing window. Therefore, the PDK described in this embodiment improves data parsing accuracy.

[0131] Furthermore, regarding the deviations (margins) considered in the design, in a PDK without MFD, the deviations are small, and the design is constrained, resulting in numerous redesigns and slower convergence. On the other hand, in the PDK with MFD described in this embodiment, the deviations are large, and the design freedom is increased. Therefore, in a PDK with MFD, no redesigns are required, resulting in extremely fast convergence.

[0132] Figure 10 It is shown in Figure 5The diagram illustrates an example of the operation of the boot and management unit 23. Here, an example of the operation of the boot and management unit 23 in the chip design process is explained. The boot and management unit 23 detects the bottleneck design block from multiple design blocks obtained by dividing the overall design. Furthermore, the boot and management unit 23 modifies the bottleneck design block, making the time spent on completing the multiple design blocks designed in parallel equal, and guides the modified multiple design blocks to the designer. (See also...) Figure 10 The actions shown (1) to (4) illustrate the actions of the guidance and management department 23.

[0133] In action (1), the guidance and management unit 23 performs optimal design segmentation for high-speed design convergence. For example, the guidance and management unit 23 divides the whole design into multiple individual design blocks HLB1~HLBn.

[0134] In action (2), for each segmented design block, the guidance and management department 23 detects bottlenecks early and identifies strategies to eliminate them. For example, as in Figure 10 As shown in the circle with a single-dotted line, suppose the guidance and management unit 23 detects design block HLB3 as a bottleneck. In this case, the guidance and management unit 23 redesigns the design block in a way that eliminates the bottleneck. At this time, the shape of each design block is changed and the netlist is updated, etc.

[0135] In action (3), the guidance and management department 23 applies the design change. At this time, the guidance and management department 23 formulates the best plan for the design change. For example, the guidance and management department 23 changes the size and shape of the design block. In addition, the guidance and management department 23 makes an ECO to the design block HLB2 that will not have a significant impact on the manufacturing schedule.

[0136] In addition, the guidance and management unit 23 performs reconfiguration routing (re-PnR) for design block HLB4. As a result, the manufacturing time of block HLB3, which was detected as a bottleneck, is shortened, and the manufacturing time of each of design blocks HLB1 to HLBn is not affected by the bottleneck, so the overall design time of design blocks HLB1 to HLBn is shortened.

[0137] In action (4), the guidance and management department 23 verifies the entire chip. The entire chip refers to the combination of design blocks HLB1~HLBn in action (3) where the bottleneck has been eliminated. If the verification results in action (4) are good, the design information is fabricated and shared in the front-end and back-end processes.

[0138] Figure 11 This is a diagram illustrating an example of a chip-based heterogeneous integration (heterogeneous) design. Figure 11 The diagram illustrates a structural example of the core material library 80 and the core materials. The core material library 80 is, for example, constructed in... Figure 4 The design DB71 is shown. Therefore, the design process learning unit 70 has a chip library 80 that stores chip information. In the packaging process according to this embodiment, a platform consisting of chips composed of multiple circuit elements (IPs) is used.

[0139] exist Figure 11 The left side shows a group of IPs including specialized IPs that bring features to the customer's product, as well as AI accelerators, etc. IPs chosen by customers for their own designs are referred to as domain-specific IP groups 81. Figure 11 In this context, "IP Core1", "IP Core2", etc., are used to represent individual IPs contained in domain-specific IP group 81.

[0140] The IPs included in the domain-specific IP group 81 do not function as standalone products, so they require controller CPUs, memory interfaces, etc. These controller CPUs, memory interfaces, etc., are generally common, shared IPs, so this platform-based IP group is called the Platform IPs group 82. The Platform IPs group 82 is used as the foundation for the core components.

[0141] The kernel library 80 is a collection of existing kernels that can be combined according to customer applications. The kernel library 80 contains various IPs, including domain-specific IP groups 81 and basic IP groups 82. Customers can select any kernel from the kernel library 80.

[0142] Even for chips not stored in chip library 80, customers can design their own chips, differentiating them from those of other companies. By using chips selected from chip library 80, customers can determine the structure of their system-on-a-chip (SoC) to their own specifications early on. Therefore, customers can mount their custom-designed chips onto the semiconductor substrate.

[0143] For example, it is shown in Figure 11 The substrate 85 shown on the right is equipped with domain-specific IPs 81a and 81b and a basic IP 82a obtained from the chip library 80. Additionally, an example is shown where a domain-specific IP 81b obtained from the chip library 80, a customer-manufactured domain-specific IP 81c, and a basic IP 82a are mounted on a substrate 86. Thus, a common basic IP 82a is mounted on substrates 85 and 86, while existing chips are mounted in combination on substrate 85. Furthermore, existing chips and new chips are mounted in combination on substrate 86.

[0144] Information about the chips mounted on substrates 85 and 86 is stored in the chip library 80, such as in Figure 11As indicated by the arrow below, this information is also fed back to the package design process (MFD). Therefore, the design unit 2 can inform the designer of the optimal chip combination, supporting chip design. For example, the guidance and management unit 23 guides the combination of basic circuit elements (basic IP group 82) and specialized circuit elements (domain-specific IP group 81) based on the chip combination information accumulated in the chip library 80. Therefore, whereas previously determining circuit elements through trial and error was time-consuming, in this embodiment, the combination of circuit elements guided by the guidance and management unit 23 is determined early on.

[0145] Figure 12 This diagram illustrates three examples of TAT processes that can shorten the packaging process.

[0146] exist Figure 12 In semiconductors, the interposer is formed by wiring on inorganic materials such as silicon using semiconductor front-end processing techniques. Multiple chips are connected by mounting multiple chips on the interposer.

[0147] In the packaging process involved in this embodiment, the following is used: Figure 12 The techniques shown include LDI (Laser Direct Imager) exposure (maskless exposure technology), chip size standardization, and parallel integration. As a maskless exposure technology, there is, for example, maskless direct drawing technology that directly draws circuits by irradiating a laser. Furthermore, as for chip size standardization and parallel integration, there are techniques such as using independent two-dimensional or three-dimensional packaging technologies.

[0148] Two-dimensional packaging technology is a technology that arranges multiple chips on a plane, while three-dimensional packaging technology is a technology that arranges multiple chips not only on a plane but also in the height direction.

[0149] Furthermore, useful information obtained from the packaging process is extracted and sent to the design process for learning (MFD). The optimization unit 22 optimizes maskless direct drawing of the interposer in the packaging process, standardization of the interposer chip size, mounting of at least one chip in the interposer, and fabrication of the packaging substrate. The guidance and management unit 23 provides design support by guiding the designer with optimization information. Therefore, designers can easily design semiconductors based on the optimization information.

[0150] Figure 12 Explanatory Figure (1) shows an example of a maskless exposure technique for forming circuit patterns on a substrate. On the left side of Explanatory Figure (1), an example of conventional step exposure is shown. In step exposure, a wiring pattern 92 is formed on the upper surface of an interposer 91 using a photomask 93. The wiring pattern 92 formed by the photomask 93 is identical in all locations.

[0151] On the right side of explanatory figure (1), an example of LDI exposure according to this embodiment is shown. LDI exposure is one of the maskless exposure techniques for directly drawing wiring patterns by irradiating the upper surface of the interposer layer 91 with a laser 95. According to the design unit 2 (see reference 2) Figure 3 The 3D CAD data of the design is used to illuminate the interposer layer 91 with a laser 95. The laser 95 can change the wiring pattern 94 for each partition of the interposer layer 91.

[0152] Figure 12 Explanatory Figure (2) shows an example of standardizing the chip size of the interposer 91. The chip size of the interposer 91 is standardized, for example, in the form of a mm × b mm. In this embodiment, by standardizing the chip size, it is not necessary to manufacture interposers 91 of various sizes, so the setting of the transfer mechanism of the interposer 91, etc., can be unified.

[0153] Figure 12 Explanatory Figure (3) shows an example of parallel integration of packaged devices. In the wafer manufacturing shown in Explanatory Figure (3), for example, a case of manufacturing 3 wafers is shown. In the interposer manufacturing shown in Explanatory Figure (3), a defective portion 96 in which a defect occurs in a part of the wiring pattern formed on the interposer 91 is indicated by an × mark. In the conventional interposer manufacturing shown on the left side of the interposer manufacturing, the defective portion 96 is retained as is. On the other hand, in the interposer manufacturing according to this embodiment, multiple chips that are determined to be qualified in wafer manufacturing are mounted on the qualified portion 97 that avoids the defective portion 96.

[0154] In the package substrate manufacturing process illustrated in Figure (3), a package substrate 98 is manufactured. The package substrate 98 is typically fabricated on a substrate formed of an organic material using semiconductor back-end processing techniques. At least one chip integrated into an interposer layer 91 is mounted on the package substrate 98 and packaged.

[0155] exist Figure 12 In the conventional packaging substrate manufacturing shown on the left side of the explanatory figure (3), the relationship between the interposer manufactured in the interposer manufacturing and the defective parts is not visible. On the other hand, in the packaging substrate manufacturing according to this embodiment, the qualified parts 97 in the interposer 91 manufactured in the interposer manufacturing are mounted onto the packaging substrate 98 as is.

[0156] Figure 13 This is a diagram illustrating an example of TAT variation during the packaging process.

[0157] exist Figure 13The top side shows an example of homogeneous integration. In homogeneous integration, all its functions are integrated on a single silicon chip, so the TAT becomes longer.

[0158] exist Figure 13 The lower side shows an example of heterogeneous integration. In heterogeneous integration, functionally segmented cores are manufactured in parallel, and these cores are integrated in an assembly step.

[0159] like Figure 13 As shown, for example, the CPU (x nm), memory (y nm), and I / O (z nm) are manufactured in parallel. The process for the CPU (x nm), which has the longest manufacturing time, is called the wafer MFG step. Furthermore, regarding the interposer, manufacturing begins at the same timing as the manufacturing of the heterogeneous integration components. The interposer manufacturing process is called the interposer MFG step. The processes performed in the interposer MFG step... Figure 12 The standardization of (1) exposure processing and (2) chip size described herein helps to shorten the processing time of the interposer MFG step. The processing time of the interposer MFG step is shorter than that of the wafer MFG step.

[0160] An integration step is performed after the wafer MFG (Mechanical Fabrication and Assembly) step. In the integration step, the individual chips are integrated in parallel on the interposer layer. Therefore, in the packaging process, [the integration process is repeated]. Figure 12 The parallel integration described in (3) helps to shorten the processing time of the integration step. Therefore, the TAT based on heterogeneous integration is shortened compared to homogeneous integration.

[0161] In the design support system 10 described in one embodiment above, the integration unit 1 obtains wafer process information from the wafer process unit 3 and packaging process information from the packaging unit 4. The design AI model 72 of the integration unit 1 analyzes the wafer process information and packaging process information, and provides the design unit 2 with information such as the optimal conditions for parameters in each process as design support information. The design unit 2 provides the designer with design support information suitable for semiconductor design, supporting the design of each process in semiconductor manufacturing. The designer's trial and error time in the design process is reduced, and the design time can be shortened.

[0162] Figure 4 The generation unit 21 of the design unit 2 shown has the function of generating the code required for the design based on the specifications described in natural language, so the designer can focus on describing the specifications in natural language. Therefore, compared to the previous situation where the designer parses the specifications to generate the code himself, code that appropriately reflects the specifications can be obtained automatically.

[0163] The optimization unit 22 of the design unit 2 optimizes each process included in the wafer process and the packaging process based on the design support information received from the integration unit 1. The design AI model 72 involved in this embodiment calculates the correlation and tendency of various manufacturing parameters based on the large amount of silicon data obtained in the monolithic process, thereby obtaining the optimal solution.

[0164] The wafer fabrication and packaging processes designed by Design Department 2 are optimized, eliminating unnecessary and repetitive processing during actual semiconductor manufacturing. Therefore, designers do not need to redesign the semiconductors or processes, shortening the time-to-application (TAT) until design completion.

[0165] Furthermore, the design department 2 and management department 23 provide guidance to designers based on past design experience, aiming to accelerate the convergence of the power product average (PPA) of the current design. Therefore, designers are able to find the optimal solution that minimizes the deviation of design parameters, thus accelerating the design of semiconductors that become qualified products.

[0166] In addition, Figure 10 In the chip design process illustrated, potential bottlenecks in the segmented design blocks are identified at an early stage. These bottlenecks are then eliminated by modifying the shape of the design blocks, among other things. As a result, the manufacturing time of the segmented design blocks is evened out, and the time to manufacture the entire chip is significantly reduced compared to previous manufacturing processes.

[0167] In addition, Figure 11 The chip library 80 shown contains domain-specific IP groups 81 and basic IP groups 82. Designers can select any chip from the chip library 80 and combine at least one chip on the substrate for design. Therefore, the design freedom of the chips can be improved.

[0168] In addition, such as Figure 12 and Figure 13 As shown, in the packaging process, the wiring pattern is directly drawn by irradiating the interposer with a laser, the chip size of the interposer is standardized, and parallel integration is performed. Therefore, in the packaging process, the TAT based on heterogeneous integration, as described in this embodiment, can be shortened compared to the conventional TAT based on homogeneous integration.

[0169] Furthermore, various manufacturing devices in the wafer processing unit 3 and the packaging unit 4 can be configured in a virtual space, and the manufacturing devices in the virtual space can be simulated based on the aforementioned silicon big data. In this simulation, the integration unit 1 can also obtain information from the manufacturing devices in the virtual space that are designed based on the design AI model 72 of the integration unit 1, as well as information about the virtual wafer, etc. By repeatedly performing simulations, foreseeable defects can be identified before actual wafer manufacturing, bottleneck processes can be extracted, and the design accuracy of the design unit 2 can be further improved.

[0170] Furthermore, the present invention is not limited to the above-described embodiments. Various other applications and modifications can be adopted as long as they do not depart from the spirit of the invention as described in the claims.

[0171] For example, the system structure has been described in detail and specifically in the above embodiments for the purpose of easily understanding and illustrating the present invention, and is not necessarily limited to having all the structures described. In addition, it is possible to add, delete, or replace other structures in a part of the structure of this embodiment.

[0172] Additionally, regarding control lines and information lines, only the parts deemed necessary for the description are shown; from a product perspective, not all control lines and information lines may be shown. It can also be assumed that almost all structures are actually interconnected.

[0173] (Explanation of reference numerals in the attached image)

[0174] 1: Integrated Unit; 2: Design Department; 3: Wafer Processing Department; 4: Packaging Department; 10: Design Support System; 21: Production Department; 22: Optimization Department; 23: Guidance and Management Department; 50: Wafer Processing Information Collection Department; 60: Packaging Processing Information Collection Department; 71: Slitting Department; 80: Chip Library; 81: Domain-Specific IP Group; 82: Basic IP Group; 91: Intermediate Layer.

Claims

1. A design support system, comprising: The design department designs the wafer manufacturing process and the packaging process for manufacturing a package from the wafer. The wafer processing department manages the wafer processing steps. The packaging department manages the packaging process for the wafer manufactured by the wafer processing department; and The integrated device obtains wafer process information measured in the wafer process from the wafer process unit, obtains packaging process information measured in the packaging process from the packaging unit, and provides design support information derived from the wafer process information and the packaging process information to the design unit.

2. The design support system according to claim 1, wherein, The integrated device includes: The wafer process information collection unit accumulates wafer process information for each wafer manufactured in the wafer process; A packaging process information collection unit accumulates packaging process information, which is acquired each time a chip cut from the wafer during the packaging process is packaged; and The design process learning unit has a design AI model. The design AI model calculates first design support information to support the design of the wafer process based on the wafer process information output from the wafer process information collection unit, and calculates second design support information to support the design of the packaging process based on the packaging process information output from the packaging process information collection unit.

3. The design support system according to claim 2, wherein, The design AI model has the following characteristics: The generation department generates the code required for the design based on the specifications described in natural language. The optimization department searches for the optimal solution for the combination of design parameters under predetermined constraints. as well as The guidance and management department, based on the combined optimal solution, provides at least one of the first design support information and the second design support information, thereby guiding and managing the design. The design department is provided with the function of the design AI model.

4. The design support system according to claim 3, wherein, The optimization unit, for each of the wafer process information and the packaging process information, finds the minimum value of a function that uses multiple manufacturing parameters as variables as the optimal solution. The guidance and management department guide the optimal solution.

5. The design support system according to claim 4, wherein, The guidance and management department detects the bottleneck design blocks from the multiple design blocks obtained by dividing the overall design, modifies the bottleneck design blocks, and makes the time spent until the multiple design blocks designed in parallel become equal, guiding the modification of the multiple design blocks.

6. The design support system according to claim 4, wherein, The design process learning unit has a core library that stores core information. The guidance and management unit guides the combination of basic circuit elements and specialized circuit elements based on the combination information of the cores accumulated in the core library.

7. The design support system according to claim 6, wherein, The optimization unit optimizes the maskless direct drawing of the interposer layer in the packaging process, the standardization of the chip size of the interposer layer, and the mounting of the chip in the interposer layer and the manufacturing of the packaging substrate. The guidance and management department guidance are optimized information.

8. An integrated device, wherein, The wafer process unit, which manages the wafer manufacturing process, obtains wafer process information measured in the wafer process. The packaging unit, which manages the packaging process for the wafer manufactured by the wafer process unit, obtains packaging process information measured in the packaging process. Design support information derived from the wafer process information and the packaging process information is provided to the design unit that designs the wafer process and the packaging process, wherein the packaging process is the process of manufacturing a package from the wafer.

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