A method and apparatus for failure analysis of power chips

Abstract

This invention discloses a failure analysis method and apparatus for power chips. The failure analysis method includes: locating the failure location on the power chip; obtaining a diffraction image of the power chip using X-ray diffraction, and determining the spatial location of the crystal defect within the chip based on the contrast difference in the diffraction image; and matching the spatial location of the crystal defect with the failure location in the same spatial reference coordinate system to improve the accuracy and efficiency of failure mechanism judgment.

Description

Technical Field

[0001] This invention relates to the field of power chip testing technology, and more particularly to a method and apparatus for power chip failure analysis. Background Technology

[0002] In existing power chip failure analysis workflows, it is typically necessary to first destructively peel off or prepare thin-film samples from suspected faulty areas, and then use microscopy to observe the microscopic morphology or atomic-level structure to determine the cause of failure, such as film cracking, metal residue, gate oxide breakdown, or crystal defects. Since the root cause of failure can often only be definitively confirmed after directly accessing the failure site and obtaining its actual morphology and structural information, this process is highly dependent on destructive analysis. For crystal defects, their extremely small size, weak signal, and complex characterization further exacerbate the analytical difficulty, not only being time-consuming and labor-intensive but also significantly increasing the overall analysis cost. Summary of the Invention

[0003] This invention provides a failure analysis method and apparatus for power chips, which improves the accuracy and efficiency of failure mechanism determination.

[0004] In a first aspect, embodiments of the present invention disclose a failure analysis method for power chips, comprising: Locate the failure point on the power chip; The diffraction image of the power chip is obtained by X-ray diffraction, and the spatial location of the crystal defect within the chip is determined based on the contrast difference in the diffraction image. In the same spatial reference coordinate system, the spatial location of the crystal defect is matched with the failure location.

[0005] Optionally, the diffraction image of the power chip is obtained using X-ray diffraction, including: Based on the substrate material type of the power chip and the type of crystal defect to be detected, the wavelength of the X-ray source and the target crystal plane index for diffraction imaging are preset. Diffraction imaging is performed based on the wavelength of the X-ray source and the target crystal plane index to obtain the diffraction image.

[0006] Optionally, the X-ray diffraction method includes at least one of X-ray diffraction topology and synchrotron radiation X-ray topology.

[0007] Optionally, locating the failure location on the power chip includes: The failure location on the power chip is located using physical location methods; the physical location methods include at least one of emission microspectroscopy analysis, beam-induced resistance change and indium antimonide infrared thermal imaging.

[0008] Optionally, after determining that the failure location is caused by the crystal defect, the method further includes: The remaining failure sites are subjected to destructive sample preparation to form transmission electron microscopy (TEM) or scanning electron microscopy (SEM) samples; The crystal defects are analyzed using microscopic characterization techniques to obtain the defect types corresponding to the remaining failure locations, wherein the microscopic characterization techniques include at least one of transmission electron microscopy, scanning electron microscopy, and atomic force microscopy.

[0009] Optionally, before locating the failure site on the power chip, the following steps are included: Electrical tests are performed on the power chip to determine the type of electrical failure of the power chip; After analyzing the crystal defects using microscopic characterization techniques, the process also includes: Based on the defect type and the electrical failure type, a corresponding failure physics model is constructed. The failure physics model is used to characterize the mapping relationship between the defect type and the electrical failure type.

[0010] Optionally, the crystal defect includes at least one of screw dislocations, basal plane dislocations, edge dislocations, and slip dislocations.

[0011] Secondly, embodiments of the present invention provide a failure analysis apparatus for a power chip, comprising: The positioning unit is used to locate the failure location on the power chip; A diffraction unit is used to obtain a diffraction image of the power chip using X-ray diffraction, and to determine the spatial location of crystal defects within the chip based on the contrast differences in the diffraction image. The matching unit is used to match the spatial location of the crystal defect with the failure location in the same spatial reference coordinate system.

[0012] Optionally, the diffraction unit includes: The parameter preset subunit is used to preset the wavelength of the X-ray source and the target crystal plane index for diffraction imaging based on the substrate material type of the power chip and the type of crystal defect to be detected. The test subunit is used to perform diffraction imaging based on the wavelength of the X-ray source and the target crystal plane index to obtain the diffraction image.

[0013] Optionally, the failure analysis device for the power chip also includes: An electrical testing unit is used to perform electrical tests on the power chip to determine the type of electrical failure of the power chip; The detection unit is used to perform destructive sample preparation on the remaining failure locations to form transmission electron microscope (TEM) samples or scanning electron microscope (SEM) samples. An analysis unit is used to analyze the crystal defects using microscopic characterization techniques to obtain the defect types corresponding to the remaining failure locations, wherein the microscopic characterization techniques include at least one of transmission electron microscopy, scanning electron microscopy, and atomic force microscopy. The model unit is used to construct a corresponding failure physics model based on the defect type and the electrical failure type. The failure physics model is used to characterize the mapping relationship between the defect type and the electrical failure type.

[0014] This invention provides a failure analysis method for power chips. By introducing non-destructive X-ray diffraction before destructive analysis and spatially matching it with the localization results, the possibility of crystal defects as the root cause of failure can be confirmed or ruled out at an early stage. This achieves direct, in-situ localization of crystal defects, reduces the number of slices and sample preparations, lowers analysis costs, and avoids the loss of original defect information caused by destructive operations, thereby improving the accuracy and efficiency of failure mechanism judgment. Attached Figure Description

[0015] Figure 1 A flowchart illustrating a failure analysis method for a power chip provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a diffraction test structure provided in an embodiment of the present invention; Figure 3 A flowchart illustrating another failure analysis method for power chips provided in an embodiment of the present invention; Figure 4 A comparative schematic diagram of hotspot locations and diffraction images provided for embodiments of the present invention; Figure 5 A flowchart illustrating another failure analysis method for power chips provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of another power chip failure analysis device provided in an embodiment of the present invention. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] Figure 1This is a flowchart illustrating a failure analysis method for a power chip according to an embodiment of the present invention. This embodiment is applicable to failure analysis of power chips. The method can be executed by a failure analysis device for power chips, which can be implemented in hardware and / or software. The method specifically includes the following steps: S110, Locate the failure position on the power chip; Specifically, a power chip is the exposed semiconductor device body after removing the packaging shell, typically including structures such as source, drain, gate, and substrate. For example, non-destructive or minimally invasive physical localization methods can be used to test the power chip and locate the two-dimensional or three-dimensional coordinates of one or more suspected failure points distributed within the power chip, i.e., the failure location. Optionally, physical localization methods may include: emission microscopy (EMMI), which locates hotspots by detecting photons generated during device operation due to carrier recombination or avalanche effects; beam-induced resistance change (OBIRCH), which uses laser scanning to induce local resistance changes to locate short circuits or leakage paths; and indium antimonide (InSb) infrared thermal imaging, which identifies high-power areas by detecting Joule heat distribution. For instance, in this embodiment of the invention, by capturing weak photon signals generated by carrier recombination or avalanche breakdown during the power chip's operation using EMMI, abnormal bright spots can be located, and these locations are the failure locations of the chip.

[0018] S120. The diffraction image of the power chip is obtained by X-ray diffraction, and the spatial location of the crystal defect in the chip is determined based on the contrast difference in the diffraction image. Specifically, X-ray diffraction is an analytical method that utilizes the diffraction effect that occurs when electromagnetic waves or particle streams, such as X-rays, neutrons, and electrons, pass through periodic structures like crystals to detect the microstructure of matter. The advantage of X-ray diffraction is that it allows for structural analysis without destroying the sample. For example, in this embodiment of the invention, the X-ray diffraction method can employ either X-ray diffraction topology (XRDI) or synchrotron radiation X-ray topology (SXRT), both of which are non-destructive imaging techniques based on the interaction between X-rays and the crystal lattice. Figure 2 This is a schematic diagram of a diffraction test structure provided in an embodiment of the present invention. See also... Figure 2 In this embodiment of the invention, X-ray diffraction topology can be used. When X-rays emitted from the light source 2 pass through the semiconductor substrate of the power chip 1, a strong and uniform diffraction signal is generated in the perfect lattice region, while the diffraction conditions deviate due to local lattice distortion in the region with crystal defects. This results in a contrast difference in the diffraction image on the receiver 3, typically manifested as a weakened signal and a darker image in the defect region. By selecting diffraction crystal plane indices that are sensitive to specific defects, the imaging contrast can be enhanced. Furthermore, by combining sample rotation, multi-angle projection, or tomographic reconstruction algorithms, the three-dimensional spatial positioning of crystal defects within the chip can be achieved.

[0019] S130. Under the same spatial reference coordinate system, match the spatial location of crystal defects with the location of failure.

[0020] Specifically, to achieve effective data comparison, a unified spatial reference coordinate system can be established. This coordinate system can be constructed based on the external geometric features of the power chip, such as stable and easily identifiable physical benchmarks like pad edges, alignment marks, scribe lines, or package pins. Through image registration, the coordinates of the failure location and the crystal defect coordinates from X-ray diffraction imaging are transformed to the same coordinate system. If the spatial location of the crystal defect and the chip failure location coincide within the spatial error tolerance, this is considered a matching condition, allowing for a reasonable inference that the initially located failure location was caused by the crystal defect. Therefore, a direct correlation between failure and crystal defect can be established without destructive analysis, significantly improving the efficiency and accuracy of failure analysis.

[0021] This invention provides a failure analysis method for power chips. By introducing non-destructive X-ray diffraction before destructive analysis and spatially matching it with the localization results, the possibility of crystal defects as the root cause of failure can be confirmed or ruled out at an early stage. This achieves direct, in-situ localization of crystal defects, reduces the number of slices and sample preparations, lowers analysis costs, and avoids the loss of original defect information caused by destructive operations, thereby improving the accuracy and efficiency of failure mechanism judgment.

[0022] Figure 3 A flowchart of another power chip failure analysis method provided in this embodiment of the invention is shown below. Figure 3 ,include: S210, Locate the failure location on the power chip; S220. Based on the substrate material type of the power chip and the type of crystal defect to be detected, preset the wavelength of the X-ray source and the target crystal plane index for diffraction imaging. Specifically, the substrate material of power chips is typically a semiconductor crystal material, commonly including silicon and silicon carbide. Different materials have different lattice constants, crystal structures, and defect behaviors. Crystal defect types are anomalies in the microstructure of a crystal that deviate from the ideal periodic arrangement. These mainly include point defects, such as vacancies and impurities; line defects, such as slip dislocations, screw dislocations, edge dislocations, and basal plane dislocations; and plane defects, such as stacking faults and stacking faults. Different types of defects have different sensitivities to the diffraction response of a specific crystal plane. In X-ray diffraction, the wavelength of the X-ray source can affect the diffraction angle and imaging resolution. Different crystal planes have different diffraction contrast sensitivities to different types of crystal defects. Therefore, for the detection of different types of crystal defects, the wavelength of the X-ray source and the target crystal plane index can be set by combining factors such as imaging resolution, diffraction contrast sensitivity, etc. For example, Table 1 shows the X-ray diffraction parameters for different substrate material types and crystal defects. Referring to Table 1, the target material for the source can be a molybdenum target or a copper target, and the exposure time of the X-ray camera is dynamically adjusted according to the signal-to-noise ratio to meet the requirements for clear imaging.

[0023] Table 1 shows the X-ray diffraction parameters for different substrate material types and crystal defects. S230. Diffraction imaging is performed based on the wavelength of the X-ray source and the target crystal plane index to obtain diffraction images.

[0024] Specifically, after presetting the X-ray wavelength λ and the target crystal plane indices, the power chip is placed in the X-ray beam path, and the sample orientation is adjusted to satisfy the Bragg diffraction conditions of the selected (hkl) crystal plane, i.e., the incident angle θ satisfies the Bragg equation. After the X-rays penetrate the chip substrate, the receiver records the diffraction intensity distribution in the reflection mode, generating a diffraction image. For complex three-dimensional defects, the spatial distribution of the defects can also be obtained by rotating the sample or acquiring data from multiple angles, combined with tomographic reconstruction algorithms.

[0025] S240. Under the same spatial reference coordinate system, match the spatial location of crystal defects with the location of failure.

[0026] In this embodiment of the invention, for example, the X-ray diffraction method for silicon carbide MOSFET chips can be X-ray diffraction morphology. In step S210, the hot spot is located in the gate finger region at the center of the chip by infrared thermal imaging of indium antimonide (InSb). In the X-ray diffraction method, the diffraction conditions are set as follows: the light source target material is a molybdenum target, the corresponding light source wavelength is 0.071nm, the target crystal plane index is hkl=0016, the X-ray incident angle is 34°, the diffraction exit angle is 34°, and the X-ray camera exposure time is 1200s for diffraction imaging. Figure 4This is a comparative schematic diagram of the hotspot location and diffraction image provided in an embodiment of the present invention, where the left side shows the location of the hotspot and the right side shows the diffraction image. A screw dislocation defect was obtained at the same gate finger location, therefore it can be determined that the failure at this point is related to a screw dislocation. Further imaging was performed using different diffraction conditions to test for edge dislocations and base plane dislocations; neither of these two types of defects was found near the hotspot.

[0027] Figure 5 A flowchart of another power chip failure analysis method provided in this embodiment of the invention is shown below. Figure 5 ,include: S310. Perform electrical tests on the power chip to determine the type of electrical failure of the power chip; Specifically, electrical testing, without damaging the power chip structure, involves applying voltage, current, or frequency excitation to the source, drain, and gate to measure key electrical parameters of the power chip, such as leakage current, breakdown voltage, on-resistance, and threshold voltage. This allows for the identification of abnormal data that deviates from normal specifications. Based on the abnormal data, the corresponding electrical failure type can be determined, including but not limited to open circuit, short circuit, excessive leakage current, parameter drift, or dynamic performance degradation. Identifying the current electrical failure type of the power chip through electrical testing provides electrical parameter basis for subsequent defect localization, improving the targeting of data analysis.

[0028] S320, locate the failure point on the power chip; S330. The diffraction image of the power chip is obtained by X-ray diffraction, and the spatial location of the crystal defect in the chip is determined based on the contrast difference in the diffraction image. S340. Under the same spatial reference coordinate system, match the spatial location of crystal defects with the location of failure.

[0029] S350. Perform destructive sample preparation on the remaining failure sites to form transmission electron microscope (TEM) samples or scanning electron microscope (SEM) samples. Specifically, after comparing the failure location with the diffraction image, failure locations that could not be confirmed through crystal defect matching still exhibit electrical anomalies and require further analysis. Irreversible processes such as local cutting, thinning, and polishing of the power chip are then performed to create transmission electron microscopy (TEM) or scanning electron microscopy (SEM) samples suitable for microscopic observation. Although this step involves destructive operations, it achieves targeted sample preparation at the failure location, avoiding blindly cutting large areas and significantly improving the efficiency and success rate of subsequent microscopic analysis.

[0030] S360. Analyze crystal defects using microscopic characterization techniques to obtain the defect types corresponding to the remaining failure locations.

[0031] Specifically, microscopic characterization techniques are high-resolution instrumental methods used to observe the microstructure, composition, or electrical properties of materials. Microscopic characterization techniques include at least one of transmission electron microscopy (TEM), scanning electron microscopy (SEM), and atomic force microscopy (AFM). TEM utilizes high-energy electrons to penetrate ultrathin samples, resolving atomic arrangements, dislocation core structures, grain boundaries, and microprecipitates. SEM scans the sample surface and collects secondary or backscattered electrons, providing information on micron- to nanometer-scale surface morphology, cracks, pores, or metal migration. AFM uses the interaction forces between a probe and the sample surface to map the three-dimensional surface morphology, suitable for detecting insulating materials or surface steps and stress concentration areas.

[0032] In this embodiment of the invention, the prepared sample is observed using a transmission electron microscope, a scanning electron microscope, or an atomic force microscope. For example, under a transmission electron microscope, through bright-field images, dark-field images, or high-resolution lattice images, the orientation of dislocation lines, stacking fault planes, or local amorphous regions can be clearly identified. By combining image features with a known defect database, the specific defect type corresponding to the failure location can be determined.

[0033] S370. Based on the defect type and combined with the electrical failure type, construct the corresponding failure physics model. The failure physics model is used to characterize the mapping relationship between the defect type and the electrical failure type.

[0034] Specifically, failure physics models are used to describe the coupling relationship between defect types and electrical failure types. For example, line defects such as dislocations typically cause device leakage and parameter drift, while planar defects such as stacking faults, if present below a conductive channel, can cause device breakdown and even complete failure upon power application. For instance, consider a screw dislocation as the defect type and avalanche breakdown voltage drop as the electrical failure type. A physical model is established by combining the power chip structure, such as the JFET region, termination structure, material properties, and operating conditions. The model can indicate that a screw dislocation becomes a carrier multiplication center under high reverse bias, triggering local avalanche and consequently reducing the overall breakdown voltage. Failure physics models not only explain the root cause of current failures but also possess predictive and guiding properties. They can be used to optimize device design, such as improving processes to suppress defects; and by establishing a knowledge base between defects and failures using failure physics models, the speed of identifying similar problems can be improved.

[0035] Figure 6 A schematic diagram of another power chip failure analysis device provided in an embodiment of the present invention is shown below. Figure 6 ,include: Positioning unit 110 is used to locate the failure location on the power chip; The diffraction unit 120 is used to obtain a diffraction image of the power chip using X-ray diffraction and to determine the spatial location of crystal defects within the chip based on the contrast difference in the diffraction image. Matching unit 130 is used to match the spatial location of crystal defects with the location of failure in the same spatial reference coordinate system.

[0036] Specifically, a power chip is the exposed semiconductor device body after the packaging shell is removed, typically containing structures such as a source, drain, gate, and substrate. The positioning unit 110 tests the power chip using non-destructive or minimally invasive physical positioning methods to locate the two-dimensional or three-dimensional coordinates of one or more suspected failure points distributed within the power chip, i.e., the failure location. Optionally, the physical positioning method may include one of the following: emission microscopy, beam-induced resistance change, and indium antimonide (InSb) infrared thermography. For example, the positioning unit 110 can capture weak photon signals generated by carrier recombination or avalanche breakdown during device operation using emission microscopy, accurately identifying abnormal bright spots; these locations are the failure locations of the chip.

[0037] The diffraction unit 120 can employ one of the non-destructive imaging techniques: X-ray diffraction topology (XRDI) or synchrotron X-ray topology (SXRT). When X-rays emitted from the light source pass through the semiconductor substrate of the power chip, a strong and uniform diffraction signal is generated in a perfect lattice region. However, in regions with crystal defects, the diffraction conditions deviate due to local lattice distortion, resulting in contrast differences in the diffraction image on the receiver. This typically manifests as a weakened signal and a darker image in the defect region. By selecting diffraction plane indices that are sensitive to specific defects, the imaging contrast can be enhanced. Furthermore, by combining sample rotation, multi-angle projection, or tomographic reconstruction algorithms, the three-dimensional spatial location of crystal defects within the chip can be achieved.

[0038] Matching unit 130 can establish a unified spatial reference coordinate system. This coordinate system can be constructed based on the external geometric features of the power chip, such as stable and easily identifiable physical references like pad edges, alignment marks, scribe lines, or package pins. Through image registration, the coordinates of the failure location and the crystal defect coordinates from X-ray diffraction imaging are transformed to the same coordinate system. If the spatial location of the crystal defect and the chip failure location coincide within the spatial error tolerance, this is considered a matching condition, allowing for a reasonable inference that the initially located failure location was caused by the crystal defect. Therefore, a direct correlation between the failure and the crystal defect can be established without destructive analysis, significantly improving the efficiency and accuracy of failure analysis.

[0039] Optionally, the diffraction unit includes: The parameter preset subunit is used to preset the wavelength of the X-ray source and the target crystal plane index for diffraction imaging based on the substrate material type of the power chip and the type of crystal defect to be detected. The test subunit is used to perform diffraction imaging based on the wavelength of the X-ray source and the target crystal plane index to obtain diffraction images.

[0040] Specifically, the substrate material of power chips is typically a semiconductor crystal material, commonly including silicon and silicon carbide. Different materials have different lattice constants, crystal structures, and defect behaviors. Crystal defect types are anomalies in the microstructure of a crystal that deviate from the ideal periodic arrangement. These mainly include point defects, such as vacancies and impurities; line defects, such as slip dislocations, screw dislocations, edge dislocations, and basal plane dislocations; and plane defects, such as stacking faults and stacking faults. Different types of defects have different sensitivities to the diffraction response of a specific crystal plane. In X-ray diffraction, the wavelength of the X-ray source can affect the diffraction angle and imaging resolution. Different crystal planes have different diffraction contrast sensitivities to different types of crystal defects. Therefore, the parameter preset subunit can set the wavelength of the X-ray source and the target crystal plane index by combining factors such as imaging resolution, diffraction contrast sensitivity, and other factors for the detection of different types of crystal defects.

[0041] After presetting the X-ray wavelength λ and the target crystal plane indices, the test subunit adjusts the sample orientation to satisfy the Bragg diffraction conditions of the selected (hkl) crystal plane, i.e., the incident angle θ satisfies the Bragg equation. After the X-rays penetrate the chip substrate, the diffraction intensity distribution in the reflection mode is received and recorded to generate a diffraction image. For complex three-dimensional defects, the spatial distribution of the defects can also be obtained by rotating the sample or acquiring data from multiple angles, combined with tomographic reconstruction algorithms.

[0042] Optionally, the failure analysis device for the power chip also includes: The electrical testing unit is used to perform electrical tests on the power chip to determine the type of electrical failure of the power chip; The detection unit is used to perform destructive sample preparation on the remaining failure sites to form transmission electron microscope (TEM) samples or scanning electron microscope (SEM) samples; The analysis unit is used to analyze crystal defects using microscopic characterization techniques to obtain the defect type corresponding to the remaining failure location. The microscopic characterization techniques include at least one of transmission electron microscopy, scanning electron microscopy, and atomic force microscopy. The model unit is used to construct a corresponding failure physics model based on the defect type and the electrical failure type. The failure physics model is used to characterize the mapping relationship between the defect type and the electrical failure type.

[0043] Specifically, electrical testing, without damaging the power chip structure, involves applying voltage, current, or frequency excitation to the source, drain, and gate to measure key electrical parameters of the power chip, such as leakage current, breakdown voltage, on-resistance, and threshold voltage. This allows for the identification of abnormal data that deviates from normal specifications. Based on the abnormal data, the corresponding electrical failure type can be determined, including but not limited to open circuits, short circuits, excessive leakage current, parameter drift, or dynamic performance degradation. Identifying the current electrical failure type of the power chip through electrical testing provides electrical parameter basis for subsequent defect localization, improving the targeting of data analysis.

[0044] After comparing the failure location with the diffraction image, failure locations that could not be confirmed through crystal defect matching still exhibited electrical anomalies and required further analysis. The detection unit performed irreversible processing on the power chip, including local cutting, thinning, and polishing, to create transmission electron microscopy (TEM) or scanning electron microscopy (SEM) samples suitable for microscopic observation. Although this step involves destructive operations, it achieves targeted sample preparation at the failure location, avoiding blindly cutting large areas and significantly improving the efficiency and success rate of subsequent microscopic analysis.

[0045] The analysis unit uses transmission electron microscopy, scanning electron microscopy, or atomic force microscopy to observe the prepared samples. For example, under transmission electron microscopy, through bright-field images, dark-field images, or high-resolution lattice images, the orientation of dislocation lines, stacking fault planes, or localized amorphous regions can be clearly identified. By combining image features with a known defect database, the specific defect type corresponding to the failure location can be determined.

[0046] Failure physics models describe the coupling relationship between defect types and electrical failure types. For example, line defects such as dislocations typically cause device leakage and parameter drift, while planar defects such as stacking faults, if present below a conductive channel, can cause device breakdown and even complete failure upon power application. For instance, consider a screw dislocation as the defect type and avalanche breakdown voltage drop as the electrical failure type. The model unit incorporates power chip structure, such as the JFET region, termination structure, material properties, and operating conditions, to establish a physical model. The model can indicate that a screw dislocation becomes a carrier multiplication center under high reverse bias, triggering local avalanche and consequently reducing the overall breakdown voltage. Failure physics models not only explain the root cause of current failures but also possess predictive and guiding properties. They can be used to optimize device design, such as improving processes to suppress defects; and to establish a knowledge base between defects and failures using failure physics models, thereby improving the speed of identifying similar problems.

[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method of failure analysis of a power chip, characterized by, include: Locate the failure point on the power chip; The diffraction image of the power chip is obtained by X-ray diffraction, and the spatial location of the crystal defect within the chip is determined based on the contrast difference in the diffraction image. In the same spatial reference coordinate system, the spatial location of the crystal defect is matched with the failure location.

2. The failure analysis method for power chips according to claim 1, characterized in that, Obtaining the diffraction image of the power chip using X-ray diffraction includes: Based on the substrate material type of the power chip and the type of crystal defect to be detected, the wavelength of the X-ray source and the target crystal plane index for diffraction imaging are preset. Diffraction imaging is performed based on the wavelength of the X-ray source and the target crystal plane index to obtain the diffraction image.

3. The failure analysis method for power chips according to claim 1, characterized in that, The X-ray diffraction method includes at least one of X-ray diffraction topology and synchrotron radiation X-ray topology.

4. The failure analysis method for power chips according to claim 1, characterized in that, Locating the failure location on the power chip includes: The failure location on the power chip is located using physical location methods; the physical location methods include at least one of emission microspectroscopy analysis, beam-induced resistance change and indium antimonide infrared thermal imaging.

5. The failure analysis method for power chips according to any one of claims 1-4, characterized in that, After determining that the failure location was caused by the crystal defect, the method further includes: The remaining failure sites are subjected to destructive sample preparation to form transmission electron microscopy (TEM) or scanning electron microscopy (SEM) samples; The crystal defects are analyzed using microscopic characterization techniques to obtain the defect types corresponding to the remaining failure locations, wherein the microscopic characterization techniques include at least one of transmission electron microscopy, scanning electron microscopy, and atomic force microscopy.

6. The failure analysis method for power chips according to claim 5, characterized in that, Before locating the failure site on the power chip, the following steps are included: Electrical tests are performed on the power chip to determine the type of electrical failure of the power chip; After analyzing the crystal defects using microscopic characterization techniques, the process also includes: Based on the defect type and the electrical failure type, a corresponding failure physics model is constructed. The failure physics model is used to characterize the mapping relationship between the defect type and the electrical failure type.

7. The failure analysis method for power chips according to claim 1, characterized in that, The crystal defects include at least one of screw dislocations, basal plane dislocations, edge dislocations, and slip dislocations.

8. A failure analysis device for power chips, characterized in that, include: The positioning unit is used to locate the failure location on the power chip; A diffraction unit is used to obtain a diffraction image of the power chip using X-ray diffraction, and to determine the spatial location of crystal defects within the chip based on the contrast differences in the diffraction image. The matching unit is used to match the spatial location of the crystal defect with the failure location in the same spatial reference coordinate system.

9. The power chip failure analysis device according to claim 8, characterized in that, The diffraction unit includes: The parameter preset subunit is used to preset the wavelength of the X-ray source and the target crystal plane index for diffraction imaging based on the substrate material type of the power chip and the type of crystal defect to be detected. The test subunit is used to perform diffraction imaging based on the wavelength of the X-ray source and the target crystal plane index to obtain the diffraction image.

10. The power chip failure analysis device according to claim 9, characterized in that, Also includes: An electrical testing unit is used to perform electrical tests on the power chip to determine the type of electrical failure of the power chip; The detection unit is used to perform destructive sample preparation on the remaining failure locations to form transmission electron microscope (TEM) samples or scanning electron microscope (SEM) samples. An analysis unit is used to analyze the crystal defects using microscopic characterization techniques to obtain the defect types corresponding to the remaining failure locations, wherein the microscopic characterization techniques include at least one of transmission electron microscopy, scanning electron microscopy, and atomic force microscopy. The model unit is used to construct a corresponding failure physics model based on the defect type and the electrical failure type. The failure physics model is used to characterize the mapping relationship between the defect type and the electrical failure type.

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