Load type identification circuit and energy storage device

Abstract

The application relates to a load type identification circuit and an energy storage device. The load type identification circuit comprises a load voltage and current sampling module for collecting a load voltage signal and a load current signal; a first load judgment module for outputting a first judgment signal according to whether the load voltage signal and the load current signal have a phase difference; a second load judgment module for outputting a second judgment signal according to the phase sequence relationship between the load current signal and the load voltage signal when the load voltage signal and the load current signal have a phase difference; and a signal synthesis output module for generating an analog voltage signal representing a load type according to the first judgment signal and the second judgment signal and outputting the analog voltage signal to a microcontroller. The method can identify the load type.

Description

Technical Field

[0001] This application relates to the field of new energy technology, and in particular to a load type identification circuit and an energy storage device. Background Technology

[0002] During actual grid-connected or off-grid operation, the type of load connected to the output terminal of energy storage power supply is highly uncertain, covering various types such as resistive, inductive, and capacitive. The electrical characteristics of different loads are significantly different, which puts forward differentiated requirements for power supply control strategies.

[0003] Existing energy storage power supply control strategies mostly adopt a single fixed threshold and algorithm logic, which makes it difficult to effectively suppress peak voltage and inrush current caused by inductive and capacitive loads. This results in insufficient system reliability, poor load adaptability, and inability to meet the safe operation requirements under complex working conditions. Summary of the Invention

[0004] Therefore, it is necessary to provide a load type identification circuit and energy storage device that can identify the load type in order to address the above-mentioned technical problems.

[0005] In a first aspect, this application provides a load type identification circuit, including:

[0006] The load voltage and current sampling module is used to acquire load voltage and load current signals;

[0007] The first load determination module is used to output a first determination signal based on whether there is a phase difference between the load voltage signal and the load current signal;

[0008] The second load judgment module is used to output a second judgment signal based on the phase order relationship between the load current signal and the load voltage signal when there is a phase difference between the load voltage signal and the load current signal.

[0009] The signal synthesis output module is used to generate an analog voltage signal representing the load type based on the first judgment signal and the second judgment signal, and output it to the microcontroller.

[0010] In one embodiment, the first load determination module includes:

[0011] A square wave conversion unit is used to convert the load voltage signal and the load current signal into two square wave signals respectively.

[0012] The phase difference detection unit is used to perform logical operations on the two square wave signals and output a pulse signal;

[0013] The integration comparison unit is used to integrate the pulse signal to obtain an integrated voltage value, compare the integrated voltage value with a preset reference voltage, and output the first judgment signal.

[0014] In one embodiment, the two square wave signals include a first square wave signal and a second square wave signal, and the phase difference detection unit includes:

[0015] The first NOT gate is used to invert the first square wave signal and output the first inverted square wave signal.

[0016] The second NOT gate is used to invert the second square wave signal and output the second inverted square wave signal.

[0017] The first AND gate is used to perform an AND operation on the first square wave signal and the second square wave signal to obtain the first output signal;

[0018] The second AND gate is used to perform an AND operation on the first inverted square wave signal and the second inverted square wave signal to obtain the second output signal.

[0019] An OR gate is used to perform an OR operation on the first output signal and the second output signal to output the pulse signal;

[0020] The high-level width of the pulse signal is proportional to the phase difference between the first square wave signal and the second square wave signal.

[0021] In one embodiment, the integration comparison unit includes:

[0022] An RC charging circuit is used to integrate the pulse signal to obtain the signal integral value;

[0023] The comparator has its first input terminal connected to the output terminal of the RC charging circuit and receiving the integrated signal value. The second input terminal of the comparator is connected to the preset reference voltage, and the output terminal of the comparator outputs the first judgment signal.

[0024] In one embodiment, the second load determination module includes:

[0025] The zero-crossing detection unit is used to generate a voltage zero-crossing square wave signal based on the load voltage signal and a current zero-crossing square wave signal based on the load current signal.

[0026] A phase direction detection unit is used to detect the level state of the current zero-crossing square wave signal at each rising edge of the voltage zero-crossing square wave signal, and output a first pulse signal or a second pulse signal according to the level state.

[0027] The charging and discharging unit is used to store energy when receiving the first pulse signal to obtain a first energy storage voltage, and to store energy when receiving the second pulse signal to obtain a second energy storage voltage;

[0028] The comparison output unit is used to compare the first energy storage voltage with the second energy storage voltage and output the second judgment signal.

[0029] In one embodiment, the phase direction detection unit includes:

[0030] The first AND gate is used to perform an AND operation on the voltage zero-crossing square wave signal and the current zero-crossing square wave signal, and output the first pulse signal;

[0031] The NOT gate is used to invert the square wave signal at the zero-crossing point of the current to obtain a second inverted signal;

[0032] The second AND gate is used to perform an AND operation on the voltage zero-crossing square wave signal and the second inverted signal to output the second pulse signal.

[0033] In one embodiment, the charging and discharging unit includes: a first capacitor and a second capacitor;

[0034] The first terminal of the first capacitor is connected to the output terminal of the first AND gate, and the second terminal of the first capacitor is connected to the reference ground, for charging when the first pulse signal is received to obtain the first energy storage voltage;

[0035] The first terminal of the second capacitor is connected to the output terminal of the second AND gate, and the second terminal of the second capacitor is connected to the reference ground, for charging when the second pulse signal is received to obtain the second energy storage voltage;

[0036] A periodic reset circuit is used to reset and discharge the first capacitor and the second capacitor after each power frequency cycle.

[0037] In one embodiment, the comparison output unit includes a comparator, the non-inverting input of which is connected to the first capacitor, and the inverting input of which is connected to the second capacitor.

[0038] In one embodiment, the signal synthesis output module includes:

[0039] A first switching transistor, the control terminal of the first switching transistor is connected to the first judgment signal, the first terminal of the first switching transistor is connected to the signal output terminal, and the second terminal of the first switching transistor is grounded, and is used to turn on when the first judgment signal indicates the existence of a phase difference;

[0040] The second switch has its control terminal connected to the second judgment signal, its first terminal connected to the signal output terminal, and its second terminal grounded. It is used to turn on when the second judgment signal indicates that the load current signal leads the load voltage signal.

[0041] Wherein: when both the first switch and the second switch are off, the signal output terminal outputs a first analog voltage signal representing a resistive load; when the first switch is on and the second switch is off, the signal output terminal outputs a second analog voltage signal representing an inductive load; when both the first switch and the second switch are on, the signal output terminal outputs a third analog voltage signal representing a capacitive load.

[0042] Secondly, this application also provides an energy storage device, including a load type identification circuit as described in the first aspect or any embodiment thereof.

[0043] The aforementioned load type identification includes: a load voltage and current sampling module for acquiring load voltage and load current signals; a first load judgment module for outputting a first judgment signal based on whether there is a phase difference between the load voltage and load current signals; a second load judgment module for outputting a second judgment signal based on the phase order of the load current and load voltage signals when there is a phase difference between them; and a signal synthesis output module for generating an analog voltage signal characterizing the load type based on the first and second judgment signals and outputting it to the microcontroller. This scheme employs a hierarchical identification architecture that includes voltage and current sampling, phase difference judgment, phase sequence determination, and signal synthesis output. It can accurately detect the phase characteristics and timing of load voltage and current, quickly distinguish between resistive, inductive, and capacitive load types, and convert them into analog voltage signals for uploading to the microcontroller. This effectively solves the problems caused by uncertain load types and large differences in electrical characteristics in existing energy storage power supplies. It overcomes the shortcomings of traditional control strategies with fixed thresholds and algorithm logic, providing precise load type criteria for targeted adjustment of control logic in energy storage power supplies. This effectively suppresses voltage spikes and inrush currents caused by inductive and capacitive loads, improves the reliability of energy storage power supply systems and their adaptability to multiple load types, and meets the safe and stable operation requirements of grid-connected and off-grid scenarios under complex operating conditions. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a schematic diagram of a load type identification circuit in one embodiment;

[0046] Figure 2 This is a schematic diagram of the first load determination module in one embodiment;

[0047] Figure 3 This is a schematic diagram of the first load determination module in one embodiment;

[0048] Figure 4 This is a schematic diagram of a load voltage and current sampling module in one embodiment;

[0049] Figure 5 This is a schematic diagram of the second load determination module in one embodiment;

[0050] Figure 6 This is a schematic diagram of the second load determination module in one embodiment;

[0051] Figure 7 This is a schematic diagram of a signal synthesis output module in one embodiment;

[0052] Figure 8 This is a schematic diagram of the waveforms of key nodes under capacitive load conditions in one embodiment;

[0053] Figure 9 This is a schematic diagram of the waveforms at key nodes under inductive load conditions in one embodiment;

[0054] Figure 10 This is a schematic diagram of the key node waveforms under resistive load conditions in one embodiment. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0056] Currently, when an energy storage power supply outputs power, the load type can be resistive, inductive, or capacitive. For resistive loads, the voltage and current are in phase (0°), with no phase difference; only the impact of large currents needs to be considered. For inductive loads, due to the characteristics of inductance, the inductor current cannot change abruptly when a large current is turned off. The relatively high rate of change of current with respect to time leads to a relatively large reverse voltage. Similarly, for capacitive loads, since the voltage across the capacitor cannot change abruptly when a large voltage is turned off, assuming there is no discharge path, a relatively high voltage will exist. Therefore, it is necessary to determine the load type to ascertain the conditions required for the software to change its strategy.

[0057] Among them, resistive loads are loads where the voltage and current are in phase and there is no phase difference, and there is only the problem of large current surge; the core characteristic of inductive loads (L loads) is that the current cannot change abruptly, and high reverse voltage is easily generated when turned off; the core characteristic of capacitive loads (C loads) is that the voltage cannot change abruptly, and high voltage is easily generated when there is no discharge path when turned off.

[0058] The rate of change of current with respect to time (di / dt): This indicates how fast the current changes over time. When an inductive load is turned off, the larger the di / dt, the higher the reverse induced voltage generated, which can easily damage circuit components.

[0059] Existing energy storage power supply control strategies mostly adopt a single fixed threshold and algorithm logic, which makes it difficult to effectively suppress peak voltage and inrush current caused by inductive and capacitive loads. This results in insufficient system reliability, poor load adaptability, and inability to meet the safe operation requirements under complex working conditions.

[0060] To address the aforementioned issues, this application provides a load type identification circuit and an energy storage device. It can quickly distinguish between resistive, inductive, and capacitive load types, effectively solving the problems caused by the uncertainty of load types and large differences in electrical characteristics in existing energy storage power supplies. It overcomes the shortcomings of traditional control strategies with fixed thresholds and algorithm logic, providing accurate load type information for targeted adjustment of control logic in energy storage power supplies. This effectively suppresses voltage spikes and inrush currents caused by inductive and capacitive loads, improving the operational reliability and multi-load adaptability of the energy storage power supply system, and meeting the safe and stable operation requirements of grid-connected and off-grid scenarios under complex operating conditions.

[0061] For example, such as Figure 1 As shown, this is a load type identification circuit provided in an embodiment of this application. The circuit may include:

[0062] The load voltage and current sampling module 11 is used to acquire load voltage signals and load current signals;

[0063] The first load judgment module 12 is used to output a first judgment signal based on whether there is a phase difference between the load voltage signal and the load current signal;

[0064] The second load judgment module 13 is used to output a second judgment signal based on the phase order of the load current signal and the load voltage signal when there is a phase difference between the load voltage signal and the load current signal.

[0065] The signal synthesis output module 14 is used to generate an analog voltage signal (LOAD_TYPE) representing the load type based on the first judgment signal and the second judgment signal, and output it to the microcontroller.

[0066] The aforementioned load voltage signal can be an electrical signal reflecting the magnitude and waveform of the voltage output from the energy storage power source to the load. The load current signal can be an electrical signal reflecting the magnitude and waveform of the current flowing through the load.

[0067] The aforementioned first load judgment module 12 distinguishes between resistive loads and non-resistive (inductive or capacitive) loads by determining whether there is a phase difference between the load voltage signal and the load current signal, and outputs a corresponding judgment result signal, namely the first judgment signal. This first judgment signal characterizes whether a phase difference exists between the load voltage signal and the load current signal.

[0068] The aforementioned phase difference refers to the time offset between the load voltage signal and the load current signal within the same period, which is a key basis for determining the load type.

[0069] The aforementioned phase sequence refers to whether the load current signal waveform or the load voltage signal waveform reaches the zero-crossing point first within the same cycle, used to distinguish between inductive and capacitive loads. The second judgment signal is used to characterize whether the load voltage signal or the load current signal leads or lags behind.

[0070] In the aforementioned analog voltage signals, different amplitudes can represent resistive, inductive, and capacitive load types, facilitating rapid identification by the microcontroller. The microcontroller can receive these analog voltage signals to determine the load type and adjust its power control strategy accordingly.

[0071] The load type identification circuit of this application embodiment can first obtain the load voltage signal and the load current signal through the load voltage and current sampling module; then the first load judgment module detects the phase difference and outputs the first judgment signal to distinguish between resistive and non-resistive loads; when a phase difference exists, the second load judgment module outputs the second judgment signal according to the phase relationship between current and voltage to distinguish between inductive and capacitive loads; finally, the signal synthesis output module combines the two judgment signals into analog voltage signals corresponding to different load types and outputs them to the microcontroller to complete the hardware identification of the load type.

[0072] The load type identification circuit shown in the above embodiments achieves rapid load type identification through a modular hardware structure without the need for software algorithms. It can accurately distinguish between resistive, inductive, and capacitive loads and output stable analog signals, providing real-time and accurate load basis for the microcontroller to adjust the control strategy, thereby suppressing peak voltage and inrush current, and improving the load adaptability and system reliability of the energy storage power supply.

[0073] For example, Figure 2 This is a schematic diagram of the first load determination module 12 in one embodiment. Figure 2 The first load judgment module 12 mentioned above may include: a square wave conversion unit 121, used to convert the load voltage signal and the load current signal into two square wave signals respectively; a phase difference detection unit 122, used to perform logical operations on the two square wave signals and output a pulse signal; and an integration comparison unit 123, used to integrate the pulse signal to obtain an integrated voltage value, compare the integrated voltage value with a preset reference voltage, and output a first judgment signal.

[0074] The aforementioned square wave conversion unit 121 can convert the load voltage signal and the load current signal into square wave signals of the same frequency, which facilitates subsequent phase logic detection.

[0075] The pulse signal output by the phase difference detection unit 122 is a pulse signal that is proportional to the magnitude of the phase difference. The larger the phase difference, the wider the pulse high level.

[0076] The aforementioned integration and comparison unit 123 can convert the pulse signal into a DC voltage through RC integration, then compare it with a preset reference voltage, and output a first judgment signal. The DC voltage obtained after integrating the pulse signal has an amplitude that is positively correlated with the phase difference.

[0077] In one implementation, when the integrated voltage value is compared with a preset reference voltage and it is determined that the integrated voltage value is greater than the preset reference voltage, it is determined that there is a phase difference between the load voltage signal and the load current signal, and a first judgment signal representing the non-resistive load is output.

[0078] In another implementation, when the integrated voltage value is compared with a preset reference voltage and it is determined that the integrated voltage value is less than or equal to the preset reference voltage, it is determined that there is no phase difference between the load voltage signal and the load current signal, and a first judgment signal characterizing the resistive load is output.

[0079] The first load judgment module in this embodiment uses a hardware structure of square wave conversion, phase difference logic detection, and integral comparison to quickly and stably identify whether there is a phase difference between voltage and current, and can accurately distinguish between resistive loads and non-resistive loads (inductive or capacitive loads). By integrating the voltage value and a preset reference voltage, a tolerable phase difference threshold can be flexibly set to reduce recognition errors. The entire judgment process does not require software intervention or a clock signal, has a fast response speed and strong anti-interference ability, and provides a judgment basis for subsequent load type differentiation and control strategy adjustment, thereby improving the stability and adaptability of the overall recognition circuit.

[0080] For example, Figure 3 This is a schematic diagram of the first load determination module 12 in one embodiment.

[0081] like Figure 3 As shown above, Figure 2 The square wave conversion unit 121 shown can be composed of... Figure 3 The U1A and U5A implementations shown are in Figure 3 The load current signal AD_I shown can be compared and shaped using U1A to convert the sinusoidal current signal into a first square wave signal. This first square wave signal is... Figure 3 Represented as AD_I_COM, the load voltage signal AD_V is compared and shaped by U5A, converting the sinusoidal voltage signal into a second square wave signal. The second square wave signal is then... Figure 3 This is represented as AD_V_COM.

[0082] Optionally, the square wave signal mentioned above can be a 50Hz square wave signal, or it can be a 60Hz square wave signal.

[0083] For example, Figure 3 U1A and U5A in the above are both operational amplifiers.

[0084] like Figure 3 As shown, the two square wave signals include a first square wave signal AD_I_COM and a second square wave signal AD_V_COM. Figure 2 The phase difference detection unit 122 shown includes:

[0085] The first NOT gate is used to invert the first square wave signal and output the first inverted square wave signal.

[0086] The second NOT gate is used to invert the second square wave signal and output the second inverted square wave signal.

[0087] The first AND gate U2A is used to perform an AND operation on the first square wave signal and the second square wave signal to obtain the first output signal;

[0088] The second AND gate U9A is used to perform an AND operation on the first inverted square wave signal and the second inverted square wave signal to obtain the second output signal.

[0089] OR gate U8A is used to perform an OR operation on the first output signal and the second output signal to output a pulse signal;

[0090] The high-level width of the pulse signal is proportional to the phase difference between the first square wave signal and the second square wave signal.

[0091] exist Figure 3 In the middle, the first NOT gate and the second NOT gate pass through Figure 3 The U4 in the code is a digital logic NOT gate (inverter), a dual-channel NOT gate chip. In U4, 1A represents the first input pin; 1Y represents the first output pin; GND represents the ground terminal; VCC represents the power supply terminal; 2A represents the second input pin; and 2Y represents the second output pin.

[0092] In one implementation, the integration comparison unit 123 includes: an RC charging circuit for integrating the pulse signal to obtain the signal integration value; a comparator, the first input terminal of the comparator being connected to the output terminal of the RC charging circuit and receiving the signal integration value, the second input terminal of the comparator being connected to a preset reference voltage, and the output terminal of the comparator outputting a first judgment signal.

[0093] Figure 3 In the first square wave signal AD_I_COM and the second square wave signal AD_V_COM are passed through a NOT gate U4, an AND gate U2A, an AND gate U9A, and an OR gate U8A to obtain a pulse signal representing the phase difference. If a phase difference exists (maximum phase 180 degrees), the duty cycle will be relatively large, which will charge the RC charging circuit. The larger the phase difference and the larger the duty cycle, the greater the charging voltage will be.

[0094] The above Figure 2 The integral comparison unit 123 in the middle passes through Figure 3 The circuit is implemented using the eighth resistor R8, the fifth capacitor C5, and comparator U3B. R8 and C5 form an RC charging circuit to integrate the pulse signal and obtain the integrated signal value. This RC charging circuit integrates the pulse signal output from the phase difference detection unit, converting it into a DC integrated voltage proportional to the phase difference. U3B, as a comparator, has the DC integrated voltage connected at one end and a preset reference voltage VREF connected at the other. By comparing the DC integrated voltage with the preset reference voltage, it outputs a first judgment signal indicating whether a phase difference exists between the load voltage and current, thus distinguishing between resistive and non-resistive loads. Figure 3 The first judgment signal is represented as LOAD_R.

[0095] In the above embodiments, Figure 3 The first load judgment module shown is implemented in hardware circuit. Through operational amplifier shaping, logic gate phase detection and RC integral comparison, it can quickly and accurately distinguish resistive loads from non-resistive loads and output a stable and reliable first judgment signal. It does not require software intervention and has the characteristics of fast response speed, high judgment accuracy and strong anti-interference ability. It can provide a stable judgment basis for subsequent load type subdivision and energy storage power supply control strategy adjustment.

[0096] For example, Figure 4 This is a schematic diagram of the load voltage and current sampling module 11 in one embodiment.

[0097] like Figure 4 As shown, the load voltage and current sampling module 11 includes a current sampling branch and a voltage sampling branch, which respectively realize the sampling and conditioning of the load current signal and the load voltage signal, providing a stable input signal for the subsequent circuit.

[0098] In the current sampling branch, the live-wire input signal I_AC_Input_L of the AC current is connected to the non-inverting input of operational amplifier U3A via current-limiting resistors R2 and R3, and the neutral-wire input signal I_AC_Input_N of the AC current is connected to the inverting input of operational amplifier U3A via current-limiting resistors R5 and R6. C3 is a filter capacitor used to filter out high-frequency interference in the input signal. C1, C2, and R1 form a DC bias circuit, providing a static bias voltage of +1.65V to the non-inverting input of U3A. The feedback branch of U3A includes R7 (feedback resistor) and C4 (compensation capacitor), forming a differential amplifier circuit that converts the input differential current signal into a single-ended output load current signal AD_I. C1 and C2 are both capacitors, and R1 is a resistor.

[0099] In the voltage sampling branch, the AC voltage live-wire output signal V_AC_Output_L is connected to the non-inverting input of operational amplifier U10A via current-limiting resistors R10 and R11, and the AC voltage output signal V_AC_Output_N is connected to the inverting input of operational amplifier U10A via current-limiting resistors R14 and R15. C8 is a filter capacitor used to filter out high-frequency interference in the input signal. C6, C7, and R9 form a DC bias circuit, providing a static bias voltage of +1.65V to the non-inverting input of U10A. The feedback branch of U10A includes R17 (feedback resistor) and C9 (compensation capacitor), forming a differential amplifier circuit that converts the input differential voltage signal into a single-ended output load voltage signal AD_V. C6 and C7 are both capacitors, and R9 is a resistor.

[0100] Figure 4In the process, after being processed by the load voltage and current sampling module 11, the output load current signal AD_I and load voltage signal AD_V provide the original analog signals with DC bias, low noise, and high fidelity for the square wave shaping and phase difference detection of the subsequent first load judgment module and second load judgment module, ensuring the accuracy of the back-end phase judgment and load type identification.

[0101] In the above embodiments, Figure 4 The load voltage and current sampling module 11 shown employs a differential amplifier circuit to sample and condition the current and voltage signals. Combined with a DC bias circuit, it boosts the AC signal to a range that the operational amplifier can handle. Interference is suppressed through RC filtering. The overall structure is simple and has strong anti-interference capabilities, providing a reliable input signal foundation for the subsequent hardware load identification circuit, ensuring the stability and identification accuracy of the overall circuit. For example, Figure 5 This is a schematic diagram of a second load determination module 13 in one embodiment. The second load determination module 13 includes:

[0102] The zero-crossing detection unit 131 is used to generate a voltage zero-crossing square wave signal based on the load voltage signal and a current zero-crossing square wave signal based on the load current signal.

[0103] The phase direction detection unit 132 is used to detect the level state of the current zero-crossing square wave signal at each rising edge of the voltage zero-crossing square wave signal, and output a first pulse signal or a second pulse signal according to the level state.

[0104] The charging and discharging unit 133 is used to store energy when receiving a first pulse signal to obtain a first energy storage voltage, and to store energy when receiving a second pulse signal to obtain a second energy storage voltage;

[0105] The comparison output unit 134 is used to compare the first energy storage voltage with the second energy storage voltage and output a second judgment signal.

[0106] The zero-crossing detection unit 131 converts the load voltage signal and load current signal into square wave signals based on the zero-crossing point, providing a time reference for phase order determination. The voltage zero-crossing square wave signal is a square wave signal formed with the load voltage zero-crossing moment as the reversal point, serving as a reference signal for determining phase lead or lag; the current zero-crossing square wave signal is a square wave signal formed with the load current zero-crossing moment as the reversal point, used to compare the phase order with the voltage zero-crossing point.

[0107] The aforementioned phase direction detection unit 132 uses the voltage zero-crossing point as a reference to detect the phase sequence of the current signal and outputs pulse signals corresponding to the inductive or capacitive load. The rising edge refers to the instant the voltage zero-crossing square wave changes from low to high, serving as the trigger moment for phase detection; the level state refers to whether the current zero-crossing square wave is high or low at the voltage rising edge, used to distinguish between inductive and capacitive loads; the first and second pulse signals correspond to the identification pulses for the inductive and capacitive loads, respectively, and are used to drive subsequent charging and discharging units.

[0108] The aforementioned charging and discharging unit 133 charges and stores energy for the pulse signal, converting the pulse signal into a stable DC voltage for easy comparison; the first energy storage voltage and the second energy storage voltage are respectively formed by two pulse charging paths, and are used to compare and determine whether the load is inductive or capacitive.

[0109] The aforementioned comparison output unit 134 compares the two stored voltages and outputs a second judgment signal in the form of a high or low level. The second judgment signal is used to characterize whether the load is inductive or capacitive, and is used by the subsequent signal synthesis output module.

[0110] In one implementation, if the current zero-crossing square wave signal is high at the rising edge of the voltage zero-crossing square wave signal, the phase direction detection unit 132 outputs a first pulse signal, and the charging and discharging unit 133 outputs a first energy storage voltage; the comparison output unit 134 outputs a second judgment signal characterizing the inductive load based on the first energy storage voltage being greater than the second energy storage voltage.

[0111] In another implementation, if the current zero-crossing square wave signal is low at the rising edge of the voltage zero-crossing square wave signal, the phase direction detection unit 132 outputs a second pulse signal, and the charging and discharging unit 133 outputs a second energy storage voltage; the comparison output unit 134 outputs a second judgment signal characterizing the capacitive load based on the fact that the second energy storage voltage is greater than the first energy storage voltage.

[0112] The second load judgment module in the above embodiment accurately distinguishes between inductive and capacitive loads through a hardware structure of zero-crossing detection, phase direction judgment, and voltage energy storage comparison. It does not require software algorithms or clock intervention, has fast judgment speed, accurate phase recognition, and strong anti-interference ability. It can stably output a second judgment signal and cooperate with the first load judgment module to complete the identification of all types of loads, providing a reliable load type basis for adjusting the energy storage power supply control strategy.

[0113] For example, Figure 6 This is a schematic diagram of the second load determination module 13 in one embodiment.

[0114] like Figure 6 As shown above, Figure 5The phase direction detection unit 132 shown includes: NOT gate U7, first AND gate U2B, and second AND gate U2C. The NOT gate U7 is used to detect the square wave signal at the zero-crossing point of the current (…). Figure 6 The AD_I_COM signal in the second AND gate is inverted to obtain the second inverted signal; the second AND gate U2C generates the square wave signal at the zero-crossing voltage point ( Figure 6 The first AND gate (U2B) performs an AND operation on the voltage zero-crossing square wave signal and the current zero-crossing square wave signal, outputting the first pulse signal; the second AND gate (U2B) performs an AND operation on the voltage zero-crossing square wave signal and the second inverted signal, outputting the second pulse signal. Through the above logic operations, the state of current phase lagging or leading voltage phase can be accurately identified at the rising edge of the voltage zero-crossing square wave signal, and pulse signals corresponding to different load types can be output respectively.

[0115] like Figure 6 As shown, in one embodiment, Figure 5 The charging / discharging unit 133 shown includes a first capacitor EC1, a second capacitor EC2, and a periodic reset circuit. The first terminal of the first capacitor EC1 is connected to the output of the second AND gate U2C, and the second terminal of the first capacitor EC1 is connected to reference ground. It is used to charge upon receiving a first pulse signal to obtain a first energy storage voltage. The first terminal of the second capacitor EC2 is connected to the output of the first AND gate U2B, and the second terminal of the second capacitor EC2 is connected to reference ground. It is used to charge upon receiving a second pulse signal to obtain a second energy storage voltage. The periodic reset circuit is used to reset and discharge the first capacitor EC1 and the second capacitor EC2 after each power frequency cycle to ensure detection accuracy.

[0116] Among them, the aforementioned periodic reset circuit is in Figure 6 This is achieved through a pair of reset switches, i.e. Figure 6 The circuit is implemented using Q1 and Q4. One end of the first capacitor EC1 is connected to the output of the second AND gate U2C, and the other end of the first capacitor EC1 is connected to the reference ground. Simultaneously, one end of the first capacitor EC1 is also connected to the drain of the reset switch Q1, used to charge upon receiving the first pulse signal to obtain the first energy storage voltage. One end of the second capacitor EC2 is connected to the output of the first AND gate U2B, and the other end of the second capacitor EC2 is connected to the reference ground. Simultaneously, one end of the second capacitor EC2 is also connected to the drain of the reset switch Q4, used to charge upon receiving the second pulse signal to obtain the second energy storage voltage. The periodic reset circuit, through the conduction of Q1 and Q4 at the end of each power frequency cycle, discharges the charge on the first capacitor EC1 and the second capacitor EC2 to the reference ground, achieving reset discharge and preventing residual charge from the previous cycle from affecting the comparison result of the next cycle, thus ensuring detection accuracy.

[0117] like Figure 6 As shown, in one embodiment, Figure 5The comparison output unit 134 shown includes a comparator U6A. The non-inverting input of comparator U6A is connected to a first capacitor EC1 to receive a first energy storage voltage, and the inverting input of comparator U6A is connected to a second capacitor EC2 to receive a second energy storage voltage. Comparator U6A compares the first energy storage voltage with the second energy storage voltage and outputs a corresponding second judgment signal based on the comparison result. This second judgment signal... Figure 6 This is represented as LOAD_CorL. When the first energy storage voltage is greater than the second energy storage voltage, a second judgment signal representing an inductive load is output; when the second energy storage voltage is greater than the first energy storage voltage, a second judgment signal representing a capacitive load is output.

[0118] It should be noted that Figure 6 R22, R23 and R13 shown are all resistors.

[0119] In the above embodiments, Figure 6 The second load judgment module shown is implemented using pure hardware circuitry. Through logic gate phase direction detection, capacitor charging and discharging energy storage, and comparator voltage comparison, it can quickly and accurately distinguish between inductive and capacitive loads without the need for software intervention or clock signals. It features fast response speed, stable judgment, and strong anti-interference capability. It can work with the first load judgment module to complete the identification of all types of loads, providing a reliable secondary judgment basis for adjusting the energy storage power supply control strategy.

[0120] For example, Figure 7 This is a schematic diagram of the second load determination module 13 in one embodiment.

[0121] like Figure 7 As shown, the signal synthesis output module 14 includes a first switch Q2, a second switch Q3, and a matching voltage divider circuit. The control terminal of the first switch Q2 is connected to a first judgment signal LOAD_R, the first terminal of the first switch Q2 is connected to the signal output terminal, and the second terminal of the first switch Q2 is grounded. It is used to turn on when the first judgment signal indicates a phase difference between the load voltage and the load current. The control terminal of the second switch Q3 is connected to a second judgment signal LOAD_CorL, the first terminal of the second switch Q3 is connected to the signal output terminal, and the second terminal of the second switch Q3 is grounded. It is used to turn on when the second judgment signal indicates that the load current signal leads the load voltage signal.

[0122] Specifically: when both the first switch Q2 and the second switch Q3 are off, the signal output terminal outputs a first analog voltage signal representing a resistive load; when the first switch Q2 is on and the second switch Q3 is off, the signal output terminal outputs a second analog voltage signal representing an inductive load; when both the first switch Q2 and the second switch Q3 are on, the signal output terminal outputs a third analog voltage signal representing a capacitive load. These three analog voltage signals LOAD_TYPE, each with different amplitudes, can be directly identified by the microcontroller to distinguish between resistive, inductive, and capacitive load types.

[0123] It should be noted that, Figure 7 R16, R18, and R19 in the diagram all represent resistors.

[0124] In the above embodiments, Figure 7 The signal synthesis output module shown adopts a hardware structure that combines switching transistors and voltage division. It synthesizes the first judgment signal and the second judgment signal into analog voltage signals corresponding to different load types. The output is stable and the recognition is intuitive. No software algorithm is required. It can standardize the load type judgment result and output it to the microcontroller, providing an accurate and reliable input signal for the real-time adjustment and control strategy of the energy storage power supply.

[0125] For example, Figure 8 This is a schematic diagram of key node waveforms under capacitive load conditions, used to verify the working process and identification results of the load type identification circuit in this application.

[0126] like Figure 8 As shown, the waveforms from top to bottom are: load current sampling signal AD_I, load voltage sampling signal AD_V, first judgment signal LOAD_R output by the first load judgment module, output waveform of the first AND gate U2B in the second load judgment module, output waveform of the second AND gate U2C, second judgment signal LOAD_CorL output by the second load judgment module, and finally output analog voltage signal LOAD_TYPE representing the load type.

[0127] Among them, AD_I is the load current sampling waveform, and AD_V is the load voltage sampling waveform. The two show a phase relationship where the current leads the voltage, which is consistent with the electrical characteristics of a capacitive load. LOAD_R is high, indicating that there is a phase difference between the load voltage and the current. U2B always remains low, and U2C outputs a periodic pulse signal at the rising edge of the voltage zero crossing, indicating that the phase direction detection unit has identified the state of current leading voltage. LOAD_CorL is high, indicating that the load is capacitive. Finally, LOAD_TYPE outputs a stable third analog voltage signal, corresponding to the identification result of the capacitive load.

[0128] Figure 8The two vertical lines in the image are time measurement cursors used to mark two time points within the same power frequency cycle. Measurements show that within this cycle, the zero-crossing time of the load current sampling signal AD_I is earlier than that of the load voltage sampling signal AD_V, directly verifying the phase relationship of current leading voltage. Simultaneously, at this time, the U2C output pulse, LOAD_R, and LOAD_CorL are all at high levels, and LOAD_TYPE outputs a stable voltage value corresponding to the capacitive load. The signal logic relationships at each node are consistent with the circuit design expectations.

[0129] The above Figure 8 The waveform diagram shown verifies the complete working process of the circuit under capacitive load conditions. The timing of each node signal is correct and the logic is clear. Finally, it can stably output an analog voltage signal representing the capacitive load, providing a reliable basis for the energy storage power supply microcontroller to adjust the control strategy.

[0130] For example, Figure 9 This is a schematic diagram of key node waveforms under an inductive load condition, used to verify the working process and identification results of the load type identification circuit in this application.

[0131] like Figure 9 As shown, the waveforms from top to bottom are: load current sampling signal AD_I, load voltage sampling signal AD_V, first judgment signal LOAD_R output by the first load judgment module, output waveform of the first AND gate U2B in the second load judgment module, output waveform of the second AND gate U2C, second judgment signal LOAD_CorL output by the second load judgment module, and finally output analog voltage signal LOAD_TYPE representing the load type.

[0132] Among them, AD_I is the load current sampling waveform, and AD_V is the load voltage sampling waveform. The two show a phase relationship where the current lags the voltage, which is consistent with the electrical characteristics of an inductive load. LOAD_R is high, indicating that there is a phase difference between the load voltage and the current. U2C always remains low, and U2B outputs a periodic pulse signal at the rising edge of the voltage zero crossing, indicating that the phase direction detection unit has identified the state of the current lags the voltage. LOAD_CorL is low, indicating that the load is inductive. Finally, LOAD_TYPE outputs a stable second analog voltage signal, corresponding to the identification result of the inductive load.

[0133] Figure 9The two vertical lines in the diagram are time measurement cursors used to mark two time points within the same power frequency cycle. Measurements show that within this cycle, the zero-crossing time of the load current sampling signal AD_I is later than that of the load voltage sampling signal AD_V, directly verifying the phase relationship of current lags voltage. Simultaneously, at this time, the U2B output pulse, LOAD_R is high, LOAD_CorL is low, and LOAD_TYPE outputs a stable voltage value corresponding to the inductive load. The signal logic relationships at each node are consistent with the circuit design expectations.

[0134] The above Figure 9 The waveform diagram shown verifies the complete working process of the circuit under inductive load conditions. The timing of each node signal is correct and the logic is clear. Finally, it can stably output an analog voltage signal representing the inductive load, providing a reliable basis for the energy storage power supply microcontroller to adjust the control strategy.

[0135] For example, Figure 10 This is a schematic diagram of key node waveforms under resistive load conditions, used to verify the working process and identification results of the load type identification circuit in this application.

[0136] like Figure 10 As shown, the waveforms from top to bottom are: load current sampling signal AD_I, load voltage sampling signal AD_V, first judgment signal LOAD_R output by the first load judgment module, output waveform of the first AND gate U2B in the second load judgment module, output waveform of the second AND gate U2C, second judgment signal LOAD_CorL output by the second load judgment module, and finally output analog voltage signal LOAD_TYPE representing the load type.

[0137] Among them, AD_I is the load current sampling waveform, and AD_V is the load voltage sampling waveform. The two are in phase, which is consistent with the electrical characteristics of a resistive load. LOAD_R is low, indicating that there is no phase difference between the load voltage and current. U2B and U2C have no effective pulse output, indicating that the phase direction detection unit has not been triggered. LOAD_CorL is high, which is only used as the status output when there is no phase difference. Finally, LOAD_TYPE outputs a stable first analog voltage signal, corresponding to the identification result of the resistive load.

[0138] Figure 10The two vertical lines in the diagram are time measurement cursors used to mark two time points within the same power frequency cycle. Measurements show that within this cycle, the zero-crossing times of the load current sampling signal AD_I and the load voltage sampling signal AD_V essentially coincide, directly verifying the in-phase relationship between voltage and current. Simultaneously, LOAD_R is low at this time, U2B and U2C have no valid pulse output, and LOAD_TYPE outputs a stable resistive load voltage value. The signal logic relationships at each node are consistent with the circuit design expectations.

[0139] The above Figure 10 The waveform diagram shown verifies the complete working process of the circuit under resistive load conditions. The timing of each node signal is correct and the logic is clear. Finally, it can stably output an analog voltage signal representing the resistive load, providing a reliable basis for the energy storage power supply microcontroller to adjust the control strategy.

[0140] This application also provides an energy storage device that includes a load type identification circuit as shown in any of the above embodiments.

[0141] The energy storage device in this application embodiment can achieve the same technical effect as the load type identification circuit described above.

[0142] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0143] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A load type identification circuit, characterized in that, include: The load voltage and current sampling module is used to acquire load voltage and load current signals; The first load determination module is used to output a first determination signal based on whether there is a phase difference between the load voltage signal and the load current signal; The second load judgment module is used to output a second judgment signal based on the phase order relationship between the load current signal and the load voltage signal when there is a phase difference between the load voltage signal and the load current signal. The signal synthesis output module is used to generate an analog voltage signal representing the load type based on the first judgment signal and the second judgment signal, and output it to the microcontroller. The load type includes any one of resistive load, capacitive load and inductive load. The analog voltage signal represents different load types through different amplitudes. The first load judgment module includes: a square wave conversion unit, used to convert the load voltage signal and the load current signal into two square wave signals respectively; a phase difference detection unit, used to perform logical operations on the two square wave signals and output a pulse signal; and an integration comparison unit, used to integrate the pulse signal to obtain an integrated voltage value, compare the integrated voltage value with a preset reference voltage, and output the first judgment signal. The two square wave signals include a first square wave signal and a second square wave signal. The phase difference detection unit includes: a first NOT gate for inverting the first square wave signal and outputting a first inverted square wave signal; a second NOT gate for inverting the second square wave signal and outputting a second inverted square wave signal; a first AND gate for performing an AND operation on the first and second square wave signals to obtain a first output signal; a second AND gate for performing an AND operation on the first and second inverted square wave signals to obtain a second output signal; and an OR gate for performing an OR operation on the first and second output signals to output the pulse signal. The high-level width of the pulse signal is proportional to the phase difference between the first and second square wave signals.

2. The load type identification circuit according to claim 1, characterized in that, The integral comparison unit includes: An RC charging circuit is used to integrate the pulse signal to obtain the signal integral value; The comparator has its first input terminal connected to the output terminal of the RC charging circuit and receiving the integrated signal value. The second input terminal of the comparator is connected to the preset reference voltage, and the output terminal of the comparator outputs the first judgment signal.

3. The load type identification circuit according to claim 1 or 2, characterized in that, The second load determination module includes: The zero-crossing detection unit is used to generate a voltage zero-crossing square wave signal based on the load voltage signal and a current zero-crossing square wave signal based on the load current signal. A phase direction detection unit is used to detect the level state of the current zero-crossing square wave signal at each rising edge of the voltage zero-crossing square wave signal, and output a first pulse signal or a second pulse signal according to the level state. The charging and discharging unit is used to store energy when receiving the first pulse signal to obtain a first energy storage voltage, and to store energy when receiving the second pulse signal to obtain a second energy storage voltage; The comparison output unit is used to compare the first energy storage voltage with the second energy storage voltage and output the second judgment signal.

4. The load type identification circuit according to claim 3, characterized in that, The phase direction detection unit includes: The first AND gate is used to perform an AND operation on the voltage zero-crossing square wave signal and the current zero-crossing square wave signal, and output the first pulse signal; The NOT gate is used to invert the square wave signal at the zero-crossing point of the current to obtain a second inverted signal; The second AND gate is used to perform an AND operation on the voltage zero-crossing square wave signal and the second inverted signal to output the second pulse signal.

5. The load type identification circuit according to claim 4, characterized in that, The charging and discharging unit includes: a first capacitor and a second capacitor; The first terminal of the first capacitor is connected to the output terminal of the first AND gate, and the second terminal of the first capacitor is connected to the reference ground, for charging when the first pulse signal is received to obtain the first energy storage voltage; The first terminal of the second capacitor is connected to the output terminal of the second AND gate, and the second terminal of the second capacitor is connected to the reference ground, for charging when the second pulse signal is received to obtain the second energy storage voltage; A periodic reset circuit is used to reset and discharge the first capacitor and the second capacitor after each power frequency cycle.

6. The load type identification circuit according to claim 5, characterized in that, The comparison output unit includes a comparator, the non-inverting input of which is connected to the first capacitor, and the inverting input of which is connected to the second capacitor.

7. The load type identification circuit according to claim 1 or 2, characterized in that, The signal synthesis output module includes: The first switch has its control terminal connected to the first judgment signal, its first terminal connected to the signal output terminal, and its second terminal grounded, and is used to turn on when the first judgment signal indicates the existence of a phase difference. The second switch has its control terminal connected to the second judgment signal, its first terminal connected to the signal output terminal, and its second terminal grounded. It is used to turn on when the second judgment signal indicates that the load current signal leads the load voltage signal. Wherein: when both the first switch and the second switch are off, the signal output terminal outputs a first analog voltage signal representing a resistive load; when the first switch is on and the second switch is off, the signal output terminal outputs a second analog voltage signal representing an inductive load; when both the first switch and the second switch are on, the signal output terminal outputs a third analog voltage signal representing a capacitive load.

8. An energy storage device, characterized in that, Includes the load type identification circuit as described in any one of claims 1 to 7.

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