Vehicle-mounted system, dormancy method of vehicle-mounted system, and wake-up method of vehicle-mounted system

Abstract

The invention discloses a vehicle-mounted system, a dormancy method of the vehicle-mounted system and an awakening method of the vehicle-mounted system. The vehicle-mounted system comprises a microcontroller, a system-on-chip and a power management chip, the microcontroller comprises a first universal pin group, the system-on-chip comprises a second universal pin group, the first universal pin group is correspondingly connected with the second universal pin group, and the power management chip is connected with the microcontroller and the system-on-chip. The microcontroller is configured to set the first universal pin group and the second universal pin group to be in a first state in response to a detected dormancy signal, transmit the dormancy signal to the system-on-chip so as to enable the system-on-chip to execute dormancy operation, further determine that the first universal pin group and the second universal pin group are in a second state, and transmit the dormancy signal to the system-on-chip so as to enable the system-on-chip to execute dormancy operation after determining that the first universal pin group and the second universal pin group are in the second state. And controlling the power management chip to power off the system-on-chip, so that the system-on-chip enters a dormant state. The vehicle-mounted system can be quickly started, the cost and the power consumption are reduced, and the user experience is improved.

Description

Technical Field

[0001] The embodiments disclosed in this application relate to the field of vehicle technology, and more specifically, to a vehicle system, a hibernation method for a vehicle system, and a wake-up method for a vehicle system. Background Technology

[0002] In the design of in-vehicle infotainment systems, cold start, as the first startup process after the system is powered on, is the "first hurdle" for the normal operation of the entire vehicle's electronic system. Its stability directly affects whether key functions such as the central control system, navigation, and voice interaction can respond in a timely manner, thus having a profound impact on user experience, safety, and brand perception. However, with the increasing complexity of in-vehicle system functions and the ever-growing size of software stacks, the cold start process involves a large number of operations such as driver loading, middleware initialization, UI system construction, and background service startup. On platforms with limited hardware resources (such as limited CPU frequency and storage I / O performance), this can easily lead to prolonged cold start time and sluggish system response, resulting in negative perceptions of "system sluggishness" and "slow interface loading" after the vehicle is started. Summary of the Invention

[0003] According to embodiments of this application, this application proposes an in-vehicle system, a hibernation method for the in-vehicle system, and a wake-up method for the in-vehicle system to solve the above-mentioned problems.

[0004] The first aspect of this application discloses an in-vehicle system, including: a microcontroller including a first general-purpose pin group; a system-on-a-chip (SoC) including a second general-purpose pin group, the second general-purpose pin group being correspondingly connected to the first general-purpose pin group; and a power management chip connected to the microcontroller and the SoC. The microcontroller is configured to: in response to detecting a sleep signal, set the first general-purpose pin group and the second general-purpose pin group to a first state, transmit the sleep signal to the SoC to cause the SoC to perform a sleep operation, wherein in response to the SoC completing the sleep operation, the SoC sets the first general-purpose pin group and the second general-purpose pin group to a second state; and, upon determining that the first general-purpose pin group and the second general-purpose pin group are in the second state, control the power management chip to power off the SoC, causing the SoC to enter a sleep state.

[0005] In this embodiment, the in-vehicle system includes a microcontroller, a system-on-a-chip (SoC), and a power management chip. The microcontroller includes a first general-purpose pin group, and the SoC includes a second general-purpose pin group. The first and second general-purpose pin groups are connected to each other. The power management chip connects the microcontroller and the SoC. The microcontroller is configured to, in response to detecting a sleep signal, set the first and second general-purpose pin groups to a first state, transmit the sleep signal to the SoC to cause it to perform a sleep operation, and further, after determining that the first and second general-purpose pin groups are in a second state, control the power management chip to power off the SoC, causing it to enter a sleep state. By utilizing the interaction between the microcontroller and the power management chip, and between the microcontroller and the SoC, to control the SoC to enter sleep mode, the in-vehicle system can achieve rapid startup, reduce cost and power consumption, and improve user experience.

[0006] In some embodiments, the microcontroller is further configured to: in response to detecting a wake-up signal, set the first general-purpose pin group and the second general-purpose pin group to a third state, transmit the wake-up signal to the system-on-a-chip, and control the power management chip to power on the system-on-a-chip so that the system-on-a-chip enters a wake-up state.

[0007] In some embodiments, the vehicle system further includes memory and a logic switching circuit, wherein the logic switching circuit includes at least four logic pins, respectively connected to the memory, the microcontroller, the system-on-a-chip (SoC), and a constant voltage supply terminal; the microcontroller is configured to: in response to the completion of the hibernation operation performed by the SoC, control the logic switching circuit to switch the reset pin of the memory from a first connection state to a second connection state; wherein the first connection state includes the reset pin being connected to the SoC, and the second connection state includes the reset pin being connected to the constant voltage supply terminal.

[0008] In some embodiments, the vehicle system includes a first power supply circuit and a second power supply circuit. The first power supply circuit is connected to the system-on-a-chip (SoC), the microcontroller, and the power management chip, respectively. The second power supply circuit is connected to the SoC and the power management chip. The SoC includes a first power terminal and a second power terminal. The first power terminal is connected to the power management chip via the first power supply circuit, and the second power terminal is connected to the power management chip via the second power supply circuit. The power management chip is configured to: control the connection pin between the power management chip and the first power supply circuit to be in a first pin state, so that the first power supply circuit stops supplying power to the SoC; and / or control the connection between the second power supply circuit and the SoC to be disconnected.

[0009] In some embodiments, the second power supply circuit includes a second power supply and a switching circuit, wherein the switching circuit is connected to the second power supply, the power management chip, and the second power supply terminal; the power management chip is configured to control the switching circuit to turn off, thereby disconnecting the connection between the second power supply terminal and the second power supply.

[0010] In some embodiments, the first general-purpose pin group includes a first control pin, a second control pin, a third control pin, and a fourth control pin; the second general-purpose pin group includes a first chip pin, a second chip pin, a third chip pin, and a fourth chip pin; wherein the first control pin is connected to the first chip pin, the second control pin is connected to the second chip pin, the third control pin is connected to the third chip pin, and the fourth control pin is connected to the fourth chip pin; the microcontroller is configured to: in response to detecting a sleep signal, configure the first control pin to a high-level state, so that the first chip pin is in a high-level state, thereby the first general-purpose pin group and the second general-purpose pin group are in the first state.

[0011] In some embodiments, the system-on-a-chip is configured to: in response to the completion of the hibernation operation, configure the third chip pin to a high level state, so that the third control pin is in a high level state, thereby the first general-purpose pin group and the second general-purpose pin group are in the second state.

[0012] In some embodiments, the microcontroller is configured to: in response to detecting a wake-up signal, configure a second control pin to a high level state, so that the second chip pin is in a high level state, thereby the first general-purpose pin group and the second general-purpose pin group are in a third state; and control the power management chip to perform a power-on operation on the system-on-a-chip.

[0013] In some embodiments, the system-on-a-chip is configured to: in response to the completion of a wake-up operation, configure a fourth chip pin to a high level state, so that a fourth control pin is in a high level state; the microcontroller is configured to: in response to the fourth control pin being in a high level state, configure a second control pin to a low level state, and control the logic switch circuit to perform state switching, so as to switch the memory reset pin from a second connection state to a first connection state.

[0014] In some embodiments, the first general-purpose pin group further includes a fifth control pin, and the second general-purpose pin group further includes a fifth chip pin, wherein the fifth control pin is connected to the fifth chip pin; the microcontroller is configured to: control the system-on-a-chip (SoC) to perform a cold start if, after configuring the first control pin to a high level, no second control pin is detected to be in a high level state within a first preset time; or control the SoC to perform a cold start if, after controlling the power management chip to perform a power-on operation on the SoC, no fourth control pin is detected to be in a high level state within a second preset time; or control the power management chip to re-execute the power-on operation if, after controlling the power management chip to perform a power-on operation on the SoC, no fifth control pin is detected to be in a high level state within a third preset time.

[0015] The second aspect of this application discloses a sleep mode method for an in-vehicle system, applied to the in-vehicle system described in the first aspect, comprising: in response to detecting a sleep signal, setting a first general-purpose pin group and a second general-purpose pin group to a first state, transmitting the sleep signal to the system-on-a-chip (SoC) to cause the SoC to perform a sleep operation, wherein in response to the SoC completing the sleep operation, the SoC sets the first general-purpose pin group and the second general-purpose pin group to a second state; determining that the first general-purpose pin group and the second general-purpose pin group are in the second state, controlling the power management chip to power off the SoC, causing the SoC to enter a sleep state.

[0016] In this embodiment, in response to the detection of a sleep signal, the first general-purpose pin group and the second general-purpose pin group are set to a first state, and the sleep signal is transmitted to the system-on-a-chip (SoC) to cause the SoC to perform a sleep operation. Further, after determining that the first and second general-purpose pin groups are in a second state, the power management chip is controlled to power off the SoC, causing the SoC to enter a sleep state. By utilizing the interaction between the microcontroller and the power management chip in the vehicle system, and between the microcontroller and the SoC, the SoC is controlled to enter sleep mode, reducing cost and power consumption while improving the stability of the vehicle system, thereby enhancing the user experience.

[0017] In some embodiments, the method includes: in response to the completion of the hibernation operation by the system-on-a-chip, controlling the logic switch circuit to switch the reset pin of the memory from a first connection state to a second connection state; wherein the first connection state includes the reset pin being connected to the system-on-a-chip, and the second connection state includes the reset pin being connected to the constant voltage terminal.

[0018] In some embodiments, the method includes: controlling the connection pin between the power management chip and the first power circuit to be in a first pin state, so that the first power circuit stops supplying power to the system-on-a-chip; and / or controlling the connection between the second power circuit and the system-on-a-chip to be disconnected.

[0019] In some embodiments, the method includes: controlling the switching circuit to disconnect, thereby disconnecting the connection between the second power supply terminal and the second power supply.

[0020] In some embodiments, the method includes: in response to detecting a sleep signal, configuring a first control pin to a high level state, so that a first chip pin is in a high level state, thereby the first general-purpose pin group and the second general-purpose pin group are in the first state.

[0021] In some embodiments, the method includes: in response to the completion of the hibernation operation, configuring the third chip pin to a high level state, so that the third control pin is in a high level state, thereby the first general-purpose pin group and the second general-purpose pin group are in the second state.

[0022] In some embodiments, the method includes: controlling the system-on-a-chip to perform a cold start in response to the fact that no second control pin is detected to be in a high-level state within a first preset time after configuring the first control pin to a high-level state.

[0023] The third aspect of this application discloses a wake-up method for an in-vehicle system, applied to the in-vehicle system described in the first aspect, comprising: in response to detecting a wake-up signal, setting the first general-purpose pin group and the second general-purpose pin group to a third state; transmitting the wake-up signal to the system-on-a-chip (SoC) and controlling the power management chip to power on the SoC, so that the SoC enters a wake-up state.

[0024] In this embodiment, in response to the detection of a wake-up signal, the first general-purpose pin group and the second general-purpose pin group are set to a third state; the wake-up signal is transmitted to the system-on-a-chip (SoC), and the power management chip is controlled to power on the SoC, thereby enabling the SoC to enter a wake-up state. Through the interaction between the microcontroller and the power management chip in the vehicle system, and between the microcontroller and the SoC, the SoC is controlled to enter a wake-up state, thereby achieving rapid startup, reducing cost and power consumption while improving the stability of the vehicle system and enhancing the user experience.

[0025] In some embodiments, the method includes: in response to detecting a wake-up signal, configuring a second control pin to a high level state, so that the second chip pin is in a high level state, thereby the first general-purpose pin group and the second general-purpose pin group are in a third state; controlling the power management chip to perform a power-on operation on the system-on-a-chip.

[0026] In some embodiments, the method includes: in response to the completion of a wake-up operation, configuring a fourth chip pin to a high level state to cause a fourth control pin to be in a high level state; in response to the fourth control pin being in a high level state, configuring a second control pin to a low level state, and controlling a logic switch circuit to perform a state switching to switch the memory reset pin from a second connection state to a first connection state.

[0027] In some embodiments, the method includes: controlling the system-on-chip to perform a cold start if the fourth control pin is not detected to be in a high-level state within a second preset time after the power management chip performs a power-on operation on the system-on-chip; or controlling the power management chip to re-execute the power-on operation if the fifth control pin is not detected to be in a high-level state within a third preset time after the power management chip performs a power-on operation on the system-on-chip.

[0028] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this application. Attached Figure Description

[0029] The present application will be further described below with reference to the accompanying drawings and embodiments. In the drawings:

[0030] Figure 1 This is a schematic diagram of the structure of the vehicle-mounted system according to an embodiment of this application;

[0031] Figure 2 This is a schematic diagram of the structure of an in-vehicle system according to an embodiment of this application;

[0032] Figure 3 This is a schematic diagram of the structure of an in-vehicle system according to another embodiment of this application;

[0033] Figure 4 This is a partial structural schematic diagram of an embodiment of the vehicle-mounted system of this application;

[0034] Figure 5 This is a circuit diagram of an in-vehicle system according to another embodiment of this application;

[0035] Figure 6 This is a schematic flowchart of a sleep method for an in-vehicle system according to an embodiment of this application;

[0036] Figure 7This is a flowchart illustrating a wake-up method for an in-vehicle system according to an embodiment of this application;

[0037] Figure 8 This is a schematic diagram of a hibernation process according to an embodiment of this application;

[0038] Figure 9 This is a schematic diagram of the wake-up process according to an embodiment of this application;

[0039] Figure 10 This is a schematic diagram of the wake-up process and sleep process according to an embodiment of this application. Detailed Implementation

[0040] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0041] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Additionally, the character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, "many" in this application means two or more. Moreover, the term "at least one" in this application means any combination of at least two of any one or more of a plurality of objects. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C. Furthermore, the terms "first," "second," and "third" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0042] In the design of dedicated vehicle infotainment systems, in order to adapt to the varied and harsh operating conditions in the vehicle environment, including frequent start-stop operations, power voltage fluctuations, large temperature difference operation (such as from extremely cold to high temperature environments), and the continuous test of system stability during long-term operation, it is necessary to pay attention to the reliability and responsiveness of the system in the cold start state, and to minimize the standby power consumption cost of the vehicle infotainment system.

[0043] In some examples, the System-on-Chip (SoC) of an automotive system is divided into multiple power domains, each powered by discrete power devices. Unused power domains can be shut down in standby mode, leaving only the minimum power domain powered. Alternatively, a Power Management Integrated Circuit (PMIC) approach can be used, employing an external PMIC power management module to provide minimum power. However, this approach results in high SoC design complexity, excessive use of power devices, and high cost. If the SoC's power-on / power-down timing relies entirely on the external MCU's I / O ports, issues arise such as inaccurate timing, excessive MCU I / O resource consumption, and the inability to completely power down the SoC, making power consumption difficult to control. While delegating power supply to the PMIC allows for complete SoC power-off, the PMIC chip controls the SoC's power supply; if the SoC malfunctions or freezes, the PMIC cannot be controlled to power down the SoC to complete the hibernation / reset / reboot process.

[0044] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of an in-vehicle system according to an embodiment of this application. The in-vehicle system 10 includes a microcontroller 100, a system-on-a-chip (SoC) 200, and a power management chip 300. The microcontroller 100 is connected to both the SoC 200 and the power management chip 300, and the SoC 200 is also connected to the power management chip 300. The microcontroller 100, also known as a microcontroller unit (MCU) or single-chip microcomputer, can be used to perform real-time control tasks with fast response speed. The SoC 200, also known as a system-on-a-chip (SoC), can support running complex operating systems, autonomous driving, and other high-computing tasks. The power management chip 300, also known as a power management unit (PMU), can manage multiple power domains of the microcontroller 100 and the SoC 200.

[0045] The microcontroller 100 includes a first general-purpose pin group 110, and the system-on-a-chip 200 includes a second general-purpose pin group 210. The first general-purpose pin group 110 and the second general-purpose pin group 210 are correspondingly connected. For example, at least one pin in the first general-purpose pin group 110 is connected to at least one pin in the second general-purpose pin group 210 in a one-to-one correspondence, that is, the microcontroller 100 and the system-on-a-chip 200 can maintain a connection through the first general-purpose pin group 110 and the second general-purpose pin group 210.

[0046] The microcontroller 100 is configured to, in response to the detection of a sleep signal, set the first general-purpose pin group 110 and the second general-purpose pin group 210 to a first state, and transmit the sleep signal to the system-on-a-chip 200, so that the system-on-a-chip 200 performs a sleep operation. For example, when the vehicle system 10 is operating normally, if the microcontroller 100 detects an external sleep event, it can set the pins in the first general-purpose pin group 110 and the second general-purpose pin group 210 to a first level state, so that the system-on-a-chip 200 enters a sleep process and terminates all processes. Further, after the microcontroller 100 determines that the first general-purpose pin group 110 and the second general-purpose pin group 210 are in a second state, it controls the power management chip 300 to power off the system-on-a-chip 200, so that the system-on-a-chip 200 enters a sleep state. In response to the completion of the sleep operation by the system-on-chip 200, the system-on-chip 200 sets the first general-purpose pin group 110 and the second general-purpose pin group 210 to a second state, for example, setting the level state of the pins in the first general-purpose pin group 110 and the second general-purpose pin group 210 to the second level state.

[0047] In this embodiment, the vehicle system 10 includes a microcontroller 100, a system-on-a-chip (SoC) 200, and a power management chip 300. The microcontroller 100 includes a first general-purpose pin group 110, and the SoC 200 includes a second general-purpose pin group 210. The first general-purpose pin group 110 and the second general-purpose pin group 210 are connected to each other. The power management chip 300 is connected to the microcontroller 100 and the SoC 200. The microcontroller 100 is configured to, in response to detecting a sleep signal, set the first general-purpose pin group 110 and the second general-purpose pin group 210 to a first state, transmit the sleep signal to the SoC 200 to cause the SoC 200 to perform a sleep operation, and further, after determining that the first general-purpose pin group 110 and the second general-purpose pin group 210 are in a second state, control the power management chip 300 to power off the SoC 200, causing the SoC 200 to enter a sleep state. By utilizing the interaction between the microcontroller 100 and the power management chip 300 of the vehicle system 10, and between the microcontroller 100 and the system-on-a-chip 200, the system-on-a-chip 200 can be controlled to enter sleep mode, thereby enabling the vehicle system 10 to start up quickly, reducing cost and power consumption, and improving user experience.

[0048] In some embodiments, the microcontroller 100 is further configured to, in response to detecting a wake-up signal, set the first general-purpose pin group 110 and the second general-purpose pin group 210 to a third state, transmit the wake-up signal to the system-on-a-chip 200, and control the power management chip 300 to power on the system-on-a-chip 200 so that the system-on-a-chip 200 enters a wake-up state.

[0049] The microcontroller 100 is configured to set the first general-purpose pin group 110 and the second general-purpose pin group 210 to a third state in response to the detection of a wake-up signal. For example, after the vehicle system 10 enters sleep mode, if an external wake-up event triggers, the microcontroller 100 can change the voltage level of the pins in the first general-purpose pin group 110 and the second general-purpose pin group 210 to the third voltage level state to transmit the wake-up signal to the system-on-a-chip 200. Simultaneously, the microcontroller 100 controls the power management chip 300 to power on the system-on-a-chip 200, enabling the system-on-a-chip 200 to start and enter the wake-up process.

[0050] In some embodiments, such as Figure 2 As shown, Figure 2 This is a schematic diagram of the structure of an in-vehicle system according to an embodiment of this application. The in-vehicle system 10 also includes a memory 400 and a logic switch circuit 500. The logic switch circuit 500 includes at least four logic pins 501, which are respectively connected to the microcontroller 100, the system-on-a-chip 200, the memory 400 and the constant voltage terminal VDD.

[0051] Memory 400 can be a synchronous dynamic random access memory (Double Data Rate SDRAM), such as LPDDR4 / 4X. Microcontroller 100 is configured to respond to the completion of a sleep operation by system-on-chip 200, i.e., detecting that the first general-purpose pin group 110 and the second general-purpose pin group 210 are in a second state, and then control logic switching circuit 500 to switch the reset pin 401 of memory 400 from a first connection state to a second connection state. The first connection state includes reset pin 401 being connected to system-on-chip 200, and the second connection state includes reset pin 401 being connected to a constant supply voltage terminal VDD. Switching the reset pin 401 of memory 400 from the first connection state to the second connection state means that microcontroller 100 takes over the DDR's RESET, realizing the IO PAD state that needs to be maintained in DDR self-refresh mode.

[0052] In other words, after the system-on-a-chip 200 enters a sleep state, the system-on-a-chip 200 is powered off, and only the microcontroller 100 and the memory 400 work. Moreover, the microcontroller 100 is in a standby state, which reduces the overall power consumption of the vehicle system 10.

[0053] In some embodiments, such as Figure 3 As shown, Figure 3This is a schematic diagram of the structure of an in-vehicle system according to another embodiment of this application. The in-vehicle system 10 includes a first power supply circuit 610 and a second power supply circuit 620. The first power supply circuit 610 is connected to a microcontroller 100, a system-on-a-chip (SoC) 200, and a power management chip 300, respectively. The second power supply circuit 620 is connected to both the SoC 200 and the power management chip 300. The SoC 200 includes a first power terminal 201 and a second power terminal 202. The first power terminal 201 is connected to the power management chip 300 through the first power supply circuit 610, and the second power terminal 202 is connected to the power management chip 300 through the second power supply circuit 620. The first power supply circuit 610 may be the core power supply of the SoC 200, and the second power supply circuit 620 may include multiple power domains within the SoC 200.

[0054] The power management chip 300 is configured to control the connection pin between the power management chip 300 and the first power circuit 610 to be in a first pin state, so that the first power circuit 610 stops supplying power to the system-on-a-chip 200; and / or control the connection between the second power circuit 620 and the system-on-a-chip 200 to be disconnected.

[0055] In some examples, after the microcontroller 100 determines that the first general-purpose pin group 110 and the second general-purpose pin group 210 are in a second state, it controls the power management chip 300 to power off the system-on-a-chip 200, causing the system-on-a-chip 200 to enter a sleep state. Power management chip 300 powering off the system-on-a-chip 200 can be achieved, for example, by controlling the connection pin between the power management chip 300 and the first power circuit 610 to be in a first pin state, so that the first power circuit 610 stops supplying power to the system-on-a-chip 200. The first pin state can refer to a low-level state, such as the power management chip 300 controlling the pull-down of the enable signal input to the first power circuit 610. After the first power circuit 610 stops supplying power to the system-on-a-chip 200, the power management chip 300 controls the connection between the second power circuit 620 and the SOC to disconnect, so that the second power circuit 620 also stops supplying power to the system-on-a-chip 200. Of course, this can also be done simultaneously with or before the first power circuit 610 stops supplying power to the system-on-a-chip 200; this application does not specifically limit this.

[0056] In some embodiments, such as Figure 3 As shown, the second power supply circuit 620 includes a second power supply 6201 and a switching circuit 6202. The switching circuit 6202 is connected to the second power supply 6201, the power management chip 300, and the second power supply terminal 202.

[0057] The second power supply circuit 620 may include multiple second power supplies 6201 and corresponding switching circuits 6202, the specific number of which is not limited herein. Figure 3 Taking the second power supply 6201 and the switching circuit 6202 as an example, the switching circuit 6202 is connected to the second power supply 6201, the power management chip 300, and the second power supply terminal 202. When the switching circuit 6202 is on, the second power supply 6201 supplies power to the system-on-a-chip 200; when the switching circuit 6202 is off, the second power supply 6201 stops supplying power to the system-on-a-chip 200.

[0058] The power management chip 300 is configured to control the switch circuit 6202 to turn off, thereby disconnecting the connection between the second power supply terminal 202 and the second power supply 6201. In some examples, the microcontroller 100 controls the switch circuit 6202 to turn off after determining that the first general-purpose pin group 110 and the second general-purpose pin group 210 are in a second state, thus disconnecting the connection between the second power supply terminal 202 and the second power supply 6201, and consequently, the second power supply 6201 stops supplying power to the system-on-a-chip 200.

[0059] Understandably, in this embodiment, the power-on and power-off timing of the system-on-chip 200 can be implemented through the MTP (Manufacturing Test Program) program built into the power management chip 300, reducing the dependence of the system-on-chip 200's power timing on the microcontroller 100's control. The microcontroller 100 only acts as the overall controller. Furthermore, utilizing the power management chip 300's own I / O in the power-on and power-off timing of the system-on-chip 200 allows for more accurate timing synchronization and reduces the number of I / O operations required by the microcontroller 100.

[0060] like Figure 4 As shown, Figure 4 This is a partial structural diagram of an in-vehicle system according to an embodiment of this application. The first general-purpose pin group 110 includes a first control pin M_IO_0, a second control pin M_IO_1, a third control pin M_IO_2, and a fourth control pin M_IO_3; the second general-purpose pin group 210 includes a first chip pin S_IO_0, a second chip pin S_IO_1, a third chip pin S_IO_2, and a fourth chip pin S_IO_3; wherein, the first control pin M_IO_0 is connected to the first chip pin S_IO_0, the second control pin M_IO_1 is connected to the second chip pin S_IO_1, the third control pin M_IO_2 is connected to the third chip pin S_IO_2, and the fourth control pin M_IO_3 is connected to the fourth chip pin S_IO_3.

[0061] In some examples, the signal transmission between the first control pin M_IO_0 and the first chip pin S_IO_0 is output from the microcontroller 100 to the system-on-a-chip 200. The system-on-a-chip 200 reads the I / O change to determine if a sleep signal is present. The signal transmission between the second control pin M_IO_1 and the second chip pin S_IO_1 is output from the microcontroller 100 to the system-on-a-chip 200 to determine the system startup status; a high level indicates resumption, and a high level indicates normal operation. The signal transmission between the third control pin M_IO_2 and the third chip pin S_IO_2 is output from the system-on-a-chip 200 to the microcontroller 100. The microcontroller 100 uses the I / O signal to determine the current system suspend status of the system-on-a-chip; a high level indicates successful system suspend. The signal transmission between the fourth control pin M_IO_3 and the fourth chip pin S_IO_3 is output from the system-on-a-chip 200 to the microcontroller 100; a high level indicates resumption is complete.

[0062] In some embodiments, the microcontroller 100 is configured to configure the first control pin M_IO_0 to a high level state in response to the detection of a sleep signal, so that the first chip pin S_IO_0 is in a high level state, thereby the first general-purpose pin group 110 and the second general-purpose pin group 210 are in a first state.

[0063] For example, when the vehicle system 10 is operating normally, the microcontroller 100 detects a sleep signal and configures the first control pin M_IO_0 to a high level, thereby putting the first chip pin S_IO_0 at a high level. At this time, the first general-purpose pin group 110 and the second general-purpose pin group 210 are in the first state. Further, the system-on-a-chip 200 detects a change in the state of the first chip pin S_IO_0, indicating an external request for sleep, and thus enters the sleep process, performs a sleep operation, and terminates all processes.

[0064] In some embodiments, the system-on-a-chip 200 is configured to configure the third chip pin S_IO_2 to a high level in response to the completion of a sleep operation, so that the third control pin M_IO_2 is in a high level state, and the first general-purpose pin group 110 and the second general-purpose pin group 210 are in a second state.

[0065] For example, in response to the completion of the sleep operation by the system-on-chip 200, the system-on-chip 200 configures the third chip pin S_IO_2 to a high level, thereby putting the third control pin M_IO_2 at a high level. At this time, the first general-purpose pin group 110 and the second general-purpose pin group 210 are in the second state. Further, the microcontroller 100 detects the state change of the third control pin M_IO_2, determines that the system-on-chip 200 has ended all processes, and then controls the power management chip 300 to power off the system-on-chip 200, so that the system-on-chip 200 enters a sleep state.

[0066] In some embodiments, the microcontroller 100 is configured to configure the second control pin M_IO_1 to a high level in response to the detection of a wake-up signal, so that the second chip pin S_IO_1 is in a high level state, and then the first general-purpose pin group 110 and the second general-purpose pin group 210 are in a third state; and control the power management chip 300 to perform a power-on operation on the system-on-a-chip 200.

[0067] After the vehicle system 10 enters sleep mode, an external wake-up event triggers. The microcontroller 100 detects the wake-up signal and configures the second control pin M_IO_1 to a high level, thereby putting the second chip pin S_IO_1 at a high level. This means that the first general-purpose pin group 110 and the second general-purpose pin group 210 are in their third state. Simultaneously, the microcontroller 100 controls the power management chip 300 to perform a power-on operation on the system-on-a-chip 200. Further, if the system-on-a-chip 200 detects a change in the state of the second chip pin S_IO_1, indicating an external wake-up request, it will enter the wake-up process after power-on.

[0068] In some embodiments, the system-on-a-chip 200 is configured to set the fourth chip pin S_IO_3 to a high level in response to the completion of a wake-up operation, thereby causing the fourth control pin M_IO_3 to be in a high level state. The microcontroller 100 is configured to set the second control pin M_IO_1 to a low level in response to the fourth control pin M_IO_3 being in a high level state, and to control the logic switch circuit 500 to perform a state switching to switch the reset pin 401 of the memory 400 from a second connection state to a first connection state.

[0069] After the system-on-a-chip (SoC) 200 completes the wake-up operation, it configures the fourth chip pin S_IO_3 to a high level, thereby putting the fourth control pin M_IO_3 at a high level. Further, the microcontroller 100 detects that the fourth control pin M_IO_3 is at a high level, thus determining that the SoC 200 has started. It then configures the second control pin M_IO_1 to a low level and controls the logic switch circuit 500 to switch the reset pin 401 of the memory 400 from the second connection state to the first connection state. In other words, the SoC 200 takes over the DDR's RESET, completing one wake-up process.

[0070] In some embodiments, the first general-purpose pin group 110 further includes a fifth control pin M_IO_4 ( Figure 4 (Not shown in the image), the second general-purpose pin group 210 also includes a fifth chip pin S_IO_4 ( Figure 4 (Not shown in the image), the fifth control pin M_IO_4 is connected to the fifth chip pin S_IO_4.

[0071] Microcontroller 100 is configured to control system-on-a-chip 200 to perform a cold start if the second control pin M_IO_1 is not detected to be high within a first preset time after configuring the first control pin M_IO_0 to a high level. In some examples, during the sleep process, microcontroller 100 starts timing by pulling the first control pin M_IO_0 high. If the second control pin M_IO_1 is not detected to be high within the first preset time, microcontroller 100 controls power management chip 300 to power on system-on-a-chip 200. Microcontroller 100 then pulls the first control pin M_IO_0 high again, causing system-on-a-chip 200 to enter the sleep process again. If the sleep operation cannot be completed within the first preset time, system-on-a-chip 200 is powered down directly, and the next operation is marked as a cold start, rather than entering a sleep state. The difference between a cold start and entering a sleep state for system-on-a-chip 200 includes whether the memory 400 is powered down. If the sleep operation can be completed within the first preset time, the next operation can be marked as a wake-up start. The first preset time can be 60 seconds.

[0072] The microcontroller 100 is configured to control the system-on-chip 200 to perform a cold start if the fourth control pin M_IO_3 is not detected to be high within a second preset time after the power management chip 300 performs a power-on operation on the system-on-chip 200. In some examples, during the wake-up process, after the microcontroller 100 controls the power management chip 300 to perform a power-on operation on the system-on-chip 200, a timer starts. If the fourth control pin M_IO_3 is not detected to be high within the second preset time, meaning the system-on-chip 200 has not completed the wake-up operation, the microcontroller 100 controls the system-on-chip 200 to directly perform a cold start, i.e., restart the system-on-chip 200. The second preset time can be 3 seconds.

[0073] The microcontroller 100 is configured to control the power management chip 300 to re-execute the power-on operation in response to a third preset time period after the power management chip 300 performs a power-on operation on the system-on-chip 200. In some examples, the microcontroller 100 controls the system-on-chip 200 to be powered on via the power management chip 300. If the system-on-chip 200 fails to configure the fifth chip pin S_IO_4 to a high level after the third preset time period, the microcontroller 100 will control the power management chip 300 to power on the system-on-chip 200 again. The first preset time period can be 1 second.

[0074] Please see Figure 5 , Figure 5 This is a circuit diagram of an in-vehicle system according to another embodiment of this application. Figure 5 The vehicle-mounted system includes an MCU, a SOC, a PMU, LPDDR4 / 4X, logic switches, a CORE power supply U3, and an ACC Detect circuit. Specifically, the MCU can be the microcontroller 100 mentioned above, the SOC can be the system-on-a-chip 200 mentioned above, the PMU can be the power management chip 300 mentioned above, the LPDDR4 / 4X can be the memory 400 mentioned above, the logic switches can be the logic switch circuit 500 mentioned above, and the CORE power supply U3 can be the first power supply circuit 610 mentioned above.

[0075] In some examples, such as Figure 5As shown, the vehicle's infotainment system can be powered by the vehicle's 12V battery. The battery BATT is connected to the infotainment system, and the front-end circuit of the system is a voltage regulator and filter circuit. The low-power automotive-grade MCU is powered by a wide-input LDO power supply U5. U5 is in constant output mode, meaning that U5 has an output whenever the battery is connected, so the MCU is in a continuous running state, but it exists in a normal (normal operation) state and a sleep (sleep) state. It is in normal state when ACC ON is detected, and enters sleep state when ACC OFF is detected. When an external ACC ON signal is received, Q1 will conduct, and MCU IO_5 will detect a low level. The MCU enters the normal state and pulls IO_6 high to output the enable signal of U2. U2 outputs the power supply SYS_VCC for U1 (PMU). After enabling U2 by pulling IO_6 high, the MCU pulls IO_7 high to enable U1, and pulls IO_8 high to put U1 (PMU) into normal state. Finally, it pulls IO_9 high to control U9 so that the RESET source of LPDDR4 comes from the SOC.

[0076] After U1 (PMU) enters the normal state, according to the internal NVM program, it first pulls IO_0 high to enable U3 to output CORE power to supply power to the SOC. Then, it pulls IO_1 and IO_2 high to enable SW1 and SW2 (the aforementioned switch circuit 6202), connecting them to the SOC terminal, and then outputs VDD1 and VDD2. After the SOC and LPDDR4 power supplies are powered on, the SOC starts up and pulls DDR_RST_N high to load the program, and the system startup is complete. After the system startup is complete, the SOC's IO_0 to IO_4 (the aforementioned first chip pin S_IO_0, second chip pin S_IO_1, third chip pin S_IO_2, fourth chip pin S_IO_3, and fifth chip pin S_IO_4) interact with the MCU's IO_0 to IO_4 (the aforementioned first control pin M_IO_0, second control pin M_IO_1, third control pin M_IO_2, fourth control pin M_IO_3, and fourth control pin M_IO_4) to confirm the status.

[0077] Furthermore, when an external ACC OFF signal arrives, Q1 will turn off. The MCU's IO_5 will then detect a high level. The MCU interacts with the SOC's IO_0 to IO_4 via IO_0 to IO_4, causing the SOC to terminate all processes and obtain its current state. After the SOC terminates all processes and feeds back its current state to the MCU, the MCU pulls IO_9 low, switching the LPDDR4's RESET source to VDD2, and then pulls IO_8 low, causing U1 (PMU) to enter standby mode.

[0078] The process of U1 entering standby mode involves first pulling IO_0 low to disable the SOC's CORE power supply U3, then pulling IO_ and IO_2 low to disconnect VDD1 and VDD2 from the SOC, thus officially entering standby mode. At this time, all SOC power supplies are turned off, except for VDD1 and VDD2 power supplies of U7, keeping the LPDDR4 in self-refresh mode. The MCU can detect via I2C (Inter-Integrated Circuit) that U1 and U3 have turned off their power and entered standby mode; the MCU then enters low-power mode, ending the sleep process.

[0079] Please see Figure 6 , Figure 6 This is a flowchart illustrating the hibernation method of an in-vehicle system according to an embodiment of this application. The entity executing this method can be the aforementioned in-vehicle system 10. For example, the in-vehicle system 10 can be integrated into various in-vehicle devices, including intelligent transportation terminals such as autonomous vehicles.

[0080] It should be noted that if substantially the same result is obtained, the method of this application is not based on... Figure 6 The sequence of processes shown is limited.

[0081] In some possible implementations, this method can be implemented by the processor calling computer-readable instructions stored in memory, such as... Figure 6 As shown, the method may include the following steps:

[0082] S61: In response to detecting a sleep signal, the first general-purpose pin group and the second general-purpose pin group are set to a first state, and the sleep signal is transmitted to the system-on-a-chip (SoC) to cause the SoC to perform a sleep operation. In response to the completion of the sleep operation by the SoC, the SoC sets the first general-purpose pin group and the second general-purpose pin group to a second state.

[0083] In some examples, in response to the detection of a sleep signal, the microcontroller 100 sets the first general-purpose pin group 110 and the second general-purpose pin group 210 to a first state and transmits the sleep signal to the system-on-a-chip 200, causing the system-on-a-chip 200 to perform a sleep operation. For example, when the vehicle system 10 is operating normally, if the microcontroller 100 detects an external sleep event, it can set the pins in the first general-purpose pin group 110 and the second general-purpose pin group 210 to a first level state, causing the system-on-a-chip 200 to enter a sleep process and terminate all processes.

[0084] In response to the completion of the sleep operation by the system-on-chip 200, the system-on-chip 200 sets the first general-purpose pin group 110 and the second general-purpose pin group 210 to a second state, for example, setting the level state of the pins in the first general-purpose pin group 110 and the second general-purpose pin group 210 to the second level state.

[0085] S62: Determine that the first general-purpose pin group and the second general-purpose pin group are in the second state, control the power management chip to power off the system chip, so that the system chip enters the sleep state.

[0086] For example, after the microcontroller 100 determines that the first general-purpose pin group 110 and the second general-purpose pin group 210 are in the second state, it controls the power management chip 300 to cut off the power to the system-on-a-chip 200, so that the system-on-a-chip 200 enters a sleep state.

[0087] In this embodiment, in response to the detection of a sleep signal, the first general-purpose pin group 110 and the second general-purpose pin group 210 are set to a first state, and the sleep signal is transmitted to the system-on-a-chip 200 to cause the system-on-a-chip 200 to perform a sleep operation. Further, after determining that the first general-purpose pin group 110 and the second general-purpose pin group 210 are in a second state, the power management chip 300 is controlled to power off the system-on-a-chip 200, causing the system-on-a-chip 200 to enter a sleep state. The interaction between the microcontroller 100 of the vehicle system 10 and the power management chip 300, and between the microcontroller 100 and the system-on-a-chip 200, controls the system-on-a-chip 200 to enter sleep mode, reducing cost and power consumption while improving the stability of the vehicle system 10, thereby enhancing the user experience. In some embodiments, in response to the completion of the hibernation operation by the system-on-a-chip 200, the control logic switch circuit 500 performs a state switch to switch the reset pin 401 of the memory 400 from a first connection state to a second connection state; wherein, the first connection state includes the reset pin 401 being connected to the system-on-a-chip 200, and the second connection state includes the reset pin 401 being connected to the constant supply voltage terminal VDD.

[0088] In some embodiments, the connection pin between the control power management chip 300 and the first power circuit 610 is in a first pin state, so that the first power circuit 610 stops supplying power to the system-on-a-chip 200; and / or the connection between the second power circuit 620 and the system-on-a-chip 200 is disconnected.

[0089] In some embodiments, the control switch circuit 6202 is turned off, thereby disconnecting the connection between the second power supply terminal 202 and the second power supply 6201.

[0090] In some embodiments, in response to the detection of a sleep signal, the first control pin M_IO_0 is configured to a high level state, so that the first chip pin is in a high level state S_IO_0, and the first general-purpose pin group 110 and the second general-purpose pin group 120 are in a first state.

[0091] In some embodiments, in response to the completion of the sleep operation, the third chip pin S_IO_2 is configured to a high level state, so that the third control pin M_IO_2 is in a high level state, and then the first general-purpose pin group 110 and the second general-purpose pin group 120 are in a second state.

[0092] In some embodiments, in response to the fact that the second control pin M_IO_1 is not detected to be in a high-level state within a first preset time after configuring the first control pin M_IO_0 to a high-level state, the system SoC 200 performs a cold start.

[0093] Please see Figure 7 , Figure 7 This is a flowchart illustrating the wake-up method for an in-vehicle system according to an embodiment of this application. The entity executing this method can be the aforementioned in-vehicle system 10. For example, the in-vehicle system 10 can be integrated into various in-vehicle devices, including intelligent transportation terminals such as autonomous vehicles.

[0094] It should be noted that if substantially the same result is obtained, the method of this application is not based on... Figure 7 The sequence of processes shown is limited.

[0095] In some possible implementations, this method can be implemented by the processor calling computer-readable instructions stored in memory, such as... Figure 7 As shown, the method may include the following steps:

[0096] S71: In response to the detection of a wake-up signal, the first general-purpose pin group and the second general-purpose pin group are set to the third state, and the wake-up signal is transmitted to the system-on-a-chip.

[0097] In response to the detection of a wake-up signal, the microcontroller 100 sets the first general-purpose pin group 110 and the second general-purpose pin group 210 to a third state. For example, after the vehicle system 10 enters sleep mode, if an external wake-up event is triggered, the microcontroller 100 can change the level state of the pins in the first general-purpose pin group 110 and the second general-purpose pin group 210 to the third level state to transmit the wake-up signal to the system-on-a-chip 200.

[0098] S72: Controls the power management chip to power on the system-on-a-chip (SoC) so that the SoC enters a wake-up state.

[0099] The microcontroller 100 controls the power management chip 300 to power on the system-on-a-chip 200, so that the system-on-a-chip 200 starts up and enters the wake-up process.

[0100] In this embodiment, in response to the detection of a wake-up signal, the first general-purpose pin group 110 and the second general-purpose pin group 210 are set to a third state; the wake-up signal is transmitted to the system-on-a-chip 200, and the power management chip 300 is controlled to power on the system-on-a-chip 200, so that the system-on-a-chip 200 enters the wake-up state. The interaction between the microcontroller 100 and the power management chip 300, and between the microcontroller 100 and the system-on-a-chip 200, controls the system-on-a-chip 200 to enter the wake-up state, thereby achieving rapid startup, reducing cost and power consumption while improving the stability of the vehicle system 10 and enhancing the user experience.

[0101] In some embodiments, in response to the detection of a wake-up signal, the second control pin M_IO_1 is configured to a high level state, so that the second chip pin S_IO_2 is in a high level state, and then the first general-purpose pin group 110 and the second general-purpose pin group 120 are in a third state; the power management chip 300 is controlled to perform a power-on operation on the system-on-a-chip 200.

[0102] In some embodiments, in response to the completion of the wake-up operation, the fourth chip pin S_IO_3 is configured to a high level state, so that the fourth control pin M_IO_3 is in a high level state; in response to the fourth control pin M_IO_3 being in a high level state, the second control pin M_IO_1 is configured to a low level state, and the logic switch circuit 500 is controlled to perform state switching, so as to switch the reset pin 401 of the memory 400 from the second connection state to the first connection state.

[0103] In some embodiments, in response to the control power management chip 300 not detecting the fourth control pin M_IO_3 being in a high level state within a second preset time after performing a power-on operation on the system-on-chip 200, the control power management chip 300 performs a cold start; or in response to the control power management chip 300 not detecting the fifth control pin M_IO_4 being in a high level state within a third preset time after performing a power-on operation on the system-on-chip 200, the control power management chip 300 re-performs the power-on operation.

[0104] For easier understanding, please refer to Figures 8-10 and combined Figure 5 The application scenarios of this application embodiment are illustrated with examples. At the MCU, such as... Figures 8-9 As shown, Figure 8 This is a schematic diagram of a hibernation process according to an embodiment of this application. Figure 9 This is a schematic diagram of the wake-up process according to an embodiment of this application. At the SOC, as... Figure 10 As shown, Figure 10 This is a schematic diagram illustrating the wake-up and sleep processes according to an embodiment of this application. It should be noted that the numbers and labels in the diagram are for descriptive reference only and do not limit the order of steps.

[0105] In some examples, the MCU can enter the first process phase when the in-vehicle system is operating normally, such as... Figure 8 As shown.

[0106] S81: Determine if GPIO_4 is pulled high. Determining if GPIO_4 is pulled high determines if the SOC is powered on correctly. GPIO stands for General-purpose input / output port.

[0107] One of the judgment results of step S81 is that GPIO_4 is not pulled high, so step S82 is executed.

[0108] The second result of step S81 is that GPIO_4 goes high, and step S83 is executed.

[0109] S82: Determine if the third preset time has been exceeded. The third preset time can be 1 second.

[0110] If one of the judgment results of step S82 is that GPIO_4 has not been pulled high for more than the third preset time, then step S821 will be executed.

[0111] S821: Reboot the SOC.

[0112] The second result of step S82 is that the time GPIO_4 has not been pulled high has not exceeded the third preset time, so step S81 is executed.

[0113] S83: Detect whether there is a hibernation event.

[0114] One of the judgment results of step S83 is that no hibernation event was detected, so step S83 continues.

[0115] The second result of step S83 is that a hibernation event was detected, and step S84 is executed.

[0116] S84: MCU pulls GPIO_0 high. The MCU pulls GPIO_0 high to send an external request to the SOC to sleep, causing it to perform a sleep operation.

[0117] S85: Determines whether GPIO_2 is pulled high. That is, it determines whether the MCU has received the signal that the SOC has completed sleep mode.

[0118] One of the judgment results of step S85 is that GPIO_2 is pulled high, confirming that the SOC has completed the sleep operation, and then step S861 is executed.

[0119] The second result of step S85 is that GPIO_2 is not pulled high, so step S871 is executed.

[0120] S861: Power off the SOC. The MUC determines that the SOC has completed its hibernation operation and further controls the PNU to power off the SOC.

[0121] S862: MCU takes over DDR RESET.

[0122] S863: MCU pulls GPIO_2 and GPIO_0 low to save the sleep state.

[0123] S864: Check if the SOC power-off was successful.

[0124] One of the judgment results of step S864 is that the SOC was successfully powered off, confirming that hibernation was completed.

[0125] The second result of step S864 is that the SOC was not successfully powered off, so step S861 is executed.

[0126] S871: Determine if the first preset time has been exceeded. Determine if the time GPIO_2 has not been pulled high has exceeded the first preset time, which can be 60 seconds.

[0127] If one of the judgment results of step S871 is that the first preset time has not been exceeded, then step S85 will continue to be executed.

[0128] If the second result of step S871 exceeds the first preset time, then step S872 is executed.

[0129] S872: Determine if this is the first hibernation timeout.

[0130] If the result of step S872 is not the first timeout, but the second timeout, then proceed to step S875.

[0131] The second result of step S872 is that the first sleep timeout has occurred, and step S873 is executed.

[0132] S873: Reboot the SOC.

[0133] S874: The MCU marks the SOC to enter the sleep process again. The response is that the first sleep timeout has occurred. After restarting the SOC, the MCU can still control the SOC to continue performing the sleep operation. If the sleep is successful, the process ends; if the sleep fails, a sleep timeout check is performed (i.e., step S85).

[0134] S875: Powering down the SOC marks the next startup as a cold start. In response to a sleep timeout that is not the first time, the MCU powers down the SOC and does not power it back on, marking the next startup as a cold start instead of a wake-up.

[0135] After confirming that the hibernation is complete, the MCU can enter the second process stage, such as... Figure 9 As shown.

[0136] S91: Detection wake-up.

[0137] S92: Detect whether there is a wake-up event.

[0138] One of the results of step S92 is that there is a wake-up event, so step S93 is executed.

[0139] The second result of step S92 is that there is no wake-up event, so step S92 is executed.

[0140] S93: Pull GPIO_1 high. The MCU pulls GPIO_1 high to enable the SOC to perform a wake-up operation.

[0141] S94: Determines if GPIO_3 is pulled high. The MCU determines if the SOC has completed the wake-up operation.

[0142] One of the results of step S94 is that GPIO_3 goes high, and step S95 is executed.

[0143] The second result of step S94 is that GPIO_3 is not pulled high, so step S98 is executed.

[0144] S95: Pull GPIO_1 low.

[0145] S96: SOC takes over DDR RESET.

[0146] S97: Wake-up complete.

[0147] S98: Determine if the second preset time has been exceeded. For example, the second preset time is 3 seconds.

[0148] If one of the judgment results of step S98 exceeds the second preset time, then step S99 is executed.

[0149] The second result of step S98 is that the second preset time has not been exceeded, so step S94 is executed.

[0150] S99: Reboot the SOC and mark the SOC as a cold boot.

[0151] In some examples, the SOC workflow, such as Figure 10 As shown.

[0152] S1011: SOC powered on.

[0153] S1012: SOC startup.

[0154] S1013: Pull GPIO_4 high. Indicates that the SOC is powered on normally.

[0155] S1014: Determine if GPIO_1 is pulled high. Detect if there is a wake-up signal.

[0156] One of the judgment results of step S1014 is that GPIO_1 is pulled high, and step S1015 is executed.

[0157] The second result of step S1014 is that GPIO_1 is not pulled high, so step S1016 is executed.

[0158] S1015: Execute the SOC wake-up process.

[0159] S1016: Execute the SOC cold start process.

[0160] S1017: Launch the main interface.

[0161] S1018: Pull GPIO_3 high. GPIO_3 is pulled high when the SOC is performing a wake-up process. If the SOC is performing a cold start process, GPIO_3 does not need to be pulled high.

[0162] S1019: Detect GPIO_0 edge events.

[0163] S1020: Send a hibernation request to the vehicle system.

[0164] S1021: The vehicle system has entered hibernation mode.

[0165] S1022: SOC hibernation complete.

[0166] S1023: Pull GPIO_3 low, pull GPIO_2 high.

[0167] For a normal cold start of the SOC, please refer to [the relevant documentation / reference]. Figure 5 and Figure 10In short, when the entire device powers on (GPIO0-GPIO4 are all low when the device is powered off), the MCU powers on the PMU, controlling the SOC to power on. After the SOC starts, it boots into the preloader (hardware boot loader). First, it pulls GPIO4 high to indicate that the chip is powered on normally (if the SOC has an I / O detection pin, this GPIO4 does not need to be set; and if a quick power-on check of the SOC is not required, this GPIO4 also does not need to be set). In the preloader, it checks if GPIO1 is high. If it is not high, it indicates a normal boot, and the DDR initialization (DDR Init) normal boot process is followed. After the HSM (Hardware Security Module) boots, it determines that the boot is normal and does not send a wake-up message to the Kernel. The Kernel follows the Android system's initialization loading process. When the Android Home screen (main interface) is displayed, it sends a Home Ready message to the HSM via IPC (Inter-Process Communication). The HSM pulls GPIO3 high. When the MCU detects GPIO3 being high, it indicates that a boot process is complete, and the entire device is in normal working condition. "Home Ready" can refer to the status message indicating that the in-vehicle infotainment system has been successfully started and has entered the home screen.

[0168] For information on the hibernation process, please refer to [link / reference]. Figure 5 and Figure 8When the device is operating normally, the MCU detects an external sleep event and pulls GPIO0 high. The HSM detects the change in GPIO0's state, indicating an external request to sleep. The HSM sends a message to the virt_pwrkey (Virtual Power Key) driver in the kernel via IPC. The virt_pwrkey driver generates a sleep socket message and sends it to the VHAL (Vehicle Hardware Abstraction Layer) module. The VHAL then reports the corresponding sleep event to the Car Power Management service for processing based on the event mechanism of the Android Automotive infotainment platform, following the native sleep process of Android Automotive. After the sleep process completes the Kernel Suspend Flow, the CPU enters the ATF (ARM Trusted Firmware) for data storage and processing, and notifies the HSM to perform a suspend (secure suspension) via IPC when the last CPU shuts down. After the HSM receives the hibernation request, it processes the callbacks of the Task processes registered by each driver, saves the data, and finally pulls GPIO3 low and GPIO2 high. The MCU detects GPIO2 going high and operates the PMU register to power down the SOC. The MCU controls the logic switch to make the constant power supply VDD2 take over the DRAM's reset, and the DDR enters self-refresh mode. Finally, the MCU pulls GPIO0, 1, 2, 3, and 4 low to avoid increasing power consumption due to weakly high GPIO states, and the MCU saves the hibernation state. At this point, the MCU checks the PMU's I / O status again to determine if the SOC power-down was successful. If the power-down was unsuccessful, it will operate the PMU again to power down the SOC. If the power-down was successful, the entire hibernation process is complete.

[0169] Regarding sleep timeout handling, in some examples, the MCU starts timing by pulling GPIO0 high. If the set time (e.g., 80 seconds) is exceeded and GPIO2 is not pulled high, the MCU will control the PMU to perform a power-down / power-on process on the SOC. For a cold start of the SOC, the MCU will pull GPIO0 high, and the SOC will re-enter the sleep process. If sleep cannot be completed within 80 seconds, the SOC will be powered down directly, and the next attempt will be marked as a cold start. If the next sleep cycle is successful, the next attempt will be marked as a wake-up start. Regarding chip power supply timeout handling, in some examples, the MCU controls the SOC to power on via the PMU. If the set time (e.g., 1 second) is exceeded and GPIO4 is not pulled high, the MCU will control the PMU to power on the SOC again.

[0170] For information on the wake-up process, please refer to [link / reference]. Figure 5 and Figure 9 After the entire machine enters sleep mode, if an external wake-up event is triggered, the MCU pulls GPIO1 high and controls the PMU to power on the SOC. After the SOC starts up, it starts up to the preloader, which first pulls GPIO4 high to indicate that the chip is powered on normally (if the SOC has an IO detection pin, there is no need to set GPIO4; if there is no need to quickly determine the SOC power-on, there is no need to set GPIO4). In the preloader, if GPIO1 is high, the HSM will initiate the wake-up process. After the HSM completes the FreeRTOS (Free Real-Time Operating System) startup, it will perform a Task Resume callback and then wake up the AP core using Warm boot. The AP (Application Processor) core, which is woken up by Warm boot, will first perform a Kernel Resume using the Suspend reverse process. The virt_pwrkey module will then simulate sending a wake-up socket event to VHAL to perform the Android Automotive wake-up operation. Then, it will return to userspace to follow the Android system's wake-up process. After the Home screen is displayed, a HomeReady message will be sent to the HSM via IPC. After receiving the Home Ready message, the HSM will pull GPIO3 high. The MCU will detect that GPIO3 is high and pull GPIO1 low. The MCU will control the logic switch to make the SOC (DRAM RESET is output by Y) take over the DRAM RESET, indicating that a wake-up has been completed.

[0171] Regarding wake-up timeout handling, in some examples, the MCU controls the PMU to power the SOC and start timing. If the MCU does not detect GPIO3 going high within the set time (e.g., 3 seconds), it will restart the SOC and go through the cold start process.

[0172] Understandably, the vehicle-mounted system in this embodiment fully utilizes existing vehicle resources, eliminating the need for additional power supply devices and enabling the complete shutdown of all power domains of the SOC, thus reducing power consumption. System power supply can be achieved through a single PMU, reducing the number of external discrete power supply devices. Furthermore, the PMU's built-in MTP program implements the SOC's power-on and power-off timing, reducing the SOC power timing's dependence on MCU control; the MCU only acts as the overall controller. By cleverly utilizing the PMU's own I / O to participate in the SOC power-on and power-off timing, the timing becomes more precise while saving on the number of MCU I / Os used. In other words, multiple I / Os are cleverly used to establish MCU and SOC status acquisition.

[0173] Furthermore, by using an MCU as the main control unit, the status of the SOC and PMU can be obtained in real time. When an abnormality occurs in the SOC or PMU, the MCU plays a central control role and can restart the entire system.

[0174] In this system, after hibernation, the SOC is powered off, and only the MCU and DRAM operate. The MCU is in standby mode with low power consumption. In other words, using the MCU as the main control unit improves the stability and recoverability of the entire system. Simultaneously, it reduces the design complexity of the SOC and increases the success rate of SOC tape-out.

[0175] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.

[0176] In the several embodiments provided in this application, it should be understood that the disclosed methods and related devices can be implemented in other ways. For example, the related device implementations described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication disconnection shown or discussed may be indirect coupling or communication disconnection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0177] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0178] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0179] Those skilled in the art will readily recognize that numerous modifications and variations can be made to the apparatus and method while maintaining the teachings of this application. Therefore, the above disclosure should be considered limited only by the scope of the appended claims.

Claims

1. A vehicle-mounted system, characterized in that, include: The microcontroller includes a first general-purpose pin group; The system-on-a-chip includes a second general-purpose pin group, which is correspondingly connected to the first general-purpose pin group; A power management chip, wherein the power management chip is connected to the microcontroller and the system-on-a-chip; The microcontroller is configured as follows: In response to the detection of a sleep signal, the first general-purpose pin group and the second general-purpose pin group are set to a first state, and the sleep signal is transmitted to the system-on-a-chip (SoC) to cause the SoC to perform a sleep operation. In response to the completion of the sleep operation by the SoC, the SoC sets the first general-purpose pin group and the second general-purpose pin group to a second state. Once the first general-purpose pin group and the second general-purpose pin group are determined to be in the second state, the power management chip is controlled to power off the system-on-a-chip, causing the system-on-a-chip to enter a sleep state.

2. The vehicle-mounted system according to claim 1, characterized in that, The microcontroller is also configured to: In response to the detection of a wake-up signal, the first general-purpose pin group and the second general-purpose pin group are set to a third state, the wake-up signal is transmitted to the system-on-a-chip, and the power management chip is controlled to power on the system-on-a-chip so that the system-on-a-chip enters a wake-up state.

3. The vehicle-mounted system according to claim 1, characterized in that, The vehicle system also includes memory and logic switching circuitry, wherein the logic switching circuitry includes at least four logic pins, which are respectively connected to the memory, the microcontroller, the system-on-a-chip and the constant voltage supply terminal. The microcontroller is configured to: In response to the completion of the hibernation operation by the system-on-a-chip, the logic switch circuit is controlled to switch the state of the memory reset pin from the first connection state to the second connection state. The first connection state includes the reset pin being connected to the system-on-a-chip, and the second connection state includes the reset pin being connected to the constant voltage terminal.

4. The vehicle-mounted system according to claim 1, characterized in that, The vehicle system includes a first power supply circuit and a second power supply circuit. The first power supply circuit is connected to the system-on-a-chip, the microcontroller, and the power management chip, respectively. The second power supply circuit is connected to the system-on-a-chip and the power management chip. The system-on-a-chip includes a first power supply terminal and a second power supply terminal. The first power supply terminal is connected to the power management chip through a first power supply circuit, and the second power supply terminal is connected to the power management chip through a second power supply circuit. The power management chip is configured as follows: Control the connection pin between the power management chip and the first power circuit to be in a first pin state, so that the first power circuit stops supplying power to the system-on-a-chip; and / or The connection between the second power supply circuit and the system-on-a-chip is disconnected.

5. The vehicle-mounted system according to claim 4, characterized in that, The second power supply circuit includes a second power supply and a switching circuit, wherein the switching circuit is connected to the second power supply, the power management chip and the second power supply terminal; The power management chip is configured as follows: The switch circuit is turned off, thus disconnecting the second power supply terminal from the second power supply.

6. The vehicle-mounted system according to claim 1, characterized in that, The first general-purpose pin group includes a first control pin, a second control pin, a third control pin, and a fourth control pin; the second general-purpose pin group includes a first chip pin, a second chip pin, a third chip pin, and a fourth chip pin. Wherein, the first control pin is connected to the first chip pin, the second control pin is connected to the second chip pin, the third control pin is connected to the third chip pin, and the fourth control pin is connected to the fourth chip pin; The microcontroller is configured to: In response to the detection of a sleep signal, the first control pin is configured to a high level state, so that the first chip pin is in a high level state, and the first general-purpose pin group and the second general-purpose pin group are in the first state.

7. The vehicle-mounted system according to claim 6, characterized in that, The system-on-chip is configured as follows: In response to the completion of the sleep operation, the third chip pin is configured to a high level, so that the third control pin is in a high level state, thereby causing the first general-purpose pin group and the second general-purpose pin group to be in the second state; or The microcontroller is configured to: In response to the detection of a wake-up signal, the second control pin is configured to a high level state, so that the second chip pin is in a high level state, and then the first general-purpose pin group and the second general-purpose pin group are in a third state; The power management chip is controlled to perform a power-on operation on the system-on-a-chip.

8. The vehicle-mounted system according to claim 6, characterized in that, The first general-purpose pin group further includes a fifth control pin, and the second general-purpose pin group further includes a fifth chip pin, wherein the fifth control pin is connected to the fifth chip pin; The system-on-chip is configured as follows: In response to the completion of the wake-up operation, the fourth chip pin is configured to a high level state, so that the fourth control pin is in a high level state; The microcontroller is configured to: In response to the fourth control pin being in a high-level state, the second control pin is configured to a low-level state, and the logic switch circuit is controlled to switch the memory reset pin from the second connection state to the first connection state; or In response to the system-on-a-chip performing a cold start if no second control pin is detected to be high within a first preset time after the first control pin is configured to be high; or In response to the power management chip performing a power-on operation on the system-on-a-chip and not detecting the fourth control pin being in a high-level state within a second preset time, the system-on-a-chip is controlled to perform a cold start; or If the fifth control pin is not detected to be in a high-level state within a third preset time after the power management chip performs a power-on operation on the system-on-chip, the power management chip is controlled to re-execute the power-on operation.

9. A method for hibernation of an onboard system, characterized in that, The vehicle system applied to any one of claims 1-8 comprises: In response to the detection of a sleep signal, the first general-purpose pin group and the second general-purpose pin group are set to a first state, and the sleep signal is transmitted to the system-on-a-chip (SoC) to cause the SoC to perform a sleep operation. In response to the completion of the sleep operation by the SoC, the SoC sets the first general-purpose pin group and the second general-purpose pin group to a second state. Once the first general-purpose pin group and the second general-purpose pin group are determined to be in the second state, the power management chip is controlled to power off the system-on-a-chip, causing the system-on-a-chip to enter a sleep state.

10. A wake-up method for an in-vehicle system, characterized in that, The vehicle system applied to any one of claims 1-8 comprises: In response to the detection of a wake-up signal, the first general-purpose pin group and the second general-purpose pin group are set to a third state, and the wake-up signal is transmitted to the system-on-a-chip; The power management chip is controlled to power on the system-on-a-chip (SoC) so that the SoC enters a wake-up state.

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