A chip testing device, a chip testing system and a chip testing method
By performing logical operations on multiple input and output pins of the chip under test, a unified test result is obtained and output, which solves the problem of low resource utilization in chip reliability testing and achieves more efficient testing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2024-12-31
- Publication Date
- 2026-06-30
AI Technical Summary
Existing chip reliability testing resources have low utilization rates, especially when the data bit width is large. The number of input and output pins of the sample under test is large, occupying a lot of signal ports on the aging board, resulting in low resource utilization.
By performing logical operations on the signals output from multiple input/output pins of the chip under test, a unified test result is obtained, and the result is output through a unified output pin, thus reducing the occupation of pin resources.
It improves the resource utilization of chip testing equipment, reduces the demand for test output pins, and improves testing efficiency and accuracy.
Smart Images
Figure CN122307298A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of chip testing technology, specifically to a chip testing apparatus, a chip testing system, and a chip testing method. Background Technology
[0002] In the design and development phase of semiconductor chips, reliability testing is a crucial step in ensuring product quality. Reliability testing of semiconductor chips typically employs aging tests, which involve aging the sample (e.g., the chip under test) in an aging device. After aging to a certain time point or a certain number of cycles, functional tests are performed to determine whether the sample has failed after aging.
[0003] However, the resource utilization rate of the above reliability tests still needs to be improved. Summary of the Invention
[0004] To address the aforementioned issues, this disclosure provides a chip testing apparatus, a chip testing system, and a chip testing method.
[0005] In a first aspect, embodiments of this disclosure provide a chip testing apparatus, including:
[0006] The chip under test includes multiple input / output pins, which output test output signals during the testing process of the chip under test;
[0007] A logic operation circuit is used to perform logic operations on multiple test output signals output from the multiple input / output pins to obtain the test result of the chip under test, and to output the test result through a unified output pin.
[0008] Secondly, embodiments of this disclosure provide a chip testing system, including:
[0009] An aging apparatus for aging chips to be tested, the aging apparatus including an aging board;
[0010] The aging board is connected to at least one chip testing device, which is the chip testing device as described in the first aspect.
[0011] The aging board is used to read the test results of the chip under test output by the chip testing device, and to determine whether the chip under test has failed based on the test results.
[0012] Thirdly, embodiments of this disclosure provide a chip testing method, including:
[0013] Aging the chip to be tested;
[0014] A chip testing device is used to apply a test signal to the chip under test, so that multiple input / output pins of the chip under test output test output signals respectively; wherein, the chip testing device is the chip testing device as described in the first aspect;
[0015] Furthermore, the chip testing device for the chip under test performs logical operations on multiple test output signals output from multiple input / output pins of the chip under test to obtain the test result of the chip under test, wherein the test result of the chip under test is output through a unified output pin of the chip testing device;
[0016] Based on the test results of the chip under test obtained from the unified output pin, it is determined whether the chip under test has failed.
[0017] The chip testing apparatus provided in this disclosure, when testing a chip under test, performs logical operations on multiple test output signals from multiple input / output pins of the chip under test to obtain the test result of the chip under test, and then outputs the test result through a unified output pin. It is evident that the multiple test output signals from the multiple input / output pins of the chip under test are not output as separate test results, but rather, after performing logical operations on the multiple test output signals from multiple input / output pins, a unified test result of the chip under test is obtained and then output through a unified output pin. Therefore, the chip testing apparatus does not need to set multiple test output pins; it can use a unified output pin to output a unified test result of the chip under test, reducing the pin resources of the chip testing apparatus's test output pins. Thus, the pin resources occupied by the test result of the chip under test are saved, and resource utilization is improved. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0019] Figure 1 This is a schematic diagram of the signal connection of an aging board.
[0020] Figure 2 This is a schematic diagram of the chip testing apparatus provided in this disclosure.
[0021] Figure 3 This is a schematic diagram of the logic operation circuit in the chip testing device provided in this disclosure.
[0022] Figure 4This is another schematic diagram of the logic operation circuit in the chip testing device provided in this disclosure.
[0023] Figure 5 This is another schematic diagram of the logic operation circuit in the chip testing device provided in this disclosure.
[0024] Figure 6 It is a truth table of the logic operation circuit in the chip testing device provided in this disclosure.
[0025] Figure 7 This is a schematic diagram of a signal connection between an aging plate and multiple test samples.
[0026] Figure 8 This is a table showing the relationship between the DUT output bit width and the resources of the aging equipment.
[0027] Figure 9 This is a graph showing the relationship between the number of DUTs that can be tested simultaneously and the output bit width of the DUTs.
[0028] Figure 10 This is a schematic diagram of the chip testing system provided in this publication.
[0029] Figure 11 This is a flowchart illustrating the chip testing method provided in this disclosure.
[0030] Figure 12 This is a timing diagram of each signal in the chip testing method provided in this disclosure.
[0031] Figure 13 This is a schematic diagram of a simulation result of the chip testing device provided in this disclosure.
[0032] Figure 14 This is another simulation result diagram of the chip testing device provided in this disclosure. Detailed Implementation
[0033] As the background technology shows, the resource utilization rate of existing chip reliability testing methods needs to be improved. The following analysis, using an existing chip reliability testing method, explains why the resource utilization rate of chip testing methods needs to be improved.
[0034] In existing aging test methods, an aging furnace is required to age the chip under test in order to simulate the impact of conditions such as temperature, humidity and voltage that often occur during chip use on chip reliability.
[0035] During aging testing, each chip under test is mounted on a carrier board (Test Chip), which includes test circuitry. The carrier board is connected to an aging board in an aging oven. Multiple carrier boards, also known as Device Under Test (DUTs), are connected to the aging board. Each DUT has at least control pins and input / output pins (IO pins).
[0036] Figure 1 This is a signal connection diagram for an aging board, such as... Figure 1 As shown, the aging board has multiple signal ports (e.g., Signal 1 to Signal n), which can be divided into control ports and acquisition ports. The control ports (e.g., Signal 1) are used to control the control pins of the sample under test (e.g., DUT1), which are typically used to control the sample during the aging test. The acquisition ports (e.g., Signal 2 to Signal n) are used to acquire the outputs of the input / output pins of the sample under test, which can be used to return test data from the sample during the aging test.
[0037] The number of input / output pins on a test sample is related to the data bit width of the chip under test (DUT). The larger the data bit width of the DUT, the more input / output pins the test sample needs. For example, if the data bit width of a DUT chip is 32 bits, the test sample requires 32 input / output pins to output the test data. Therefore, when the data bit width of the DUT chip is large, the test sample needs to provide a large number of input / output pins to connect to the burn-in board, occupying more pins and signal ports on the burn-in board, resulting in lower resource utilization.
[0038] Therefore, this disclosure provides a chip testing apparatus, comprising:
[0039] The chip under test includes multiple input / output pins, which output test output signals during the testing process of the chip under test;
[0040] A logic operation circuit is used to perform logic operations on multiple test output signals output from the multiple input / output pins to obtain the test result of the chip under test, and to output the test result through a unified output pin.
[0041] The chip testing apparatus provided in this disclosure, when testing a chip under test, performs logical operations on multiple test output signals from multiple input / output pins of the chip under test to obtain the test result of the chip under test, and then outputs the test result through a unified output pin. It is evident that the multiple test output signals from the multiple input / output pins of the chip under test are not output as separate test results, but rather, after performing logical operations on the multiple test output signals from multiple input / output pins, a unified test result of the chip under test is obtained and then output through a unified output pin. Therefore, the chip testing apparatus does not need to set multiple test output pins; it can use a unified output pin to output a unified test result of the chip under test, reducing the pin resources of the chip testing apparatus's test output pins. Thus, the pin resources occupied by the test result of the chip under test are saved, and resource utilization is improved.
[0042] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.
[0043] Figure 2 This is a schematic diagram of the chip testing apparatus provided in this disclosure. Figure 2 As shown, the chip testing apparatus 10 provided in this disclosure includes:
[0044] The chip under test 11 includes multiple input / output pins 110, which output test output signals during the testing process of the chip under test;
[0045] The logic operation circuit 12 is used to perform logic operations on the multiple test output signals output from the multiple input / output pins 110 to obtain the test result of the chip under test 11, and to output the test result through a unified output pin 120.
[0046] When testing the chip under test 11, multiple input / output pins 110 will output test output signals. These multiple test output signals are input to the logic operation circuit 12 for logic operation to obtain the test result of the chip under test 11. The test result is then output through a unified output pin 120.
[0047] For example, specifically, since each input / output pin 110 outputs a test output signal during testing, meaning the number of output signals is the same as the number of input / output pins 110, and after the logic operation performed by the logic operation circuit 12, the test result of the chip under test 11 is obtained. Since the test result of the chip under test 11 is a single signal, and the test result can be output through the output pin 120, the pin resources occupied by the test result are saved compared to the test output signal, thereby reducing the time cost of chip testing and improving the efficiency of chip testing. Furthermore, the test result output by the output pin 120 is used to indicate whether the chip has failed.
[0048] In some specific implementations, the chip under test can be a memory chip, such as a non-volatile memory chip (eFlash).
[0049] In some embodiments, the logic operation circuit 12 has multiple logic operation modes, each of which corresponds to a desired value of the test output signal. In this case, such as... Figure 3 As shown, the logic operation circuit 12 includes:
[0050] Multiple logic operation modules 121 are provided, wherein each logic operation module 121 corresponds to a logic operation mode and is used to perform logic operations of the corresponding logic operation mode by taking multiple test output signals output from the multiple input / output pins 110 as inputs. Each logic operation module 121 also receives test output signals from all input / output pins of the chip under test and performs logic operations on the test output signals corresponding to the target logic operation module.
[0051] The mode pin 123 is used to set the target logic operation module of the logic operation circuit 12. Specifically, the target logic operation module is the logic operation module 121 corresponding to the logic operation mode. The operation mode signal input / output selection module 122 provided by the mode pin 123 is used to set the output selection module 122 to select the output result of the target logic operation module.
[0052] The output selection module 122 is used to select the logic operation result of the target logic operation module as the test result of the chip under test based on the setting of the mode pin 123, and to output the test result of the chip under test through the unified output pin 120. The output selection module 122 selects the test result of the target logic operation module corresponding to the mode pin from the test results of the chip under test output by multiple logic operation modules 121 according to the setting of the mode pin 123, and outputs it through the output pin 120.
[0053] In some embodiments, the logic operation circuit 12 further includes: a logic operation selection module, configured to select and enable a target logic operation module from the plurality of logic transport modules 121 based on the setting of the mode pin 123, so that the target logic operation module performs corresponding logic operations on the plurality of test output signals output by the plurality of input / output pins; and to disable non-target logic operation modules among the plurality of logic transport modules.
[0054] Since the method of selecting the logic operation result of the target logic operation module as the test result of the chip under test based on the setting of the mode pin 123 requires all logic operation modules 121 to participate in the operation, it may lead to a waste of computing resources. Therefore, the logic operation selection module can be used to select the enabled target logic operation module from the multiple logic transport modules 121 based on the mode pin 123, and perform corresponding logic operations on the multiple test output signals output by the multiple input and output pins to improve the utilization rate of computing resources.
[0055] In some specific implementations, the mode pin 123, used to set the target logic operation module of the logic operation circuit, includes setting the target logic operation module based on the expected value of the test output signal. The expected value of the test output signal is the expected test output signal output during the aging test when the chip under test is not faulty. When the expected value of the test output signal is the same as the actual test output signal output by the chip under test, it indicates that the chip is not faulty.
[0056] In some implementations, the multiple target logic operation modes include: an AND operation mode and an OR NOT operation mode; wherein the AND operation mode corresponds to a first value of the expected value of the test output signal, and the OR NOT operation mode corresponds to a zero value of the expected value of the test output signal.
[0057] At this time, the plurality of logical operation modules include:
[0058] The AND gate module, corresponding to the AND operation mode, is used to perform an AND operation with multiple test output signals output from the multiple input / output pins as inputs;
[0059] The NOR gate module, corresponding to the NOR operation mode, is used to perform NOR operations with multiple test output signals output from the multiple input / output pins as inputs.
[0060] For some chips under test, such as memory chips, the test output signal during the test process can only be a first value or a zero value. The first value and the zero value indicate different values at the same bit in the data output by the memory chip during the test. Specifically, the first value can be 1, and the zero value can be 0. Therefore, when the expected value of the test output signal is the first value, the test result of the chip under test can be obtained by performing an AND operation on the multiple test output signals output from the multiple input / output pins. Similarly, when the expected value of the test output signal is the zero value, the test result of the chip under test can be obtained by performing a NOR operation on the multiple test output signals output from the multiple input / output pins.
[0061] Figure 4 This is another schematic diagram of the logic operation circuit in the chip testing device provided in this disclosure. In one specific embodiment, such as Figure 4 As shown, in the logic operation circuit, the multiple input / output pins include IO0, IO1, IO2, ..., IO71. The AND gate module and the NOR gate module receive multiple test output signals from IO0 to IO71. The AND gate module performs an AND operation, and the NOR gate module performs a NOR operation to obtain the test results of the chip under test. These two test results are input to the output selection module MUXBlock. According to the mode selection pin Mode, the test result of the chip under test that needs to be output is selected from the test results and output through the output pin Q.
[0062] Figure 5 An exemplary circuit diagram of a logic operation circuit including two input / output pins is provided, such as... Figure 5 As shown, when the input / output pins are IO0 and IO1, according to... Figure 5The logic operation circuit shown can perform logical operations on the test output signal, select and output the test result. For example, when the mode selection pin Mode is set to 1, the target logic operation module is a NOR operation module; when the mode selection pin Mode is set to 0, the target logic operation module is an AND operation module. When the mode selection pin Mode is 1, it indicates that the expected value of the test output signal is zero. The logic operation circuit operates in NOR operation mode, and therefore the test result output by the circuit connected to the "1" input terminal of the MUX is selected as the test result of the chip under test. When the mode selection pin Mode is 0, it indicates that the expected value of the test output signal is first. Therefore, the logic operation circuit operates in AND operation mode, and the test result output by the circuit connected to the "0" input terminal of the MUX is selected as the test result of the chip under test. Finally, the test result of the chip under test is output through the output pin Q.
[0063] In some specific implementations, the mode pin is used to set the target logic operation module based on the expected value of the test output signal, including:
[0064] If the expected value of the test output signal is the first value, then the AND gate module is set as the target logic operation module;
[0065] If the expected value of the test output signal is zero, then the NOR gate module is set as the target logic operation module.
[0066] Wherein, the first value indicates logical truth. Therefore, when the expected value of the test output signal is the first value, the AND gate module can be set as the target logic operation module, so that when any test output signal is not the first value, the logic operation result calculated by the AND gate module is the zeroth value indicating logical false, indicating chip failure. When the expected value of the test output signal is the zeroth value, the NOR gate module can be set as the target logic operation module, so that when any test output signal is not the zeroth value, the logic operation result calculated by the NOR gate module is the zeroth value indicating logical false, indicating chip failure.
[0067] Furthermore, in some specific embodiments, the AND gate module is used to perform an AND operation with multiple test output signals output from the multiple input / output pins as inputs, including:
[0068] If all of the multiple test output signals are the first value, perform an AND operation to obtain the logical operation result of the first value, indicating that the chip under test is expected to output the first value and has not failed; if at least one of the multiple test output signals is not the first value, perform an AND operation to obtain the logical operation result of the zeroth value, indicating that the chip under test is expected to output the first value and has failed.
[0069] The NOR gate module is used to perform NOR operations by taking multiple test output signals from the multiple input / output pins as inputs, including:
[0070] If all of the multiple test output signals are zero values, perform a NOR operation to obtain the first logical operation result, indicating that the chip under test is expected to output a zero value and has not failed; if at least one of the multiple test output signals is not a zero value, perform a NOR operation to obtain the zero value logical operation result, indicating that the chip under test is expected to output a zero value and has failed.
[0071] by Figure 4 Taking the logic operation circuit shown as an example, when the mode selection pin Mode = 1, the logic operation circuit is in AND operation mode (Pattern is Read 1); when the mode selection pin Mode = 0, the logic operation circuit is in NOR operation mode (Pattern is Read 0). The first value is 1, and the zeroth value is 0. The truth table of this logic operation circuit is as follows: Figure 6 As shown in the diagram. It can be seen that when the logic operation circuit is in NOR mode, if all test output signals (IO0-71) are 0, the test result output by output pin Q is the first value 1, indicating that the chip under test is not faulty; if any of the test output signals IO0-71 is 0, the test result output by output pin Q is the first value 0, indicating that the chip under test is faulty. Similarly, when the logic operation circuit is in AND mode, if all test output signals (IO0-71) are 1, the test result output by output pin Q is the first value 1, indicating that the chip under test is not faulty; if any of the test output signals IO0-71 is 0, the test result output by output pin Q is the first value 0, indicating that the chip under test is faulty.
[0072] In some specific implementations, the expected value of the test output signal corresponds to the write value written to the chip under test; wherein, if the write value written to the chip under test is a first value, then the expected value of the test output signal is a first value, and if the write value written to the chip under test is a zero value, then the expected value of the test output signal is a zero value.
[0073] Since the chip under test is a non-volatile memory chip, the testing process requires writing test data first and then reading (rereading back) the test data to determine if the two are consistent. That is, the expected value of the read test data is the written test data. For example, when the written test data is a first value, the expected value of the read test data is also the first value. Specifically, if the test data written on a certain input / output pin is 1, and the value of the test data read through that input / output pin is 1, which is the same as the written test data, it means that the input / output pin has not failed. If all input / output pins have not failed, it means that the chip under test has not failed.
[0074] In some specific embodiments, the chip testing apparatus further includes a comparison control pin for controlling whether the logic operation circuit is enabled. Since it is sometimes necessary to analyze specific input / output pins of the chip under test, the chip testing apparatus also includes a comparison control pin COMP. When the comparison control pin COMP indicates that the logic operation circuit is enabled, the chip testing apparatus performs logic operations to obtain a test result and outputs it. When the comparison control pin COMP indicates that the logic operation circuit is disabled, the chip testing apparatus directly outputs multiple test output signals from the multiple input / output pins to analyze the test signals output from specific input / output pins.
[0075] From a hardware resource perspective, the chip testing device adds three pins: a comparison control pin, a mode selection pin, and an output pin, as well as a logic operation circuit. The increase in area and pins due to the logic operation circuit is relatively small, that is, the utilization rate of the testing device resources is improved with a small hardware resource cost.
[0076] As can be seen, the chip testing apparatus provided in this disclosure, when testing the chip under test, performs logical operations on multiple test output signals output from multiple input / output pins of the chip under test to obtain the test result of the chip under test, and outputs the test result through a unified output pin. Furthermore, since the logic operation circuit has multiple target logic operation modes, it can correspond to multiple expected values of the test output signals. Only the test result obtained by the logic operation module corresponding to the expected value needs to be output, thereby improving the chip testing efficiency. In addition, the chip testing apparatus also includes a comparison control pin, which selects between outputting the test result through the output pin and directly outputting multiple test output signals output from the multiple input / output pins, so as to analyze the test signals output from specific input / output pins and improve the accuracy and flexibility of chip testing.
[0077] Figure 7This is a schematic diagram of a signal connection between an aging plate and multiple test samples, such as... Figure 7 As shown, the aging board has multiple signal ports (e.g., Signal 1 to Signal 49), including one one-to-many signal port (e.g., Signal 1) and multiple one-to-one signal ports (e.g., Signal 2 to Signal 49). Specifically, since the control pins of the samples under test do not output signals, they can be connected to the one-to-many signal port (e.g., Signal 1) on the aging board. Thus, the aging board can control the control pins of all samples under test (e.g., D1-D48) on the aging board through a one-to-many signal. The input / output pins of the samples under test output relevant data during the test. The aging board needs to collect this data to analyze the state of the samples under test in the aging furnace, thereby obtaining test results such as whether the samples under test are operating stably or have failed in the aging furnace. Therefore, the input / output pins of each sample under test need to be connected one-to-one to the one-to-one signal port (e.g., Signal 2 to Signal 49) of the aging board.
[0078] The number of input / output pins on a test sample (DPS) is related to the data bit width of the chip under test (DUT). The larger the data bit width of the DUT, the more input / output pins the DPS will have. (Reference) Figure 8 With 48 test samples (DUTs) connected to the aging board, if the test samples have 30 control pins and the data bit width of the chip under test (i.e., the DUT output bit width) is 1 bit, 78 signal ports on the aging board will be required; if the test samples have 30 control pins and the DUT output bit width is 4 bits, 222 signal ports on the aging board will be required; and so on. If the DUT output bit width is N bits, N*48+30 signal ports on the aging board will be required.
[0079] However, the number of signal ports on the burn-in board cannot be increased indefinitely, and the number of signal ports that the burn-in board can control simultaneously is also limited. With 256 signal ports on the burn-in board and 30 control pins on the test sample, the relationship between the number of DUTs that can be tested simultaneously and the DUT output bit width is as follows: Figure 9 As shown, when the DUT output bit width is 8 bits, the aging board can test 28 DUTs simultaneously; when the DUT output bit width is 36 bits, the aging board can test 6 DUTs simultaneously; and when the DUT output bit width is 72 bits, the aging board can only test 3 DUTs simultaneously. That is, if 48 DUTs need to be tested during the aging process, 16 test operations are required to test all DUTs. Assuming each test takes 10 seconds, it would take 10 * 16 = 160 seconds to complete the testing of all DUTs. Clearly, the efficiency of current chip testing methods needs improvement.
[0080] Therefore, this disclosure also provides a chip testing system, such as Figure 10 As shown, the chip testing system includes:
[0081] Aging equipment 1 is used to age the chip to be tested, and the aging equipment 1 includes an aging board 20.
[0082] The aging board 20 is connected to at least one chip testing device 10, and the chip testing device 10 is the chip testing device described in the foregoing embodiment;
[0083] The aging board 20 is used to read the test results of the chip under test output by the chip testing device 10, and to determine whether the chip under test has failed based on the test results.
[0084] As can be seen, the chip testing system provided in this disclosure ages the chip under test using the aging equipment. The aging board in the aging equipment is connected to the chip testing device, reads the test results output by the output pins, and determines whether the chip under test is faulty based on the test results. Compared with directly reading the test output signal output by the chip under test, reading the test results output by the output pins can determine the validity of a larger number of chips under test at once, thereby improving chip testing efficiency.
[0085] In some embodiments, the aging board 20 is used to read the test results of the chip under test output by the chip testing device 10, and to determine whether the chip under test tested by the chip testing device 10 has failed based on the test results, including:
[0086] If the test result of the chip under test output by the chip testing device is the first value, then the chip under test is determined to be valid.
[0087] If the test result of the chip under test output by the chip testing device is zero, then the chip under test is determined to be faulty.
[0088] In some specific implementations, the first value represents logical true, that is, the first value is 1; the zeroth value represents logical false, that is, the zeroth value is 0. The aging board can determine whether the chip under test is faulty based on the value of the test result output by the chip testing device. For example, when the test result is 1, it means that the chip under test is not faulty, and when the test result is 0, it means that the chip under test is faulty.
[0089] When there are multiple chip testing devices, the chip testing system can determine the failed chip among the multiple chips to be tested based on the multiple test results received by the aging board. In some specific embodiments, the aging board includes multiple test result interfaces, and each test result interface is connected to a unified output pin of a chip testing device to obtain the test results output through the unified output pin.
[0090] Specifically, refer to Figure 10 Based on the test results received from different signal ports of the aging board 20, it can be determined whether the chip under test in each chip testing device 10 connected to the aging board 20 is faulty. When one or more test results are not zero, it is determined that the chip under test in the chip testing device 10 corresponding to the zero-value test result is faulty.
[0091] During the testing of a chip under test by a chip testing system, if a readback operation is not performed, and the chips are tested one by one after aging is completed, it becomes impossible to determine at which stage of the testing process the chip failed. This would necessitate retesting, which requires re-dicing and repackaging, resulting in increased testing costs. Therefore, when a chip failure is detected, testing can be stopped immediately, and the failed chip can be analyzed to avoid situations where the failure stage cannot be determined, thus requiring retesting. Performing a readback operation during the testing of the chip under test allows test engineers to monitor test data in real time, improving the efficiency of chip testing.
[0092] This disclosure also provides a chip testing method, such as Figure 11 As shown, the method includes the following steps:
[0093] Step S10: Aging the chip to be tested;
[0094] The purpose of aging the chip under test is to simulate the impact of conditions such as temperature, humidity, and voltage that frequently occur during chip use on the chip's reliability. After aging, proceed to step S20.
[0095] Step S20: Using a chip testing device for the chip under test, apply a test signal to the chip under test, so that multiple input / output pins of the chip under test output test output signals respectively. The chip testing device is the chip testing device described in the foregoing embodiments.
[0096] After aging, the chip under test may fail or other problems. Therefore, it is necessary to use a chip testing device to apply test signals to the chip under test and test it.
[0097] In some specific implementations, the expected value of the test output signal corresponds to the write value written to the chip under test; the step of applying the test signal to the chip under test includes:
[0098] A first value is applied to the chip under test, wherein the write value written to the chip under test is the first value, and the expected value of the test output signal is the first value.
[0099] Alternatively, a zero-value write is applied to the chip under test, wherein the write value written to the chip under test is zero, and the expected value of the test output signal is zero.
[0100] Furthermore, in some specific embodiments, the chip under test is a non-volatile memory chip.
[0101] Since the test chip is a non-volatile memory chip, the test process requires writing test data first and then reading (rereading back) the test data to determine whether the two are consistent. In other words, the expected value of the read test data is the written test data. The test signal applied to the chip under test includes the signal that controls the chip under test to write test data and the written test data.
[0102] After applying the test signal, continue with step S30.
[0103] Step S30: Use the chip testing device for the chip under test to perform logical operations on the multiple test output signals output from the multiple input / output pins of the chip under test to obtain the test result of the chip under test, wherein the test result of the chip under test is output through a unified output pin.
[0104] In some embodiments, the chip testing device for the chip under test performs logical operations on multiple test output signals output from multiple input / output pins of the chip under test to obtain the test results of the chip under test, including:
[0105] Multiple logic operation modules are used to perform logic operations on multiple test output signals from multiple input / output pins of the chip under test; among them, multiple logic operation modules correspond to multiple logic operation modes, and one logic operation module corresponds to one logic operation mode.
[0106] Select the target logic operation module from multiple logic operation modules.
[0107] The logical operation result of the target logic operation module is used as the test result of the chip under test.
[0108] The chip testing device described in the foregoing embodiments performs logical operations on multiple test output signals of the chip under test to obtain the test result of the chip under test. The test result of the chip under test is output through a unified output pin, which avoids direct analysis and judgment of the multiple test output signals, thereby saving hardware resources.
[0109] Furthermore, the multiple target logic operation modes include: an AND operation mode and a NOR operation mode; the multiple logic operation modules include: an AND gate module corresponding to the AND operation mode and a NOR gate module corresponding to the NOR operation mode; the logical operation of multiple test output signals output from multiple input / output pins of the chip under test using the multiple logic operation modules includes: using an AND gate module to perform an AND operation on the multiple test output signals output from multiple input / output pins of the chip under test; and using a NOR gate module to perform a NOR operation on the multiple test output signals output from multiple input / output pins of the chip under test.
[0110] For some chips under test, such as memory chips, the test output signal during the test process can only be a first value or a zero value. The first value and the zero value indicate different values at the same bit of the data output by the memory chip during the test. Specifically, the first value can be 1, and the zero value can be 0. Therefore, when the expected value of the test output signal is the first value, the test result of the chip under test can be obtained by performing an AND operation on the multiple test output signals output from the multiple input / output pins. Similarly, when the expected value of the test output signal is the zero value, the test result of the chip under test can be obtained by performing a NOR operation on the multiple test output signals output from the multiple input / output pins.
[0111] In some specific embodiments, using the logical operation result of the target logic operation module as the test result of the chip under test includes:
[0112] If the target logic operation module is selected as an AND gate module, the logic operation result obtained by the AND gate module will be used as the test result of the chip under test.
[0113] If the target logic operation module is selected as a NOR gate module, the logic operation result obtained by the NOR gate module will be used as the test result of the chip under test.
[0114] In some specific implementations, the target logic operation module is associated with the expected value of the test output signal. If the expected value of the test output signal is the first value, then the AND gate module is the target logic operation module; if the expected value of the test output signal is the zeroth value, then the NOR gate module is the target logic operation module.
[0115] In some specific implementations, the AND operation performed using an AND gate module on multiple test output signals output from multiple input / output pins of the chip under test includes:
[0116] If all of the test output signals are the first value, then the AND gate module is used to perform an AND operation to obtain the logical operation result of the first value, indicating that the chip under test is expected to output the first value and has not failed.
[0117] If at least one of the multiple test output signals is not the first value, then an AND operation is performed using an AND gate module to obtain the logical operation result of the zeroth value, indicating that the chip under test is expected to fail when it outputs the first value.
[0118] The process of performing NOR operations on multiple test output signals from multiple input / output pins of the chip under test using a NOR gate module includes:
[0119] If all of the test output signals are zero, then the NOR gate module is used to perform NOR operation to obtain the first logical operation result, indicating that the chip under test is not expected to fail when it outputs the zeroth value.
[0120] If at least one of the multiple test output signals is not the zeroth value, then the NOR gate module is used to perform NOR operation to obtain the logical operation result of the zeroth value, indicating that the chip under test is expected to fail when it outputs the zeroth value.
[0121] After the test result is output on the output pin, continue to execute step S40.
[0122] Step S40: Based on the test results of the chip under test obtained from the unified output pin, determine whether the chip under test has failed.
[0123] Since the test results of the chip under test indicate whether the chip under test has failed, the failure of the chip under test can be determined based on the test results.
[0124] In some specific embodiments, the method further includes: if multiple chips to be tested are tested, then the test results output by the chip testing devices corresponding to the multiple chips to be tested are obtained respectively, and a test result indicates whether the corresponding chip to be tested has failed; wherein, the test result of a chip to be tested is output through a unified output pin of the corresponding chip testing device.
[0125] Since the output pin of each chip under test is connected to the signal port of the aging board when testing multiple chips under test, the failed chip testing device can be determined based on the signal port corresponding to the test result indicating the failure of the chip under test received on the aging board, thereby identifying the failed chip under test in the chip testing device.
[0126] The chip testing method disclosed herein ages the chip under test, tests it using a chip testing device, and determines whether the chip under test is faulty based on the test results output by the chip testing device. Compared to directly reading the test output signal of the chip under test, reading the test results output by the output pins allows for the simultaneous determination of the validity of a larger number of chips under test, thereby improving chip testing efficiency. Furthermore, when testing multiple chips under test, the faulty chip can be identified from among the multiple chips by using the signal port corresponding to the test result indicating chip failure, further improving chip testing efficiency.
[0127] Figure 12 This is a timing diagram of each signal in the chip testing method provided in this disclosure, such as... Figure 12 As shown, when testing the chip under test, on the falling edge of the clock signal CLK, the chip enable signal Ceb is set to low and the read enable signal RDEN is set to high. Then, the data stored in the chip under test is read through the address signal ADDRPAD[15:0]. After the next falling edge of the clock signal CLK, the operation mode signal MODE is set to high or low to set the logic operation mode of the chip test device. Specifically, the state of the MODE pin can be set to the corresponding value at the beginning according to the test result data read. Then, the COMP pin is set to high, indicating that the test result should be output from the output pin Q. After COMP is set to high, wait for the preset time tpq, and then the test result can be read from the output pin Q.
[0128] The inventors also conducted simulations of the chip testing device provided in this disclosure, and the simulation results are as follows: Figure 13 , Figure 14 As shown.
[0129] like Figure 13As shown, when the operation mode signal MODE is 0, the chip testing device is in NOR operation mode, and the test output signals output by input / output pins IO2:71 (i.e., IO2, IO3, ..., IO71) are always 0, while the test output signals output by input / output pins IO0 and IO1 change over time. When both input / output pins IO0 and IO1 output test signals are 0, the test result output by output pin Q is 1, indicating that the chip under test is valid; when either input / output pins IO0 or IO1 output test signals are not 0, the test result output by output pin Q is 0, indicating that the chip under test is faulty.
[0130] like Figure 14 As shown, when the operation mode signal MODE is 1, the chip testing device is in AND operation mode. Except for input / output pins IO31 and IO50, the test output signal is always 1, while the test output signals from input / output pins IO31 and IO50 change over time. When both input / output pins IO31 and IO50 output test signals are 1, the test result output by output pin Q is 1, indicating that the chip under test is valid. When either input / output pin IO31 or IO50 output test signal is not 1, the test result output by output pin Q is 0, indicating that the chip under test is faulty.
[0131] The foregoing describes multiple embodiments of the present invention. The optional methods described in each embodiment can be combined and cross-referenced without conflict, thereby extending to a variety of possible embodiments. These can all be considered as embodiments disclosed or made public by the present invention.
[0132] While the above disclosure is provided, it is not limited thereto. Any person skilled in the art may make various alterations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure shall be determined by the scope defined in the claims.
Claims
1. A chip testing device, characterized in that, include: The chip under test includes multiple input / output pins, which output test output signals during the testing process of the chip under test; A logic operation circuit is used to perform logic operations on multiple test output signals output from the multiple input / output pins to obtain the test result of the chip under test, and to output the test result through a unified output pin.
2. The chip testing apparatus as described in claim 1, characterized in that, The logic operation circuit has multiple logic operation modes, and each logic operation mode corresponds to a desired value of the test output signal. The logic operation circuit includes: Multiple logic operation modules, wherein each logic operation module corresponds to a logic operation mode, and is used to perform logic operations of the corresponding logic operation mode by taking multiple test output signals output from the multiple input and output pins as inputs; The mode pin is used to set the target logic operation module of the logic operation circuit. The output selection module is used to select the logic operation result of the target logic operation module as the test result of the chip under test based on the setting of the mode pin, and to output the test result of the chip under test through the unified output pin.
3. The chip testing apparatus as described in claim 2, characterized in that, The logic operation circuit also includes: A logic operation selection module is used to select, based on the settings of the mode pins, a target logic operation module to enable from the plurality of logic transport modules, so that the target logic operation module performs corresponding logic operations on the plurality of test output signals output from the plurality of input / output pins; and to disable non-target logic operation modules among the plurality of logic transport modules.
4. The chip testing apparatus as described in claim 2 or 3, characterized in that, The mode pin, used to set the target logic operation module of the logic operation circuit, includes: Based on the expected value of the test output signal, the target logic operation module is configured.
5. The chip testing apparatus as described in claim 4, characterized in that, The various target logic operation modes include: AND operation mode, and OR NOT operation mode; The plurality of logical operation modules include: The AND gate module, corresponding to the AND operation mode, is used to perform an AND operation with multiple test output signals output from the multiple input / output pins as inputs; The NOR gate module, corresponding to the NOR operation mode, is used to perform NOR operations with multiple test output signals output from the multiple input / output pins as inputs.
6. The chip testing apparatus as described in claim 5, characterized in that, The mode pin is used to set the target logic operation module based on the expected value of the test output signal, including: If the expected value of the test output signal is the first value, then the AND gate module is set as the target logic operation module; If the expected value of the test output signal is zero, then the NOR gate module is set as the target logic operation module.
7. The chip testing apparatus as described in claim 6, characterized in that, The AND gate module is used to perform AND operations on multiple test output signals from the multiple input / output pins as inputs, including: If all of the multiple test output signals are the first value, perform an AND operation to obtain the logical operation result of the first value, indicating that the chip under test is expected to output the first value and has not failed; if at least one of the multiple test output signals is not the first value, perform an AND operation to obtain the logical operation result of the zeroth value, indicating that the chip under test is expected to output the first value and has failed. The NOR gate module is used to perform NOR operations by taking multiple test output signals from the multiple input / output pins as inputs, including: If all of the multiple test output signals are zero values, perform a NOR operation to obtain the first logical operation result, indicating that the chip under test is expected to output a zero value and has not failed; if at least one of the multiple test output signals is not a zero value, perform a NOR operation to obtain the zero value logical operation result, indicating that the chip under test is expected to output a zero value and has failed.
8. The chip testing apparatus as described in claim 6, characterized in that, The expected value of the test output signal corresponds to the write value written to the chip under test; wherein, if the write value written to the chip under test is a first value, then the expected value of the test output signal is a first value, and if the write value written to the chip under test is a zero value, then the expected value of the test output signal is a zero value.
9. The chip testing apparatus as described in claim 1, characterized in that, The chip testing device also includes: The comparison control pin is used to control whether the logic operation circuit is enabled.
10. The chip testing apparatus as described in claim 1, characterized in that, The chip under test is a non-volatile memory chip.
11. A chip testing system, characterized in that, include: An aging apparatus for aging chips to be tested, the aging apparatus including an aging board; The aging board is connected to at least one chip testing device, and the chip testing device is the chip testing device as described in any one of claims 1-10. The aging board is used to read the test results of the chip under test output by the chip testing device, and to determine whether the chip under test has failed based on the test results.
12. The chip testing system as described in claim 11, characterized in that, The aging board is used to read the test results of the chip under test output by the chip testing device, and to determine whether the chip under test tested by the chip testing device has failed based on the test results, including: If the test result of the chip under test output by the chip testing device is the first value, then the chip under test is determined to be valid. If the test result of the chip under test output by the chip testing device is zero, then the chip under test is determined to be faulty.
13. The chip testing system as described in claim 11, characterized in that, The aging board includes multiple test result interfaces. Each test result interface is connected to a unified output pin of a chip testing device to obtain the test results output through the unified output pin.
14. A chip testing method, characterized in that, The method includes: Aging the chip to be tested; A chip testing device is used to apply a test signal to the chip under test, so that multiple input / output pins of the chip under test output test output signals respectively; wherein, the chip testing device is the chip testing device as described in any one of claims 1-10; Furthermore, the chip testing device for the chip under test performs logical operations on multiple test output signals output from multiple input / output pins of the chip under test to obtain the test result of the chip under test, wherein the test result of the chip under test is output through a unified output pin of the chip testing device; Based on the test results of the chip under test obtained from the unified output pin, it is determined whether the chip under test has failed.
15. The chip testing method as described in claim 14, characterized in that, The chip testing device for the chip under test performs logical operations on multiple test output signals output from multiple input / output pins of the chip under test to obtain the test results of the chip under test, including: Multiple logic operation modules are used to perform logic operations on multiple test output signals output from multiple input / output pins of the chip under test; wherein, multiple logic operation modules correspond to multiple logic operation modes, and one logic operation module corresponds to one logic operation mode; Select the target logic operation module from multiple logic operation modules; The logical operation result of the target logic operation module is used as the test result of the chip under test.
16. The chip testing method as described in claim 15, characterized in that, The multiple target logic operation modes include: AND operation mode, and OR NOT operation mode; the multiple logic operation modules include: AND gate module corresponding to AND operation mode, and OR NOT gate module corresponding to OR operation mode; The step of performing logical operations on multiple test output signals from multiple input / output pins of the chip under test using multiple logic operation modules includes: Using an AND gate module, perform an AND operation on the multiple test output signals output from multiple input / output pins of the chip under test; The NOR gate module is used to perform NOR operations on multiple test output signals from multiple input / output pins of the chip under test.
17. The chip testing method as described in claim 16, characterized in that, The step of using the logic operation result of the target logic operation module as the test result of the chip under test includes: If the target logic operation module is selected as an AND gate module, the logic operation result obtained by the AND gate module shall be used as the test result of the chip under test; If the target logic operation module is selected as a NOR gate module, the logic operation result obtained by the NOR gate module will be used as the test result of the chip under test.
18. The chip testing method as described in claim 17, characterized in that, The target logic operation module is associated with the expected value of the test output signal. If the expected value of the test output signal is the first value, then the AND gate module is the target logic operation module. If the expected value of the test output signal is the zeroth value, then the NOR gate module is the target logic operation module.
19. The chip testing method as described in claim 18, characterized in that, The method of using an AND gate module to perform an AND operation on multiple test output signals output from multiple input / output pins of the chip under test includes: If all of the test output signals are the first value, then the AND gate module is used to perform an AND operation to obtain the logical operation result of the first value, indicating that the chip under test is expected to output the first value and has not failed. If at least one of the multiple test output signals is not the first value, then an AND operation is performed using an AND gate module to obtain the logical operation result of the zeroth value, indicating that the chip under test is expected to fail when it outputs the first value. The process of performing NOR operations on multiple test output signals from multiple input / output pins of the chip under test using a NOR gate module includes: If all of the test output signals are zero values, then the NOR gate module is used to perform NOR operation to obtain the first logical operation result, indicating that the chip under test is expected to not fail when it outputs the zero value; If at least one of the multiple test output signals is not the zeroth value, then the NOR gate module is used to perform NOR operation to obtain the logical operation result of the zeroth value, indicating that the chip under test is expected to fail when it outputs the zeroth value.
20. The chip testing method as described in claim 15, characterized in that, The expected value of the test output signal corresponds to the value written to the chip under test; Applying a test signal to the chip under test includes: A first value is applied to the chip under test, wherein the write value written to the chip under test is the first value, and the expected value of the test output signal is the first value. Alternatively, a zero-value write is applied to the chip under test, wherein the write value written to the chip under test is zero, and the expected value of the test output signal is zero.
21. The chip testing method as described in claim 15, characterized in that, The method further includes: If multiple chips are tested, the test results output by the chip testing device corresponding to each chip are obtained. Each test result indicates whether the corresponding chip has failed. The test result of a chip is output through the unified output pin of the corresponding chip testing device.