A chip testing system, method and equipment

Abstract

This disclosure provides a chip testing system, method, and apparatus. The system includes: an instruction sequence module for generating corresponding test instruction sequence identifiers based on a test instruction set; a test vector generation module for configuring a mode based on rate mode configuration information to determine the target number of channels; and generating a test vector for each channel based on the test instruction sequence identifier; and a test signal output module for performing signal conversion processing on the test vectors to generate a target test signal to complete the chip testing.

Description

Technical Field

[0001] This disclosure relates to the field of chip testing technology, and in particular to a chip testing system, method and equipment. Background Technology

[0002] As integrated circuit process nodes continue to shrink, chip integration density increases significantly and physical size decreases, not only does the difficulty of testing integrated circuit chips increase significantly, but it also leads to a continuous rise in chip research and development and testing costs. Among them, memory chips, as a core component of integrated circuits, have made testing efficiency and compatibility a key research direction in the field of chip testing.

[0003] Currently, the main testing methods for memory chips in the industry include: board-level testing, built-in self-test (BIST) testing, and automated test equipment (ATE) testing. While board-level testing is lower in cost and closer to real-world applications, its test coverage and efficiency are limited, making it difficult to meet the demands of large-scale mass production. BIST-based testing achieves rapid self-testing through built-in chip test circuits, resulting in high testing efficiency, but it increases chip design complexity and area, and its fixed testing algorithms lack flexibility. ATE-based testing offers high accuracy and coverage, adapting to the needs of large-scale mass production, but traditional dedicated testing equipment struggles to flexibly adapt to the testing requirements of different types and speeds of memory chips. Summary of the Invention

[0004] This disclosure provides a chip testing system, method, and device to address the problem that existing technical solutions are difficult to flexibly adapt to the testing needs of different types and speeds of memory chips, resulting in insufficient universality and adaptability of the testing solutions and an inability to further improve the overall efficiency of memory chip testing.

[0005] In view of the above problems, firstly, the present disclosure provides a chip testing system, including: The instruction sequence module is used to generate corresponding test instruction sequence identifiers based on the test instruction set; The test vector generation module is used to configure the mode according to the rate mode configuration information to determine the target number of channels; and to generate a test vector for each channel according to the test instruction sequence identifier. The test signal output module is used to perform signal conversion processing on the test vector to generate a target test signal in order to complete the test of the chip.

[0006] In conjunction with the first aspect, in one possible implementation, the rate mode configuration information carries channel number information for generating test vectors; the test vector generation module includes a mode generator unit and an address data shaping unit; the mode generator unit includes multiple mode generators; The test vector generation module is used to group multiple pattern generators according to the channel number information, so that each group corresponds to one channel, resulting in a target number of channels; each channel is used to perform corresponding operations according to the test instruction sequence identifier to generate the corresponding target intermediate quantity. The address data shaping unit is used to generate the target number of test vectors based on the target intermediate quantity.

[0007] In conjunction with the first aspect, in one possible implementation, each pattern generator within the channel is configured to perform the same operation to generate candidate intermediate quantities based on the test instruction sequence identifier. The test vector generation module is used to take the candidate intermediate quantity generated by any pattern generator in the channel as the target intermediate quantity output by the channel.

[0008] In conjunction with the first aspect, in one possible implementation, the pattern generator includes: an initialization module, an address selection module, and an address calculation module; The initialization module is used to initialize and configure multiple address initialization parameters to obtain initialization parameter values; The address selection module is used to select the corresponding initialization parameter value according to the first selection instruction carried by the test instruction sequence identifier, and determine the parameter value of the address selection parameter. The address calculation module is used to perform a first operation on the parameter value of the address selection parameter and the parameter value of the address generation parameter according to the calculation instruction carried by the test instruction sequence identifier, and to determine the target parameter value of the address generation parameter; the first operation includes at least one of the following: arithmetic operation and logical operation; The pattern generator is used to select the corresponding target parameter value according to the second selection instruction carried by the test instruction sequence identifier, and to determine the candidate intermediate quantity.

[0009] In conjunction with the first aspect, in one possible implementation, it further includes: A high-speed communication interface module is used to receive test parameter data, which includes a test instruction set, rate mode configuration information, and sequence parameter packet. The sequence parameter packet includes: start test instruction sequence identifier, loop count, and jump condition. The instruction sequence module is used to use the starting test instruction sequence identifier as the test instruction sequence identifier for the first clock cycle after the instruction sequence module is started. Following the clock cycle sequence, the microinstructions corresponding to the test instruction set are read sequentially according to the test instruction sequence identifier of the current clock cycle; the jump condition code or loop flag carried by the microinstruction is matched with the corresponding jump condition or loop count in the sequence parameter package to generate the test instruction sequence identifier for the next clock cycle, until the chip test is completed.

[0010] In conjunction with the first aspect, in one possible implementation, the test signal output module includes: a routing selection unit and a drive output unit; the routing selection unit includes a first number of first pins; the drive output unit includes a first number of second pins; the second pins are connected to the chip; The routing selection unit is used to select the test vector, and each first pin outputs the target number of routing selection test signals in parallel; The drive output unit is used to convert the routing selection test signal output from each first pin to generate a target test signal, and output it to the chip through the corresponding second pin.

[0011] In conjunction with the first aspect, in one possible implementation, it further includes: A high-speed communication interface module is used to receive test parameter data, which includes a channel index mapping table; The test vector includes: address information and data information for accessing the chip; the routing test signal includes: address signal and data signal; The routing unit is used to select a target channel from a target number of channels according to the channel index mapping table, and use the address information generated by the target channel as an address signal; wherein, the number of target channels is the target number, and each first pin outputs the target number of address signals in parallel; The data information generated by the target channel is used as a data signal; wherein, each first pin outputs the target number of data signals in parallel.

[0012] In conjunction with the first aspect, in one possible implementation, the drive output unit is used to encode the routing selection test signal for each routing selection signal output from the first pin to generate an encoded test signal. The encoded test signal is converted from parallel to serial to generate the target test signal, and then output to the chip through the corresponding second pin.

[0013] Secondly, a chip testing method is provided, including: Generate the corresponding test instruction sequence identifier based on the test instruction set; Based on the rate mode configuration information, the mode configuration is performed to determine the target number of channels; and a test vector is generated for each channel according to the test instruction sequence identifier. The test vector is processed by signal conversion to generate a target test signal, thereby completing the test of the chip.

[0014] Thirdly, a chip testing apparatus is provided, comprising: a chip testing system as described in the first aspect or any possible embodiment in conjunction with the first aspect.

[0015] The beneficial effects of the embodiments disclosed herein include: This disclosure provides a chip testing system, method, and apparatus, including an instruction sequence module for generating corresponding test instruction sequence identifiers based on a test instruction set; a test vector generation module for configuring modes according to rate mode configuration information to determine the target number of channels; and generating test vectors for each channel based on the test instruction sequence identifiers; and a test signal output module for performing signal conversion processing on the test vectors to generate target test signals to complete the chip testing. The chip testing system provided in this disclosure allows the test vector generation module to flexibly configure parallel modes such as 8WAY, 4WAY, 2WAY, and 1WAY according to rate mode configuration information, generating test signals at different rates. Each functional module can flexibly adapt to new test instructions and protocols, effectively enhancing multi-scenario adaptability and solution versatility, solving the problem of existing technologies being unable to be compatible with testing multiple types and rates of memory chips. The generation of corresponding test instruction sequence identifiers based on the test instruction set, as well as the parallel generation and encoding of test vectors and signal conversion processing such as parallel-to-serial conversion, effectively avoids micro-instruction execution deviations and high-speed transmission interference and distortion problems, ensuring test accuracy and signal stability, and improving the reliability of test results. Attached Figure Description

[0016] Figure 1 This is one of the structural schematic diagrams of the chip testing system provided in the embodiments of this disclosure; Figure 2 This is a second schematic diagram of the structure of the chip testing system provided in the embodiments of this disclosure; Figure 3 This is one of the structural schematic diagrams of the test vector generation module provided in the embodiments of this disclosure; Figure 4 This is a second schematic diagram of the structure of the test vector generation module provided in the embodiments of this disclosure; Figure 5 This is a schematic diagram of the chip testing process provided in an embodiment of the present disclosure; Figure 6 A flowchart of a chip testing method provided in an embodiment of this disclosure. Detailed Implementation

[0017] This disclosure provides a chip testing system, method, and apparatus. Preferred embodiments of this disclosure are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustrative and explanatory purposes only and are not intended to limit the scope of this disclosure. Furthermore, the embodiments and features described herein can be combined with each other unless otherwise specified.

[0018] This disclosure provides a chip testing system, such as... Figure 1 As shown, it includes: The instruction sequence module 101 is used to generate corresponding test instruction sequence identifiers based on the test instruction set; The test vector generation module 102 is used to configure the mode according to the rate mode configuration information to determine the target number of channels; and to generate a test vector for each channel according to the test instruction sequence identifier. The test signal output module 103 is used to perform signal conversion processing on the test vector to generate the target test signal in order to complete the test of the chip.

[0019] In this embodiment of the disclosure, as integrated circuit process nodes continue to shrink, chip integration density increases significantly and physical size continues to decrease. This not only significantly increases the testing difficulty of integrated circuit chips but also leads to a year-on-year increase in chip R&D and testing costs. Among them, memory chips, as a core component of integrated circuits, have become a core research topic in the current chip testing field due to their testing efficiency and multi-scenario compatibility. Currently, the main testing methods for memory chips in the industry include: board-level testing, built-in self-test (BIST), and automated test equipment (ATE). Although board-level testing has the advantages of low cost and close relevance to actual application scenarios, its test coverage and efficiency are relatively low, making it difficult to meet the needs of large-scale mass production. BIST testing achieves rapid self-testing through the chip's built-in test circuit, resulting in high testing efficiency, but it increases the complexity of chip design and layout area, and the test algorithm is fixed, lacking flexibility. ATE testing has excellent accuracy and coverage, adapting to large-scale mass production scenarios, but the cost of dedicated equipment is high, and it is difficult to flexibly accommodate the testing needs of different types and speeds of memory chips. To balance efficiency, cost, and flexibility in memory chip testing, test solutions based on Field-Programmable Gate Arrays (FPGAs) have gradually become the mainstream development direction in the semiconductor testing field due to their unique advantages. An FPGA can refer to a user-configurable, ultra-large-scale programmable logic device. Its core consists of programmable logic resources, programmable interconnect resources, and programmable input / output resources, possessing extremely high energy efficiency and parallel processing capabilities. Compared to Application-Specific Integrated Circuits (ASICs), FPGAs do not require dedicated mold design, can be repeatedly erased and rewritten infinitely, and can be reconfigured online, quickly adapting to different testing needs. They balance customized performance with flexible scalability, effectively reducing R&D costs and time. Furthermore, their parallel architecture supports simultaneous processing of multiple signals, adapting to high-speed testing scenarios, and their hardware resources can be configured on demand, flexibly integrating various functional modules required for testing. Among these, test vector generation acceleration technology based on Algorithmic Logical Pattern Generators (ALPGs), leveraging the parallel processing advantages of FPGAs to achieve high-speed generation of test vectors, is the core key to improving the overall efficiency of FPGA test solutions. Existing technologies have undertaken numerous studies and improvements related to ALPG, such as resolving multi-channel ALPG synchronization issues, optimizing the test vector compilation acceleration process (accelerating the process by compiling the test program on a host computer and then loading it onto the FPGA), simplifying the programming logic of the Pattern program in interleaved multi-channel mode, and reducing programming limitations. However, none of these solutions have overcome the bottleneck of flexible adaptation to multiple data rates and types of memory chips, resulting in insufficient versatility and adaptability of the test solutions, and failing to further improve the overall performance of memory chip testing.

[0020] In this embodiment of the disclosure, such as Figure 2 As shown, the chip testing system may include an FPGA and a host computer 201. The FPGA internally includes multiple functional modules, such as an instruction sequence module 101, a test vector generation module 102, a test signal output module 103, and a high-speed communication interface module 202. The high-speed communication interface module 202 serves as the data transmission bridge between the FPGA and the host computer 201. Its core function is to accurately receive test parameter data sent by the host computer 201, ensuring high-speed and stable data transmission, and providing basic data support for subsequent testing processes. The high-speed communication interface module 202 can use a high-speed transceiver (such as SerDes), building a transmission link based on the FPGA's high-speed I / O resources. This effectively avoids data transmission delays and packet loss, ensuring that test parameters are accurately sent to the parameter storage units (such as registers) of each functional module within the FPGA, laying the foundation for the synchronous execution of subsequent processes. The test parameter data includes test instruction sets and rate mode configuration information. The test instruction set, including the functional test logic, read and write operation instructions, and fault detection standards of the memory chip under test, is the core basis for test execution; the rate mode configuration information is used to define key parameters such as the number of parallel channels and output rate of the test system to adapt to the test requirements of different types and different rates of memory chips.

[0021] The instruction sequence module 101 can be an internal sequence module of the FPGA. Its core function is to parse and transform the test instruction set, generating a unique corresponding test instruction sequence identifier (i.e., instruction sequence number (PC, ProgramCounter)), providing an index for the accurate generation of test vectors. The instruction sequence module 101 first reads the cached test instruction set, sorts it according to microinstruction priority and execution logic, forming an ordered microinstruction execution flow; then, it assigns a unique sequence identifier to each microinstruction, obtaining the test instruction sequence identifier. This test instruction sequence identifier not only locates the microinstruction itself but also associates it with the corresponding operation logic and parameter configuration. Through this transformation, the abstract test instruction set issued by the host computer 201 is transformed into hardware-level signals that can be recognized and executed by various functional modules within the FPGA, achieving standardized scheduling of the instruction flow and ensuring the orderly progress of the test process. Furthermore, the instruction sequence module 101 supports flexible switching between different microinstruction sequences, adapting to diverse test scenario requirements based on the reconfigurable characteristics of the FPGA.

[0022] Furthermore, the test vector generation module 102 is used to generate test vectors. The test vector generation module 102 can be an ALPG module within the FPGA. Based on the rate mode configuration information, the test vector generation module 102 completes hardware adaptation and, combined with the test instruction sequence identifier, generates accurate test vectors, which is a key step in achieving multi-way parallelism and multi-rate adaptation. Internally, it integrates a pattern generator unit 1021 and an address data shaping unit 1022. The pattern generator unit includes multiple pattern generators 10211 (PG), which achieve flexible switching between different parallel channels through group configuration. The test vector generation module 102 reads the rate mode configuration information and manages the multiple pattern generators 10211 in groups: pattern generators 10211 within the same group perform the same operations, while those in different groups perform different operations, thereby determining the target number of parallel channels (e.g., 8-way, 4-way, 2-way, 1-way modes), achieving precise matching between the number of channels and the chip test rate. The number of channels is directly proportional to the test rate. The more channels there are, the faster the test rate; conversely, the fewer channels there are, the slower the test rate. Then, the address data shaping unit 1022 uses the test instruction sequence identifier as an index, combines the test parameter data cached in the register with the target intermediate values ​​output by each channel mode generator 10211, to generate the address and data information for accessing the chip (such as SDRAM), thus obtaining the test vector. Furthermore, the test vectors for each channel are output synchronously and in parallel; the FPGA-based parallel architecture significantly improves vector generation efficiency.

[0023] The test signal output module 103 is the conversion and output terminal for test signals. It may include a routing selection unit 1031 (PDS module) and a driver output unit 1032 (DRV module) within the FPGA. Its core function is to optimize and convert the parallel output test vectors to generate target test signals that meet the interface protocol and rate requirements of the chip under test, and finally complete the test execution. The routing selection unit 1031 can be a programmable data selector (PDS) within the FPGA. The driver output unit 1032 can be a driver module (DRV) within the FPGA. For example, the routing unit 1031 filters and allocates test vectors to ensure accurate transmission of test vectors in each channel; the drive output unit 1032 performs FC encoding on the test vectors to generate different code patterns that adapt to the interface protocol of the chip under test, optimizes signal transmission quality, and avoids interference and distortion in high-speed transmission; the drive output unit 1032 converts the multi-channel parallel test vectors into high-speed serial signals, and outputs test signals at corresponding rates (such as 2.4Gbps, 1.2Gbps, etc.) in combination with the rate mode configuration, and transmits them to the chip under test through the FPGA's IO pins to complete functional and performance testing.

[0024] In this embodiment, based on an FPGA-based parallel processing architecture, the test vector generation module 102 generates test vectors in parallel through a multi-mode generator 10211. By configuring the rate mode, it can flexibly switch between parallel channel modes such as 8WAY, 4WAY, 2WAY, and 1WAY, generating test signals at different rates. Combined with the reconfigurable characteristics of FPGA hardware, each functional unit can flexibly adapt to new test instructions and protocols, effectively enhancing multi-scenario adaptability and solution versatility, solving the pain point of existing technologies' inability to be compatible with testing multiple types and rates of memory chips. Compared to traditional ATE equipment, it does not require special mold making and can be repeated an unlimited number of times. The rewritable configuration avoids the high R&D costs and long cycles of customized designs compared to ASICs, achieving a balance between cost and performance while ensuring test performance. The precise indexing design of the test instruction sequence identifier, combined with parallel generation and encoding of test vectors, and signal optimization processing such as parallel-to-serial conversion, effectively avoids micro-instruction execution deviations and high-speed transmission interference and distortion problems, ensuring test accuracy and signal stability, and improving the reliability of test results. The entire process can be automated by sending parameters to the host computer. The modular design and reconfigurable characteristics also reduce the difficulty of test logic adjustment and scheme debugging and optimization, simplifying the test process and improving operational flexibility.

[0025] In another embodiment of this disclosure, the rate mode configuration information carries channel number information for generating test vectors; the test vector generation module 102 includes a mode generator unit 1021 and an address data shaping unit 1022; the mode generator unit 1021 includes a plurality of mode generators 10211. The test vector generation module 102 is used to group multiple pattern generators 10211 according to the channel number information, so that each group corresponds to one channel, and obtains the target number of channels; each channel is used to perform corresponding operations according to the test instruction sequence identifier to generate the corresponding target intermediate quantity; Address data shaping unit 1022 is used to generate a target number of test vectors based on the target intermediate quantity.

[0026] In this embodiment, the test vector generation module 102 first groups multiple pattern generators 10211 according to the channel number information, so that each group corresponds to a test channel; the pattern generators 10211 in each channel group perform calculations to generate target intermediate quantities in combination with the test instruction sequence identifier; finally, the address data shaping unit 1022 converts the target intermediate quantities into test vectors that meet the test requirements, thereby realizing the accurate generation of multi-channel, configurable test vectors, laying the foundation for subsequent signal conversion and chip testing compatible with multiple rates.

[0027] The test vector generation module 102 is used to manage the grouping of multiple internal pattern generators 10211 (PG units) according to the channel number parameter in the rate mode configuration information, and to establish the correspondence between groups and channels. The channel number information carried in the rate mode configuration information determines the target number of channels (e.g., 8 channels, 4 channels, 2 channels, 1 channel), and the test vector generation module 102 formulates a grouping strategy based on this channel number information. For example, when the number of channels is 8, all pattern generators 10211 are in an independent group, corresponding to 8 channels; when the number of channels is 4, every 2 pattern generators 10211 are grouped together, for a total of 4 groups corresponding to 4 channels; when the number of channels is 2, every 4 pattern generators 10211 are grouped together, for a total of 2 groups corresponding to 2 channels; when the number of channels is 1, all pattern generators 10211 are grouped together, corresponding to 1 channel. The pattern generators 10211 of each channel execute collaboratively, and in conjunction with the test instruction sequence identifier, generate target intermediate quantities for subsequent shaping processing. Each channel pattern generator 10211 receives the test instruction sequence identifier (PC) issued by the instruction sequence module 101. Using this test instruction sequence identifier as an index, it matches the cached test instruction logic, operation rules, and parameter configuration, and synchronously executes the corresponding operation. Due to differences in the operation logic between groups, the target intermediate quantities generated by different channels are independent and can correspond to different test scenario requirements. Within a group, the pattern generator 10211 performs the same operation, ensuring the consistency and stability of the target intermediate quantities for the same channel. For example, as shown... Figure 3As shown, the pattern generator 10211 consists of PG1 to PG8, a total of 8 PG units. In the 8-way mode, there are 8 channels, with PG1-PG8 performing different operations, effectively outputting the target intermediate value in parallel across 8ways. In the 4-way mode, there are 4 channels, with the 8-way PGs executing in parallel; PG1-PG2 perform the same calculations, PG3-PG4 perform the same calculations, PG5-PG6 perform the same calculations, and PG7-PG8 perform the same calculations, effectively outputting the target intermediate value in parallel across 4ways. In the 2-way mode, there are 2 channels, with the 8-way PGs executing in parallel; PG1-PG4 and PG5-PG8 perform the same calculations, outputting the target intermediate value in parallel across 2ways. In the 1-way mode, there is 1 channel, with the 8-way PGs executing in parallel; PG1-PG8 perform the same calculations, effectively outputting the target intermediate value in 1way. This provides hardware architecture support for multi-channel parallel generation of test vectors, adapting to different testing rate requirements. The address data shaping unit 1022 processes the target intermediate quantities output by each channel mode generator 10211 to generate test vectors. The test vectors may include address information and data information for accessing the chip. For example, ... Figure 4 As shown, the address data shaping unit 1022 includes an Address channel 401 and a Data channel 402. The Address channel 401 generates address information including row (X) and column (Y) information based on a target intermediate value. The address information is used to characterize the row and column addresses of the accessed chip. The Data channel 402 generates data information based on the target intermediate value. The data information is used to characterize data that should be written to the chip or expected to be read from the chip.

[0028] The rate mode configuration information includes: N-WAY mode, where N represents the number of channels. The N-WAY mode specifies the number of test channels, with N representing the number of channels. This value can be flexibly set according to testing requirements (e.g., N=8, 4, 2, 1, corresponding to 8-WAY, 4-WAY, 2-WAY, and 1-WAY modes), directly determining the number of channels in the grouping logic of subsequent mode generators and the test vectors. This configuration information is issued by the host computer and transmitted to the FPGA's internal parameter storage unit (register) cache via the high-speed communication interface module, providing a clear configuration basis for the test vector generation module and serving as a fundamental prerequisite for multi-scenario adaptation. The value of N is strongly correlated with the subsequent output rate; the more channels N, the stronger the parallel processing capability and the higher the test rate, allowing for precise matching of the testing requirements of memory chips with different rate levels.

[0029] Based on a dynamic grouping pattern generator using channel number information, test vectors for each channel are generated independently, accurately adapting to the testing requirements of memory chips with different speeds and types, thus improving the versatility and adaptability of the solution. Furthermore, based on the reconfigurable characteristics of FPGAs, the shaping rules and operational logic can be flexibly adjusted, adapting to new testing requirements without modifying the hardware structure, significantly reducing R&D and maintenance costs compared to traditional dedicated testing equipment.

[0030] In another embodiment of this disclosure, each pattern generator in the channel is used to perform the same operation to generate candidate intermediate quantities according to the test instruction sequence identifier; The test vector generation module is used to take the candidate intermediate quantity generated by any pattern generator in the channel as the target intermediate quantity output by that channel.

[0031] In this embodiment, for each channel, each pattern generator within the channel performs the same operation based on the test instruction sequence identifier, synchronously generating candidate intermediate quantities. Then, an output strategy of "taking any candidate intermediate quantity" is adopted to determine the final target intermediate quantity output by the channel. Each test channel corresponds to a set of pattern generators (PG units). All pattern generators within this group synchronously receive the same test instruction sequence identifier (PC) issued by the instruction sequence module, and use this test instruction sequence identifier as a unique index to call the cached test instruction logic, operation rules, and supporting parameters, executing a completely consistent operation process. During the operation, each pattern generator within the group works in parallel and synchronously. Based on the parallel characteristics of FPGA hardware, the synchronization of the operation process and the consistency of the results are ensured. The generated candidate intermediate quantities are all basic data containing address prototypes, data prototypes, and operation identifiers, and the candidate intermediate quantities of each pattern generator within the group are completely identical, providing redundant support for subsequent output strategies. Furthermore, the operations between channels do not interfere with each other, ensuring the independence of multi-channel parallel processing. Based on the consistency of the operation results of each pattern generator within the channel, the output logic is simplified. Since all pattern generators within a channel perform the same operations, the generated candidate intermediate quantities are completely consistent. Therefore, there is no need to merge or verify all candidate intermediate quantities. The test vector generation module can directly select any candidate intermediate quantity generated by any pattern generator within the group as the target intermediate quantity for the final output of the channel, and transmit it to the subsequent address data shaping unit. For example, the test vector generation module can be used to select the corresponding candidate intermediate quantity as the target intermediate quantity based on the candidate intermediate quantity selection instruction included in the test instruction sequence identifier. This design avoids the cumbersome process of comparing and integrating multiple candidate intermediate quantities, reducing hardware resource consumption and computational latency. Furthermore, due to the consistency of candidate intermediate quantities within the group, there is no need to worry about output data deviation. It also retains the fault tolerance of redundant operations within the group; even if a single pattern generator experiences a temporary failure, candidate intermediate quantities from other pattern generators can still be selected, ensuring output stability. The pattern generators within the channel execute the same operations synchronously. Based on the redundant operation design, the consistency and reliability of candidate intermediate quantities are ensured, effectively avoiding data errors caused by the failure of a single hardware unit and improving the fault tolerance of the testing process.

[0032] In another embodiment of this disclosure, the pattern generator includes: an initialization module, an address selection module, and an address calculation module; The initialization module is used to initialize and configure multiple address initialization parameters and obtain the initialization parameter values; The address selection module is used to select the corresponding initialization parameter value according to the first selection instruction carried by the test instruction sequence identifier, and to determine the parameter value of the address selection parameter. An address operation module, configured to perform a corresponding first operation on the parameter value of an address selection parameter and the parameter value of an address generation parameter according to an operation instruction carried by a test instruction sequence identifier, and determine a target parameter value of the address generation parameter; the first operation includes at least one of the following: arithmetic operation, logical operation; A pattern generator, configured to select a corresponding target parameter value according to a second selection instruction carried by a test instruction sequence identifier, and determine a candidate intermediate quantity.

[0033] In an embodiment of the present disclosure, a pattern generator architecture is proposed, which can generate complex address sequences required for memory testing. The pattern generator includes an initialization module, an address selection module, and an address operation module, and realizes a highly flexible address generation capability through a programmable test instruction sequence. The entire architecture supports symmetric generation of an X / Y two-dimensional address space, and can meet the stringent requirements for address diversity, algorithm complexity, and timing accuracy in modern memory testing.

[0034] The initialization module is the data source layer of the pattern generator, and is responsible for providing basic parameter values for subsequent address generation. The initialization module initializes and configures multiple groups of address initial parameters to generate initialization parameter values. For the X address, the initialization module configures group D1 (D1A, D1B, D1C, D1D, D1E, D1F, D1G), group D2 (D2A, D2B, D2C, D2D), and the initial value of XH; for the Y address, the initialization module configures group Y1 (Y1A, Y1B, Y1C, Y1D, Y1E, Y1F, Y1G), group Y2 (Y2A, Y2B, Y2C, Y2D), and the initial value of YH. XH / YH is a reference address register, which stores the starting value or reference value of address generation. When the test instruction sequence identifier carries a designation of X<XH or Y<YH, the address directly outputs this initial value, which is often used for the starting point positioning or reset operation of the test sequence. For group D1 / group Y1, each group contains 7 registers (D1A-G / Y1A-G), which are usually used to store the reference value of the main address sequence or the main test parameters. For group D2 / group Y2, each group contains 4 registers (D2A-D / Y2A-D), which are usually used to store auxiliary parameters, alternate addresses, or offsets. By managing the initial parameters in groups, the classification organization of the data source is realized, which is convenient for subsequent flexible selection and the implementation of complex algorithms. The X / Y symmetric design ensures the independence and coordination of two-dimensional address space generation.

[0035] The address selection module is the data selection layer of the pattern generator, responsible for selecting the corresponding value from the initialization parameter values ​​as the address selection parameter value according to the test instruction. The address selection module selects the corresponding initialization parameter value from the initialization parameter values ​​based on the first selection instruction carried in the test instruction sequence identifier, thus determining the address selection parameter value. For example, the address selection parameter can be signals such as XH, XOS, XT, XBMUX, YH, YOS, YT, and YBMUX. For the X address, the address selection module outputs signals such as XH, XOS, XT, and XBMUX, where XBMUX acts as a key multiplexer, selecting one of the 13 inputs as the output from the 7 registers in group D1, the 4 registers in group D2, or directly taking the initial value of XH. For the Y address, the address selection module outputs signals such as YH, YOS, YT, and YBMUX, with YBMUX selecting from the 13 inputs in groups Y1, Y2, and YH. The first selection instruction can refer to the instruction part in the test instruction sequence identifier used to control the address selection module to select the data source, determining which initialization parameter value to use in the current cycle. The XBMUX / YBMUX (address selection multiplexer) is the core component for implementing 13-to-1 data selection, and its output serves as the input data source for the address calculation module. XOS / XT and YOS / YT are other control signals output by the address selection module, used for timing control or mode identification in the address generation process. Through the multiplexer mechanism, the diversity of X / Y address outputs is ensured; addresses can originate from different data groups (D1 group, D2 group, XH or Y1 group, Y2 group, YH), providing a rich data foundation for the implementation of complex testing algorithms. This design allows for dynamic switching of data sources within the same test sequence, supporting advanced functions such as data background switching and multi-bank testing.

[0036] The address operation module is the data processing layer of the pattern generator, responsible for performing operations on the parameter values of the address selection parameters and the parameter values of the address generation parameters to generate a dynamically changing address sequence. The address operation module performs a corresponding first operation on the parameter values of the address selection parameters and the parameter values of the address generation parameters according to the operation instruction carried by the test instruction sequence identifier, and determines the target parameter values of the address generation parameters. The address generation parameters include XB, XC, XS, XK, XR1-XR4 (in the X direction) and YB, YC, YS, YK, YR1-YR4 (in the Y direction), which are programmable registers inside the address operation module and store the address values after being operated. The first operation at least includes arithmetic operations (addition, subtraction), logical operations (shift, exclusive OR), etc. For example, when the test instruction sequence identifier carries the operation instruction XB<XH, XB<=XB+1, the address operation module assigns XH to the current XB, and the value of the current XB is incremented by 1 based on the current value; the calculation processes of other address generation parameters XC, XS, XK, XR1-XR4 (and YB, YC, YS, YK, YR1-YR4 in the Y direction) are similar to that of XB. After the calculation is completed, the address operation module outputs the calculated data such as XB, XC, XS, XK, XR1-XR4 as the target parameter values. The operation instruction can refer to the instruction part in the test instruction sequence identifier used to control the address operation module to perform specific operation operations, and the format is usually [target register]<=[source operand][operator][operand]. The first operation is the core operation performed by the address operation module, including arithmetic operations and logical operations such as addition (+), subtraction (-), left shift (<<), right shift (>>), exclusive OR (XOR), AND, OR, etc. XB is usually used for basic address traversal, XC is used for column offset calculation, XS is used for step size extension, XK is used for address scrambling, and XR1-XR4 are used for temporary storage or boundary calculation of complex algorithms. YB / YC / YS / YK / YR1-YR4 correspond to the X direction and are used for address generation in the Y dimension.

[0037] The pattern generator, acting as the final output control layer, is responsible for selecting a corresponding value from the target parameter values ​​as a candidate intermediate quantity according to the second selection instruction. Based on the second selection instruction carried in the test instruction sequence identifier, the pattern generator selects the corresponding target parameter value (XB, XC, XS, XK, XR1-XR4 or YB, YC, YS, YK, YR1-YR4) from the target parameter values ​​for address generation parameters to determine the candidate intermediate quantity. The output X address can be selected from XB, XC, XS, XK, XR1-XR4, and the Y address can be selected from YB, YC, YS, YK, YR1-YR4. These are combined to form a complete (X,Y) address pair of candidate intermediate quantities. The second selection instruction can refer to the instruction portion in the test instruction sequence identifier used to control the pattern generator to perform the final address selection, determining from which address the parameter is generated to output the final address. The candidate intermediate quantity refers to the address value determined after selection by the second selection instruction, such as the X address and Y address values. This enables flexible selection of the final output from multiple address generation parameters (e.g., 6 address generation parameters or 48 sources across 8 channel PGs), supports dynamic switching of different registers within the same PG (e.g., XB / XC / XS polling) and cross-PG bank interleaving access. This design allows the XY two-dimensional address to operate independently, with the X address selected from D1 / D2 groups for row scanning and the Y address fixed at YH; it can also cooperate, using the base address of D1 group in the X direction and the offset parameters of Y2 group in the Y direction to achieve two-dimensional matrix traversal; and it can also be cross-linked, using instructions carried by the test instruction sequence identifier to achieve joint operation of XB and YK to generate diagonal addresses, fully meeting the stringent requirements of address diversity and programmability for complex algorithms such as row and column scanning, bank interleaving, and data background switching in memory testing.

[0038] In another embodiment of this disclosure, a high-speed communication interface module is used to receive test parameter data, the test parameter data including a test instruction set, rate mode configuration information and a sequence parameter packet, the sequence parameter packet including: a start test instruction sequence identifier, a loop count and a jump condition; The instruction sequence module is used to use the starting test instruction sequence identifier as the test instruction sequence identifier for the first clock cycle after the instruction sequence module is started. Following the clock cycle sequence, the micro-instructions corresponding to the test instruction set are read sequentially according to the test instruction sequence identifier of the current clock cycle. Based on the jump condition code or loop flag carried by the micro-instruction, the corresponding jump condition or loop count in the sequence parameter package is matched to generate the test instruction sequence identifier for the next clock cycle, until the chip test is completed.

[0039] In this embodiment, after the instruction sequence module starts, it uses the initial test instruction sequence identifier as the test instruction sequence identifier for the first clock cycle. Then, following the clock cycle sequence, it reads the corresponding microinstruction using the current test instruction sequence identifier as an index. Through the jump condition code or loop flag carried by the microinstruction, it precisely matches the jump condition or loop count in the sequence parameter package, iteratively generating the test instruction sequence identifier for the next clock cycle until chip testing is completed, thus achieving automated and precise scheduling of the instruction sequence. The test parameter data also includes the sequence parameter package, which is the core parameter set for instruction sequence module scheduling. The sequence parameter package includes: the initial test instruction sequence identifier, the loop count, and the jump condition. The initial test instruction sequence identifier serves as the instruction index for the first clock cycle of the entire chip testing process, clearly defining the starting execution node of the test; the loop count defines the number of times a specific test instruction sequence needs to be executed repeatedly, adapting to test scenarios such as cyclic read / write of memory chips and repeated fault detection; the jump condition clarifies the triggering condition for the instruction sequence to switch from the current execution flow to other execution flows (such as specific data verification results, timing signal feedback, etc.), supporting flexible switching of complex test logic. The sequence parameter package, along with the test parameter data, is transmitted to the FPGA's internal parameter storage unit cache via a high-speed communication interface module. This ensures that the instruction sequence module can quickly read and call the data, laying the foundation for automated instruction sequence scheduling. Upon receiving the start signal, the instruction sequence module (corresponding to the FPGA's internal Sequence module) first reads the starting test instruction sequence identifier from the parameter storage unit and uses it as the test instruction sequence identifier (PC) for the first clock cycle. This ensures the test process starts precisely from the preset starting node, avoiding disordered instruction execution order. Based on the FPGA's clock synchronization characteristics, the first test instruction sequence identifier is strictly aligned with the clock cycle, providing a timing reference for subsequent iterations to generate new test instruction sequence identifiers according to the clock cycle, ensuring the synchronization and stability of instruction execution. Within each clock cycle, the instruction sequence module uses the test instruction sequence identifier of the current clock cycle as an index to read the corresponding microinstruction from the test instruction set. This microinstruction contains both the specific test operation logic and a jump condition code or loop flag. The module precisely matches the jump condition code carried by the microinstruction with the jump conditions in the sequence parameter package, or compares the loop flag with the loop count in the sequence parameter package, to determine whether a jump or loop operation is needed. Based on the matching and comparison results, the module generates the test instruction sequence identifier for the next clock cycle. If the jump condition is met, the test instruction sequence identifier corresponding to the jump target is generated. If a loop needs to be executed but the preset loop count has not been reached, the test instruction sequence identifier at the beginning of the current loop is generated to repeat the corresponding instruction sequence. If neither the jump condition is met nor a loop needs to be executed, the next test instruction sequence identifier, incrementing sequentially, is generated. This process is repeated until all test instructions are executed, at which point the generation of test instruction sequence identifiers terminates.The entire process is based on clock cycles for ordered iteration, ensuring a strict match between the instruction sequence and the test timing, thus adapting to the testing requirements of high-speed memory chips. The sequence parameter package integrates core parameters such as the initial test instruction sequence identifier, loop count, and jump conditions, allowing for flexible configuration of instruction execution rules without modifying hardware logic. This adapts to complex test scenarios and the testing needs of diverse memory chips, significantly improving the flexibility and versatility of the solution. Implemented on an FPGA hardware architecture, the iterative generation logic for the test instruction sequence identifier is simple and efficient, consuming minimal hardware resources, and balancing testing flexibility, accuracy, and efficiency.

[0040] In another embodiment of this disclosure, the test signal output module includes: a routing selection unit and a drive output unit; the routing selection unit includes a first number of first pins; the drive output unit includes a first number of second pins; the second pins are connected to the chip; The routing unit is used to select test vectors, and each first pin outputs the target number of routing test signals in parallel. The drive output unit is used to convert the routing selection test signal output from each first pin, generate the target test signal, and output it to the chip through the corresponding second pin.

[0041] In this embodiment, the test signal output module, in collaboration with the routing selection unit and the drive output unit, completes the conversion and output of the test vector into a target test signal. The routing selection unit can be a PDS module. The drive output unit can be a DRV module. The first pin of the routing selection unit corresponds to the second pin of the drive output unit, and the second pin is connected to the chip under test. The routing selection unit selects the test vector (address information and data information) output by the ALPG module, and each first pin outputs a routing selection test signal in parallel; then the drive output unit sequentially converts the routing selection test signals output by each first pin to generate a high-speed serial target test signal, which is transmitted to the chip under test through the corresponding second pin, realizing multi-way parallel, high-speed and stable test signal output.

[0042] The test signal output module consists of a routing selection unit and a drive output unit, both with the same number of pins (both are the first number). The second pin directly connects to the interface of the chip under test (DUT), serving as the final output of the target test signal; the first pin serves as the output of the routing selection test signal, responsible for accurately transmitting the filtered signal to the corresponding drive output unit link. This hardware configuration provides structural support for multi-way parallel signal transmission and independent signal processing, adapting to the design requirement of N-way output per pin of the PDS module, where N represents the number of channels. Each first pin of the PDS module corresponds to an N-way output path. The routing selection unit filters the received multi-channel test vectors path by path, with each first pin simultaneously selecting signals from Nways, outputting the target number of routing selection test signals in parallel, and all first pins working synchronously to achieve full-link N-way parallel signal output.

[0043] The Drive Output Unit (DRV module) operates independently for each first pin link. The DRV module receives the routing test signal transmitted from the corresponding first pin, first performs FC encoding on the signal, and generates different code patterns based on the interface protocol of the chip under test (DUT) to optimize signal transmission quality and avoid inter-symbol interference and clock synchronization deviations during high-speed transmission, ensuring the signal can be correctly parsed by the DUT. Subsequently, a parallel-to-serial conversion circuit converts the encoded N-way parallel signal into a high-speed serial test signal. The serial signal rate corresponds one-to-one with the N-way mode (e.g., 2.4Gbps for 8-way mode, 1.2Gbps for 4-way mode, etc.). Finally, the DRV module transmits the high-speed serial target test signal to the corresponding interface of the DUT through the corresponding second pin, completing the test signal output. All second pins output signals synchronously in parallel, forming a closed loop with the parallel processing logic of the routing unit, ensuring efficient progress of the overall test process. The N-way parallel signal processing and end-to-end synchronous transmission architecture, based on the parallel hardware characteristics of FPGA, significantly improves the test signal output efficiency and adapts to various test rate requirements of memory chips.

[0044] In another embodiment of this disclosure, it further includes: The high-speed communication interface module is used to receive test parameter data, which includes a channel index mapping table. The test vectors include: access chip address information and data information; routing selection test signals, including: address signals and data signals; The routing unit is used to select a target channel from the target number of channels according to the channel index mapping table, and use the address information generated by the target channel as the address signal; wherein, the number of target channels is the target number, and each first pin outputs the target number of address signals in parallel; The data information generated by the target channel is used as a data signal; wherein, each first pin outputs the target number of data signals in parallel.

[0045] In this embodiment, the routing unit accurately filters the address and data information in the test vector and outputs it in parallel across multiple ways. It selects the target channel based on the channel index mapping table in the test parameter data. The test vector includes address and data information for accessing the chip under test. The routing unit first selects the target channel from the target number of channels according to the channel index mapping table, extracting the address and data information of the target channel as address and data signals, respectively. Then, it outputs the target number of address and data signals in parallel through each first pin, providing standardized parallel signals for the subsequent FC encoding and parallel-to-serial conversion of the DRV module. This achieves independent routing and synchronous parallel transmission of address / data signals, adapting to multi-way testing requirements. The test vector consists of the address information (corresponding to the X / Y address output by the ALPG module) and data information (corresponding to the Data signal output by the ALPG module) for accessing the chip under test. These two are the core objects of routing selection, used for addressing and locating the chip under test and for data read / write testing, respectively. The routing selection test signal is output after routing selection. The test parameter data includes a channel index mapping table, which serves as the core configuration basis for target channel selection. This channel index mapping table is stored in the FPGA's internal registers and clarifies the correspondence between channel number, signal source, and routing path, providing rule support for the PDS module to accurately select target channels, while also adapting to the hardware design of each IO N WAY output.

[0046] The PDS module reads the channel index mapping table stored in the register and, according to the rules in the mapping table, selects target channels that meet the current test requirements from the previously determined target number of channels (the number of target channels must match the target number). Then, it extracts the address information (X / Y address) generated by each target channel as the address signal, completing the precise routing selection of address information. It also extracts the data information (Data signal) generated by each target channel as the data signal. Based on the design of the PDS module with N WAY outputs per IO, each first pin synchronously adapts to N WAY parallel output logic, outputting the target number of address and data signals in parallel, and all first pins operate synchronously, achieving N WAY parallel transmission of address and data signals across the entire link.

[0047] The channel index mapping table clarifies the channel selection rules, filtering out channels that meet the current test requirements from the X address, Y address, and Data signals output by the upper-level ALPG module. The test vector generated by this channel is then used as the output signal of that WAY. This ensures precise adaptation to the various test rate requirements of the memory chip.

[0048] In another embodiment of this disclosure, the drive output unit is used to encode the routing selection test signal for each routing selection signal output from the first pin to generate an encoded test signal. The encoded test signal is converted from parallel to serial to generate the target test signal, which is then output to the chip through the corresponding second pin.

[0049] In this embodiment, the drive output unit optimizes, converts, and finally outputs the routing selection unit's output signals. For each routing selection test signal (including address and data signals) output from a first pin, the drive output unit first performs FC encoding processing to generate coded test signals with various code types. Then, it performs parallel-to-serial conversion on the coded test signals, transforming the multi-way parallel signals into high-speed serial target test signals. Finally, these signals are transmitted to the chip under test (DUT) through a second pin, completing the final optimization and output of the test signals to meet high-speed testing requirements. The DRV module synchronously receives the routing selection test signals output from each first pin, which include multi-way parallel address and data signals filtered by the PDS module. For each signal, the DRV module performs FC encoding processing according to preset encoding rules. Based on the interface protocol and transmission requirements of the chip under test, it generates coded test signals of different types. Different code types can adapt to different interface protocols, while effectively reducing DC components and inter-symbol interference during high-speed transmission, strengthening clock synchronization information, and avoiding signal distortion or parsing failure. This lays the foundation for signal quality in subsequent high-speed serial transmission. Furthermore, the encoding process is compatible with multi-way parallel architecture and does not affect overall signal processing efficiency. After completing FC encoding, a parallel-to-serial conversion process is initiated for each coded test signal, converting the coded signals transmitted in N-way parallel transmission into a single high-speed serial signal, generating the target test signal that meets the test rate requirements. The serial signal rate is strictly matched to the N-way mode (e.g., 2.4Gbps for 8-way mode, 1.2Gbps for 4-way mode, etc.), leveraging the characteristics of FPGA hardware to achieve high-speed signal generation. Because the second pin of the DRV module is directly connected to the interface of the chip under test (DUT), the converted high-speed serial target test signal is accurately transmitted to the corresponding interface of the DUT through the corresponding second pin. All second pins output synchronously and in parallel, ensuring the synchronization and efficiency of the overall test process. Based on the reconfigurable characteristics of FPGAs, it can be flexibly adjusted to adapt to different types and speeds of DUTs without modifying the hardware structure, improving the versatility and flexibility of the solution. Compared with traditional test solutions, it significantly reduces the hardware adaptation cost and debugging difficulty of high-speed testing, achieving a multi-dimensional balance between test performance, compatibility, and cost.

[0050] In another embodiment of this disclosure, the system further includes a host computer, which is used to send test parameter data to a high-speed communication interface module.

[0051] In this embodiment, the host computer acts as the terminal for generating and distributing test parameter data, integrating and transmitting the test parameter data to provide core configuration basis for the entire FPGA testing system process. The host computer first generates complete test parameter data (including test instruction sets, rate mode configuration information, sequence parameter packets, channel index mapping tables, etc.) based on the specifications of the chip under test and test requirements. Then, it sends the data to the FPGA's high-speed communication interface module via a preset transmission link, ensuring accurate and stable data transmission to the FPGA and supporting the orderly execution of subsequent instruction sequence generation, test vector routing selection, signal conversion output, and other stages.

[0052] like Figure 5 As shown, Figure 5 A schematic diagram of the chip testing process provided in this disclosure includes the following steps: S501: The host computer sends test parameter data to the FPGA through the high-speed communication interface module, and the FPGA forwards the data to the registers of various functional modules through the internal bus. S502, Start the instruction sequence module to generate the corresponding test instruction sequence identifier according to the test instruction set; S503, the test vector generation module configures the mode according to the rate mode configuration information to determine the target number of channels; and generates a test vector for each channel according to the test instruction sequence identifier; S504, the routing selection unit selects the test vector, and each first pin outputs the target number of routing selection test signals in parallel; The S505 driver output unit converts the routing selection test signal output from each first pin to generate a target test signal, and outputs it to the chip through the corresponding second pin to complete the chip test.

[0053] Based on the same disclosed concept, this disclosure also provides a chip testing method and apparatus. Since the principle of these apparatuses in solving the problem is similar to that of the aforementioned chip testing system, the implementation of the method and apparatus can refer to the implementation of the aforementioned system, and the repeated parts will not be described again.

[0054] This disclosure provides a chip testing method, such as... Figure 6 As shown, it includes: S601. Generate the corresponding test instruction sequence identifier according to the test instruction set; S602. Based on the rate mode configuration information, perform mode configuration to determine the target number of channels; and generate a test vector for each channel based on the test instruction sequence identifier. S603. Perform signal conversion processing on the test vector to generate the target test signal to complete the chip test.

[0055] In another embodiment of this disclosure, the rate mode configuration information carries information about the number of channels used to generate the test vector; Based on the rate mode configuration information, the mode is configured to determine the target number of channels; and based on the test instruction sequence identifier, a test vector is generated for each channel, including: Multiple pattern generators are grouped according to the channel number information so that each group corresponds to one channel, resulting in the target number of channels; for each channel, the corresponding operation is performed according to the test instruction sequence identifier to generate the corresponding target intermediate quantity; Generate the target number of test vectors based on the target intermediate value.

[0056] In another embodiment of this disclosure, performing corresponding operations based on the test instruction sequence identifier to generate a corresponding target intermediate quantity includes: Based on the test instruction sequence identifier, perform the same operation to generate candidate intermediate quantities; Use any candidate intermediate value within the channel as the target intermediate value output by that channel.

[0057] In another embodiment of this disclosure, generating candidate intermediate quantities by performing the same operation based on the test instruction sequence identifier includes: Initialize the configuration of multiple address initial parameters to obtain the initial parameter values; Select the corresponding initialization parameter value according to the first selection instruction carried by the test instruction sequence identifier, and determine the parameter value of the address selection parameter; Based on the arithmetic instructions carried by the test instruction sequence identifier, perform the corresponding first operation on the parameter values ​​of the address selection parameter and the address generation parameter to determine the target parameter value of the address generation parameter; the first operation includes at least one of the following: arithmetic operation and logical operation; Select the corresponding target parameter value based on the second selection instruction carried by the test instruction sequence identifier, and determine the candidate intermediate quantity.

[0058] In another embodiment of this disclosure, the method further includes: Receive test parameter data, which includes test instruction set, rate mode configuration information and sequence parameter packet. The sequence parameter packet includes: start test instruction sequence identifier, number of loops and jump condition. Based on the test instruction set, generate corresponding test instruction sequence identifiers, including: After the instruction sequence module starts, the starting test instruction sequence identifier is used as the test instruction sequence identifier for the first clock cycle; Following the clock cycle sequence, the micro-instructions corresponding to the test instruction set are read sequentially according to the test instruction sequence identifier of the current clock cycle. Based on the jump condition code or loop flag carried by the micro-instruction, the corresponding jump condition or loop count in the sequence parameter package is matched to generate the test instruction sequence identifier for the next clock cycle, until the chip test is completed.

[0059] In another embodiment of this disclosure, the test vector is subjected to signal conversion processing to generate a target test signal to complete the chip test, including: The test vector is selected, and each first pin outputs the target number of routing selection test signals in parallel; For each routing test signal output from the first pin, the routing test signal is converted to generate a target test signal, which is then output to the chip through the corresponding second pin.

[0060] In another embodiment of this disclosure, the method further includes: receiving test parameter data, wherein the test parameter data includes a channel index mapping table; The test vectors include: access chip address information and data information; routing selection test signals, including: address signals and data signals; The test vector is selected, and each first pin outputs a target number of routing selection test signals in parallel, including: According to the channel index mapping table, select the target channel from the target number of channels, and use the address information generated by the target channel as the address signal; wherein, the number of target channels is the target number, and each first pin outputs the target number of address signals in parallel; The data information generated by the target channel is used as a data signal; wherein, each first pin outputs the target number of data signals in parallel.

[0061] In another embodiment of this disclosure, for each routing selection test signal output from a first pin, the routing selection test signal is converted to generate a target test signal, and then output to the chip through the corresponding second pin, including: For each routing selection signal output from the first pin, the routing selection test signal is encoded to generate an encoded test signal; The encoded test signal is converted from parallel to serial to generate the target test signal, which is then output to the chip through the corresponding second pin.

[0062] This disclosure provides a chip testing device, including a chip testing system as described in any of the above embodiments.

[0063] Through the above description of the embodiments, those skilled in the art can clearly understand that the embodiments of this disclosure can be implemented in hardware or by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solutions of the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, mobile hard drive, etc.) and includes several instructions to cause a computer device (such as a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments of this disclosure.

[0064] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of a preferred embodiment, and the modules or processes in the drawings are not necessarily essential for implementing this disclosure.

[0065] Those skilled in the art will understand that the modules in the apparatus of the embodiments can be distributed in the apparatus of the embodiments as described in the embodiments, or they can be located in one or more devices different from this embodiment with corresponding changes. The modules of the above embodiments can be combined into one module, or they can be further divided into multiple sub-modules.

[0066] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0067] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A chip testing system, characterized in that, include: The instruction sequence module is used to generate corresponding test instruction sequence identifiers based on the test instruction set; The test vector generation module is used to configure the mode according to the rate mode configuration information to determine the target number of channels; and to generate a test vector for each channel according to the test instruction sequence identifier. The test signal output module is used to perform signal conversion processing on the test vector to generate a target test signal in order to complete the test of the chip.

2. The system as described in claim 1, characterized in that, The rate mode configuration information carries the number of channels for generating test vectors; the test vector generation module includes a mode generator unit and an address data shaping unit; the mode generator unit includes multiple mode generators; The test vector generation module is used to group multiple pattern generators according to the channel number information, so that each group corresponds to one channel, resulting in a target number of channels; each channel is used to perform corresponding operations according to the test instruction sequence identifier to generate the corresponding target intermediate quantity. The address data shaping unit is used to generate the target number of test vectors based on the target intermediate quantity.

3. The system as described in claim 2, characterized in that, Each pattern generator in the channel is used to perform the same operation to generate candidate intermediate quantities according to the test instruction sequence identifier; The test vector generation module is used to take the candidate intermediate quantity generated by any pattern generator in the channel as the target intermediate quantity output by the channel.

4. The system as described in claim 3, characterized in that, The pattern generator includes: an initialization module, an address selection module, and an address calculation module; The initialization module is used to initialize and configure multiple address initialization parameters to obtain initialization parameter values; The address selection module is used to select the corresponding initialization parameter value according to the first selection instruction carried by the test instruction sequence identifier, and determine the parameter value of the address selection parameter. The address calculation module is used to perform a first operation on the parameter value of the address selection parameter and the parameter value of the address generation parameter according to the calculation instruction carried by the test instruction sequence identifier, and to determine the target parameter value of the address generation parameter; the first operation includes at least one of the following: arithmetic operation and logical operation; The pattern generator is used to select the corresponding target parameter value according to the second selection instruction carried by the test instruction sequence identifier, and to determine the candidate intermediate quantity.

5. The system as described in claim 1, characterized in that, Also includes: A high-speed communication interface module is used to receive test parameter data, which includes a test instruction set, rate mode configuration information, and sequence parameter packet. The sequence parameter packet includes: start test instruction sequence identifier, loop count, and jump condition. The instruction sequence module is used to use the starting test instruction sequence identifier as the test instruction sequence identifier for the first clock cycle after the instruction sequence module is started. Following the clock cycle sequence, the microinstructions corresponding to the test instruction set are read sequentially according to the test instruction sequence identifier of the current clock cycle; the jump condition code or loop flag carried by the microinstruction is matched with the corresponding jump condition or loop count in the sequence parameter package to generate the test instruction sequence identifier for the next clock cycle, until the chip test is completed.

6. The system as described in claim 1, characterized in that, The test signal output module includes a routing selection unit and a drive output unit; the routing selection unit includes a first number of first pins; the drive output unit includes a first number of second pins; the second pins are connected to the chip. The routing selection unit is used to select the test vector, and each first pin outputs the target number of routing selection test signals in parallel; The drive output unit is used to convert the routing selection test signal output from each first pin to generate a target test signal, and output it to the chip through the corresponding second pin.

7. The system as described in claim 6, characterized in that, Also includes: A high-speed communication interface module is used to receive test parameter data, which includes a channel index mapping table; The test vector includes: address information and data information for accessing the chip; the routing test signal includes: address signal and data signal; The routing unit is used to select a target channel from a target number of channels according to the channel index mapping table, and use the address information generated by the target channel as an address signal; wherein, the number of target channels is the target number, and each first pin outputs the target number of address signals in parallel; The data information generated by the target channel is used as a data signal; wherein, each first pin outputs the target number of data signals in parallel.

8. The system as described in claim 6, characterized in that, The drive output unit is used to encode the routing selection test signal for each routing selection signal output from the first pin to generate an encoded test signal. The encoded test signal is converted from parallel to serial to generate the target test signal, and then output to the chip through the corresponding second pin.

9. A chip testing method, characterized in that, include: Generate the corresponding test instruction sequence identifier based on the test instruction set; Based on the rate mode configuration information, perform mode configuration to determine the target number of channels; And based on the test instruction sequence identifier, a test vector is generated for each channel; The test vector is processed by signal conversion to generate a target test signal, thereby completing the test of the chip.

10. A chip testing device, characterized in that, include: The chip testing system as described in any one of claims 1 to 8.

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