Methods for calculating the flight time of lidar devices
By using FPGA modules to construct carry chains in lidar devices, the data output bottleneck problem of traditional lidar devices in multi-channel ToF applications is solved, achieving efficient, real-time data processing and multi-channel parallel processing, reducing costs and noise interference.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GUANGDONG JATEN ROBOT & AUTOMATION
- Filing Date
- 2026-05-29
- Publication Date
- 2026-06-30
AI Technical Summary
Traditional lidar devices, in high-performance, multi-channel ToF applications, are limited by the number of channels and bus bandwidth, resulting in non-real-time data output and bottleneck issues. In particular, the SPI bus becomes a serious bottleneck when performing high-speed continuous measurements.
By employing an FPGA module and utilizing its internal logic units to construct a carry chain, TDC (Time-to-Dial) conversion is achieved. This integrates laser control, time capture, digital signal processing, and AI decision-making. The FPGA carry chain algorithm is used to calculate time of flight, reducing inter-chip communication bottlenecks and enabling high-speed real-time data output.
It achieves efficient and real-time data output from the lidar device, supports multi-channel parallel processing, reduces thermal noise interference, automatically calibrates temperature changes, reduces PCB board area, and lowers overall cost.
Smart Images
Figure CN122307574A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of lidar devices, and in particular to a method for calculating the flight time of a lidar device. Background Technology
[0002] LiDAR emits and receives lasers during operation. By calculating the time it takes for the laser to travel through the air, the detection distance can be estimated. Traditional time-of-flight calculations use dedicated Time-of-Flight (TDC) chips. While TDC chips have advantages in power consumption and ease of use, they are relatively disadvantageous in high-performance, multi-channel Time-of-Flight (ToF) applications due to limitations in the number of channels and bus bandwidth. Specifically, dedicated TDC chips use SPI or I2C interfaces, so each measurement requires reading data through a serial bus of hundreds of kHz or tens of MHz. For high-speed continuous measurements (such as high-beam lidar with millions of samples per second), the SPI bus becomes a serious bottleneck, preventing real-time data output. Summary of the Invention
[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method for calculating the flight time of a lidar device, which utilizes an FPGA module with multiple logic units inside to achieve rapid processing, calculation and control of large amounts of data.
[0004] To achieve the above objectives, the present invention adopts the following technical solution: A method for calculating the flight time of a lidar device, wherein the lidar device is equipped with an FPGA module, the FPGA module is equipped with several registers, several full adders and a TDC carry chain module, wherein at least some of the full adders are connected in series to form a full adder cascade as an FPGA carry chain, and the TDC carry chain module includes a TDC coarse measurement time module and a TDC fine measurement time module. The method for calculating flight time includes the following steps: Signal input: The Start or Stop signal enters the input of the FPGA carry chain and is passed up the chain level by level; Status data acquisition: At the rising edge of the next system clock, the register simultaneously samples the status data of the entire carry chain; Calculate the time interval: The TDC coarse time measurement module records how many complete clock cycles Tclk have passed between the Start signal and the Stop signal, and the TDC fine time measurement module calculates the residual time between the Stop signal and the nearest clock edge; Calculate flight time: The flight time is calculated based on the data from the TDC coarse time measurement module, the TDC fine time measurement module, and the carry chain record.
[0005] Compared with the prior art, the method for calculating the flight time of a lidar device according to the present invention has the following advantages: (1) This invention relates to the use of FPGA modules in lidar devices and the implementation of Time-of-Flight (ToF) calculation using FPGA carry chain algorithm. The carry chain is used to build a Time-to-Digital Converter (TDC) inside the FPGA module, thereby integrating laser control, time capture (TDC), digital signal processing (DSP), and AI decision-making into the same chip. This system-on-a-chip (SoC) architecture not only eliminates the bottleneck of inter-chip communication and realizes high-speed real-time output of large amounts of data, but also allows for flexible adjustment of measurement strategies according to different detection environments, and has a high applicability. (2) Tens of thousands of logic units can be set inside the FPGA module. By writing HDL code, 128 or even more completely independent carry chains TDC can be instantiated in parallel. Existing ASIC chips cannot achieve this kind of large-scale parallel processing capability. In addition, the programmability of the FPGA module allows for real-time calibration of the nonlinearity of the carry chain at the algorithm level (through lookup table (LUT) or least squares method). The FPGA module can automatically correct the time scale scaling caused by temperature changes during operation. Existing fixed-function dedicated hardware modules require complex hardware and algorithm settings to achieve this function. (3) The FPGA module of the present invention can adopt a scheme of simultaneous sampling of multiple carry chains in the same channel to reduce thermal noise interference, and can simultaneously use some filtering measures to filter out glitches interference, and adds automatic clock jitter compensation. (4) It is known that a TDC chip usually only supports 1-2 channels. If 64 channels are needed, dozens of chips need to be arranged, which will occupy the area of the PCB board. The FPGA module can set tens of thousands of logic units, thus having multiple channels, which can avoid occupying too much PCB board area. Moreover, the FPGA module can take into account system control, data interface (such as PCIe / Ethernet), motor control, image preprocessing and other functions. It has high integration and makes the total cost of the control device lower.
[0006] Furthermore, the latency of each carry logic stage is 10-20 ps.
[0007] The latency of each carry logic is very small, thus avoiding large data delays and ensuring real-time data transmission (e.g., about 10-20ps on Xilinx Ultrascale+).
[0008] Furthermore, during the status data acquisition process of the carry chain, the full adder sections that have passed are marked as "1", and the full adder sections that have not yet arrived are marked as "0". The number of marked "1" is counted to obtain the distance traveled by the signal under test in the current clock cycle.
[0009] The above setup actually uses a carry chain to measure distance, and then combines clock data and distance to derive the flight time.
[0010] Furthermore, the TDC coarse measurement time module is a synchronous counter.
[0011] Furthermore, the TDC fine-tuning time module is used to calculate the residual time less than one clock frequency Tclk.
[0012] Furthermore, the FPGA module is equipped with several carry chain time-of-flight calculation modules, and each carry chain time-of-flight calculation module has an input channel. During signal input, each channel uses several carry chain time-of-flight calculation modules to calculate the time of flight, and then performs averaging and filtering in sequence. Based on the echo pulse width, multiple echo overlap processing is performed to filter out echoes less than 100ps and greater than 4000ps.
[0013] Furthermore, the carry chain ranging includes coarse and fine measurement values. Cnt_wide is the coarse measurement value, with the unit being clock cycles, and Cnt_fine is the fine measurement value, with the unit being the delay of a single carry chain. The integer cycle time Cnt_wide obtained from the coarse measurement and the fractional part time Cnt_fine obtained from the fine measurement are added together to obtain the final total laser flight time. The stop input is fed into the first stage of the carry chain, and then the carry chain value is latched by the first rising edge of clk. The position of 1->0 in the carry chain is found, the number of 1s N is calculated, and N is multiplied by the time of a single carry chain to obtain the fine measurement time.
[0014] Since the start signal of the lidar is derived from the same source as the clk (start is also derived from the same master clock (CLK clock) by frequency division / multiplication), there is no need to consider the fine measurement value of the start signal. The time from start to stop is finally calculated based on the coarse and fine measurement values.
[0015] Furthermore, the method for calculating the delay of a single carry chain includes: Get the main high-speed operating clock clkn and the offset compensation clock clkn_offset, where n is the number of clocks; Clkn_offset enters the carry chain, and clkn samples the carry chain positions of the two rising edges and subtracts them to obtain the carry chain delay time.
[0016] Furthermore, the jitter time of clkn is calculated, including: Obtain the clock signal from the main high-speed operating clock clkn; Clkn enters the carry chain, Clkn samples the carry chain result, and obtains multiple carry chain results of clkn; Calculate the average of the carry chain results for multiple clkn operations; Clkn's clock jitter is the difference between the result of each carry chain and the average value.
[0017] In reality, there is jitter in each clkn cycle, so the clock jitter needs to be calculated and compensated for in order to obtain the correct coarse measurement time. Attached Figure Description
[0018] Figure 1 This is a schematic diagram of the carry chain ranging principle; Figure 2 This is a schematic diagram of data collection during the carry chain ranging process; Figure 3 This is a schematic diagram of the signal input processing procedure; Figure 4 This is a diagram illustrating the calculation principle of delay for a single carry chain. Figure 5 This is a diagram illustrating the calculation principle of clkn's jitter time. Detailed Implementation
[0019] The embodiments of the present invention are described below with reference to the accompanying drawings: A lidar device is equipped with an FPGA module. The FPGA module includes several registers, several full adders, a TDC carry chain module, a clock phase adjustment module, a carry chain calculation module, a subtractor, and a flip-flop. At least some of the full adders are connected in series to form a cascaded full adder as an FPGA carry chain (each carry output is connected to the carry input of the next stage). The TDC carry chain module includes a TDC coarse measurement time module, a TDC fine measurement time module, a TDC coarse measurement time conversion module, a TDC fine measurement time conversion module, and an adder (a digital circuit unit that implements binary digital addition operations).
[0020] The carry chain calculation module functions as follows: a set of cascaded logic gates, each with a fixed propagation delay; the input clk2_offset signal is delayed by a fixed time after each level it passes through in the chain. The calculation module records the position of the signal in the chain, i.e., how many levels the signal has passed through, and outputs the "carry chain result".
[0021] The function of the subtractor is to subtract the "average position" obtained from multiple measurements from the "carry chain result" of a single measurement to obtain the deviation.
[0022] The function of the trigger is to latch the position of the clk2_offset signal in the carry chain at the rising edge of clk2 (at time T1); this latching result corresponds to the number of units the signal passes through in the carry chain between T0 and T1.
[0023] The method for calculating the flight time of the lidar device in this embodiment includes the following steps: Signal input: The Start or Stop signal enters the input end of the FPGA carry chain (bottom of the FPGA carry chain) and is passed up the chain step by step (when the signal to be tested arrives, it begins to propagate on the carry chain). Status data acquisition: At the rising edge of the next system clock, the register simultaneously samples the status data of the entire carry chain; Calculate the time interval: The TDC coarse time measurement module records how many complete clock cycles (Tclk) have passed between the Start signal and the Stop signal, and the TDC fine time measurement module calculates the residual time between the Stop signal and the nearest clock edge; Calculate flight time: The flight time is calculated based on the data from the TDC coarse time measurement module, the TDC fine time measurement module, and the carry chain record.
[0024] Furthermore, the latency of each carry logic stage is 10-20 ps.
[0025] The latency of each carry logic is very small, thus avoiding large data delays and ensuring real-time data transmission (e.g., about 10-20ps on Xilinx Ultrascale+).
[0026] Furthermore, during the status data acquisition process of the carry chain, the full adder sections that have passed are marked as "1", and the full adder sections that have not yet arrived are marked as "0". The number of marked "1" is counted to obtain the distance traveled by the signal under test in the current clock cycle.
[0027] The above setup actually uses a carry chain to measure distance, and then combines clock data and distance to derive the flight time.
[0028] Furthermore, the TDC coarse measurement time module is a synchronous counter.
[0029] Furthermore, the TDC fine-tuning time module is used to calculate the residual time less than one clock frequency Tclk.
[0030] Furthermore, the FPGA module is equipped with several carry chain time-of-flight calculation modules, and each carry chain time-of-flight calculation module has an input channel. During signal input, each channel uses several carry chain time-of-flight calculation modules to calculate the time of flight, and then performs averaging and filtering in sequence. Based on the echo pulse width, multiple echo overlap processing is performed to filter out echoes less than 100ps and greater than 4000ps.
[0031] Furthermore, the carry chain ranging includes coarse and fine measurement values. Cnt_wide is the coarse measurement value, with the unit being clock cycles, and Cnt_fine is the fine measurement value, with the unit being the delay of a single carry chain. The integer cycle time Cnt_wide obtained from the coarse measurement and the fractional part time Cnt_fine obtained from the fine measurement are added together to obtain the final high-precision, wide-range total laser flight time (i.e., the time from start to stop). The stop is input to the first stage of the carry chain, and then the carry chain value is latched by the first rising edge of clk. The position of 1->0 in the carry chain is found, the number of 1s N is calculated, and N is multiplied by the time of a single carry chain to obtain the fine measurement time.
[0032] The rough value is the product of the pulse count (integer) read by the counter and the clock cycle, which is common knowledge and will not be described in detail here.
[0033] Since the start signal of the lidar is derived from the same source as the clk (start is also derived from the same master clock (CLK clock) by frequency division / multiplication), there is no need to consider the fine measurement value of the start signal. The time from start to stop is finally calculated based on the coarse and fine measurement values.
[0034] Furthermore, the method for calculating the delay of a single carry chain includes: Get the main high-speed operating clock clkn and the offset compensation clock clkn_offset, where n is the number of clocks; Clkn_offset enters the carry chain, and clkn samples the carry chain positions of the two rising edges and subtracts them to obtain the carry chain delay time.
[0035] Furthermore, the jitter time of clkn is calculated, including: Obtain the clock signal from the main high-speed operating clock clkn; Clkn enters the carry chain, Clkn samples the carry chain result, and obtains multiple carry chain results of clkn; Calculate the average of the carry chain results for multiple clkn operations; Clkn's clock jitter is the difference between the result of each carry chain and the average value.
[0036] In reality, there is jitter in each clkn cycle, so the clock jitter needs to be calculated and compensated for in order to obtain the correct coarse measurement time.
[0037] The following is an implementation example: like Figure 1 and Figure 2 As shown, the carry chain ranging method includes coarse and fine measurements. `cnt_wide` is the coarse measurement value in clock cycles, and `cnt_fine` is the fine measurement value in the delay of one carry chain. Since the LiDAR start signal and `clk` are from the same source, we don't need to consider the fine measurement value of the start signal. The final start-to-stop time is calculated based on the coarse and fine measurement values. Using 64 cascaded carry chains, the stop input is fed into the first stage of the carry chain. The carry chain value is then latched using the rising edge of the first `clk`. The position where 1->0 is found in the carry chain, the number of 1s is counted, and then multiplied by the time of a single carry chain to obtain the fine measurement time.
[0038] like Figure 3 As shown, each channel uses four carry-chain time-of-flight calculation modules to calculate the time of flight, then performs averaging and filtering in sequence, and then performs multi-echo overlap processing based on the echo pulse width, filtering out echoes less than 100ps and greater than 4000ps.
[0039] Figure 4 The calculation of a single carry chain delay is shown, where clk2 is a 250MHz clock and clk2_offset is a 50MHz clock, with a phase difference of 356 degrees. The phase difference is guaranteed by the clock phase adjustment module. clk2_offset enters the carry chain. The carry chain delay time can be obtained by subtracting the carry chain positions of the two rising edges sampled by clk2.
[0040] Figure 5 The calculation of the jitter time of clk2 is shown. clk2 is a 250MHz clock. What we need to calculate is the clock jitter of clk2. clk2 enters the carry chain, and then clk2 itself samples the carry chain result. Each clock cycle is sampled to obtain many results. The average value is calculated. The clock jitter Tjitter is the average value of each sampled result.
[0041] Compared with the prior art, the method for calculating the flight time of a lidar device according to the present invention has the following advantages: (1) This invention relates to the use of FPGA modules in lidar devices and the implementation of Time-of-Flight (ToF) calculation using FPGA carry chain algorithm. The carry chain is used to build a Time-to-Digital Converter (TDC) inside the FPGA module, thereby integrating laser control, time capture (TDC), digital signal processing (DSP), and AI decision-making into the same chip. This system-on-a-chip (SoC) architecture not only eliminates the bottleneck of inter-chip communication and realizes high-speed real-time output of large amounts of data, but also allows for flexible adjustment of measurement strategies according to different detection environments, and has a high applicability. (2) Tens of thousands of logic units can be set inside the FPGA module. By writing HDL code, 128 or even more completely independent carry chains TDC can be instantiated in parallel. Existing ASIC chips cannot achieve this kind of large-scale parallel processing capability. In addition, the programmability of the FPGA module allows for real-time calibration of the nonlinearity of the carry chain at the algorithm level (through lookup table (LUT) or least squares method). The FPGA module can automatically correct the time scale scaling caused by temperature changes during operation. Existing fixed-function dedicated hardware modules require complex hardware and algorithm settings to achieve this function. (3) The FPGA module of the present invention can adopt a scheme of simultaneous sampling of multiple carry chains in the same channel to reduce thermal noise interference, and can simultaneously use some filtering measures to filter out glitches interference, and adds automatic clock jitter compensation. (4) It is known that a TDC chip usually only supports 1-2 channels. If 64 channels are needed, dozens of chips need to be arranged, which will occupy the area of the PCB board. The FPGA module can set tens of thousands of logic units, thus having multiple channels, which can avoid occupying too much PCB board area. Moreover, the FPGA module can take into account system control, data interface (such as PCIe / Ethernet), motor control, image preprocessing and other functions. It has high integration and makes the total cost of the control device lower.
[0042] Based on the disclosure and teachings of the foregoing specification, those skilled in the art can make changes and modifications to the above embodiments. Therefore, the present invention is not limited to the specific embodiments disclosed and described above, and some modifications and changes to the present invention should also fall within the protection scope of the claims of the present invention. Furthermore, although some specific terms are used in this specification, these terms are only for convenience of explanation and do not constitute any limitation on the present invention.
Claims
1. A method of calculating a time of flight of a laser radar device, characterized in that, The lidar device is equipped with an FPGA module, which includes several registers, several full adders, and a TDC carry chain module. At least some of the full adders are connected in series to form a cascaded full adder as an FPGA carry chain. The TDC carry chain module includes a TDC coarse measurement time module and a TDC fine measurement time module. The method for calculating flight time includes the following steps: Signal input: The Start or Stop signal enters the input of the FPGA carry chain and is passed up the chain level by level; Status data acquisition: At the rising edge of the next system clock, the register simultaneously samples the status data of the entire carry chain; Calculate the time interval: The TDC coarse time measurement module records how many complete clock cycles Tclk have passed between the Start signal and the Stop signal, and the TDC fine time measurement module calculates the residual time between the Stop signal and the nearest clock edge; Calculate flight time: The flight time is calculated based on the data from the TDC coarse time measurement module, the TDC fine time measurement module, and the carry chain record.
2. The method of claim 1, wherein, The delay for each carry logic level is 10-20ps.
3. The method for calculating the flight time of the lidar device according to claim 1, characterized in that, During the status data acquisition process of the carry chain, the full adder parts that have passed are marked as "1", and the full adder parts that have not yet arrived are marked as "0". The number of marked "1" is counted to obtain the distance traveled by the signal under test in the current clock cycle.
4. The method for calculating the flight time of the lidar device according to claim 1, characterized in that, The TDC coarse time measurement module is a synchronous counter.
5. The method for calculating the flight time of the lidar device according to claim 1, characterized in that, The TDC fine-tuning time module is used to calculate the residual time, which is less than one clock frequency Tclk.
6. The method for calculating the flight time of the lidar device according to claim 1, characterized in that, The FPGA module is equipped with several carry chain time-of-flight calculation modules, and each carry chain time-of-flight calculation module has an input channel. During signal input, each channel uses several carry-chain time-of-flight calculation modules to calculate the time of flight, then performs averaging and filtering in sequence, and performs multi-echo overlap processing based on the echo pulse width to filter out echoes less than 100ps and greater than 4000ps.
7. The method for calculating the flight time of the lidar device according to claim 1, characterized in that, Carry chain ranging includes coarse and fine measurements. Cnt_wide is the coarse measurement, which is in clock cycles, and Cnt_fine is the fine measurement, which is the delay of a single carry chain. The integer cycle time Cnt_wide obtained from the coarse measurement and the fractional part time Cnt_fine obtained from the fine measurement are added together to obtain the final total laser flight time. The stop input is fed into the first level of the carry chain. Then, the carry chain value is latched on the first rising edge of the following clk. The position of 1->0 in the carry chain is found, the number of 1s N is calculated, and N is multiplied by the time of a single carry chain to obtain the fine measurement time.
8. The method for calculating the flight time of the lidar device according to claim 7, characterized in that, Methods for calculating the delay of a single carry chain include: Get the main high-speed operating clock clkn and the offset compensation clock clkn_offset, where n is the number of clocks; Clkn_offset enters the carry chain, and clkn samples the carry chain positions of the two rising edges and subtracts them to obtain the carry chain delay time.
9. The method for calculating the flight time of the lidar device according to claim 8, characterized in that, The calculation of clkn's jitter time includes: Obtain the clock signal from the main high-speed operating clock clkn; Clkn enters the carry chain, Clkn samples the carry chain result, and obtains multiple carry chain results of clkn; Calculate the average of the carry chain results for multiple clkn operations; Clkn's clock jitter is the difference between the result of each carry chain and the average value.