Methods, apparatus, equipment, and storage media for building FPGA chips and their top-level netlists.

Abstract

This invention relates to the field of FPGA, and particularly to an FPGA chip and a method, apparatus, device, and storage medium for constructing its top-level netlist. The method includes: acquiring a preset model file; integrating at least one lowest-level logic unit into a basic logic unit based on the model file; integrating the at least one basic logic unit and a configuration memory into a grid cell; arranging multiple grid cells vertically to integrate them into a logic sequence cell; arranging multiple logic sequence cells horizontally to integrate them into a logic resource region cell; and arranging multiple logic resource region cells in an array to obtain a top-level netlist. Through the above method, the layout of the FPGA top-level netlist of this invention is reasonable and meets the requirements of large-scale FPGA chips.

Description

Technical Field

[0001] This invention relates to the field of FPGA, and in particular to an FPGA chip and a method, apparatus, device, and storage medium for constructing the top-level netlist of the same. Background Technology

[0002] FPGA (Field-Programmable Gate Array) is a further development based on programmable devices such as PAL (Programmable Array Logic) and CPLD (Complex Programmable Logic Device). It emerged as a semi-custom circuit in the field of Application-Specific Integrated Circuits (ASICs), addressing the shortcomings of custom circuits while overcoming the limited gate count of traditional programmable devices.

[0003] As process nodes continue to advance, higher demands are placed on the system integration, programmable resources, and device scale of FPGAs. Due to the complexity of the logic netlist architecture, the construction process is not only cumbersome but also prone to errors. Therefore, a grid system is constructed to standardize the arrangement of various devices. A grid system, at the device level, utilizes the regularity of the architecture to uniformly divide a 2D logic grid system, with each device assigned to a unique logic grid. Existing FPGA architectures, from bottom to top, include: basic logic units, grid units, logic sequence units, and top-level modules. Grid units are arranged vertically to form logic sequence units, and logic sequence units are arranged horizontally to form the top-level netlist. As device scale increases, since the height of the logic sequence units is related to the frame length of the bitstream, changing the frame length significantly increases the complexity of the entire system. To maintain a constant frame length, the only option is to increase the number of logic sequence units of the same height horizontally, resulting in a unidirectional expansion. Furthermore, with larger device scales, the top-level netlist exhibits an unreasonable layout where it is very long horizontally and very short vertically.

[0004] Therefore, there is an urgent need in the field for an FPGA chip and a method, apparatus, device, and storage medium for building its top-level netlist to solve the above problems. Summary of the Invention

[0005] Based on this, the present invention provides a method, apparatus, device, and storage medium for building an FPGA chip and its top-level netlist, so as to make the layout of the FPGA top-level netlist more reasonable and meet the requirements of FPGA chips with larger device scale.

[0006] To solve the above technical problems, one technical solution adopted by the present invention is: to provide a method for constructing a top-level netlist for an FPGA, comprising:

[0007] Obtain a preset model file, and integrate at least one lowest-level logic unit into a basic logic unit based on the model file;

[0008] Integrate at least one of the basic logic units and the configuration memory into a grid cell;

[0009] Multiple grid units are arranged vertically and integrated into a logical sequence unit;

[0010] Multiple logical sequence units are arranged horizontally and integrated into a logical resource area unit;

[0011] Multiple logical resource region units are arranged in an array and integrated to obtain a top-level netlist.

[0012] Preferably, the heights of the plurality of logical sequence units are consistent.

[0013] Preferably, after arranging the multiple logical resource region units in an array and integrating them to obtain the top-level netlist, the method further includes:

[0014] Verify each unit in the order of the basic logic unit, the grid unit, the logic sequence unit, and the logic resource area unit to see if they match the model file.

[0015] Preferably, the top-level netlist includes multiple horizontally arranged logical resource area units and multiple vertically arranged logical resource area units.

[0016] Preferably, the model file includes the basic logical units, the grid units, the logical sequence units, and the connections and layouts within and between the logical resource area units.

[0017] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is: providing an apparatus for building an FPGA top-level netlist, comprising:

[0018] The first integration module is used to obtain a preset model file and integrate at least one lowest-level logic unit into a basic logic unit according to the model file.

[0019] The second integration module is used to integrate at least one of the basic logic units and the configuration memory into a grid unit;

[0020] The third integration module is used to arrange multiple grid units vertically and integrate them into a logical sequence unit;

[0021] The fourth integration module is used to arrange multiple logical sequence units horizontally and integrate them into a logical resource area unit;

[0022] The fifth integration module is used to arrange multiple logical resource area units in an array and integrate them to obtain a top-level netlist.

[0023] Preferably, the FPGA top-level netlist building device further includes:

[0024] The verification module is used to verify whether each unit matches the model file in the order of the basic logic unit, the grid unit, the logical sequence unit, and the logical resource area unit.

[0025] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is to provide an FPGA chip, wherein the top-level netlist of the FPGA chip is made by the above-mentioned method for building the top-level netlist of the FPGA.

[0026] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is to provide a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the above-mentioned method for building the FPGA top-level netlist.

[0027] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is to provide a computer-readable storage medium storing a program file, wherein the program file, when executed by a processor, implements the steps of the above-mentioned FPGA top-level netlist construction method.

[0028] The beneficial effects of this invention are: the FPGA top-level netlist construction method of this invention constructs the FPGA top-level netlist according to the hierarchy of basic logic unit - grid unit - logic sequence unit - logic resource area unit - top-level netlist, ensuring high reliability, verifiability, and easy iteration of system integration. The layout of the top-level netlist constructed by this method is more reasonable, meeting the requirements of FPGA chips with larger device scale, and providing a new method and specification for constructing top-level netlists for those skilled in the art. Attached Figure Description

[0029] Figure 1 This is a flowchart illustrating the method for constructing the FPGA top-level netlist according to an embodiment of the present invention.

[0030] Figure 2 This is a schematic diagram of the structure of the FPGA top-level netlist building device according to an embodiment of the present invention;

[0031] Figure 3 This is a schematic diagram of the structure of a computer device according to an embodiment of the present invention;

[0032] Figure 4 This is a schematic diagram of the structure of a computer storage medium according to an embodiment of the present invention. Detailed Implementation

[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0034] The terms "first," "second," and "third" used in this invention are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this invention are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0035] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0036] Figure 1 This is a flowchart illustrating the method for constructing the FPGA top-level netlist according to the first embodiment of the present invention. It should be noted that if substantially the same result is achieved, the method of the present invention is not necessarily identical. Figure 1The illustrated process sequence is limited. This method is based on a grid system to build a top-level netlist. Utilizing the regularity of the grid system architecture, a 2D logic grid system is uniformly divided, and various devices / units are assigned and placed on unique logic grid points.

[0037] like Figure 1 As shown, the method includes the following steps:

[0038] Step S101: Obtain a preset model file, and integrate at least one of the lowest-level logic units into a basic logic unit based on the model file.

[0039] In step S101, the lowest-level logic unit (Prim device) includes at least one unit electronic device, which can be a register, NAND gate, or NOR gate. At least one lowest-level logic unit integrates a basic logic unit (Grid device), and generally multiple lowest-level logic units integrate a basic logic unit. Basic logic units include, but are not limited to: programmable interconnects (signal routing block, SRB), programmable logic modules (CLMs), arithmetic units (APMs), etc. The basic logic units integrated in this step are the smallest units that make up the top-level netlist of the FPGA.

[0040] For example, multiple multiplexers (mux) are used to integrate programmable interconnects (SRB); multiple lookup tables (LUTs) are used to integrate programmable logic blocks (CLMs). There are many types of basic logic units on actual FPGA chips. Two of them are listed here.

[0041] It should be noted that the model file is a pre-configured file. The model file includes the attribute information and connection relationship information of each unit in the FPGA, that is, the internal connections and layout of the lowest level logic unit, basic logic unit, grid unit, logic sequence unit, and logic resource area unit. Specifically, hardware description languages ​​such as Verilog and VHDL can be used to construct the model file.

[0042] Step S102: Integrate at least one basic logic unit and configuration memory into a grid cell.

[0043] In step S102, a grid device is a hardware module formed by at least one basic logic unit (Grid device) and a configuration memory (CRAM device). Each grid device corresponds to a logic point in the grid system. Different functions are achieved by integrating different grid devices. In an optional embodiment, a grid device consists of several basic logic units and several configuration memories. The configuration memory is a basic logic unit used to store configuration points; it is a special type of basic logic unit and does not contain user-programmable resources. Grid devices include, but are not limited to, programmable interconnects (SRB tiles) at the grid device level and programmable logic blocks (CRAM tiles) at the grid device level.

[0044] For example, a single grid-level programmable interconnect (SRB tile) can be integrated using two programmable interconnects (SRBs), long wire drivers (LWDs), and configuration memory (CRAM devices); a single grid-level programmable logic block (CLM tile) can be integrated using four programmable logic blocks (CLMs), logic switch blocks (LSBs), and configuration memory (CRAM devices). In reality, there are many types of grid cells; only two are listed here.

[0045] Step S103: Arrange multiple grid units vertically to integrate them into a logical sequence unit.

[0046] In step S103, multiple grid cells are arranged vertically to form a new layer, called a logic column. During the vertical integration of the grid cells, to ensure the overall structure of the FPGA chip is neat, each logic column has the same height. This also facilitates the generation of the bitstream file. Therefore, the height of the logic column is a common multiple of the cell heights.

[0047] For example: a programmable interconnect (SRB) at the level of 48 grid cells is used to form a programmable interconnect (SRB) at the level of a logical sequence cell; a programmable logic block (CLM) at the level of 48 grid cells is used to form a programmable logic block (CLM) at the level of a logical sequence cell; an arithmetic operation unit (APM) at the level of 24 grid cells is used to form an arithmetic operation unit (APM) at the level of a logical sequence cell; and a dedicated static random access memory (DRM36K) at the level of 12 grid cells is used to form a dedicated static random access memory (DRM36K) at the level of a logical sequence cell.

[0048] Step S104: Arrange multiple logical sequence units horizontally and integrate them into a logical resource area unit.

[0049] In step S104, a new layer, called a fabric region, is obtained by horizontally arranging different types and quantities of logical sequence units according to a preset rule. The resulting fabric region varies depending on the horizontal arrangement of the logical sequence units. It is understandable that since the fabric region is obtained by horizontally arranging logical sequence units, and the logical sequence units have the same height, the fabric region units also have the same height.

[0050] It should be noted that logic resource area units can be composed entirely of traditional FPGA resources, such as programmable interconnects (SRBs), programmable logic blocks (CLMs), and arithmetic units (APMs); they can also integrate independent IP modules, such as Ethernet modules (EMACs) and expansion modules (PCIe), on top of traditional FPGA resources; and they can be further integrated with I / O modules, etc. The above three points are just examples; logic resource area units can be flexibly constructed according to actual needs.

[0051] For example, five different types of logical resource area units are formed by horizontally arranging the programmable interconnects (srbcolumn), programmable logic blocks (clm column), arithmetic operation units (apm column), and dedicated static random access memory (drm36k column) at the logical sequence unit level as composed in step S103.

[0052] Step S105: Arrange multiple logical resource area units in an array and integrate them to obtain the top-level netlist.

[0053] In step S105, the array arrangement includes both horizontal and vertical arrangements, forming an N*M (N≥1, M≥1) array distribution. In an optional embodiment, the top-level netlist (architecture) includes multiple horizontally arranged logical resource area units and multiple vertically arranged logical resource area units.

[0054] For example, by using the five different types of logic resource area units integrated in step S104 to expand horizontally and vertically respectively, a 4*5 array is formed to obtain the top-level netlist of the FPGA.

[0055] Understandably, the top-level netlist is ultimately composed of several grid cells and the interconnections between them. Under the specification of the grid system, the grid cells are arranged in 2D.

[0056] Furthermore, after step S105, the method for building the FPGA top-level netlist in this embodiment further includes:

[0057] S106. Verify whether each unit matches the model file in the order of basic logic unit, grid unit, logic sequence unit, and logic resource area unit.

[0058] In step S106, the verification content for whether each unit matches the model file includes: whether the arrangement order of each unit is consistent with the preset, whether the internal and external interconnections of each unit are accurate, and whether each unit can achieve the preset function.

[0059] The FPGA top-level netlist construction method of this invention constructs the FPGA top-level netlist according to the hierarchy of basic logic unit - grid unit - logic sequence unit - logic resource region unit - top-level netlist, ensuring high reliability, verifiability, and ease of iteration in system integration. The top-level netlist constructed by this method has a more reasonable layout, meeting the requirements of larger-scale FPGA chips and solving the problem that existing top-level netlists are difficult to implement reasonably when designing large-scale FPGA chips. This provides a new method and specification for constructing top-level netlists for those skilled in the art.

[0060] Figure 2 This is a schematic diagram of the FPGA top-level netlist construction device according to an embodiment of the present invention. Figure 2 As shown, the FPGA top-level netlist building device 20 includes: a first integration module 21, a second integration module 22, a third integration module 23, a fourth integration module 24, and a fifth integration module 25.

[0061] The first integration module 21 is used to obtain a preset model file and integrate at least one bottom-level logic unit into a basic logic unit based on the model file.

[0062] The second integration module 22 is used to integrate at least one basic logic unit and configuration memory into a grid cell.

[0063] The third integration module 23 is used to arrange multiple grid units vertically and integrate them into a logical sequence unit.

[0064] The fourth integration module 24 is used to arrange multiple logical sequence units horizontally and integrate them into a logical resource area unit.

[0065] The fifth integration module 25 is used to arrange multiple logical resource area units in an array and integrate them to obtain a top-level netlist.

[0066] Furthermore, the FPGA top-level netlist building device 20 of this embodiment of the invention also includes a verification module 26, which is used to verify whether each unit matches the model file in the order of basic logic unit, grid unit, logic sequence unit, and compiled resource area unit.

[0067] This invention also provides an FPGA chip, the top-level netlist of which is constructed using the aforementioned method for constructing an FPGA top-level netlist. For specific construction methods, please refer to the limitations regarding the method for constructing an FPGA top-level netlist; these will not be repeated here.

[0068] Please see Figure 3 , Figure 3 This is a schematic diagram of the structure of a computer device according to an embodiment of the present invention. Figure 3 As shown, the computer device 30 includes a processor 31 and a memory 32 coupled to the processor 31. The memory 32 stores a computer program for implementing the FPGA top-level netlist construction method described in any of the above embodiments. When the processor 31 executes the computer program, it implements the FPGA top-level netlist construction method described in any of the above embodiments.

[0069] The processor 31 can also be referred to as a CPU (Central Processing Unit). The processor 31 may be an integrated circuit chip with signal processing capabilities. The processor 31 can also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. A general-purpose processor can be a microprocessor or any conventional processor.

[0070] See Figure 4 , Figure 4This is a schematic diagram of the structure of a computer storage medium 40 according to an embodiment of the present invention. The computer storage medium 40 of this embodiment stores a program file 41 capable of implementing all the above-described methods. The program file 41 can be stored in the computer storage medium in the form of a software product, including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned computer storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks, or terminal devices such as computers, servers, mobile phones, and tablets.

[0071] In the embodiments provided by this invention, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0072] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0073] The above are merely embodiments of the present invention and do not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method for constructing a top-level netlist for an FPGA, characterized in that, include: Obtain a preset model file, and integrate at least one lowest-level logic unit into a basic logic unit based on the model file; Integrate at least one of the basic logic units and the configuration memory into a grid cell; Multiple grid units are arranged vertically and integrated into a logical sequence unit; Multiple logical sequence units are arranged horizontally and integrated into a logical resource area unit, with each logical resource area unit having the same height. The multiple logical resource region units are arranged in a column array and integrated to obtain a top-level netlist; The logical resource area unit is obtained by horizontally arranging different types and quantities of logical sequence units according to a preset rule. The logical sequence unit includes at least one of the following: a programmable interconnect, a programmable logic block, an arithmetic operation unit, or a dedicated static random access memory.

2. The method for constructing the FPGA top-level netlist according to claim 1, characterized in that, The multiple logical sequence units are highly consistent.

3. The method for constructing the FPGA top-level netlist according to claim 1, characterized in that, After arranging the multiple logical resource region units in an array and integrating them to obtain the top-level netlist, the process further includes: Verify each unit in the order of the basic logic unit, the grid unit, the logic sequence unit, and the logic resource area unit to see if they match the model file.

4. The method for constructing the FPGA top-level netlist according to claim 1, characterized in that, The top-level netlist includes multiple horizontally arranged logical resource area units and multiple vertically arranged logical resource area units.

5. The method for constructing the FPGA top-level netlist according to claim 1, characterized in that, The model file includes the basic logical units, the grid units, the logical sequence units, and the connections and layouts within and between the logical resource area units.

6. A device for constructing a top-level netlist for an FPGA, characterized in that, include: The first integration module is used to obtain a preset model file and integrate at least one lowest-level logic unit into a basic logic unit according to the model file. The second integration module is used to integrate at least one of the basic logic units and the configuration memory into a grid unit; The third integration module is used to arrange multiple grid units vertically and integrate them into a logical sequence unit; The fourth integration module is used to arrange multiple logical sequence units horizontally and integrate them into a logical resource area unit, wherein each logical resource area unit has the same height. The fifth integration module is used to arrange multiple logical resource area units in an array and integrate them to obtain a top-level netlist; The logical resource area unit is obtained by horizontally arranging different types and quantities of logical sequence units according to a preset rule. The logical sequence unit includes at least one of the following: a programmable interconnect, a programmable logic block, an arithmetic operation unit, or a dedicated static random access memory.

7. The apparatus for building an FPGA top-level netlist according to claim 6, characterized in that, The FPGA top-level netlist building device also includes: The verification module is used to verify whether each unit matches the model file in the order of the basic logic unit, the grid unit, the logical sequence unit, and the logical resource area unit.

8. An FPGA chip, characterized in that, The top-level netlist of the FPGA chip is constructed by the method for constructing the top-level netlist of the FPGA as described in any one of claims 1-5.

9. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method for building the FPGA top-level netlist as described in any one of claims 1-5.

10. A computer-readable storage medium storing a program file, characterized in that, When the program file is executed by the processor, it implements the steps of the FPGA top-level netlist construction method as described in any one of claims 1-5.

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