A 3D packaging system and computational method for wafer reconstruction of optical chips

Abstract

This invention relates to the field of optical-electric hybrid packaging technology, specifically to a 3D packaging system and computing method for wafer reconstruction of optical chips. The 3D packaging system enables large-scale high-speed computation. The 3D packaging system includes: a printed circuit board, a metal frame, and an optical computing layer arranged sequentially. The optical computing layer includes: an optical computing region comprising: a first optical chip with its first optical port adjacent to a first side region for connection to an optical fiber; a second optical chip optically connected to the first optical chip; and an electrical transmission layer with an electrical transmission region corresponding to the optical computing region, comprising: multiple electrical chips; each electrical chip having a first electrical channel and a second electrical channel, the first electrical channel connected to a converter, and the second electrical channel connected to an adjacent electrical chip. This invention provides a 3D packaging system for the large-scale joint packaging of multiple optical and electrical chips, thereby facilitating the realization of ultra-large-scale optical computation.

Description

[0001] Divisional application This application is a divisional application of Chinese invention patent application CN202511974073.5, filed on December 25, 2025, entitled "A 3D Packaging System and Optical Computing Method for Optical Computing". Technical Field

[0002] This invention relates to the field of large-scale optoelectronic hybrid packaging technology, specifically to a 3D packaging system and calculation method for wafer reconstruction of optical chips. Background Technology

[0003] With the development of information technology, increasingly higher requirements are being placed on the transmission rate, latency, and energy efficiency of optical modules. The Chip Package Optimization (CPO) structure, which encapsulates both a Photonic Integrated Circuit (PIC) and an Electronic Integrated Circuit (EIC) within the same package, is becoming increasingly widely used.

[0004] Existing optoelectronic packaging solutions include Chip on Board (COB) integration and Through Silicon Via (TSV) integration. COB integration involves assembling discrete electrical and optical chips onto a substrate using wire bonding or flip-chip bonding, with interconnection achieved through substrate wiring. This solution is inexpensive but suffers from poor high-speed interconnection performance between electrical and optical chips. TSV integration, on the other hand, involves creating through silicon vias within the optical or electrical chips and filling them with conductive material, achieving three-dimensional stacked packaging of the optical and electrical chips, resulting in high interconnection speeds.

[0005] However, with the increasing demand for large-scale optical computing, the existing packaging scale is no longer sufficient to solve the problem. Therefore, there is a need for a packaging application technology that can further scale up. Summary of the Invention

[0006] The purpose of this invention is to provide a 3D packaging system that partially solves or alleviates the above-mentioned shortcomings in the prior art, and provides a new solution for optoelectronic hybrid packaging.

[0007] To solve the aforementioned technical problems, the present invention specifically adopts the following technical solution: A first aspect of the present invention is to provide a 3D packaging system for optical computing, comprising: Printed circuit boards; A metal frame is disposed on the printed circuit board; the metal frame is provided with a plurality of conductive channels, and one end of each conductive channel is connected to a conductive interface of the printed circuit board. An optical computing layer disposed on the metal frame, the optical computing layer comprising: At least one optical computing region, wherein the optical computing region comprises: n*n optical chips, wherein each optical chip has a through-silicon via (TSV), and the other end of a conductive channel is connected to the TSV. The n*n optical chips include: At least one first optical chip, and the first optical chip has a first optical port; At least one second optical chip, and the second optical chip has a second optical port; The first optical chip is disposed in the first side area of ​​the 3D packaging system, wherein the first optical port is disposed adjacent to the first side area, thereby exposing the first optical port so that it can be connected to the fiber array; The second optical chip is optically connected to the first optical chip through the second optical port; An electrical transmission layer, comprising: at least one electrical transmission region disposed corresponding to the optical computing region, and the electrical transmission region comprising: a plurality of electrical chips; In this embodiment, at least one electrical chip is provided with a first electrical channel and at least one second electrical channel, wherein the first electrical channel is connected to a converter and the second electrical channel is connected to another adjacent electrical chip; The converter is located in the second side area of ​​the 3D packaging system, so that the converter and the fiber array are located in different areas.

[0008] In some embodiments, at least two of the electrical transmission regions are electrically connected.

[0009] In some embodiments, in one optical computing region, at least one first optical chip and at least one second optical chip are encapsulated as a whole by a first adhesive layer; and / or, in one electrical transmission region, a plurality of electrical chips are encapsulated as a whole by a second adhesive layer.

[0010] In some embodiments, the metal frame includes: A first metal frame and a second metal frame are arranged sequentially; wherein, the first metal frame is provided with a plurality of first conductive channels, and the second metal frame is provided with second conductive channels corresponding to the first conductive channels; Wherein, the first surface of the first metal frame and the first surface of the second metal frame are disposed opposite to each other, and the second surface of the first metal frame is disposed facing the printed circuit board, so that the first conductive channel is connected to the conductive interface. The second metal frame has at least one mounting area on its second side corresponding to the optical computing area, and the mounting area is used to mount the corresponding optical chip.

[0011] In some embodiments, the converter is disposed on the electrical transmission layer, or the converter is disposed on the metal frame.

[0012] In some embodiments, the first side area and the second side area are different side areas.

[0013] The present invention also provides an optical computing method, which can be applied to the 3D packaging system in any of the above embodiments. Correspondingly, the method includes: S100, acquire at least one optical computing task; S101, mark the optical chips that meet the preset operating rules as candidate chips; S102, at least one of the candidate chips is selected as the execution chip, and the execution chip is used to execute at least one of the optical computing tasks; S103, Obtain the exception level of the execution chip; S104, when the anomaly level is greater than the preset first anomaly level, the execution chip is marked as a sleep chip, and a replacement chip is selected from the remaining candidate chips to continue executing the corresponding optical computing task; The step of selecting a replacement chip from the remaining candidate chips includes: Obtain the total priority of the candidate chip; the total priority is defined by the transmission distance of the optical channel and auxiliary information, the transmission distance is the distance between the candidate chip and the corresponding fiber array, and the auxiliary information includes: temperature, health status or functional matching degree; The replacement chip is selected from the candidate chips based on the total priority.

[0014] In some embodiments, it also includes: S105, when the anomaly level is greater than a preset second anomaly level, and the anomaly level is less than or equal to the first anomaly level, then the following steps are executed: The optical computing task is divided into at least two sub-tasks; One of the sub-tasks is executed using the currently described execution chip, and at least one replacement chip is selected from the remaining candidate chips to execute the remaining sub-tasks.

[0015] In some embodiments, the step of obtaining the total priority of the candidate chip includes: A first priority is determined based on the transmission distance; wherein, the greater the transmission distance, the lower the first priority. A second priority is determined based on the auxiliary information; The total priority is determined based on the first priority and the second priority.

[0016] In some embodiments, the operating rules include: requiring the temperature of the candidate chip to be lower than a preset temperature threshold, or requiring the error reporting frequency of the candidate chip in historical operating periods to be lower than a preset frequency.

[0017] Beneficial technical effects: This invention provides a layer arrangement scheme in which a printed circuit board, a metal frame, an optical computing layer, and an electrical transmission layer are arranged in sequence. The metal frame is positioned between the circuit board and the optical computing layer. This not only alleviates the warpage problem between the optical computing layer and the electrical transmission layer in multi-chip applications to some extent, but also, while carrying and conducting electrical signals, provides some heat dissipation for the optical computing layer located in the middle region, thus relieving the heat dissipation pressure on the optical computing layer when performing large-scale data computation.

[0018] Preferably, the spatial design of the optical computing layer and the electrical transmission layer is such that the protruding areas of the optical computing layer and the metal frame are located on different sides, so that the fiber array 110 and the converter 109 are located on different sides. Therefore, the signal transmission channels of the optical chip and the electrical chip are less likely to interfere with each other in space.

[0019] Preferably, the present invention uses a combination connection method in which multiple optical chips share a light source (such as shared optical fiber) and multiple electrical chips share a connector.

[0020] Furthermore, during multi-chip operation, the chip's calling priority is determined by combining its connection relationship with the shared light source (such as communication distance) and the chip's personalized information (such as auxiliary information). Therefore, chips that may pose potential problems (i.e., chips with higher anomaly levels) are promptly replaced or maintained based on their calling priority.

[0021] Specifically, this invention provides a fault handling method that allows for optimal switching between overall and local tasks. In this coordinated approach of overall and local switching, a chip with potential for failure is not immediately discarded but instead assigned a lightweight task matching its current capabilities. While the overall system performance may be slightly reduced, core services remain uninterrupted, providing users with valuable buffer time.

[0022] From another perspective, this switching mode can, to some extent, keep the core computing system (such as the area initially selected for optical computing chips) in a relatively stable state (such as an enabled state). Therefore, in the event of a fault, it minimizes the reliance on backup resources.

[0023] Furthermore, this switching mode allows for the restricted use of redundant configuration resources, which also helps to reduce the requirements for chip performance or quality in redundant configuration resources, thereby reducing the cost of redundant configuration. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. The elements or parts in the drawings are not necessarily drawn to scale. Obviously, the drawings described below are some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0025] Figure 1 This is a schematic diagram of the structure of a hybrid packaging system in an exemplary embodiment of the present invention; Figure 2 This is a schematic diagram of the hybrid packaging system in another exemplary embodiment of the present invention; Figure 3 This is a top view of a hybrid packaging system according to an exemplary embodiment of the present invention; Figure 4 This is a schematic planar diagram of an exemplary wafer reconstruction according to the present invention; Figure 5a for Figure 4 A schematic diagram of an exemplary side-view architecture of the embodiment shown; Figure 5b for Figure 4 Another exemplary side architecture diagram of the illustrated embodiment; Figure 5c This is a schematic diagram of the structure of the second metal frame in an exemplary embodiment; Figure 6 This is a schematic planar diagram of another exemplary wafer reconstruction according to the present invention; Figure 7 for Figure 6 The side view of the embodiment shown is a schematic diagram. Figure 8 This is a schematic diagram of the method flow in an exemplary embodiment of the present invention.

[0026] Reference numerals: 101, Printed circuit board; 102, Substrate; 103, Optical computing layer; 1031, Optical chip; 1031a, First optical chip; 1031b, Second optical chip; 1032, First adhesive layer; 1033, Through-silicon via (TSV); 1034, Second metal frame; 10341, Mounting area; 104, Electrical transport layer; 1041, Electrical chip; 1041a, First electrical chip; 1041b, Second electrical chip; 1042, Second adhesive layer; 104a, SOC chip; 104b, DRAM chip; 104c, Auxiliary chip; 105, First optical port; 106, First metal frame; 1061, Conductive channel; 107, Bonding structure; 108, Heat dissipation layer; 109, Connector; 110, Fiber optic array; 111, Retransmission layer; L1, First electrical channel; L2, Second electrical channel. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0028] In this document, suffixes such as "module," "part," or "unit" used to denote elements are used only for the purpose of illustrative purposes and have no specific meaning in themselves. Therefore, "module," "part," or "unit" may be used interchangeably.

[0029] In this document, the terms "upper," "lower," "inner," "outer," "front," "rear," "one end," and "the other end," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the present invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0030] In this document, unless otherwise explicitly specified and limited, the terms "installed," "equipped with," "connected," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0031] In this document, "and / or" includes any and all combinations of one or more of the listed related items.

[0032] In this article, "multiple" means two or more, that is, it includes two, three, four, five, etc.

[0033] As used in this specification, the term "about" typically means + / -5% of the value, more typically + / -4% of the value, more typically + / -3% of the value, more typically + / -2% of the value, even more typically + / -1% of the value, and even more typically + / -0.5% of the value.

[0034] In this specification, certain embodiments may be disclosed in a range-bound format. It should be understood that this "range-bound" description is merely for convenience and brevity and should not be construed as a rigid limitation on the disclosed range. Therefore, the description of a range should be considered as having specifically disclosed all possible subranges and the individual numerical values ​​within those ranges. For example, a description of the range 1-6 should be considered as having specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., and the individual numbers within those ranges, such as 1, 2, 3, 4, 5, and 6. This rule applies regardless of the breadth of the range.

[0035] Optical chips (or photonic chips): Optical chips are chips that integrate optoelectronic devices and play a crucial role in communication and information processing. Their basic structure includes photoelectric conversion devices, electronic devices, and optoelectronic interconnects. The photoelectric conversion devices convert optical signals into electrical signals, the electronic devices process and control the electrical signals, and the optoelectronic interconnects enable high-speed photoelectric signal transmission. Optical chips have advantages such as small size, low power consumption, and strong anti-interference capabilities, which can greatly improve the speed and efficiency of communication and information processing, and have broad application prospects in communication, computers, fiber optic sensing, and other fields.

[0036] Electrical chips (or electronic chips): Electrical chips mainly refer to traditional integrated circuit chips, which are composed of electronic devices such as logic gates, amplifiers, and clock circuits. The main function of these electronic devices is to process and control electrical signals. Unlike optical chips, electrical chips focus on the processing of electrical signals and are the core components for electronic devices to realize various functions.

[0037] Bonding structure: Chip bonding structure is a structural method that connects multiple chips (i.e., optical chips or electrical chips) or wafers together. It is a key technology for realizing chip stacking and interconnection. It can combine chips with different functions, improving chip integration and performance. The bonding process requires ensuring precise alignment between chips, while monitoring parameters such as surface roughness, surface cleanliness, and flatness to guarantee the quality and stability of the bonding. Common bonding methods include chip-to-wafer bonding and wafer-to-wafer bonding. In advanced packaging technologies such as TSV, the bonding structure is an indispensable part. For example, the bonding structure can be solder balls made of metal materials.

[0038] TSV (Through Silicon Via) is a vertical interconnect structure that passes through a silicon wafer or chip. It achieves vertical electrical interconnection by creating vertical connections between chips or wafers and filling them with conductive materials such as copper, tungsten, or polysilicon. Vertical interconnection via TSVs can reduce interconnect length, signal delay, and capacitance / inductance, enabling low-power, high-speed communication between chips, increasing bandwidth, and facilitating miniaturization of device integration.

[0039] "SOC chip": System on Chip (SOC), also known as a system-on-a-chip, is an integrated circuit with a specific purpose, containing a complete system and all embedded software. In a preferred embodiment, the SOC chip is the core chip integration of an information system, integrating key system components onto a single chip.

[0040] "Auxiliary chip": Also known as "auxiliary die" or simply "die," in the semiconductor industry, an auxiliary die refers to an unpackaged bare chip cut from a wafer. An auxiliary die contains a complete integrated circuit but lacks a casing and pin connections, directly corresponding to an independent functional unit on the wafer. As a key intermediate product in chip manufacturing, it carries a complete electronic circuit pattern and is formed after multiple precise processes such as photolithography, etching, and doping.

[0041] Alternatively, a die refers to a single, fully functional integrated circuit chip (IC Chip) on a wafer, also known as a die. Specifically, a die can refer to a small square that is cut (diced) and separated from the wafer after front-end manufacturing processes.

[0042] "DRAM": Also known as "DRAM chip", DRAM stands for Dynamic Random Access Memory, a type of semiconductor memory. Its main working principle is to use the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0.

[0043] PCB (Printed Circuit Board): A PCB is an important electronic component, serving as the support for electronic components and the carrier for their electrical interconnection. It is typically manufactured using electronic printing techniques.

[0044] Wafer: refers to the silicon wafer used to manufacture silicon semiconductor circuits. In other words, a wafer is the basic substrate material for semiconductor manufacturing, usually a thin circular sheet made of high-purity single-crystal silicon (sometimes gallium arsenide, silicon carbide, etc.).

[0045] Molding (or encapsulation) refers to the process of injecting or pressing molten molding compound (such as epoxy molding compound (EMC)) into a mold cavity containing a chip, allowing it to flow, fill, and solidify to form a molding layer (or adhesive layer) on the outside of the chip. For example, molding multiple chips can encapsulate them into a single unit. Specifically, multiple dies can be repackaged into a wafer through molding.

[0046] See Figures 1-7 As shown, the present invention provides a 3D packaging system for optical computing.

[0047] Example 1 This invention provides a 3D packaging system, comprising: Printed circuit board 101; A metal frame is disposed on the printed circuit board 101; the metal frame is provided with a plurality of conductive channels, and one end of the conductive channel is connected to the conductive interface of the printed circuit board. The optical computing layer 103 disposed on the metal frame includes: At least one optical computing region, wherein the optical computing region comprises: n*n optical chips, wherein each optical chip has a through-silicon via (TSV), and the other end of a conductive channel is connected to the TSV. The n*n optical chips include: At least one first optical chip 1031a, and the first optical chip 1031a has a first optical port 105; At least one second optical chip 1031b, and the second optical chip 1031b has a second optical port; The first optical chip is disposed in the first side area of ​​the 3D packaging system, wherein the first optical port is disposed adjacent to the first side area, thereby exposing the first optical port 105 so that it can be connected to the fiber array 110. The second optical chip 1031b is optically connected to the first optical chip 1031a through the second optical port; An electrical transmission layer 104 is provided, comprising at least one electrical transmission region corresponding to the optical computing region, and the electrical transmission region comprising a plurality of electrical chips 1041. At least one electrical chip is provided with a first electrical channel L1 and at least one second electrical channel L2, wherein the first electrical channel L1 is connected to the converter 109 and the second electrical channel L2 is connected to another adjacent electrical chip; The converter 109 is disposed in the second side area of ​​the packaging system so as to place the converter and the fiber array in different areas.

[0048] For example, in some embodiments, see Figure 6 As shown, the electrical transmission area includes: a first electrical chip 1041a, which can be directly connected to the converter 109; and a second electrical chip 1041b, which is connected to the converter through at least one electrical chip.

[0049] For example, see Figure 4 As shown, multiple optical / electrical chips are arranged sequentially to form a matrix or polygonal geometric shape on a plane. The converter and fiber optic array can be positioned on different sides of this geometric area to mitigate potential spatial conflicts caused by multiple intersecting lines.

[0050] like Figure 4 As shown, multiple optical chips can be arranged in a matrix structure, with converters arranged on three sides of the rectangle and an optical fiber array arranged on the other side.

[0051] Preferably, in this embodiment, the fiber optic array adopts a one-to-many configuration. Specifically, the optical chips located at the edge can be directly connected to the fiber optic array to introduce external light sources. The remaining optical chips located on the inner side can communicate optically through the optical channels between the chips.

[0052] The longer the optical transmission distance in the optical chip, the greater the loss that needs to be considered, meaning that the power of the input optical signal needs to be increased accordingly.

[0053] To address the demand for large-scale optical computing, this invention provides a solution that enables the hybrid packaging of a large number of optical and electrical chips.

[0054] It should be noted that with the increasing number of optical and electrical chips, the difficulty of chip packaging and application has increased significantly. For example, the difficulty of circuit layout and heat dissipation increases, and the risk of chip warpage also increases.

[0055] To address this, the present invention employs a multi-layered collaborative design to reduce heat dissipation and space conflicts while increasing the number of chips in 3D packaging.

[0056] Specifically, this embodiment adopts a layer layout scheme in which a printed circuit board, a metal frame, an optical computing layer, and an electrical transmission layer are arranged in sequence. The metal frame is positioned between the circuit board and the optical computing layer. This not only alleviates the warpage problem between the multi-chip optical computing layer and the electrical transmission layer to some extent, but also, while carrying and conducting electrical signals, provides some heat dissipation for the optical computing layer located in the middle region, thus relieving the heat dissipation pressure on the optical computing layer when performing large-scale data computation.

[0057] At the same time, from the perspective of space optimization, with Figure 7 For example, this embodiment uses a metal frame (such as a first metal frame 106), an optical computing layer 103, and an electrical transmission layer 104 arranged sequentially. The optical computing layer 103 is disposed on the metal frame, and at least a portion of the metal frame protrudes from the optical computing layer 103 to accommodate a converter 109 (such as a connector) in the protruding area. Furthermore, the electrical transmission layer 104 can be disposed on the optical computing layer via a retransmission layer 111 (also called a rewiring layer), and at least a portion of the optical computing layer protrudes from the electrical transmission layer 104 to accommodate an optical fiber array 110 in its protruding area.

[0058] The protruding areas of the optical computing layer and the metal frame are positioned on different sides, allowing the fiber optic array 110 and the converter 109 to be located on different sides. Therefore, the signal transmission channels of the optical chip and the electrical chip are less likely to interfere with each other spatially.

[0059] In other words, the optimized arrangement of the multi-layer structure in the vertical and horizontal directions in this embodiment can reduce the pressure of circuit layout during the multi-chip integration process.

[0060] In some embodiments, at least two of the electrical transmission regions are electrically connected.

[0061] Preferably, in some embodiments, a row of optical chips can use a fiber optic array for light source input.

[0062] In some embodiments, any two electrical chips can be directly or indirectly connected. For example, direct connection means that two electrical chips are directly connected by electrical wires. Indirect connection means that one or more electrical chips can be arranged between two electrical chips for signal transmission.

[0063] In some embodiments, in one of the optical computing regions, at least one first optical chip and at least one second optical chip are packaged as a whole by a first adhesive layer 1032.

[0064] Preferably, in this embodiment, wafer reconstruction is performed on the optical chip. Specifically, wafer reconstruction can be performed on a single optical computing area.

[0065] See Figure 7 As shown, a wafer-to-wafer process is preferably used to achieve large-scale hybrid packaging of optical and electrical chips. That is, in this embodiment, multiple electrical chips (corresponding to multiple dies) in an electrical transport region can be packaged into a single unit. In other words, multiple dies can be reconstructed into a wafer using a molding process. Similarly, multiple optical chips in the optical computing region are also reconstructed into a wafer using a molding process. Therefore, the connection between the electrical transport layer and the optical computing layer is achieved using a wafer-to-wafer process.

[0066] Alternatively, in some embodiments, a large optical chip can be directly used in an optical computing area, and multiple dies can be bonded and packaged on the large optical chip.

[0067] See Figure 5a As shown, an optical computing area can include 3*3 optical chips. Furthermore, these nine optical chips can be molded into a single unit.

[0068] In some embodiments, in one of the electrical transmission regions, a plurality of electrical chips are encapsulated as a whole by a second adhesive layer 1042.

[0069] Preferably, in this embodiment, wafer reconstruction can be performed on the electrical chip. Specifically, also using... Figure 7 For example, one optical chip can correspond to at least one electrical chip. For instance, for an optical computing area with 3*3 optical chips, an electrical transmission area consisting of 3*3 electrical chips can be set up, and the 3*3 electrical chips can be packaged into a whole through molding.

[0070] Preferably, such as Figure 5a As shown, in order to achieve large-scale hybrid packaging of optical and electrical chips, the dieto wafer packaging process was adopted.

[0071] Specifically, in this embodiment, multiple optical chips in the optical computing region are reconstructed into a wafer through molding. Multiple electrical chips can then be bonded relatively independently to corresponding areas of the wafer.

[0072] In some embodiments, the converter 109 is disposed on the electrical transmission layer, or the converter 109 is disposed on the metal frame.

[0073] In some embodiments, the first side area and the second side area are different side areas.

[0074] In some embodiments, the retransmission layer may be disposed on the optical computing layer.

[0075] In some embodiments, the retransmission layer may be disposed on the electrical transmission layer.

[0076] For example, in some embodiments, see Figure 5a As shown, converter 109 can be disposed on the retransmission layer.

[0077] Preferably, at least a portion of the optical computing layer protrudes beyond the electrical transmission layer, such that the optical port of the optical chip on at least one side of the optical computing layer protrudes beyond the electrical transmission layer (i.e., is exposed), thereby allowing the optical port to be connected to the fiber optic array. A retransmission layer is further arranged on the optical computing layer, and this retransmission layer, on the one hand, reserves space for the fiber optic array to be led out, and on the other hand, can also protrude beyond the electrical chip layer to accommodate a converter in the protruding area.

[0078] In some embodiments, one or more electrical chips may be stacked on an optical chip.

[0079] In some embodiments, see Figure 5b As shown, the metal frame includes a first metal frame 106, which is disposed between the optical computing layer 103 and the printed circuit board 101. The first metal frame 106 has a conductive channel 1061, one end of which is connected to a conductive interface on the printed circuit board, and the other end is connected to a through-silicon via 1033 disposed on the optical chip.

[0080] Furthermore, in some other embodiments, in order to reduce or mitigate the warpage risk that may occur in large-scale packaging systems while increasing the scale of optical and electrical packaging, the present invention provides an interlayer connection implemented using a bimetallic frame.

[0081] For example, see Figure 5b As shown, the metal frame includes: a first metal frame 106 and a second metal frame 1034 arranged sequentially; wherein, the first metal frame 106 is provided with a plurality of first conductive channels, and the second metal frame 1034 is provided with a second conductive channel corresponding to the first conductive channels; that is, the first conductive channels are connected to form a conductive channel. The first surface of the first metal frame 106 and the first surface of the second metal frame 1034 are disposed opposite each other. The second surface of the first metal frame 106 faces the printed circuit board so that the first conductive channel is connected to the conductive interface. The second surface of the second metal frame faces the optical chip.

[0082] The optical chip can be bonded or attached to the second metal frame 1034. Specifically, the through-silicon via 1033 in the optical chip needs to be connected to the second conductive channel on the second metal frame 1034.

[0083] Preferably, see Figure 5c As shown, the second side of the second metal frame 1034 is provided with at least one mounting area 10341 corresponding to the optical computing area, and the mounting area is used to set the corresponding optical chip.

[0084] For example, in some embodiments, the mounting area refers to the mounting region formed by an inwardly recessed second surface of the second metal frame 1034. Specifically, the optical chip can be bonded to the mounting area using molding compound or adhesive to securely connect the optical chip and the second metal frame.

[0085] Preferably, in this embodiment, the second metal frame and the first metal frame can be detachably connected using a quick-release structure (e.g., through a snap-fit ​​structure).

[0086] In this embodiment, the use of a double-layer metal frame design facilitates the modular disassembly of the 3D packaging system.

[0087] For example, during the packaging process, the optical computing layer and the electrical computing layer can be packaged separately on the second metal frame to form the first module, and the printed circuit board can be packaged on the first metal frame to form the second module. Subsequently, the first and second modules are connected, such as via a quick-release structure. In this embodiment, this modular packaging process simplifies the packaging difficulty at each stage and improves the effective utilization rate of devices / modules. For example, modules with potential faults can be partially replaced to reduce application costs.

[0088] For example, the first module or the second module can be replaced. As another example, smaller modules within the first module (such as a wafer obtained by refactoring multiple dies) can be replaced.

[0089] For example, the second metal frame and the first metal frame can be glued together.

[0090] In this embodiment, the metal frame can actually replace the traditional retransmission layer (such as the RDL layer), see [link to documentation]. Figure 5c As shown, in this case, the optical chip can avoid the need for a rewiring layer. This multi-layer bonding scheme, which eliminates the need for a rewiring layer, can reduce the difficulty of multi-layer packaging to some extent.

[0091] For example, it can reduce the risk of warping caused by an excessive number of chips on a horizontal scale. It can also avoid the routing difficulties associated with large-scale routing in redistribution layers.

[0092] Alternatively, in some embodiments, the first metal frame and the second metal frame can be integrally formed. In other words, the above-mentioned electrical conduction and chip mounting functions can be achieved using a single-layer metal frame.

[0093] Example 2: See Figures 1-3 As shown, the present invention provides a hybrid packaging system (or hybrid packaging scheme) that uses an optical chip as a sandwich layer to stack multiple electrical chips.

[0094] Specifically, see Figure 1 As shown, the hybrid packaging scheme includes: Printed circuit board 101 (PCB board); The upper surface of the printed circuit board 101 (PCB) is provided with a substrate 102 connected by a bonding structure 107. At least one optical chip 1031 is connected and disposed on the upper surface of the substrate 102 by a bonding structure. The optical chip 1031 is provided with a plurality of first conductive vias for realizing the conduction and transmission of electrical signals. Preferably, the first conductive via is a TSV via. The upper surface of the optical chip 1031 is provided with at least one layer of electrical chip 1041, and the at least one layer of electrical chip includes: a plurality of electrical chips arranged at intervals, and a second conductive via is provided on the electrical chip directly connected to the optical chip, the second conductive via being connected to the first conductive via (e.g., by bonding structure).

[0095] For example, in some embodiments, multiple optical chips can be arranged at intervals on the upper surface of the substrate to form a large optical chip. For instance, four or sixteen optical chips can be disposed on the substrate.

[0096] In some embodiments, the optical chip and the electrical chip can cooperate in the data processing as follows: The optical chip can receive externally input optical signals via optical fiber (not shown in the figure) and externally input electrical signals (such as weighting adjustment signals) via a substrate. By modulating the optical signals with these electrical signals, the optical chip can perform calculations on the optical signals. Finally, the calculation results from the optical chip can be processed by an electrical chip, such as data format processing and data storage.

[0097] In some embodiments, at least one layer of electrical chip 1041 includes: a first electrical chip layer. The first electrical chip layer includes a plurality of electrical chips.

[0098] Preferably, in some embodiments, at least one layer of electrical chip includes: A first electrical chip layer is disposed on the upper surface of the optical chip 1031, and the first electrical chip layer includes: a plurality of SOC chips 104a; A second electrical chip layer is disposed on the upper surface of the first electrical chip layer, and the second electrical chip layer includes a plurality of DRAM chips 104b.

[0099] For example, in an exemplary embodiment, the optical chip performs calculations on the externally input optical signal, and the result of the calculations can be transmitted to the SOC chip through a conductive via for further processing (such as format conversion, etc.). The SOC chip can then transfer the processed data to the DRAM chip, which can store the data.

[0100] Furthermore, in some embodiments, at least one layer of electrical chip further includes: The third electrical chip layer is disposed between the first electrical chip layer and the second electrical chip layer, and includes a plurality of auxiliary chips 104c. The auxiliary chips can reduce the design pressure of the SOC chip 104a, that is, the auxiliary chips can undertake part of the functions of the SOC chip.

[0101] Figure 3 A top view of the packaging structure in an exemplary embodiment of the present invention is shown. Figure 3 As shown, a substrate 102, an optical chip 1031, and an electrical chip 1041 are sequentially arranged on the PCB board. The optical chip 1031 is provided with a first optical port 105 for connecting with an optical fiber to introduce optical signals.

[0102] It is understood that the number of stacking layers and the stacking type (such as the type of electrical chips in different layers) of the multi-layer stacking scheme proposed in this invention can be adaptively selected during the design stage based on actual design requirements (such as computational requirements).

[0103] Example 3: This invention also provides a light computing method applicable to any of the embodiments of the 3D packaging system, see [link to relevant documentation]. Figure 8 As shown, the method includes: S100, acquire at least one optical computing task; For example, in some embodiments, the computational task requiring optical computing can be a very large-scale matrix multiplication (e.g., above ten thousand orders). For this type of computational task, it can be broken down into multiple smaller optical computing tasks (e.g., dividing matrix multiplication into multiple sub-matrices). Subsequently, multiple optical chips are used to compute the product of the sub-matrices in parallel.

[0104] For example, in some embodiments, computational tasks with high real-time throughput requirements can also be broken down into multiple optical computing tasks for multi-chip operation. For instance, taking visual image analysis as an example (specifically, autonomous driving visual analysis), the image analysis processing flow, such as image segmentation and different neural network layers, can be distributed to multiple optical chips in a serial relay.

[0105] S101, mark the optical chips that meet the preset operating rules as candidate chips; S102, at least one of the candidate chips is selected as the execution chip, and the execution chip is used to execute at least one of the optical computing tasks; For example, in some embodiments, different optical chips can be categorized into different classes based on their operational status, such as running chips, candidate chips, and dormant chips. Running chips refer to optical chips that are currently in the process of computation, candidate chips refer to optical chips that are ready to be called upon, and dormant chips refer to optical chips that are recommended to be suspended from use.

[0106] Furthermore, in some embodiments, the method further includes: S103, Obtain the exception level of the execution chip; S104, when the anomaly level is greater than the preset first anomaly level, the execution chip is marked as a sleep chip, and a replacement chip is selected from the remaining candidate chips to continue executing the corresponding optical computing task; The step of selecting a replacement chip from the remaining candidate chips includes: (1) Obtain the total priority (i.e., the calling priority) of the candidate chip; the total priority is defined by the transmission distance of the optical channel and auxiliary information, the transmission distance is the distance between the candidate chip and the corresponding fiber array, and the auxiliary information includes: temperature, health status or functional matching degree; (2) Select the replacement chip from the candidate chips according to the total priority.

[0107] For example, priority is given to selecting candidate chips with higher priority as replacement chips.

[0108] In some embodiments, the anomaly level can be determined based on the computational delay of the optical chip; for example, the greater the computational delay, the higher the anomaly level.

[0109] In this embodiment, a fault response mechanism based on redundancy settings is provided for large-scale optoelectronic packaging systems.

[0110] First, for large-scale chip packaging, a shared light source (such as a shared optical fiber) is used to connect multiple chips. Furthermore, during multi-chip operation, the chip's priority is determined by combining its connection relationship with the shared light source (e.g., communication distance) and its personalized information (e.g., auxiliary information). Based on this priority, chips with potential problems (i.e., chips with higher anomaly levels) are promptly replaced or maintained.

[0111] In some embodiments, the anomaly level can also be determined based on the operating temperature of the optical chip. For example, if the operating temperature exceeds a set safe temperature, an anomaly is considered to be possible. Furthermore, the higher the operating temperature, the higher the anomaly level may be.

[0112] In some embodiments, the first or second anomaly level can be set by the user according to the actual operating conditions (calculation accuracy, computational load, etc.).

[0113] In some embodiments, the method further includes: S105, when the anomaly level is greater than a preset second anomaly level, and the anomaly level is less than or equal to the first anomaly level, then the following steps are executed: The optical computing task is divided into at least two sub-tasks; One of the sub-tasks is executed using the currently described execution chip, and at least one replacement chip is selected from the remaining candidate chips to execute the remaining sub-tasks.

[0114] Preferably, in some embodiments, when the number of remaining candidate chips is less than a preset number of candidates, it is preferable to keep the current execution chip and the replacement chip enabled synchronously.

[0115] This synchronous activation method helps to control the overall consumption of candidate resources (i.e., backup resources). Especially for long-term, large-scale computing, this restrictive consumption of backup resources helps to extend the overall lifespan of backup resources.

[0116] Alternatively, in other embodiments, a second anomaly level can be set based on the overall size of the candidate resources, such as the number of all candidate chips or spare chips. For example, the more candidate resources there are, the lower the first anomaly level, in which case a complete task switchover can be performed relatively preferably. Conversely, the fewer candidate resources there are, the higher the first anomaly level, in which case it is preferable to guide optical chips that may show signs of failure to maintain reliable operation, thereby partially occupying spare resources.

[0117] Preferably, in this embodiment, the replacement chip is selected based on the total priority.

[0118] For example, in some embodiments, an optical computing task is a matrix multiplication, which can be further divided into multiple smaller matrix multiplications, i.e., subtasks.

[0119] For example, in some embodiments, an optical computing task may contain multiple cascaded computing stages, which can be divided into multiple subtasks from the perspective of stages.

[0120] For example, in some embodiments, when a signal delay or excessive temperature is detected in an optical chip, its current optical computing tasks can be partially transferred to one or more replacement chips.

[0121] It is understood that this invention actually provides a hierarchical dynamic fault tolerance mechanism.

[0122] In cases where the optical chip failure is relatively severe, a direct replacement approach is adopted, which involves a complete transfer of the computing task. In this situation, a complete task transfer can prevent the spread of errors and system crashes.

[0123] When a chip shows signs of failure, partial disassembly and replacement can avoid or mitigate the latency jitter caused by restarting the entire task, and better meet the needs of special scenarios with high service continuity requirements.

[0124] For example, if a certain degree of delay is detected in the chip's signal, it can continue to run, but its subsequent tasks can be moved to another replacement chip for further execution.

[0125] In summary, this invention provides a fault handling method that allows for optimal switching between overall and local tasks. Under this coordinated approach of overall and local switching, a chip with potential for failure is not immediately discarded but instead assigned a lightweight task that matches its current capabilities. While the overall system performance may be slightly reduced, core services remain uninterrupted, providing users with valuable buffer time.

[0126] From another perspective, this switching mode can, to some extent, keep the core computing system (such as the area initially selected for optical computing chips) in a relatively stable state (such as an enabled state). Therefore, in the event of a fault, it minimizes the reliance on backup resources.

[0127] As for maintaining the core computing system, the main computing stages can use optical chips with short-distance transmission advantages (such as optical chips that are directly connected to optical fibers) to avoid or reduce the increased energy consumption problems that may be caused by backup chips (such as backup chips that are usually long-distance transmission chips, which may generate greater optical loss).

[0128] In other words, for the multi-chip system based on the fiber sharing mode mentioned above, this invention provides a method that can use redundant configuration resources to mitigate operational failures, while limiting or reducing the problem of increased optical loss that may be introduced during the mitigation process.

[0129] For example, in some embodiments, once the chip’s malfunction is resolved, it can be switched back to single-chip processing mode, that is, the computing tasks in the replacement chip are reintegrated into the original execution chip.

[0130] Preferably, in some embodiments, the sleep chip can be configured to suspend all signal processing.

[0131] Alternatively, in some embodiments, the sleep chip can be configured to act as a transmission chip (i.e., to transmit optical or electrical signals), pausing only computational processing tasks.

[0132] In some embodiments, the step of obtaining the total priority of the candidate chip includes: A first priority is determined based on the transmission distance; wherein, the greater the transmission distance, the lower the first priority. A second priority is determined based on the auxiliary information; The total priority is determined based on the first priority and the second priority.

[0133] In some embodiments, total priority = λ1 * first priority + λ2 * second priority; where λ1 and λ2 are preset weighting coefficients.

[0134] For example, in some embodiments, a corresponding total priority can be preset for different combinations of first priority and second priority. That is, the first priority, second priority, and total priority can be mapped in a table preset by the user.

[0135] In some embodiments, determining the second priority based on auxiliary information can be: the higher the operating temperature, the greater the second priority.

[0136] Alternatively, in some embodiments, determining the second priority based on auxiliary information can be: the greater the functional matching degree, the higher the second priority.

[0137] For example, in some embodiments, multiple optical chips can be of different categories. For instance, each optical chip can be specifically designed for certain solving tasks. For example, different optimization designs can be applied for matrix multiplication, convolution, or Fourier transform. Thus, different optical chips and different optical computing tasks can have different degrees of functional compatibility, and this degree of functional compatibility can be preset by the design engineer.

[0138] In some embodiments, optical chips can be applied to various solving tasks, but they have specific advantages in one or more particular solving tasks. Therefore, different optical chips have a set functional matching degree for different solving tasks.

[0139] Alternatively, in some embodiments, determining the second priority based on auxiliary information can be: the better the health status, the higher the second priority.

[0140] For example, in some embodiments, the health status can be determined by the test data of the optical chip before it leaves the factory or the yield data of the batch of optical chips.

[0141] Alternatively, in some embodiments, the health status can be determined by the operational data of the optical chip during operation. For example, the more errors reported during operation, the worse its health status is considered to be.

[0142] It is understandable that different priority scores can be set for the specific circumstances of the transmission distance and auxiliary information, and the specific scoring rules can be preset by the user.

[0143] In some embodiments, the operating rules include: requiring the temperature of the candidate chip to be lower than a preset temperature threshold, or requiring the error frequency of the candidate chip during its historical operating periods to be lower than a preset frequency.

[0144] For example, in some embodiments, when an optical chip is found to have an excessively high temperature, it is recommended that the optical chip be marked as a sleep chip, that is, that is, its use should be suspended during the current period.

[0145] For example, in some embodiments, the state of an optical chip can be assessed using its historical operating data, such as error frequency. If an optical chip's error frequency is too high, it can be temporarily marked as a dormant chip. For example, the error types could include excessive computational latency, large computational errors, or inability to output results, etc.

[0146] It is understood that, in order to address potential faults, this invention restrictively transfers the computational tasks of the optical chip, thereby achieving a certain degree of balance between computational reliability and computational efficiency.

[0147] For example, in the early stages of a potential fault, it's preferable to adjust the internal structure of the computing task (such as task splitting and reorganization). This allows other replacement chips to continue the computing task without interrupting the main workflow, thus improving operational smoothness to some extent. Conversely, in cases where the fault is more severe, chip-level adjustments are preferred, involving direct chip replacement.

[0148] Furthermore, it is worth noting that the restricted use of redundant configuration resources in this invention also helps to reduce the requirements for chip performance or quality in redundant configuration resources, thereby reducing the cost of redundant configuration.

[0149] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0150] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a computer terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0151] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A 3D packaging system, characterized by, include: Printed circuit board (101); A metal frame is disposed on the printed circuit board (101); the metal frame is provided with a plurality of conductive channels, and one end of the conductive channel is connected to the conductive interface of the printed circuit board. The optical computing layer (103) disposed on the metal frame includes: At least one optical computing region, wherein the optical computing region comprises: n*n optical chips, wherein each optical chip has a through-silicon via (TSV), and the other end of a conductive channel is connected to the TSV. The n*n optical chips include: At least one first optical chip (1031a), and the first optical chip (1031a) has a first optical port (105). At least one second optical chip (1031b), and the second optical chip (1031b) has a second optical port; The first optical chip (1031a) is disposed in the first side area of ​​the 3D packaging system, wherein the first optical port is disposed adjacent to the first side area, thereby exposing the first optical port (105) so that it can be connected to the fiber array (110). The second optical chip (1031b) is optically connected to the first optical chip (1031a) through the second optical port; An electrical transmission layer (104) includes at least one electrical transmission region corresponding to the optical computing region, and the electrical transmission region includes a plurality of electrical chips (1041). At least one electrical chip is provided with a first electrical channel (L1) and at least one second electrical channel (L2), wherein the first electrical channel (L1) is connected to the converter (109) and the second electrical channel (L2) is connected to another adjacent electrical chip; The converter (109) is disposed in the second side area of ​​the 3D packaging system so as to place the converter and the fiber array in different areas.

2. The 3D packaging system of claim 1, wherein, At least two of the electrical transmission areas are electrically connected.

3. The 3D packaging system according to claim 1, characterized in that, In one of the optical computing regions, at least one first optical chip and at least one second optical chip are encapsulated as a whole by a first adhesive layer (1033); and / or, in one of the electrical transmission regions, a plurality of the electrical chips are encapsulated as a whole by a second adhesive layer (1042).

4. The 3D packaging system according to claim 1, characterized in that, The metal frame includes: A first metal frame (106) and a second metal frame (1034) are arranged sequentially; wherein, the first metal frame (106) is provided with a plurality of first conductive channels, and the second metal frame (1034) is provided with a second conductive channel corresponding to the first conductive channels; The first surface of the first metal frame (106) and the first surface of the second metal frame (1034) are disposed opposite to each other, and the second surface of the first metal frame (106) is disposed facing the printed circuit board, so that the first conductive channel is connected to the conductive interface. The second metal frame (1034) has at least one mounting area (10341) on its second side corresponding to the optical computing area, the mounting area being used to mount the corresponding optical chip.

5. The 3D packaging system according to claim 1, characterized in that, The converter (109) is disposed on the electrical transmission layer, or the converter (109) is disposed on the metal frame.

6. The 3D packaging system according to claim 1, characterized in that, The first side area and the second side area are different side areas.

7. A light computing method applied to a 3D packaging system as described in any one of claims 1-6, characterized in that, The method includes: S100, acquire at least one optical computing task; S101, mark the candidate chips with optical chips that meet the preset operating rules; S102, at least one of the candidate chips is selected as the execution chip, and the execution chip is used to execute at least one of the optical computing tasks; S103, Obtain the exception level of the execution chip; S104, when the anomaly level is greater than the preset first anomaly level, the execution chip is marked as a sleep chip, and a replacement chip is selected from the remaining candidate chips to continue executing the corresponding optical computing task; The step of selecting a replacement chip from the remaining candidate chips includes: Obtain the total priority of the candidate chip; the total priority is defined by the transmission distance of the optical channel and auxiliary information, the transmission distance is the distance between the candidate chip and the corresponding fiber array, and the auxiliary information includes: temperature, health status or functional matching degree; The replacement chip is selected from the candidate chips based on the total priority.

8. The optical computing method according to claim 7, characterized in that, Also includes: S105, when the anomaly level is greater than a preset second anomaly level, and the anomaly level is less than or equal to the first anomaly level, then the following steps are executed: The optical computing task is divided into at least two sub-tasks; One of the sub-tasks is executed using the currently described execution chip, and at least one replacement chip is selected from the remaining candidate chips to execute the remaining sub-tasks.

9. The optical computing method according to claim 7, characterized in that, The steps for obtaining the total priority of the candidate chips include: A first priority is determined based on the transmission distance; wherein, the greater the transmission distance, the lower the first priority. A second priority is determined based on the auxiliary information; The total priority is determined based on the first priority and the second priority.

10. The optical computing method according to claim 7, characterized in that, The operating rules include: requiring the temperature of the candidate chip to be lower than a preset temperature threshold, or requiring the error reporting frequency of the candidate chip in historical operating periods to be lower than a preset frequency.

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